/art/compiler/utils/ |
H A D | assembler_thumb_test.cc | 175 #define __ assembler-> macro 179 __ FinalizeCode(); 180 size_t cs = __ CodeSize(); 183 __ FinalizeInstructions(code); 196 #undef __ macro 207 #define __ assembler. macro 210 __ movs(R0, ShifterOperand(R1)); 211 __ mov(R0, ShifterOperand(R1)); 212 __ mov(R8, ShifterOperand(R9)); 214 __ mo 1611 #undef __ macro [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_thumb2_test.cc | 100 #define __ GetAssembler()-> macro 103 __ sbfx(arm::R0, arm::R1, 0, 1); 104 __ sbfx(arm::R0, arm::R1, 0, 8); 105 __ sbfx(arm::R0, arm::R1, 0, 16); 106 __ sbfx(arm::R0, arm::R1, 0, 32); 108 __ sbfx(arm::R0, arm::R1, 8, 1); 109 __ sbfx(arm::R0, arm::R1, 8, 8); 110 __ sbfx(arm::R0, arm::R1, 8, 16); 111 __ sbfx(arm::R0, arm::R1, 8, 24); 113 __ sbf [all...] |
H A D | assembler_arm.cc | 858 #define __ sp_asm-> macro 859 __ Bind(&entry_); 861 __ DecreaseFrameSize(stack_adjust_); 865 __ mov(R0, ShifterOperand(scratch_.AsCoreRegister())); 867 __ LoadFromOffset(kLoadWord, R12, TR, QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value()); 868 __ blx(R12); 869 #undef __ macro
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/art/compiler/trampolines/ |
H A D | trampoline_compiler.cc | 46 #define __ assembler. macro 58 __ LoadFromOffset(kLoadWord, PC, R0, offset.Int32Value()); 61 __ LoadFromOffset(kLoadWord, IP, R0, JNIEnvExt::SelfOffset(4).Int32Value()); 62 __ LoadFromOffset(kLoadWord, PC, IP, offset.Int32Value()); 65 __ LoadFromOffset(kLoadWord, PC, R9, offset.Int32Value()); 67 __ bkpt(0); 69 __ FinalizeCode(); 70 size_t cs = __ CodeSize(); 73 __ FinalizeInstructions(code); 88 __ JumpT [all...] |
/art/compiler/optimizing/ |
H A D | code_generator_mips.cc | 144 #define __ down_cast<CodeGeneratorMIPS*>(codegen)->GetAssembler()-> macro 154 __ Bind(GetEntryLabel()); 190 __ Bind(GetEntryLabel()); 225 __ Bind(GetEntryLabel()); 229 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex()); 252 __ B(GetExitLabel()); 283 __ Bind(GetEntryLabel()); 288 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index); 301 __ B(GetExitLabel()); 316 __ Bin 480 #undef __ macro 481 #define __ macro 5213 #undef __ macro [all...] |
H A D | intrinsics_mips.cc | 58 #define __ codegen->GetAssembler()-> macro 73 __ Move(V0, trg_reg); 79 __ MovS(F0, trg_reg); 81 __ MovD(F0, trg_reg); 107 __ Bind(GetEntryLabel()); 130 __ B(GetExitLabel()); 142 #undef __ macro 150 #define __ assembler-> macro 167 __ Mfc1(out_lo, in); 168 __ MoveFromFpuHig 2476 #undef __ macro [all...] |
H A D | intrinsics_mips64.cc | 46 #define __ codegen->GetAssembler()-> macro 61 __ Move(V0, trg_reg); 67 __ MovS(F0, trg_reg); 69 __ MovD(F0, trg_reg); 96 __ Bind(GetEntryLabel()); 119 __ Bc(GetExitLabel()); 131 #undef __ macro 139 #define __ assembler-> macro 154 __ Dmfc1(out, in); 156 __ Mfc 1739 #undef __ macro [all...] |
H A D | intrinsics_arm.cc | 66 #define __ assembler-> macro 88 __ vmovrrd(output.AsRegisterPairLow<Register>(), 92 __ vmovrs(output.AsRegister<Register>(), input.AsFpuRegister<SRegister>()); 100 __ vmovdrr(FromLowSToD(output.AsFpuRegisterPairLow<SRegister>()), 104 __ vmovsr(output.AsFpuRegister<SRegister>(), input.AsRegister<Register>()); 164 __ clz(out, in_reg_hi); 165 __ CompareAndBranchIfNonZero(in_reg_hi, &end); 166 __ clz(out, in_reg_lo); 167 __ AddConstant(out, 32); 168 __ Bin 2027 #undef __ macro [all...] |
H A D | code_generator_mips64.cc | 105 #define __ down_cast<CodeGeneratorMIPS64*>(codegen)->GetAssembler()-> macro 115 __ Bind(GetEntryLabel()); 150 __ Bind(GetEntryLabel()); 184 __ Bind(GetEntryLabel()); 188 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex()); 207 __ Bc(GetExitLabel()); 238 __ Bind(GetEntryLabel()); 243 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index); 255 __ Bc(GetExitLabel()); 270 __ Bin 426 #undef __ macro 427 #define __ macro [all...] |
H A D | intrinsics_x86_64.cc | 80 #define __ assembler-> macro 101 __ movd(output.AsRegister<CpuRegister>(), input.AsFpuRegister<XmmRegister>(), is64bit); 107 __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<CpuRegister>(), is64bit); 154 __ bswapl(out); 155 __ sarl(out, Immediate(16)); 158 __ bswapl(out); 161 __ bswapq(out); 220 __ movsd(xmm_temp, codegen->LiteralInt64Address(INT64_C(0x7FFFFFFFFFFFFFFF))); 221 __ andpd(output.AsFpuRegister<XmmRegister>(), xmm_temp); 223 __ movs 2737 #undef __ macro [all...] |
H A D | code_generator_x86.cc | 50 #define __ down_cast<X86Assembler*>(codegen->GetAssembler())-> macro 59 __ Bind(GetEntryLabel()); 85 __ Bind(GetEntryLabel()); 111 __ Bind(GetEntryLabel()); 113 __ negl(reg_); 115 __ movl(reg_, Immediate(0)); 117 __ jmp(GetExitLabel()); 135 __ Bind(GetEntryLabel()); 172 __ Bind(GetEntryLabel()); 181 __ jm 693 #undef __ macro 694 #define __ macro 7387 #undef __ macro [all...] |
H A D | intrinsics_arm64.cc | 67 #define __ codegen->GetAssembler()->vixl_masm_-> macro 82 __ Mov(trg_reg, res_reg, kDiscardForSameWReg); 86 __ Fmov(trg_reg, res_reg); 108 __ Bind(GetEntryLabel()); 131 __ B(GetExitLabel()); 143 #undef __ macro 167 #define __ masm-> macro 188 __ Fmov(is64bit ? XRegisterFrom(output) : WRegisterFrom(output), 195 __ Fmov(is64bit ? DRegisterFrom(output) : SRegisterFrom(output), 243 __ Rev1 2227 #undef __ macro [all...] |
H A D | intrinsics_x86.cc | 86 #define __ assembler-> macro 117 __ movsd(temp, input.AsFpuRegister<XmmRegister>()); 118 __ movd(output.AsRegisterPairLow<Register>(), temp); 119 __ psrlq(temp, Immediate(32)); 120 __ movd(output.AsRegisterPairHigh<Register>(), temp); 122 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>()); 133 __ movd(temp1, input.AsRegisterPairLow<Register>()); 134 __ movd(temp2, input.AsRegisterPairHigh<Register>()); 135 __ punpckldq(temp1, temp2); 136 __ movs 2652 #undef __ macro [all...] |
H A D | code_generator_x86_64.cc | 54 #define __ down_cast<X86_64Assembler*>(codegen->GetAssembler())-> macro 63 __ Bind(GetEntryLabel()); 89 __ Bind(GetEntryLabel()); 115 __ Bind(GetEntryLabel()); 118 __ negl(cpu_reg_); 120 __ xorl(cpu_reg_, cpu_reg_); 126 __ negq(cpu_reg_); 128 __ xorl(cpu_reg_, cpu_reg_); 131 __ jmp(GetExitLabel()); 150 __ Bin 712 #undef __ macro 713 #define __ macro 6798 #undef __ macro [all...] |
H A D | code_generator_arm.cc | 62 #define __ down_cast<ArmAssembler*>(codegen->GetAssembler())-> macro 71 __ Bind(GetEntryLabel()); 95 __ Bind(GetEntryLabel()); 120 __ Bind(GetEntryLabel()); 127 __ b(GetReturnLabel()); 129 __ b(arm_codegen->GetLabelOf(successor_)); 163 __ Bind(GetEntryLabel()); 205 __ Bind(GetEntryLabel()); 209 __ LoadImmediate(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex()); 227 __ 676 #undef __ macro 677 #define __ macro [all...] |
H A D | optimizing_cfi_test.cc | 175 #define __ down_cast<arm::Thumb2Assembler*>(GetCodeGenerator()->GetAssembler())-> macro 177 __ CompareAndBranchIfZero(arm::R0, &target); 180 __ ldr(arm::R0, arm::Address(arm::R0)); 182 __ Bind(&target); 183 #undef __ macro 203 #define __ down_cast<mips::MipsAssembler*>(GetCodeGenerator()->GetAssembler())-> macro 205 __ Beqz(mips::A0, &target); 208 __ Nop(); 210 __ Bind(&target); 211 #undef __ macro 231 #define __ macro 239 #undef __ macro [all...] |
H A D | code_generator_arm64.cc | 39 #ifdef __ 135 #define __ down_cast<CodeGeneratorARM64*>(codegen)->GetVIXLAssembler()-> macro 167 __ Add(new_base, base, Operand(spill_offset + core_spill_size)); 176 __ StoreCPURegList(core_list, MemOperand(base, spill_offset)); 177 __ StoreCPURegList(fp_list, MemOperand(base, spill_offset + core_spill_size)); 179 __ LoadCPURegList(core_list, MemOperand(base, spill_offset)); 180 __ LoadCPURegList(fp_list, MemOperand(base, spill_offset + core_spill_size)); 228 __ Bind(GetEntryLabel()); 258 __ Bind(GetEntryLabel()); 290 __ Bin 861 #undef __ macro 928 #define __ macro [all...] |
/art/compiler/jni/quick/ |
H A D | jni_compiler.cc | 45 #define __ jni_asm-> macro 116 __ BuildFrame(frame_size, mr_conv->MethodRegister(), callee_save_regs, mr_conv->EntrySpills()); 122 __ StoreImmediateToFrame(main_jni_conv->HandleScopeNumRefsOffset(), 127 __ CopyRawPtrFromThread64(main_jni_conv->HandleScopeLinkOffset(), 130 __ StoreStackOffsetToThread64(Thread::TopHandleScopeOffset<8>(), 134 __ CopyRawPtrFromThread32(main_jni_conv->HandleScopeLinkOffset(), 137 __ StoreStackOffsetToThread32(Thread::TopHandleScopeOffset<4>(), 151 __ LoadRef(main_jni_conv->InterproceduralScratchRegister(), 153 __ VerifyObject(main_jni_conv->InterproceduralScratchRegister(), false); 154 __ StoreRe [all...] |
/art/compiler/utils/mips/ |
H A D | assembler_mips_test.cc | 24 #define __ GetAssembler()-> macro 196 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO); 198 __ Bind(&label); 201 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO); 225 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO); 227 __ Bind(&label); 230 __ Addu(mips::ZERO, mips::ZERO, mips::ZERO); 394 __ Ins(*reg1, *reg2, pos, size); 413 __ Ext(*reg1, *reg2, pos, size); 727 __ LoadFromOffse 1487 #undef __ macro [all...] |
/art/compiler/utils/mips64/ |
H A D | assembler_mips64_test.cc | 27 #define __ GetAssembler()-> macro 220 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO); 222 __ Bind(&label); 225 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO); 249 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO); 251 __ Bind(&label); 254 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO); 581 __ Jialc(&label1, mips64::T9); 584 __ Addu(mips64::ZERO, mips64::ZERO, mips64::ZERO); 586 __ Bin 1639 #undef __ macro [all...] |
/art/runtime/hprof/ |
H A D | hprof.cc | 415 #define __ output_-> macro 547 __ AddU4(sn); 548 __ AddObjectId(c); 549 __ AddStackTraceSerialNumber(LookupStackTraceSerialNumber(c)); 550 __ AddStringId(LookupClassNameId(c)); 565 __ AddU4(id); 566 __ AddUtf8String(string.c_str()); 642 __ AddU1List(reinterpret_cast<const uint8_t*>(magic), sizeof(magic)); 649 __ AddU4(sizeof(uint32_t)); 657 __ AddU [all...] |
/art/build/ |
H A D | Android.cpplint.mk | 44 art_cpplint_touch := $$(OUT_CPPLINT)/$$(subst /,__,$$(art_cpplint_file))
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/art/compiler/utils/x86/ |
H A D | assembler_x86.cc | 2390 #define __ sp_asm-> macro 2391 __ Bind(&entry_); 2394 __ DecreaseFrameSize(stack_adjust_); 2397 __ fs()->movl(EAX, Address::Absolute(Thread::ExceptionOffset<4>())); 2398 __ fs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(4, pDeliverException))); 2400 __ int3(); 2401 #undef __ macro
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/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.cc | 3155 #define __ sp_asm-> macro 3156 __ Bind(&entry_); 3159 __ DecreaseFrameSize(stack_adjust_); 3162 __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true)); 3163 __ gs()->call(Address::Absolute(QUICK_ENTRYPOINT_OFFSET(8, pDeliverException), true)); 3165 __ int3(); 3166 #undef __ macro
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