Searched refs:BSWAP (Results 1 - 25 of 30) sorted by relevance

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/external/elfutils/libasm/
H A Dasm_addint8.c49 #define BSWAP(size) _BSWAP(size) macro
105 var = BSWAP(SIZE) (var);
/external/opencv3/modules/imgcodecs/src/
H A Dbitstrm.hpp173 inline unsigned BSWAP(unsigned v) function in namespace:cv
/external/boringssl/src/crypto/sha/asm/
H A Dsha1-586.pl418 my ($ABCD,$E,$E_,$BSWAP)=map("xmm$_",(0..3));
450 &movdqa ($BSWAP,&QWP(0x50,$tmp1)); # byte-n-word swap
457 &pshufb (@MSG[0],$BSWAP);
459 &pshufb (@MSG[1],$BSWAP);
460 &pshufb (@MSG[2],$BSWAP);
461 &pshufb (@MSG[3],$BSWAP);
494 &pshufb (@MSG[0],$BSWAP);
500 &pshufb (@MSG[1],$BSWAP);
506 &pshufb (@MSG[2],$BSWAP);
511 &pshufb (@MSG[3],$BSWAP);
[all...]
H A Dsha1-x86_64.pl329 my ($ABCD,$E,$E_,$BSWAP,$ABCD_SAVE,$E_SAVE)=map("%xmm$_",(0..3,8,9));
349 movdqa K_XX_XX+0xa0(%rip),$BSWAP # byte-n-word swap
356 pshufb $BSWAP,@MSG[0]
358 pshufb $BSWAP,@MSG[1]
359 pshufb $BSWAP,@MSG[2]
361 pshufb $BSWAP,@MSG[3]
396 pshufb $BSWAP,@MSG[0]
402 pshufb $BSWAP,@MSG[1]
408 pshufb $BSWAP,@MSG[2]
413 pshufb $BSWAP,
[all...]
H A Dsha512-x86_64.pl527 my ($Wi,$ABEF,$CDGH,$TMP,$BSWAP,$ABEF_SAVE,$CDGH_SAVE)=map("%xmm$_",(0..2,7..10));
554 movdqa $TMP,$BSWAP # offload
642 movdqa $BSWAP,$TMP
/external/opencv/otherlibs/highgui/
H A Dbitstrm.h259 #define BSWAP(v) (((v)<<24)|(((v)&0xff00)<<8)| \ macro
H A Dbitstrm.cpp67 temp = BSWAP( temp );
H A Dgrfmt_tiff.cpp289 val = BSWAP( val );
/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/Target/Mips/
H A DMips16ISelLowering.cpp149 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
150 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
H A DMipsISelLowering.cpp413 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
415 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp283 case ISD::BSWAP:
708 case ISD::BSWAP:
887 // Generate a byte wise shuffle mask for the BSWAP.
H A DSelectionDAGDumper.cpp316 case ISD::BSWAP: return "bswap";
H A DLegalizeIntegerTypes.cpp57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
315 ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
1310 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1892 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1893 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
H A DLegalizeVectorTypes.cpp71 case ISD::BSWAP:
625 case ISD::BSWAP:
2086 case ISD::BSWAP:
H A DLegalizeDAG.cpp2836 /// Open code the operations for BSWAP of the specified operation.
2842 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
3005 case ISD::BSWAP:
4255 case ISD::BSWAP: {
4258 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
H A DDAGCombiner.cpp1390 case ISD::BSWAP: return visitBSWAP(N);
2730 N0.getOpcode() == ISD::BSWAP ||
3325 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3414 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3510 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3559 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
4921 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
4923 if (N0.getOpcode() == ISD::BSWAP)
H A DSelectionDAG.cpp2901 case ISD::BSWAP:
2998 case ISD::BSWAP:
3115 case ISD::BSWAP:
3117 "Invalid BSWAP!");
3119 "BSWAP types must be a multiple of 16 bits!");
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp153 setOperationAction(ISD::BSWAP, VT, Expand);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp193 setOperationAction(ISD::BSWAP, MVT::i16, Expand);
194 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
195 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp253 setOperationAction(ISD::BSWAP, VT, Expand);
327 setOperationAction(ISD::BSWAP, VT, Expand);
H A DSIISelLowering.cpp109 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1580 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1637 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp207 // PowerPC does not have BSWAP, CTPOP or CTTZ
208 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
212 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
481 setOperationAction(ISD::BSWAP, VT, Expand);
850 setTargetDAGCombine(ISD::BSWAP);
10233 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10235 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10510 case ISD::BSWAP:
10511 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.

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