Searched refs:FMAD (Results 1 - 8 of 8) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h246 /// FMAD - Perform a * b + c, while getting the same result as the
248 FMAD, enumerator in enum:llvm::ISD::NodeType
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp201 case ISD::FMAD: return "fmad";
H A DDAGCombiner.cpp7642 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
7653 // Always prefer FMAD to FMA for precision.
7654 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7825 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
7836 // Always prefer FMAD to FMA for precision.
7837 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
8091 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT));
8102 // Always prefer FMAD to FMA for precision.
8103 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
H A DLegalizeFloatTypes.cpp1880 case ISD::FMA: // FMA is same as FMAD
1881 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;
H A DLegalizeDAG.cpp3384 case ISD::FMAD:
/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp2055 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2064 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2093 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2103 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
H A DAMDGPUISelLowering.cpp103 setOperationAction(ISD::FMAD, MVT::f32, Legal);
/external/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp792 setOperationAction(ISD::FMAD, VT, Expand);

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