Searched refs:RC (Results 1 - 25 of 232) sorted by relevance

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/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument
30 if (RC == &NVPTX::Float32RegsRegClass) {
33 if (RC == &NVPTX::Float64RegsRegClass) {
35 } else if (RC == &NVPTX::Int64RegsRegClass) {
37 } else if (RC == &NVPTX::Int32RegsRegClass) {
39 } else if (RC == &NVPTX::Int16RegsRegClass) {
41 } else if (RC == &NVPTX::Int1RegsRegClass) {
43 } else if (RC == &NVPTX::SpecialRegsRegClass) {
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument
52 if (RC
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H A DNVPTXRegisterInfo.h60 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
61 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
/external/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h66 // Compute all information about RC.
67 void compute(const TargetRegisterClass *RC) const;
69 // Return an up-to-date RCInfo for RC.
70 const RCInfo &get(const TargetRegisterClass *RC) const {
71 const RCInfo &RCI = RegClass[RC->getID()];
73 compute(RC);
85 /// registers in RC in the current function.
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
87 return get(RC).NumRegs;
90 /// getOrder - Returns the preferred allocation order for RC
119 getMinCost(const TargetRegisterClass *RC) argument
127 getLastCostChange(const TargetRegisterClass *RC) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC
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/external/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp41 const TargetRegisterClass *RC = local
51 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; local
63 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
68 const TargetRegisterClass *RC = local
73 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
74 RC->getAlignment(), false);
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local
87 RC->getSize(), RC
106 getMoveF64ViaSpillFI(const TargetRegisterClass *RC) argument
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H A DMipsSEInstrInfo.cpp182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
189 if (Mips::GPR32RegClass.hasSubClassEq(RC))
191 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
193 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
195 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
197 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
199 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
205 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
249 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const argument
458 const TargetRegisterClass *RC = STI.isABI_N64() ? local
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H A DMipsInstrInfo.h92 const TargetRegisterClass *RC,
94 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
100 const TargetRegisterClass *RC,
102 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
108 const TargetRegisterClass *RC,
115 const TargetRegisterClass *RC,
H A DMips16RegisterInfo.h35 const TargetRegisterClass *RC,
/external/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h60 bool isSGPRClass(const TargetRegisterClass *RC) const {
61 return !hasVGPRs(RC);
76 bool hasVGPRs(const TargetRegisterClass *RC) const;
81 static bool isPseudoRegClass(const TargetRegisterClass *RC) { argument
82 return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass;
89 /// \returns The register class that is used for a sub-register of \p RC for
90 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
92 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
147 const TargetRegisterClass *RC) cons
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H A DR600RegisterInfo.h41 getRegClassWeight(const TargetRegisterClass *RC) const override;
/external/llvm/lib/CodeGen/
H A DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
68 S2RCMap.insert(std::make_pair(Slot, RC));
72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
85 if (RC)
86 OS << " [" << TRI->getRegClassName(RC) << "]\n";
H A DRegisterClassInfo.cpp76 /// compute - Compute the preferred allocation order for RC with reserved
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 assert(RC && "no register class given");
81 RCInfo &RCI = RegClass[RC->getID()];
84 unsigned NumRegs = RC->getNumRegs();
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
133 // Check if RC is a proper sub-class.
135 TRI->getLargestLegalSuperClass(RC, *MF))
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ")
157 const TargetRegisterClass *RC = nullptr; local
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H A DTargetRegisterInfo.cpp111 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
112 if (!RC || RC->isAllocatable())
113 return RC;
115 const unsigned *SubClass = RC->getSubClassMask();
142 const TargetRegisterClass* RC = *I;
143 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
144 (!BestRC || BestRC->hasSubClass(RC)))
145 BestRC = RC;
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/external/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local
83 unsigned ID = RC->getID();
204 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
206 assert(RW <= RC.width());
207 return eXTR(RC, 0, RW);
210 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
212 uint16_t W = RC.width();
214 return eXTR(RC, W-RW, W);
217 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
219 assert(N*16+16 <= RC
262 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); variable
278 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); variable
283 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); variable
299 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); variable
308 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); variable
312 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3))); variable
316 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); variable
321 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); variable
326 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0)); variable
331 RegisterCell RC = eADD(rc(1), lo(M, W0)); variable
336 RegisterCell RC = eADD(rc(1), lo(M, W0)); variable
341 RegisterCell RC = eADD(rc(1), lo(M, W0)); variable
345 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3))); variable
349 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0))); variable
353 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3))); variable
357 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3))); variable
361 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3))); variable
375 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3))); variable
379 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3))); variable
383 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0))); variable
387 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3))); variable
410 RegisterCell RC = eADD(rc(1), lo(M, W0)); variable
415 RegisterCell RC = eSUB(rc(1), lo(M, W0)); variable
420 RegisterCell RC = eADD(rc(1), lo(M, W0)); variable
458 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3))); variable
462 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3))); variable
482 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3))); variable
486 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3))); variable
495 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0))); variable
499 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0))); variable
568 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1); variable
577 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1); variable
606 RegisterCell RC = rc(1); variable
611 RegisterCell RC = rc(1); variable
616 RegisterCell RC = rc(1); variable
632 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1); variable
648 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); variable
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H A DBitTracker.h49 void put(RegisterRef RR, const RegisterCell &RC);
264 bool meet(const RegisterCell &RC, unsigned SelfR);
265 RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
269 RegisterCell &cat(const RegisterCell &RC); // Concatenate.
273 bool operator== (const RegisterCell &RC) const;
274 bool operator!= (const RegisterCell &RC) const {
275 return !operator==(RC);
294 friend raw_ostream &operator<<(raw_ostream &OS, const RegisterCell &RC);
313 RegisterCell RC(Width);
315 RC
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H A DHexagonBitSimplify.cpp162 static bool isConst(const BitTracker::RegisterCell &RC, uint16_t B,
164 static bool isZero(const BitTracker::RegisterCell &RC, uint16_t B,
166 static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
288 bool HexagonBitSimplify::isConst(const BitTracker::RegisterCell &RC, argument
290 assert(B < RC.width() && B+W <= RC.width());
292 if (!RC[i].num())
298 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC,
300 assert(B < RC.width() && B+W <= RC
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H A DHexagonVLIWPacketizer.h79 const TargetRegisterClass* RC);
82 const TargetRegisterClass* RC);
87 const TargetRegisterClass* RC);
90 const TargetRegisterClass* RC);
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h142 bool hasSubClass(const TargetRegisterClass *RC) const {
143 return RC != this && hasSubClassEq(RC);
146 /// Returns true if RC is a sub-class of or equal to this class.
147 bool hasSubClassEq(const TargetRegisterClass *RC) const {
148 unsigned ID = RC->getID();
154 bool hasSuperClass(const TargetRegisterClass *RC) const {
155 return RC->hasSubClass(this);
158 /// Returns true if RC is a super-class of or equal to this class.
159 bool hasSuperClassEq(const TargetRegisterClass *RC) cons
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/external/llvm/utils/release/
H A Dtest-release.sh26 RC=""
80 -rc | --rc | -RC | --RC )
82 RC="rc$1"
85 RC=final
92 RC="`echo $ExportBranch | sed -e 's,/,_,g'`"
167 if [ -z "$RC" ]; then
172 ExportBranch="tags/RELEASE_$Release_no_dot/$RC"
212 BuildDir=$BuildDir/$RC
222 if [ $RC !
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/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses)
117 OS << " " << RC.getName() << "RegClassID"
118 << " = " << RC.EnumValue << ",\n";
180 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
182 for (const auto &RC : RegBank.getRegClasses()) {
183 const CodeGenRegister::Vec &Regs = RC.getMembers();
188 RC.buildRegUnitSet(RegUnits);
192 OS << "}, \t// " << RC.getName() << "\n";
195 << " return RCWeightTable[RC->getID()];\n"
291 << "getRegClassPressureSets(const TargetRegisterClass *RC) cons
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/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h48 const TargetRegisterClass *RC,
54 const TargetRegisterClass *RC,
H A DThumb1InstrInfo.cpp73 const TargetRegisterClass *RC,
75 assert((RC == &ARM::tGPRRegClass ||
79 if (RC == &ARM::tGPRRegClass ||
99 const TargetRegisterClass *RC,
101 assert((RC == &ARM::tGPRRegClass ||
105 if (RC == &ARM::tGPRRegClass ||
71 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
97 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2InstrInfo.h50 const TargetRegisterClass *RC,
56 const TargetRegisterClass *RC,
H A DThumbRegisterInfo.h31 getLargestLegalSuperClass(const TargetRegisterClass *RC,
57 const TargetRegisterClass *RC,
/external/llvm/lib/Target/X86/
H A DX86RegisterInfo.h71 getSubClassWithSubReg(const TargetRegisterClass *RC,
75 getLargestLegalSuperClass(const TargetRegisterClass *RC,
88 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
95 unsigned getRegPressureLimit(const TargetRegisterClass *RC,

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