History log of /external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
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cddc3e03e4ec99c0268c03a126195173e519ed58 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)

Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0c7f116bb6950ef819323d855415b2f2b0aad987 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
94ee55d4b39d6506cf4e0f4e4b1c0b7fbbfeaed5 16-Sep-2013 Benjamin Kramer <benny.kra@googlemail.com> Replace some unnecessary vector copies with references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
71faecf16fd19eadaa42e2cb6c3b5165a9217f21 11-Sep-2013 Benjamin Kramer <benny.kra@googlemail.com> llvm-tblgen: Stabilize subreg index tables.

Otherwise SequenceToOffsetTable will sort by pointer and becomes non-deterministic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d93969c32a6bbae3326a1f485c4c85be1cb39406 23-Aug-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an OtherPreserved field to the CalleeSaved TableGen class.

This field specifies registers that are preserved across function calls,
but that should not be included in the generates SaveList array.

This can be used ot generate regmasks for architectures that save
registers through other means, like SPARC's register windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a946190351e561350a9ea71c8db31ffded6d80df 26-Jul-2013 Aaron Ballman <aaron@aaronballman.com> Using a different loop induction variable than the enclosing scope. No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
bba663e30a61b138c8f76632f8cacf00d7b0649a 25-Jul-2013 Andrew Trick <atrick@apple.com> RegPressure: Order the "pressure sets" by number of regunits per set.

This lets heuristics easily pick the most important set to follow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b7110cf5b5e4832e8ded6db7ab7577e3cfa2c462 27-Jun-2013 Chad Rosier <mcrosier@apple.com> Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers.

The current algorithm, LessRecord, uses the StringRef compare_numeric
function. This function compares strings, while handling embedded numbers.
For example, the R600 backend registers are sorted as follows:

T1
T1_W
T1_X
T1_XYZW
T1_Y
T1_Z
T2
T2_W
T2_X
T2_XYZW
T2_Y
T2_Z

In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2
have an EnumValue offset of 6 from one another. However, in other parts
of the register bank, the scaling factors are different:

dEnum/dN = 5:
KC0_128_W
KC0_128_X
KC0_128_XYZW
KC0_128_Y
KC0_128_Z
KC0_129_W
KC0_129_X
KC0_129_XYZW
KC0_129_Y
KC0_129_Z

The diff lists do not work correctly because different kinds of registers have
different 'scaling factors'. This new algorithm, LessRecordRegister, tries to
enforce a scaling factor of 1. For example, the registers are now sorted as
follows:

T1
T2
T3
...
T0_W
T1_W
T2_W
...
T0_X
T1_X
T2_X
...
KC0_128_W
KC0_129_W
KC0_130_W
...

For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I
did see a few small regressions, but the differences were on the order of a
few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even
greater wins for targets with larger register files.

Patch reviewed by Jakob.
rdar://14006013


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
239f8a4e116b2ce5b340ed1401c084a8bfed86f8 06-Jun-2013 Jakub Staszak <kubastaszak@gmail.com> Remove unimplemented definition. Found using [-Wunused-member-function].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183426 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
23ed37a6b76e79272194fb46597f7280661b828f 01-Jun-2013 Ahmed Bougacha <ahmed.bougacha@gmail.com> Make SubRegIndex size mandatory, following r183020.

This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
bed23081860275c79137f65d592920e7991b8198 31-May-2013 Ahmed Bougacha <ahmed.bougacha@gmail.com> Add a way to define the bit range covered by a SubRegIndex.

NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2275cfd75b65ede0f46f3cf914e76a38daf96417 28-May-2013 Chad Rosier <mcrosier@apple.com> Remove the MCRegAliasIterator tables and compute the aliases dynamically.

The size reduction in the RegDiffLists are rather dramatic. Here are a few
size differences for MCTargetDesc.o files (before and after) in bytes:
R600 - 36160B - 11184B - 69% reduction
ARM - 28480B - 8368B - 71% reduction
Mips - 816B - 576B - 29% reduction

One side effect of dynamically computing the aliases is that the iterator does
not guarantee that the entries are ordered or that duplicates have been removed.
The documentation implies this is a safe assumption and I found no clients that
requires these attributes (i.e., strict ordering and uniqueness).

My local LNT tester results showed no execution-time failures or significant
compile-time regressions (i.e., beyond what I would consider noise) for -O0g,
-O2 and -O3 runs on x86_64 and i386 configurations.
rdar://12906217


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
997fa623fc14122153c58ddda8c90aa30f192cc8 16-May-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TargetRegisterInfo::getCoveringLanes().

This lane mask provides information about which register lanes
completely cover super-registers. See the block comment before
getCoveringLanes().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
26369a930c523b75fe8f4ba18456ff86f68d5612 17-Mar-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Use ArrayRef<MVT::SimpleValueType> when possible.

Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
fbf3b4a07690751f72302757058ab0298dfb832e 20-Dec-2012 Jim Grosbach <grosbach@apple.com> MC: Add MCInstrDesc::mayAffectControlFlow() method.

MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
553c42cefc9abe1f10ee33d34a12498b8ac12fe6 05-Dec-2012 Andrew Trick <atrick@apple.com> RegisterPresssureTracker: Track live physical register by unit.

This is much simpler to reason about, more efficient, and
fixes some corner cases involving implicit super-register defs.
Fixed rdar://12797931.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
eca1fcf3d2d8246c45648fea59bd21a4091f9115 05-Dec-2012 Andrew Trick <atrick@apple.com> RegisterPressure API. Add support for physical register units.

At build-time register pressure was always computed in terms of
register units. But the compile-time API was expressed in terms of
register classes because it was intended for virtual registers (and
physical register units weren't yet used anywhere in codegen).

Now that the codegen uses physreg units consistently, prepare for
tracking register pressure also in terms of live units, not live
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e26e8a64ab37e98c69801ac2028b187773bc1d1f 29-Nov-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an MCPhysReg typedef to replace naked uint16_t.

Use this type for arrays of physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ad0b3b21e3abea7a9e9918ae1724f7dd7376b2cf 01-Nov-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Generate a table-driven version of TRI::composeSubRegIndices().

Explicitly allow composition of null sub-register indices, and handle
that common case in an inlinable stub.

Use a compressed table implementation instead of the previous nested
switches which generated pretty bad code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
61131ab15fd593a2e295d79fe2714e7bc21f2ec8 25-Oct-2012 Joerg Sonnenberger <joerg@bec.de> Remove exception handling usage from tblgen.

Most places can use PrintFatalError as the unwinding mechanism was not
used for anything other than printing the error. The single exception
was CodeGenDAGPatterns.cpp, where intermediate errors during type
resolution were ignored to simplify incremental platform development.
This use is replaced by an error flag in TreePattern and bailout earlier
in various places if it is set.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3f7b7f8ce0b050fc6a0100839d9c5a84198b2aed 10-Oct-2012 Sean Silva <silvas@purdue.edu> tblgen: Use semantically correct RTTI functions.

Also, some minor cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6cfc806a6b82b60a3e923b6b89f2b4da62cdb50b 10-Oct-2012 Sean Silva <silvas@purdue.edu> tblgen: Mechanically move dynamic_cast<> to dyn_cast<>.

Some of these dyn_cast<>'s would be better phrased as isa<> or cast<>.
That will happen in a future patch.

There are also two dyn_cast_or_null<>'s slipped in instead of
dyn_cast<>'s, since they were causing crashes with just dyn_cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ef2340ef4848065f74f9b98c5d392028392d7cae 16-Sep-2012 Craig Topper <craig.topper@gmail.com> Add 'virtual' keywoards to output file for overridden functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a6035773d8d29827a124e65c258adbf0dcbb1a5a 11-Sep-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TRI::getSubRegIndexLaneMask().

Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
de0250728b1a9e69ca593168f1ea2ecef8e9bf95 11-Sep-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Clean the sub-reg index composition maps at emission.

Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
59f45e4610e64b88bcee4cd46816ef64e815ff7e 11-Sep-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.

Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c97eda2c9e34f4c491f59bbac81af2fd63fef49d 15-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Make synthesized sub-register indexes available in the target namespace.

TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.

Also take this opportunity to stop creating new Record objects for
synthetic indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0371cd8b1c0d2101295ca9381a0b437e1f2d8fa2 27-Jul-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Eliminate the large XXXSubRegTable constant arrays.

These tables were indexed by [register][subreg index] which made them,
very large and sparse.

Replace them with lists of sub-register indexes that match the existing
lists of sub-registers. MCRI::getSubReg() becomes a very short linear
search, like getSubRegIndex() already was.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
303c909d5bb014fbeec395090eb467d724969195 25-Jul-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Differentially encode all MC register lists.

This simplifies MCRegisterInfo and shrinks the target descriptions a bit
more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6f36fa981a59461466e12e5056ba209d289b81b1 11-Jun-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Write llvm-tblgen backends as functions instead of sub-classes.

The TableGenBackend base class doesn't do much, and will be removed
completely soon.

Patch by Sean Silva!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b2a6d8100cfb8a4f9ee251fb274c2d6688b27963 31-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Didn't mean to export this function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f5d4e5158fcbec26d1c243daa725878ca1ae560b 31-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit register unit root tables.

Each register unit has one or two root registers. The full set of
registers containing a given register unit can be computed as the union
of the root registers and their super-registers.

Provide an MCRegUnitRootIterator class to enumerate the roots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ff09e56cda85c1740ac1689018dfe0d3cf49ae6c 30-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Print uint16_t numbers without a sign.

It seems I broke C++11.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f52baf72c116d9cf8680d25a8e751ce354c7d44b 30-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit register unit lists for each register.

Register units are already used internally in TableGen to compute
register pressure sets and overlapping registers. This patch makes them
available to the code generators.

The register unit lists are differentially encoded so they can be reused
for many related registers. This keeps the total size of the lists below
200 bytes for most targets. ARM has the largest table at 560 bytes.

Add an MCRegUnitIterator for traversing the register unit lists. It
provides an abstract interface so the representation can be changed in
the future without changing all clients.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d5ce3ffa67698b9d21f58011f370a210a214d301 25-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compress MCRegisterInfo register name tables.

Store (debugging) register names as offsets into a string table instead
of as char pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3778aeb74864390bf763424c45cc355ac330fbc9 17-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Use RegUnits to compute overlapping registers.

TableGen already computes register units as the basic unit of
interference. We can use that to compute the set of overlapping
registers.

This means that we can easily compute overlap sets for one register at a
time. There is no benefit to computing all registers at once.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0ee07e013095e8c298fbcc5203e0bc9f334e15e1 15-May-2012 Jim Grosbach <grosbach@apple.com> TableGen'erate mapping physical registers to encoding values.

Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7855ec62c3b6b5b7e6d3fada589511abd964fdb3 04-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove TargetRegisterClass::SuperRegClasses.

This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
dd63a063e2df0d0bc52b50732e3462fd58a636c0 04-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Use a shared implementation of getMatchingSuperRegClass().

TargetRegisterClass now gives access to the necessary tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1a2a19dd3ce2b163837b5f0a1ea474c72527cad6 04-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TargetRegisterClass::getSuperRegIndices().

This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6a0ed18532425d637ecc1cc851c559db446ec4e8 04-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit SuperRegMasks as part of the existing SubClassMask arrays.

The RC->getSubClassMask() pointer now points to a sequence of register
class bit masks. The first bit mask is the normal sub-class mask. The
following masks are super-reg class masks used by
getMatchingSuperRegClass().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f92be238d6370fbab58f035a5bd0c6db7e207094 03-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compress tables for getMatchingSuperRegClass().

Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
309076ff76c61e03ddd3a0fbbfded3042d2da2e5 03-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't override subreg functions in targets without subregisters.

Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f0ae38ef2e806f272f6b66bcad543cb1331060b1 21-Apr-2012 Craig Topper <craig.topper@gmail.com> Remove 'XXXRegisterClass' from tablegen output. Targets should use '&XXXRegClass' instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7c0903a924b110dad0648e0b6cbdd2f38496fe28 20-Apr-2012 Andrew Trick <atrick@apple.com> TableGen'd RegPressure: Added getPressureSetName.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3cbcffc4e5990209ce80a54e615f55245fe3b824 18-Apr-2012 Benjamin Kramer <benny.kra@googlemail.com> tblgen: remove duplicated newlines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
bfb4327baa5bbab78f0da4c8c069482878660a04 18-Apr-2012 Jim Grosbach <grosbach@apple.com> Move a few more warnings to use PrintWarning().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
723fc11f91240e267dd748b467b43b6c00498e4b 18-Apr-2012 Jim Grosbach <grosbach@apple.com> Formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5bd9e0dd028202f94391a394a12a6b8c69ee52e3 18-Apr-2012 Jim Grosbach <grosbach@apple.com> Tidy up. Add a '.' at the end of the sentence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ec14cd7ddc66d47cd7927f18d8c11844c400367e 11-Apr-2012 Andrew Trick <atrick@apple.com> TableGen's regpressure: emit per-registerclass weight limits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
680363b5fdf7ce6e188d4c8c7508fc819061ba6d 11-Apr-2012 Andrew Trick <atrick@apple.com> Tablegen'd regpressure: emit the weighted pressure limit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
176194d4ee2774bc135ababc5bd6c6c9f606b2a5 10-Apr-2012 Andrew Trick <atrick@apple.com> Added register unit sets to the target description.

This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9b1b25f0631b22cd09c2fa7383ce28721fa3e212 03-Apr-2012 Craig Topper <craig.topper@gmail.com> Tidy up spacing in some tablegen outputs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153937 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
243018ffcf764e4dde2968f909f4a2e578aafe86 01-Apr-2012 Benjamin Kramer <benny.kra@googlemail.com> Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup.

This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0d4e2ea00eac5d51a74a54dd504a8f34580041d7 30-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Reapply 153764 and 153761 with a fix.

Use an explicit comparator instead of the default.

The sets are sorted, but not using the default comparator. Hopefully,
this will unbreak the Linux builders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
77ff8bbc2abf13b269bf1e66526e813955b078a7 30-Mar-2012 Rafael Espindola <rafael.espindola@gmail.com> Revert 153764 and 153761. They broke a --enable-optimized --enable-assertions
--enable-expensive-checks build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ecf2d9fc0d5ea162571b0e229f47b22e84c93eaa 30-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compress SimpleValueType lists by sharing.

Many register classes have the same value types. Share the table space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
8f36b0b139b5ba683eedf022f1b0c1279b680cf7 30-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Compress register lists by sharing suffixes.

TableGen emits lists of sub-registers, super-registers, and overlaps. Put
them all in a single table and use a SequenceToOffsetTable to share
suffixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153761 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c6a96ff6aeeb77e1007364e5603b72f3ab4cc7bd 29-Mar-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add more constness to CodeGenRegisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
904a01820c86dd1e2bc7aef2950ed75a2c9c2640 06-Mar-2012 Craig Topper <craig.topper@gmail.com> Add asserts to ensure that values will fit into the tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
52b89dd303424582d054e18417099f3a7e343b41 05-Mar-2012 Craig Topper <craig.topper@gmail.com> Shrink and reorder fields in MCRegisterClass to reduce size of static data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9ebfbf8b9fd5f982e0db9293808bd32168615ba9 05-Mar-2012 Craig Topper <craig.topper@gmail.com> Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e4fd907e72a599eddfa7a81eac4366b5b82523e3 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store register overlaps to reduce static data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b6632ba380cf624e60fe16b03d6e21b05dd07724 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
015f228861ef9b337366f92f637d4e8d624bb006 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store registers in callee saved register tables to reduce size of static data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4b1212b4bfac98c688d484bf22ae158875f06ad5 01-Mar-2012 Benjamin Kramer <benny.kra@googlemail.com> Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b3acdcc00c9dfb01663780e858e586cc5f04423f 01-Mar-2012 Jim Grosbach <grosbach@apple.com> Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.

Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
194f3fa9eadc7dfe9f1750c16e1c2a8ebe11c88c 01-Mar-2012 Jim Grosbach <grosbach@apple.com> Revert "Emit the SubRegTable with the smallest possible integer type."

This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ccc8d3ba06408feff0ca6e58973c20d15010e3fc 01-Mar-2012 Benjamin Kramer <benny.kra@googlemail.com> Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.

This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.

Shrinks ARMBaseRegisterInfo.o by ~100k.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6c449ebbe6b5e9909ee7a5673b4892d30b9c3ce8 01-Mar-2012 Benjamin Kramer <benny.kra@googlemail.com> Implement getSubRegIndex as a linear search on the SubRegTable instead of using a big switch.

- The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts.
- This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b9ace0215d20e29a0e59de2917178ad5e308a835 29-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com> Emit the SubRegTable with the smallest possible integer type.

Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
eea87153d10b9aa774eb5118a58735b4af6489b8 29-Feb-2012 Jim Grosbach <grosbach@apple.com> Tidy up. Spelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5d9651df892afb0bb4036827c327b8effe87060c 29-Feb-2012 Jim Grosbach <grosbach@apple.com> Move the subregister indicies enum into the REGINFO_ENUM section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
95b38aea959449461a9245b0a199758982125f01 29-Feb-2012 Jim Grosbach <grosbach@apple.com> Switch TargetRegisterInfo::getSubReg() to use a lookup table.

Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9d91c5d31c6758124559c0916d852295f47a2bec 23-Feb-2012 Craig Topper <craig.topper@gmail.com> Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that were added in r151038.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c528e462a18bea90d8680a96d44c6df1cd3e030a 22-Feb-2012 Craig Topper <craig.topper@gmail.com> Declare register classes as const. Fix a couple pointers to register classes that weren't already const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
44d23825d61d530b8d562329ec8fc2d4f843bb8d 22-Feb-2012 Craig Topper <craig.topper@gmail.com> Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7d9b20792bfc528647f8bd7644934b228cc6c60b 21-Feb-2012 Craig Topper <craig.topper@gmail.com> Reorder some members in MCRegisterClass to remove padding on 64-bit builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f3e3783012dc7875ed37be8aaaefd96f98454781 21-Feb-2012 Craig Topper <craig.topper@gmail.com> In generated RegisterInfo files, replace a pointer to the end of an array with just the size of the array to avoid relocations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
902af25abdc9e6d25b898310c1e4716bbe768fb9 21-Feb-2012 Craig Topper <craig.topper@gmail.com> Merge some tables in generated RegisterInfo file. Store indices into larger table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2c6ae095b8a944c8355377498b9ad11bb94af2d5 09-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com> Store just the SimpleValueType in the generated VT tables for each register class, eliminating static ctors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9bcc7a6973f76255765124fbc4e8f6022bd9f756 08-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com> Don't map registers to the invalid dwarf register (-1). It's the default value.

X86GenRegisterInfo.inc | 1032 -------------------------------------------------
1 file changed, 1032 deletions(-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
90a468c424f7d0a85b3dc783634106d9a46d6688 08-Feb-2012 Benjamin Kramer <benny.kra@googlemail.com> Value initialize MCRegisterClasses. Not sure how could miss this during the MCTargetDesc refactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
655b8de7b2ab773a977e0c524307e71354d8af29 05-Feb-2012 Craig Topper <craig.topper@gmail.com> Convert assert(0) to llvm_unreachable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f18a9a2314542ad3b7a601b86969073519e19b0d 01-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Avoid emitting empty arrays, they're not standard C++.

It's only by luck that we haven't produced any yet, and clang refuses to
compile them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ed2d17b2d4ae20a83304357d6c84ed10e88bc036 31-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Don't assign a value to NUM_TARGET_NAMED_SUBREGS.

It was wrong and completely unused.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
90498b195ba759cf4f2a98da4e46fb9a2b580396 31-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Move the composite map into CodeGenSubRegIndex.

Each SubRegIndex keeps track of how it composes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5fcc156344e0d38fa5f5eab3d9193b859b27b45e 31-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a TableGen CodeGenSubRegIndex class.

This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ec572539dd5660f9ca42027ac04df3a3f8c0cab1 17-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TableGen support for callee saved registers.

Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
570f9a972e02830d1ca223743dd6b4cc4fdf9549 19-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit a getMatchingSuperRegClass() implementation for every target.

Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e39102819e30551690ba37b526a353df542837d0 27-Oct-2011 Jim Grosbach <grosbach@apple.com> Delete dead code. Nothing ever instantiates this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1a2f9886a2a60dbd41216468a240446bbfed3e76 22-Oct-2011 Benjamin Kramer <benny.kra@googlemail.com> Move various generated tables into read-only memory, fixing up const correctness along the way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d9c1fa5205cc31474f9f9a6d715af32098a1a719 06-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the TRI::getSubRegisterRegClass() hook.

This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'. Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in? The
getSubRegisterRegClass() hook did that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
845d2c0c776abce551d16f7b1b7dc1f4d4df1a27 05-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add TRI::getSubClassWithSubReg(RC, Idx) function.

This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6fea31e7300fe012b0b2984d6bc0338d02b054d3 04-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> TableGen: Privatize CodeGenRegisterClass::TheDef and Name.

When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference. All register classes must have a
name, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7c788888872233748da10a8177a9a1eb176c1bc8 01-Oct-2011 Peter Collingbourne <peter@pcc.me.uk> Move TableGen's parser and entry point into a library

This is the first step towards splitting LLVM and Clang's tblgen executables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c8e2bb68bbc4a71cc10084c8f89565b9f05e12ef 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Store sub-class lists as a bit vector.

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes. This makes it
cheap to add them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b7359e384f7d15d3e24b3763ed66546e497fe213 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Extract a slightly more general BitVector printer.

This one can also print 32-bit groups.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f9a4bb78dadc12c7c1e604c6f17b63a71305c2ca 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute lists of super-classes in CodeGenRegisterClass.

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
29f018cee616e4082e5005bc9adee4dc777e621c 30-Sep-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Switch to ArrayRef<CodeGenRegisterClass*>.

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
05bce0beee87512e52428d4b80f5a8e79a949576 30-Jul-2011 David Greene <greened@obbligato.org> Unconstify Inits

Remove const qualifiers from Init references, per Chris' request.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f37dd02f7743ebd2424480361f5a7db510495c4f 29-Jul-2011 David Greene <greened@obbligato.org> [AVX] Constify Inits

Make references to Inits const everywhere. This is the final step
before making them unique.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5de728cfe1a922ac9b13546dca94526b2fa693b6 28-Jul-2011 Evan Cheng <evan.cheng@apple.com> Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a397a11c7c60e500baa36eea59a46a9aa2e5f35b 23-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> We always bounds check the bit set, there is no need to emit zero bytes at the end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9df8567548e15c6cd91e8a5851784574c4f09528 23-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This should be faster and smaller.

Goodbye static ctors and dtors!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f496d68493acf8d178afbbe8c3146ea09bd7776b 23-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> Give TargetRegisterClass a pointer to the MCRegisterClass and use it to access its data.

This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
256535f136739bb1240ae39104cf64e79c355bce 23-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> Use the enum value for RegClassIDs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c84806684374f44c777132e7d2bb5308444cee67 22-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> Remove unused variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
8ca9a862038e8c4e9a2ca73b3b75e1be3425155f 22-Jul-2011 Benjamin Kramer <benny.kra@googlemail.com> Teach tblgen to emit MCRegisterClasses.

- This currently introduces more instances of the static DenseSet dtor, but that should be fixable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0e6a052331f674dd70e28af41f654a7874405eab 18-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
39b5abf507b43da6b92f68b86406e0015ead18e9 18-Jul-2011 Frits van Bommel <fvbommel@gmail.com> Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
20722b6cda6a8857a00e84133c8d8516400aca4d 15-Jul-2011 NAKAMURA Takumi <geek4civic@gmail.com> Eliminate "const" from extern const to fix breakeage since r135184 on msvc.

MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d568b3f55294917d1cc701da14a8a7daeb6563e6 12-Jul-2011 Eric Christopher <echristo@apple.com> Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d4a9066c93da9a5aab47ca228d82e796fdec70c0 11-Jul-2011 David Greene <greened@obbligato.org> [AVX] Make Inits Foldable

Manage Inits in a FoldingSet. This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d5b03f252c0db6b49a242abab63d7c5a260fceae 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6844f7bcdec8c2691c8d1067d90e4a02cf658c27 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Hide more details in tablegen generated MCRegisterInfo ctor function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4987033fbd8e774e67903f50a8bd20d539c4dca5 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Alternative name enum should go into the enum portion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
bea6f615eefae279e53bbb63a31d2c3c67274c45 27-Jun-2011 Owen Anderson <resistor@mac.com> Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0.
Patch by Jim Grosbach.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ebbbfd0e2eeeb5b1a15f0e655a0a2119510713d4 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> More refactoring. MC doesn't need know about subreg indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
025b37b5f035fcc9388d9615f6401ab3095d8b3f 25-Jun-2011 Evan Cheng <evan.cheng@apple.com> Remove dead typedefs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5e6b4605bd620a864055276a6d454e5a18f9fee8 25-Jun-2011 Evan Cheng <evan.cheng@apple.com> Rename TargetRegisterDesc to MCRegisterDesc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f5fa52ed064098be7130aa4ec1236037907ce3fa 24-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5c10b63969a758992dccc830fa0c64a77e80d8d5 24-Jun-2011 Benjamin Kramer <benny.kra@googlemail.com> Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.

This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d 24-Jun-2011 Evan Cheng <evan.cheng@apple.com> Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
abdbc84b4ed4276ed3def50f554e3ba156325717 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Store CodeGenRegisters as pointers so they won't be reallocated.

Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
54c47c1ce94b9e549ef768e80fd004788d13ce85 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove MethodProtos/MethodBodies and allocation_order_begin/end.

Targets that need to change the default allocation order should use the
AltOrders mechanism instead. See the X86 and ARM targets for examples.

The allocation_order_begin() and allocation_order_end() methods have been
replaced with getRawAllocationOrder(), and there is further support
functions in RegisterClassInfo.

It is no longer possible to insert arbitrary code into generated
register classes. This is a feature.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b4c704877d1600852a55ab7bef2918a7c0af5e0d 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Provide AltOrders for specifying alternative allocation orders.

A register class can define AltOrders and AltOrderSelect instead of
defining method protos and bodies. The AltOrders lists can be defined
with set operations, and TableGen can verify that the alternative
allocation orders only contain valid registers.

This is currently an opt-in feature, and it is still possible to
override allocation_order_begin/end. That will not be true for long.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1e56a2a85fbafce5ceee72f72d41b84a71876844 15-Jun-2011 Owen Anderson <resistor@mac.com> Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists.

At the time I wrote this code (circa 2007), TargetRegisterInfo was using a std::set to perform these queries. Switching to the static hashtables was an obvious improvement, but in reality there's no reason to do anything other than scan.
With this change, total LLC time on a whole-program 403.gcc is reduced by approximately 1.5%, almost all of which comes from a 15% reduction in LiveVariables time. It also reduces the binary size of LLC by 86KB, thanks to eliminating a bunch of very large static tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133051 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ae1920b1efa72c1789d562df4746110d0c2e10bd 15-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Give CodeGenRegisterClass a real sorted member set.

Make the Elements vector private and expose an ArrayRef through
getOrder() instead. getOrder will eventually provide multiple
user-specified allocation orders.

Use the sorted member set for member and subclass tests. Clean up a lot
of ad hoc searches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
952036def97bbf3f26cb963f12f64cda281feffd 14-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Fix a compile time regression caused by too small hash tables.

Measure the worst case number of probes for a miss instead of the less
conservative number of probes required for an insertion.

Lower the limit to < 6 probes worst case.

This doubles the size of the ARM and X86 hash tables, other targets are
unaffected. LiveVariables runs 12% faster with this change.

<rdar://problem/9598545>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b95fd2d5fd4818a601dd1df05f38863e3ca5c920 12-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Tweak hash function and compress hash tables.

Make the hash tables as small as possible while ensuring that all
lookups can be done in less than 8 probes.

Cut the aliases hash table in half by only storing a < b pairs - it
is a symmetric relation.

Use larger multipliers on the initial hash function to ensure that it
properly covers the whole table, and to resolve some clustering in the
very regular ARM register bank.

This reduces the size of most of these tables by 4x - 8x. For instance,
the ARM tables shrink from 48 KB to 8 KB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
bf710cc23ed7a3cd3e114e122cf0f11a033d23b1 12-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove now dead code.

These computations have been moved to CodeGenRegisters.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4091b059ec9568228f50fd67a1a81ee35c234787 12-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Extract the generateHashTable function.

The constant hash tables for sub-registers and overlaps are generated
the same way, so extract a function to generate and print the hash
table.

Also use the information computed by CodeGenRegisters.cpp instead of the
locally data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
026dc223aeef2579d63f395007491e37d6cde3a0 12-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Compute lists of sub-regs, super-regs, and overlapping regs.

Besides moving structural computations to CodeGenRegisters.cpp, this
also well-defines the order of these lists:

- Sub-register lists come from a pre-order traversal of the graph
defined by the SubRegs lists in the .td files.

- Super-register lists are topologically ordered so no register comes
before any of its sub-registers. When the sub-register graph is not a
tree, independent super-registers appear in numerical order.

- Lists of overlapping registers are ordered according to register
number.

This reverses the order of the super-regs lists, but nobody was
depending on that. The previous order of the overlaps lists was odd, and
it may have depended on the precise behavior of std::stable_sort.

The old computations are still there, but will be removed shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b5923db192d2aa938ff3c12aaac87d80ab649625 11-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Move the list of registers into CodeGenRegBank.

Also move the sub-register index computations from RegisterInfoEmitter
into CodeGenRegBank.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
dc29c447136aabf05f48a7119e48065c3b4cee9b 10-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Move some sub-register index calculations to CodeGenRegisters.cpp

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f462e3fac7ac67503657d63dc35330d0b19359b3 03-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Make it possible to have unallocatable register classes.

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6e032942cf58d1c41f88609a1cec74eb74940ecd 30-May-2011 Rafael Espindola <rafael.espindola@gmail.com> Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7a067cc6e0b980b186696c13fe847929fbc0d373 30-May-2011 Rafael Espindola <rafael.espindola@gmail.com> Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.

The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7bf114c1bd0390f4f485905d2fe9c7c6a048b8b7 28-May-2011 Rafael Espindola <rafael.espindola@gmail.com> Fix the root cause of the bootstrap failure:

There was no way to check if a given register/mode pair was valid. We now return
an error code (-2) instead of asserting. If anyone thinks that an assert
at this point is really needed, we can autogen a hasValidDwarfRegNum instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4bfc6fba78a37ca246bd25753844788d4e562aaf 10-May-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Downgrade a tablegen warning to an error.

Ambiguous sub-register index compositions are OK as long as the backend writer
knows what he is doing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
123cab9480812e51f6d4cb118fe685691130f625 07-May-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Teach TableGen to automatically generate missing SubRegIndex instances.

The RegisterInfo.td file should only specify the indexes that sources need to
refer to. The rest is inferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 20-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Prefer cheap registers for busy live ranges.

On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.

Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.

Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
17fad045cccf34822d3163ada9e70a8f4528746e 11-Mar-2011 Jim Grosbach <grosbach@apple.com> Make the register enum value part of the CodeGenRegister struct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5d4314ef720630e6547fe41efec1608d4c14c78e 11-Mar-2011 Jim Grosbach <grosbach@apple.com> Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b83ff84193d44bb9aa75e1264ffaff55f468a303 15-Dec-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

stuff(Reg)
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
stuff(*Alias);

That can now be written as the simpler:

for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
67db883487fca3472fdde51e931657e22d4d0495 13-Dec-2010 Chris Lattner <sabre@nondot.org> eliminate the Records global variable, patch by Garrison Venn!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a2c9188560eb9a7d494960fefd28cf0998d9a78f 25-Aug-2010 Eric Christopher <echristo@apple.com> Split out register class subclassing to a separate function and clean up
accordingly. No functional change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a606d955de3b0f777131d74162eb6f11b5f95d75 18-Jun-2010 Dan Gohman <gohman@apple.com> Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7c9a6e328407d681414aa66f3e80f92c3d35ad5c 29-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit TargetRegisterInfo::composeSubRegIndices().
Also verify that all subregister indices compose unambiguously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6f0ff1d578cfa333164e806c2290f02dd5ebebd1 27-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Check that inherited subregisters all have a direct SubRegIndex.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f86a619314d431ea5ccb1becb38d8a015f6c5501 26-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Suppress emmission of empty subreg/superreg/alias sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ca561ffcf320e9dbfafcac5efcee81471f3259c3 26-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace the SubRegSet tablegen class with a less error-prone mechanism.

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b555609e73f5091bf8180c0875fb1fa6c5ad0e7a 26-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."

This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6a45d681e53a99b4c4f63e0b1664626a596a8151 26-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace the SubRegSet tablegen class with a less error-prone mechanism.

A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
76f0ad7bf5c05d6056b3bf335d0c3fb7e72de5d6 26-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Drop the SuperregHashTable. It is essentially the same as SubregHashTable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1fc8e759a767077726f9be35b93767e68bdf101f 25-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Print symbolic SubRegIndex names on machine operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
48d0c163fb60f7da7ef3657df242bf11dbdb0617 25-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
33276d95ef4191663d8e6b972481f9faf37ce541 25-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Switch SubRegSet to using symbolic SubRegIndices

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
09bc0298650c76db1a06e20ca84c1dcb34071600 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
73ea7bf4509663267317ec3911aac00ca35a2f2c 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Add the SubRegIndex TableGen class.

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e854273892a5fed9a797ed58e472cca2e95fcc33 09-Dec-2009 Daniel Dunbar <daniel@zuster.org> Remove unneeded ';' and a class/struct mismatch (noticed by clang).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
fae3e923452b85e72b2c03dd6eacc063f59d81b1 14-Nov-2009 Evan Cheng <evan.cheng@apple.com> Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e7f3107772b1c8c2b9397ab19106b8451d31e8ab 14-Sep-2009 Chris Lattner <sabre@nondot.org> eliminate the TargetRegisterDesc::AsmName field, the asmprinters now have this table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
825b72b0571821bf2d378749f69d6c4cfb52d2f9 11-Aug-2009 Owen Anderson <resistor@mac.com> Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e50ed30282bb5b4a9ed952580523f2dda16215ac 11-Aug-2009 Owen Anderson <resistor@mac.com> Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2395f011986e6c6277c71bddcd8af88f9b904fc2 30-Jul-2009 Dan Gohman <gohman@apple.com> Minor whitespace tidiness.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1a55180238dbcf11113f610aea010447e51f595b 03-Jul-2009 Daniel Dunbar <daniel@zuster.org> Replace std::iostreams with raw_ostream in TableGen.
- Sorry, I can't help myself.

- No intended functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7afcc6aa270ca51e502de9f826ecdf61568a73b9 30-Apr-2009 Jakob Stoklund Olesen <stoklund@2pi.dk> Slightly change TableGen's definition of a register subclass.

A subclass is allowed to have a larger spill size than the superclass, and the
spill alignment must be a multiple of the superclass alignment. This causes
the following new subclass relations:

=== Alpha ===
F4RC -> F8RC

=== PPC ===
F4RC -> F8RC

=== SPU ===
R8C -> R16C -> R32C/R32FP -> R64C/R64FP -> GPRC/VECREG

=== X86 ===
FR32 -> FR64 -> VR128
RFP32 -> RFP64 -> RFP80

These subclass relations are consistent with the behaviour of -join-cross-class-copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f8c7394781f7cf27ac52ca087e289436d36844da 13-Apr-2009 Dan Gohman <gohman@apple.com> Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.
This will be used to replace things like X86's MOV32to32_.

Enhance ScheduleDAGSDNodesEmit to be more flexible and robust
in the presense of subregister superclasses and subclasses. It
can now cope with the definition of a virtual register being in
a subclass of a use.

Re-introduce the code for recording register superreg classes and
subreg classes. This is needed because when subreg extracts and
inserts get coalesced away, the virtual registers are left in
the correct subclass.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3ca15c989ca0e09085648771db368d8c94ee1f19 10-Apr-2009 Owen Anderson <resistor@mac.com> Give register alias checking the hash table treatment too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7d770be047059d624f37c6fb1e5b1d0f2b4961b3 09-Apr-2009 Owen Anderson <resistor@mac.com> Convert TargetRegisterInfo's super-register checking to use a pre-computed hash table just like subregister checking does.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
41c90738e9e7e2111fbc31944b5ce2676830f267 03-Apr-2009 Chris Lattner <sabre@nondot.org> "This adds a getName() method to TargetRegisterClass, just like in TargetRegisterInfo.
This makes debugging register classes a bit easier."

Patch by Jakob Stoklund Olesen!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
536ab130ec95cbb7bf30530251dafa7dfecc8471 22-Jan-2009 Evan Cheng <evan.cheng@apple.com> Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
63f97201dc9dcebbe84d1b73113166c64212b4b8 17-Oct-2008 Dan Gohman <gohman@apple.com> Fun x86 encoding tricks: when adding an immediate value of 128,
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.

A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.

To support this, teach tablegen how to handle 64-bit constants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
84a8be3baf8ee5a43ea854e4ea7c3db840e7e285 11-Sep-2008 Evan Cheng <evan.cheng@apple.com> Indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56107 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
dd595c5998214c6ee07ed46f5db551b2abbfbbb3 11-Sep-2008 Evan Cheng <evan.cheng@apple.com> Change getSubReg semantics. It now returns zero if the specified register doesn't have a subreg of the specified index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
eb3db1cec2feff9701bf631423a691f138a367ce 08-Sep-2008 Dan Gohman <gohman@apple.com> Fix typos in (generated) comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c93457053cfecb24105ee3800c8e53921b950d8f 26-Aug-2008 Cedric Venet <cedric.venet@laposte.net> - small bug corrected: incorrect iterator type.
- fix to please VS: add a return after an assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
073ff02e0dce082e453e242cebd4fec7cd952b9d 26-Aug-2008 Chris Lattner <sabre@nondot.org> stabilize more printing, this doesn't cause a problem
in the example attached to PR2590, but is a problem in general.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
943c0e6fba6d1c4ba9f719639909e224f31e81f1 26-Aug-2008 Chris Lattner <sabre@nondot.org> stablize SubRegsSet printing, part of PR2590


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55360 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
690d80eefeb522c8697ef39d9e6d19b0be276f0e 26-Aug-2008 Chris Lattner <sabre@nondot.org> Stabilize 'getDwarfRegNumFull' output to not depend on random memory
orders, part of PR2590


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
22ae99908258dd5631fde7128a94c418ed08eae5 14-Aug-2008 Owen Anderson <resistor@mac.com> Speed up addRegisterDead by adding more fast checks before performing the expensive
subregister query, and by increasing the size of the subregister hashtable so
that there are fewer collisions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b7c3e867a5e05031ad730ae441b8602801f0f09e 08-Jul-2008 Evan Cheng <evan.cheng@apple.com> TargetRegisterDesc::Name field is the same as the abstract register name. There is no need for targets to specify register names in addition to their AsmName's.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53207 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
605041e5a81fbb18769b0613dcd14e0cff32b5ee 01-Jul-2008 Owen Anderson <resistor@mac.com> Make the subregister hashtable output more readable by wrapping the lines,
and mark it const along with the associated changes to TargetRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b43f7e05ffbc4ff0bb1211e1d47c97b81cc806d8 01-Jul-2008 Owen Anderson <resistor@mac.com> Use delete[] instead of free on an array created with new[].


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
57ce0319b7eb4418aac910d9a094e57d983a64d2 01-Jul-2008 Owen Anderson <resistor@mac.com> Implement suggestions from Chris:
- Use a more accurate heuristic for the size of the hashtable.
- Use bitwise and instead of modulo since the size is a power of two.
- Use new[] instead of malloc().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f4f9c4f1cf4d497c63e40e6c7ef545c8c716a5ce 01-Jul-2008 Owen Anderson <resistor@mac.com> Replace the dynamically computed std::set lookup method for subregisters with a hashtable-based
version that is computed by tblgen at the time LLVM is compiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2036835346ddf983d66b49505bd52db1d3f8b49d 30-Jun-2008 Evan Cheng <evan.cheng@apple.com> Eliminate TargetRegisterDesc::ImmSubRegs. It's no longer in use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b5dae003252d8e650a32bfdf33cba5aed8e41e40 26-Jun-2008 Dale Johannesen <dalej@apple.com> Fixes the last x86-64 test failure in compat.exp:
<16 x float> is 64-byte aligned (for some reason),
which gets us into the stack realignment code. The
computation changing FP-relative offsets to SP-relative
was broken, assiging a spill temp to a location
also used for parameter passing. This
fixes it by rounding up the stack frame to a multiple
of the largest alignment (I concluded it wasn't fixable
without doing this, but I'm not very sure.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb 06-Jun-2008 Duncan Sands <baldrick@free.fr> Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
cc51c3195374645b18918458bac02e85b8c27db6 15-Apr-2008 Chuck Rose III <cfr@adobe.com> VisualStudio project files updated. #include <algorithm> added to make VisualStudio happy. Also had to undefine setjmp because of #include <csetjmp> turning setjmp into _setjmp in VisualStudio.

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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
8102703d708e5d399926c6ba71ffa49bbd31fc8a 15-Apr-2008 Evan Cheng <evan.cheng@apple.com> Sort sub-registers and super-registers lists according to super-sub register relations. e.g. X86::RAX sub-register list is EAX, AX, AL, AH (order of last two are not guaranteed).


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
950a4c40b823cd4f09dc71be635229246dfd6cac 25-Mar-2008 Dan Gohman <gohman@apple.com> Add explicit keywords.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ca796402be8b4df9b359e934c7ea8e283a2e8b03 11-Mar-2008 Chris Lattner <sabre@nondot.org> emit an ID # for each regclass ID. Chris doesn't like to have to count.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e6d088acc90e422451e098555d383d4d65b6ce6b 26-Feb-2008 Bill Wendling <isanbard@gmail.com> Rename PrintableName to Name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
74ab84c31ef64538a1b56e1f282e49303412ad17 26-Feb-2008 Bill Wendling <isanbard@gmail.com> Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
181eb737b28628adc4376b973610a02039385026 24-Feb-2008 Bill Wendling <isanbard@gmail.com> Some platforms use the same name for 32-bit and 64-bit registers (like
%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6f0d024a534af18d9e60b3ea757376cd8a3a980e 10-Feb-2008 Dan Gohman <gohman@apple.com> Rename MRegisterInfo to TargetRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6cefb77a7073057fecd721ae141140d75ce76512 05-Jan-2008 Chris Lattner <sabre@nondot.org> change getQualifiedName to be a global function.
Split the pattern parsing code out from the dag isel emitter into it's own file.

No functionality change.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3060910e290949a9ac5eda8726d030790c4d60ff 29-Dec-2007 Chris Lattner <sabre@nondot.org> remove attributions from utils.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b97aec663b1591e71c9ddee6dbb327d1b827eda5 13-Nov-2007 Dale Johannesen <dalej@apple.com> Add parameter to getDwarfRegNum to permit targets
to use different mappings for EH and debug info;
no functional change yet.
Fix warning in X86CodeEmitter.



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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
e7e113361ea550afbb8bebcdc1e736c5d4833f8c 12-Nov-2007 Owen Anderson <resistor@mac.com> Fix on 64-bit machines.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f191c80cd79ee35e47b5a4feed98d687782dfe85 11-Nov-2007 Anton Korobeynikov <asl@math.spbu.ru> Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
483ec21d90295c146b5555ed66c16860bcfff942 07-Nov-2007 Dale Johannesen <dalej@apple.com> Interchange Dwarf numbers of ESP and EBP on x86 Darwin.
Much improvement in exception handling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a3ca3149f2b59c512c50aab330b5a0d8efddeffa 19-Sep-2007 Evan Cheng <evan.cheng@apple.com> Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value
between two registers in the specific class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6994040a952e5fb27605eb3cf29ed86c4e59cf62 04-Aug-2007 Chandler Carruth <chandlerc@gmail.com> This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future.

This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
936baaa5aeddb78ff41b1f655101b4d88c47473b 27-Jul-2007 Chuck Rose III <cfr@adobe.com> VStudio compiler errors and placing Function*->ExFunc map under ManagedStatic control.

This commit fixes two things. One is a pair of VStudio compiler errors stemming from variables
which defined within the for loop statement and also within the body of the for loop. I fixed these
by renaming one of the two variables. Additionally, I've made the Function*->ExFunc map in
ExternalFunctions.cpp a ManagedStatic object, so that cleanup will be done on llvm_shutdown. In repeated
uses of the interpreter, where the same Function* address may get used for completely differnet functions,
this was causing a crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
1367fd09cb021bae61e7dd2ee208f76574c8e789 26-Jul-2007 Christopher Lamb <christopher.lamb@gmail.com> Have register info provide the inverse mapping of register->superregisters. PR1350


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
5e4f292e53dc0a94b7f12218935bce55c780653c 27-Jun-2007 Evan Cheng <evan.cheng@apple.com> One additional field in TargetRegisterDesc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c4f2fe06946b9037ce82eca309d9f2c631050cee 26-Jun-2007 Evan Cheng <evan.cheng@apple.com> Add immediate sub-registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a321125e8b7e50d427d86b8053de2e6793b5df5b 14-Jun-2007 Christopher Lamb <christopher.lamb@gmail.com> Add support to tablegen for specifying subregister classes on a per register class basis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
851879c4cf1fc1f97be704a0459fb0ca5f327a44 05-Jun-2007 Bill Wendling <isanbard@gmail.com> Patches by Chuck Rose to unbreak V Studio builds.

Thanks Chuck!


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b9daee9ece898ff5bf8cf354fe2286ad44a357e8 04-Jun-2007 Dan Gohman <gohman@apple.com> Remove the operator<< for MVT::ValueType in preparation for MVT::ValueType
being changed from an enum to an integer type, which can't have a custom
operator<< overload.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37412 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6f7c8ffd9a92bdd625c5bc316187a49c0b1d41d6 01-May-2007 Nate Begeman <natebegeman@mac.com> A bit of feedback from Chris that I missed; error rather than asserting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7bf1c272ab27297a7bbab329de3f17ddb26e02a3 01-May-2007 Nate Begeman <natebegeman@mac.com> llvm bug #1350, parts 1, 2, and 3.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4fc4fab856f9616bb4f42bd658d5c8de89751628 21-Apr-2007 Evan Cheng <evan.cheng@apple.com> Bug fix; add super-registers sets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3cafbf7e5fa13b303cc387a058a511ce517b5bd5 20-Apr-2007 Evan Cheng <evan.cheng@apple.com> Add sub-registers sets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
114e5dd464f32e4275e5f0a28aa1586e463d6bbb 26-Feb-2007 Chris Lattner <sabre@nondot.org> emit an enum value for the # of target registers.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 07-Dec-2006 Bill Wendling <isanbard@gmail.com> What should be the last unnecessary <iostream>s in the library.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
60f09928a0d22d5927ff0a40fe9163cf1ba1014a 21-Jul-2006 Jim Laskey <jlaskey@mac.com> Use an enumeration to eliminate data relocations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3b0c0148ed9ec752b240dbea767ad4a9f0a682ca 19-Jul-2006 Evan Cheng <evan.cheng@apple.com> Make sub- and super- register classes const.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6f6602ce4268c60b5d602b7a3565cca4c6330811 19-Jul-2006 Evan Cheng <evan.cheng@apple.com> Make sub- super- reg-class tables static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d7c2c86239dd543906c363e45e18766223d14c6e 15-Jun-2006 Evan Cheng <evan.cheng@apple.com> Allow more use of iPTR in patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d74ea2bbd8bb630331f35ead42d385249bd42af8 24-May-2006 Chris Lattner <sabre@nondot.org> Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
764811f1452808ff8a6d84f4ec2637355356e22e 18-May-2006 Evan Cheng <evan.cheng@apple.com> Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2ca0efd71a5a25c1f3fa8b30dc5459fdaf8cd2a9 11-May-2006 Evan Cheng <evan.cheng@apple.com> Also add super- register classes info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
8d58e6a9be0ced7ad260449e882c5d2dcb5f4990 09-May-2006 Evan Cheng <evan.cheng@apple.com> Add sub-register class information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
47622e37215429c20d8278ff57496d840811cc13 24-Mar-2006 Jim Laskey <jlaskey@mac.com> Add dwarf register numbering to register data.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
12f75782141983c16e435a11dd724dfa32ed8ddd 27-Dec-2005 Duraid Madina <duraid@octopus.com.au> This gets most of the backends building with HP HappyC++.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
6510b22cec7de4f0acc9965ec24c3668a6a8a87e 01-Dec-2005 Nate Begeman <natebegeman@mac.com> Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
366080c5e6b4b8e1f07829a2489cc5d21f51bf3b 29-Oct-2005 Chris Lattner <sabre@nondot.org> Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4b2e5a680f2f6b7b3a43df1a4703ed0ff5ba07d5 02-Oct-2005 Chris Lattner <sabre@nondot.org> Emit the value type for each register class.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0f21fd5204a2627c613340269e2e39e2c8cca659 30-Sep-2005 Chris Lattner <sabre@nondot.org> Rename MRegisterDesc -> TargetRegisterDesc for consistency


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
22842105dec6ab35dc37a4901b2d791150da446b 30-Sep-2005 Chris Lattner <sabre@nondot.org> remove some more initializers


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2f02ed9a1f952e534807fae3c51de92ca0eacfd3 30-Sep-2005 Chris Lattner <sabre@nondot.org> trim down the target info structs now that we have a preferred spill register class for each callee save register


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
4794797f1213c4096a6f5ff2b6841dd5866b22ba 30-Sep-2005 Chris Lattner <sabre@nondot.org> Compute a preferred spill register class for each callee-save register


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0d0b73e9f83c45c7cba28d57564567025c7ee014 30-Sep-2005 Chris Lattner <sabre@nondot.org> allow regs to be in multiple reg classes


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
60200e5d32f63b4e54575f5cbec348f3f9baeb5d 19-Aug-2005 Chris Lattner <sabre@nondot.org> Expose the derived register classes to the public header, allowing them
to be accessed.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
ac46893e246748876d1155bb0c9e8892e52acab7 19-Aug-2005 Chris Lattner <sabre@nondot.org> Split register class "Methods" into MethodProtos and MethodBodies


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
42de581b2f28985ec0c8fcbb26ab4d78c684247f 19-Aug-2005 Chris Lattner <sabre@nondot.org> Refactor to use Target.getRegisterClasses consistently, which provides
anonymous regclass definition renaming.

Change the generated code to emit register classes as properly namespace
qualified entities like everything else.

expose the actual class definition as an object, though this isn't quite
usable yet.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3da94aec4d429b2ba0f65fa040c33650cade196b 22-Apr-2005 Misha Brukman <brukman+llvm@gmail.com> Remove trailing whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b228657acc4afbdc74dc523e9f465d08935f9e8d 14-Sep-2004 Chris Lattner <sabre@nondot.org> Revamp the Register class, and allow the use of the RegisterGroup class to
specify aliases directly in register definitions.

Patch contributed by Jason Eckhardt!


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
551ccae044b0ff658fe629dd67edd5ffe75d10e8 02-Sep-2004 Reid Spencer <rspencer@reidspencer.com> Changes For Bug 352
Move include/Config and include/Support into include/llvm/Config,
include/llvm/ADT and include/llvm/Support. From here on out, all LLVM
public header files must be under include/llvm/.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
98df506e712d51bf74ae526e2b6304bef9025a7e 21-Aug-2004 Chris Lattner <sabre@nondot.org> Make alignment be in bits, just like size is


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
987b5cc5578410c3bbc6077c2e2aa5df33cd3447 21-Aug-2004 Chris Lattner <sabre@nondot.org> Infer the spillsize/alignment of a register based on the register classes
it is embedded into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
57677755055be6c95289fbe7a2a1edd88ac39818 21-Aug-2004 Chris Lattner <sabre@nondot.org> Support "Methods" in register classes in CodgeGenRegisterClass


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
056afeface2ac98664ed8fa4799b46178a4a6fe3 21-Aug-2004 Chris Lattner <sabre@nondot.org> Start parsing register classes into a more structured form


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2c38413b3f5420f45f2f8220b21862246d446dd0 17-Aug-2004 Chris Lattner <sabre@nondot.org> Do not #include files into the llvm namespace


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
26693113201f4c9d441678e50d96f38d3288798e 16-Aug-2004 Chris Lattner <sabre@nondot.org> Use CodeGenRegister class to make reading in of register information more
systematic.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
59b92cec35af49e82e834cbef5384e170e410cbf 16-Aug-2004 Chris Lattner <sabre@nondot.org> Remove awareness of isDummyClass


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
803a5f6ecb1823280f80e3c4459aa58627d0484c 01-Aug-2004 Chris Lattner <sabre@nondot.org> Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h)


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
2082ebe8b3a5db302748828ab4f79a36d239c1d9 01-Aug-2004 Chris Lattner <sabre@nondot.org> Finegrainify namespacification


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
d0fde30ce850b78371fd1386338350591f9ff494 11-Nov-2003 Brian Gaeke <gaeke@uiuc.edu> Put all LLVM code into the llvm namespace, as per bug 109.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
01d45827a1e512f3b19ba857772bf02baa3c0c4e 20-Oct-2003 John Criswell <criswell@uiuc.edu> Added LLVM copyright header.


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
73ff5120eb8b8c0ccbfed8a17f1024c67a75f319 08-Oct-2003 Alkis Evlogimenos <alkis@evlogimenos.com> Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
for (int i = 0; AS[i]; ++i) {
// use AS[i]
}
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
// use *AS
}


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c7df109b6c4f7cbf8cc4dbee90291d4e452c7d56 15-Aug-2003 Chris Lattner <sabre@nondot.org> Ignore dummy register classes


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a40e5ad69f5ab5da1671a5e84e75a60202ad03d5 07-Aug-2003 Chris Lattner <sabre@nondot.org> Add and use a new method


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
7884b750c33b750177b3f22af75c874c97f728d8 07-Aug-2003 Chris Lattner <sabre@nondot.org> Start using the CodeGeneratorWrappers


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
38aa542f3679af5925315626a37e2d085954ce9f 06-Aug-2003 Chris Lattner <sabre@nondot.org> Export the register classes so that the instruction selector can get at them as needed


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0e5e49e6888c354ff95fc9e56d0881af78cb4269 06-Aug-2003 Chris Lattner <sabre@nondot.org> convert over to using TableGen backends


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
a8af7799dd4b9dda7016f72b2e5f7b7d07780a8a 04-Aug-2003 Chris Lattner <sabre@nondot.org> Allow registers to specify a custom name


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
13c5b4cdc8b601bdb464bf31f316233fd02e1d49 03-Aug-2003 Chris Lattner <sabre@nondot.org> * Changes to allow lists of any type
* Reorganize Target class a bit
* Fix string out of range access bug


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
0bb66fc30e60d92d65dd6b887aed38dd644c2eb6 03-Aug-2003 Chris Lattner <sabre@nondot.org> Make the register numbers line up more frequently


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
9fff8919eefa377936918eec763b392e59049353 03-Aug-2003 Chris Lattner <sabre@nondot.org> Finish the register info emitter


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
c7d58024f8bed33e0b3e795e51a62ec30248aff3 01-Aug-2003 Chris Lattner <sabre@nondot.org> add support for emitting register classes


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
54d156d33324b7715453993f21684915a28e310a 01-Aug-2003 Chris Lattner <sabre@nondot.org> Add the ability to emit register file enums


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp
3112326c88b7090f770c4ff8a1546ef84fd2e8bb 01-Aug-2003 Chris Lattner <sabre@nondot.org> Initial checkin of register info emitter


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/external/llvm/utils/TableGen/RegisterInfoEmitter.cpp