RegisterInfoEmitter.cpp revision 2ca0efd71a5a25c1f3fa8b30dc5459fdaf8cd2a9
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "RegisterInfoEmitter.h" 17#include "CodeGenTarget.h" 18#include "CodeGenRegisters.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/ADT/STLExtras.h" 22#include <set> 23using namespace llvm; 24 25// runEnums - Print out enum values for all of the registers. 26void RegisterInfoEmitter::runEnums(std::ostream &OS) { 27 CodeGenTarget Target; 28 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 29 30 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 31 32 EmitSourceFileHeader("Target Register Enum Values", OS); 33 OS << "namespace llvm {\n\n"; 34 35 if (!Namespace.empty()) 36 OS << "namespace " << Namespace << " {\n"; 37 OS << " enum {\n NoRegister,\n"; 38 39 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 40 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; 41 42 OS << " };\n"; 43 if (!Namespace.empty()) 44 OS << "}\n"; 45 OS << "} // End llvm namespace \n"; 46} 47 48void RegisterInfoEmitter::runHeader(std::ostream &OS) { 49 EmitSourceFileHeader("Register Information Header Fragment", OS); 50 CodeGenTarget Target; 51 const std::string &TargetName = Target.getName(); 52 std::string ClassName = TargetName + "GenRegisterInfo"; 53 54 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n"; 55 OS << "#include <string>\n\n"; 56 57 OS << "namespace llvm {\n\n"; 58 59 OS << "struct " << ClassName << " : public MRegisterInfo {\n" 60 << " " << ClassName 61 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 62 << " const unsigned* getCalleeSaveRegs() const;\n" 63 << " const TargetRegisterClass* const *getCalleeSaveRegClasses() const;\n" 64 << " int getDwarfRegNum(unsigned RegNum) const;\n" 65 << "};\n\n"; 66 67 const std::vector<CodeGenRegisterClass> &RegisterClasses = 68 Target.getRegisterClasses(); 69 70 if (!RegisterClasses.empty()) { 71 OS << "namespace " << RegisterClasses[0].Namespace 72 << " { // Register classes\n"; 73 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 74 const std::string &Name = RegisterClasses[i].getName(); 75 76 // Output the register class definition. 77 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 78 << " " << Name << "Class();\n" 79 << RegisterClasses[i].MethodProtos << " };\n"; 80 81 // Output the extern for the instance. 82 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 83 // Output the extern for the pointer to the instance (should remove). 84 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 85 << Name << "RegClass;\n"; 86 } 87 OS << "} // end of namespace " << TargetName << "\n\n"; 88 } 89 OS << "} // End llvm namespace \n"; 90} 91 92bool isSubRegisterClass(const CodeGenRegisterClass &RC, 93 std::set<Record*> &RegSet) { 94 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 95 Record *Reg = RC.Elements[i]; 96 if (!RegSet.count(Reg)) 97 return false; 98 } 99 return true; 100} 101 102// RegisterInfoEmitter::run - Main register file description emitter. 103// 104void RegisterInfoEmitter::run(std::ostream &OS) { 105 CodeGenTarget Target; 106 EmitSourceFileHeader("Register Information Source Fragment", OS); 107 108 OS << "namespace llvm {\n\n"; 109 110 // Start out by emitting each of the register classes... to do this, we build 111 // a set of registers which belong to a register class, this is to ensure that 112 // each register is only in a single register class. 113 // 114 const std::vector<CodeGenRegisterClass> &RegisterClasses = 115 Target.getRegisterClasses(); 116 117 // Loop over all of the register classes... emitting each one. 118 OS << "namespace { // Register classes...\n"; 119 120 // RegClassesBelongedTo - Keep track of which register classes each reg 121 // belongs to. 122 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo; 123 124 // Emit the register enum value arrays for each RegisterClass 125 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 126 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 127 128 // Give the register class a legal C name if it's anonymous. 129 std::string Name = RC.TheDef->getName(); 130 131 // Emit the register list now. 132 OS << " // " << Name << " Register Class...\n const unsigned " << Name 133 << "[] = {\n "; 134 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 135 Record *Reg = RC.Elements[i]; 136 OS << getQualifiedName(Reg) << ", "; 137 138 // Keep track of which regclasses this register is in. 139 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); 140 } 141 OS << "\n };\n\n"; 142 } 143 144 // Emit the ValueType arrays for each RegisterClass 145 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 146 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 147 148 // Give the register class a legal C name if it's anonymous. 149 std::string Name = RC.TheDef->getName() + "VTs"; 150 151 // Emit the register list now. 152 OS << " // " << Name 153 << " Register Class Value Types...\n const MVT::ValueType " << Name 154 << "[] = {\n "; 155 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 156 OS << "MVT::" << RC.VTs[i] << ", "; 157 OS << "MVT::Other\n };\n\n"; 158 } 159 OS << "} // end anonymous namespace\n\n"; 160 161 // Now that all of the structs have been emitted, emit the instances. 162 if (!RegisterClasses.empty()) { 163 OS << "namespace " << RegisterClasses[0].Namespace 164 << " { // Register class instances\n"; 165 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 166 OS << " " << RegisterClasses[i].getName() << "Class\t" 167 << RegisterClasses[i].getName() << "RegClass;\n"; 168 169 std::map<unsigned, std::set<unsigned> > SuperClassMap; 170 OS << "\n"; 171 // Emit the sub-classes array for each RegisterClass 172 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 173 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 174 175 // Give the register class a legal C name if it's anonymous. 176 std::string Name = RC.TheDef->getName(); 177 178 std::set<Record*> RegSet; 179 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 180 Record *Reg = RC.Elements[i]; 181 RegSet.insert(Reg); 182 } 183 184 OS << " // " << Name 185 << " Register Class sub-classes...\n const TargetRegisterClass* " 186 << Name << "Subclasses [] = {\n "; 187 188 bool Empty = true; 189 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 190 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 191 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || 192 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) 193 continue; 194 195 if (!Empty) OS << ", "; 196 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 197 Empty = false; 198 199 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 200 SuperClassMap.find(rc2); 201 if (SCMI == SuperClassMap.end()) { 202 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 203 SCMI = SuperClassMap.find(rc2); 204 } 205 SCMI->second.insert(rc); 206 } 207 208 OS << (!Empty ? ", " : "") << "NULL"; 209 OS << "\n };\n\n"; 210 } 211 212 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 213 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 214 215 // Give the register class a legal C name if it's anonymous. 216 std::string Name = RC.TheDef->getName(); 217 218 OS << " // " << Name 219 << " Register Class super-classes...\n const TargetRegisterClass* " 220 << Name << "Superclasses [] = {\n "; 221 222 bool Empty = true; 223 std::map<unsigned, std::set<unsigned> >::iterator I = 224 SuperClassMap.find(rc); 225 if (I != SuperClassMap.end()) { 226 for (std::set<unsigned>::iterator II = I->second.begin(), 227 EE = I->second.end(); II != EE; ++II) { 228 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 229 if (!Empty) OS << ", "; 230 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 231 Empty = false; 232 } 233 } 234 235 OS << (!Empty ? ", " : "") << "NULL"; 236 OS << "\n };\n\n"; 237 } 238 239 240 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 241 const CodeGenRegisterClass &RC = RegisterClasses[i]; 242 OS << RC.MethodBodies << "\n"; 243 OS << RC.getName() << "Class::" << RC.getName() 244 << "Class() : TargetRegisterClass(" 245 << RC.getName() + "VTs" << ", " 246 << RC.getName() + "Subclasses" << ", " 247 << RC.getName() + "Superclasses" << ", " 248 << RC.SpillSize/8 << ", " 249 << RC.SpillAlignment/8 << ", " << RC.getName() << ", " 250 << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; 251 } 252 253 OS << "}\n"; 254 } 255 256 OS << "\nnamespace {\n"; 257 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 258 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 259 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 260 << "RegClass,\n"; 261 OS << " };\n"; 262 263 // Emit register class aliases... 264 std::map<Record*, std::set<Record*> > RegisterAliases; 265 const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 266 267 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 268 Record *R = Regs[i].TheDef; 269 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); 270 // Add information that R aliases all of the elements in the list... and 271 // that everything in the list aliases R. 272 for (unsigned j = 0, e = LI.size(); j != e; ++j) { 273 Record *Reg = LI[j]; 274 if (RegisterAliases[R].count(Reg)) 275 std::cerr << "Warning: register alias between " << getQualifiedName(R) 276 << " and " << getQualifiedName(Reg) 277 << " specified multiple times!\n"; 278 RegisterAliases[R].insert(Reg); 279 280 if (RegisterAliases[Reg].count(R)) 281 std::cerr << "Warning: register alias between " << getQualifiedName(R) 282 << " and " << getQualifiedName(Reg) 283 << " specified multiple times!\n"; 284 RegisterAliases[Reg].insert(R); 285 } 286 } 287 288 if (!RegisterAliases.empty()) 289 OS << "\n\n // Register Alias Sets...\n"; 290 291 // Emit the empty alias list 292 OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; 293 // Loop over all of the registers which have aliases, emitting the alias list 294 // to memory. 295 for (std::map<Record*, std::set<Record*> >::iterator 296 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { 297 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; 298 for (std::set<Record*>::iterator ASI = I->second.begin(), 299 E = I->second.end(); ASI != E; ++ASI) 300 OS << getQualifiedName(*ASI) << ", "; 301 OS << "0 };\n"; 302 } 303 304 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 305 OS << " { \"NOREG\",\t0 },\n"; 306 307 308 // Now that register alias sets have been emitted, emit the register 309 // descriptors now. 310 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 311 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 312 const CodeGenRegister &Reg = Registers[i]; 313 OS << " { \""; 314 if (!Reg.TheDef->getValueAsString("Name").empty()) 315 OS << Reg.TheDef->getValueAsString("Name"); 316 else 317 OS << Reg.getName(); 318 OS << "\",\t"; 319 if (RegisterAliases.count(Reg.TheDef)) 320 OS << Reg.getName() << "_AliasSet },\n"; 321 else 322 OS << "Empty_AliasSet },\n"; 323 } 324 OS << " };\n"; // End of register descriptors... 325 OS << "}\n\n"; // End of anonymous namespace... 326 327 std::string ClassName = Target.getName() + "GenRegisterInfo"; 328 329 // Emit the constructor of the class... 330 OS << ClassName << "::" << ClassName 331 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 332 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1 333 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " 334 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; 335 336 // Emit the getCalleeSaveRegs method. 337 OS << "const unsigned* " << ClassName << "::getCalleeSaveRegs() const {\n" 338 << " static const unsigned CalleeSaveRegs[] = {\n "; 339 340 const std::vector<Record*> &CSR = Target.getCalleeSavedRegisters(); 341 for (unsigned i = 0, e = CSR.size(); i != e; ++i) 342 OS << getQualifiedName(CSR[i]) << ", "; 343 OS << " 0\n };\n return CalleeSaveRegs;\n}\n\n"; 344 345 // Emit information about the callee saved register classes. 346 OS << "const TargetRegisterClass* const*\n" << ClassName 347 << "::getCalleeSaveRegClasses() const {\n" 348 << " static const TargetRegisterClass * const " 349 << "CalleeSaveRegClasses[] = {\n "; 350 351 for (unsigned i = 0, e = CSR.size(); i != e; ++i) { 352 Record *R = CSR[i]; 353 std::multimap<Record*, const CodeGenRegisterClass*>::iterator I, E; 354 tie(I, E) = RegClassesBelongedTo.equal_range(R); 355 if (I == E) 356 throw "Callee saved register '" + R->getName() + 357 "' must belong to a register class for spilling.\n"; 358 const CodeGenRegisterClass *RC = (I++)->second; 359 for (; I != E; ++I) 360 if (RC->SpillSize < I->second->SpillSize) 361 RC = I->second; 362 OS << "&" << getQualifiedName(RC->TheDef) << "RegClass, "; 363 } 364 OS << " 0\n };\n return CalleeSaveRegClasses;\n}\n\n"; 365 366 // Emit information about the dwarf register numbers. 367 OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n"; 368 OS << " static const int DwarfRegNums[] = { -1, // NoRegister"; 369 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 370 if (!(i % 16)) OS << "\n "; 371 const CodeGenRegister &Reg = Registers[i]; 372 int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber"); 373 OS << DwarfRegNum; 374 if ((i + 1) != e) OS << ", "; 375 } 376 OS << "\n };\n"; 377 OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n"; 378 OS << " \"RegNum exceeds number of registers\");\n"; 379 OS << " return DwarfRegNums[RegNum];\n"; 380 OS << "}\n\n"; 381 382 OS << "} // End llvm namespace \n"; 383} 384