RegisterInfoEmitter.cpp revision 6fea31e7300fe012b0b2984d6bc0338d02b054d3 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "llvm/TableGen/Record.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/Support/Format.h"
24#include <algorithm>
25#include <set>
26using namespace llvm;
27
28// runEnums - Print out enum values for all of the registers.
29void
30RegisterInfoEmitter::runEnums(raw_ostream &OS,
31                              CodeGenTarget &Target, CodeGenRegBank &Bank) {
32  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33
34  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35
36  EmitSourceFileHeader("Target Register Enum Values", OS);
37
38  OS << "\n#ifdef GET_REGINFO_ENUM\n";
39  OS << "#undef GET_REGINFO_ENUM\n";
40
41  OS << "namespace llvm {\n\n";
42
43  OS << "class MCRegisterClass;\n"
44     << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
45
46  if (!Namespace.empty())
47    OS << "namespace " << Namespace << " {\n";
48  OS << "enum {\n  NoRegister,\n";
49
50  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
51    OS << "  " << Registers[i]->getName() << " = " <<
52      Registers[i]->EnumValue << ",\n";
53  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
54         "Register enum value mismatch!");
55  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
56  OS << "};\n";
57  if (!Namespace.empty())
58    OS << "}\n";
59
60  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
61  if (!RegisterClasses.empty()) {
62    OS << "\n// Register classes\n";
63    if (!Namespace.empty())
64      OS << "namespace " << Namespace << " {\n";
65    OS << "enum {\n";
66    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
67      if (i) OS << ",\n";
68      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
69      OS << " = " << i;
70    }
71    OS << "\n  };\n";
72    if (!Namespace.empty())
73      OS << "}\n";
74  }
75
76  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
77  // If the only definition is the default NoRegAltName, we don't need to
78  // emit anything.
79  if (RegAltNameIndices.size() > 1) {
80    OS << "\n// Register alternate name indices\n";
81    if (!Namespace.empty())
82      OS << "namespace " << Namespace << " {\n";
83    OS << "enum {\n";
84    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
85      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
86    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
87    OS << "};\n";
88    if (!Namespace.empty())
89      OS << "}\n";
90  }
91
92
93  OS << "} // End llvm namespace \n";
94  OS << "#endif // GET_REGINFO_ENUM\n\n";
95}
96
97void
98RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
99                                    const std::vector<CodeGenRegister*> &Regs,
100                                    bool isCtor) {
101
102  // Collect all information about dwarf register numbers
103  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
104  DwarfRegNumsMapTy DwarfRegNums;
105
106  // First, just pull all provided information to the map
107  unsigned maxLength = 0;
108  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109    Record *Reg = Regs[i]->TheDef;
110    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
111    maxLength = std::max((size_t)maxLength, RegNums.size());
112    if (DwarfRegNums.count(Reg))
113      errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
114             << "specified multiple times\n";
115    DwarfRegNums[Reg] = RegNums;
116  }
117
118  if (!maxLength)
119    return;
120
121  // Now we know maximal length of number list. Append -1's, where needed
122  for (DwarfRegNumsMapTy::iterator
123       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
124    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
125      I->second.push_back(-1);
126
127  // Emit reverse information about the dwarf register numbers.
128  for (unsigned j = 0; j < 2; ++j) {
129    OS << "  switch (";
130    if (j == 0)
131      OS << "DwarfFlavour";
132    else
133      OS << "EHFlavour";
134    OS << ") {\n"
135     << "  default:\n"
136     << "    assert(0 && \"Unknown DWARF flavour\");\n"
137     << "    break;\n";
138
139    for (unsigned i = 0, e = maxLength; i != e; ++i) {
140      OS << "  case " << i << ":\n";
141      for (DwarfRegNumsMapTy::iterator
142             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
143        int DwarfRegNo = I->second[i];
144        if (DwarfRegNo < 0)
145          continue;
146        OS << "    ";
147        if (!isCtor)
148          OS << "RI->";
149        OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
150           << getQualifiedName(I->first) << ", ";
151        if (j == 0)
152          OS << "false";
153        else
154          OS << "true";
155        OS << " );\n";
156      }
157      OS << "    break;\n";
158    }
159    OS << "  }\n";
160  }
161
162  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163    Record *Reg = Regs[i]->TheDef;
164    const RecordVal *V = Reg->getValue("DwarfAlias");
165    if (!V || !V->getValue())
166      continue;
167
168    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
169    Record *Alias = DI->getDef();
170    DwarfRegNums[Reg] = DwarfRegNums[Alias];
171  }
172
173  // Emit information about the dwarf register numbers.
174  for (unsigned j = 0; j < 2; ++j) {
175    OS << "  switch (";
176    if (j == 0)
177      OS << "DwarfFlavour";
178    else
179      OS << "EHFlavour";
180    OS << ") {\n"
181       << "  default:\n"
182       << "    assert(0 && \"Unknown DWARF flavour\");\n"
183       << "    break;\n";
184
185    for (unsigned i = 0, e = maxLength; i != e; ++i) {
186      OS << "  case " << i << ":\n";
187      // Sort by name to get a stable order.
188      for (DwarfRegNumsMapTy::iterator
189             I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
190        int RegNo = I->second[i];
191        OS << "    ";
192        if (!isCtor)
193          OS << "RI->";
194        OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
195           <<  RegNo << ", ";
196        if (j == 0)
197          OS << "false";
198        else
199          OS << "true";
200        OS << " );\n";
201      }
202      OS << "    break;\n";
203    }
204    OS << "  }\n";
205  }
206}
207
208// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
209// Width is the number of bits per hex number.
210static void printBitVectorAsHex(raw_ostream &OS,
211                                const BitVector &Bits,
212                                unsigned Width) {
213  assert(Width <= 32 && "Width too large");
214  unsigned Digits = (Width + 3) / 4;
215  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
216    unsigned Value = 0;
217    for (unsigned j = 0; j != Width && i + j != e; ++j)
218      Value |= Bits.test(i + j) << j;
219    OS << format("0x%0*x, ", Digits, Value);
220  }
221}
222
223// Helper to emit a set of bits into a constant byte array.
224class BitVectorEmitter {
225  BitVector Values;
226public:
227  void add(unsigned v) {
228    if (v >= Values.size())
229      Values.resize(((v/8)+1)*8); // Round up to the next byte.
230    Values[v] = true;
231  }
232
233  void print(raw_ostream &OS) {
234    printBitVectorAsHex(OS, Values, 8);
235  }
236};
237
238//
239// runMCDesc - Print out MC register descriptions.
240//
241void
242RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
243                               CodeGenRegBank &RegBank) {
244  EmitSourceFileHeader("MC Register Information", OS);
245
246  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
247  OS << "#undef GET_REGINFO_MC_DESC\n";
248
249  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
250  RegBank.computeOverlaps(Overlaps);
251
252  OS << "namespace llvm {\n\n";
253
254  const std::string &TargetName = Target.getName();
255  std::string ClassName = TargetName + "GenMCRegisterInfo";
256  OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
257     << "  explicit " << ClassName << "(const MCRegisterDesc *D);\n";
258  OS << "};\n";
259
260  OS << "\nnamespace {\n";
261
262  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
263
264  // Emit an overlap list for all registers.
265  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
266    const CodeGenRegister *Reg = Regs[i];
267    const CodeGenRegister::Set &O = Overlaps[Reg];
268    // Move Reg to the front so TRI::getAliasSet can share the list.
269    OS << "  const unsigned " << Reg->getName() << "_Overlaps[] = { "
270       << getQualifiedName(Reg->TheDef) << ", ";
271    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
272         I != E; ++I)
273      if (*I != Reg)
274        OS << getQualifiedName((*I)->TheDef) << ", ";
275    OS << "0 };\n";
276  }
277
278  // Emit the empty sub-registers list
279  OS << "  const unsigned Empty_SubRegsSet[] = { 0 };\n";
280  // Loop over all of the registers which have sub-registers, emitting the
281  // sub-registers list to memory.
282  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283    const CodeGenRegister &Reg = *Regs[i];
284    if (Reg.getSubRegs().empty())
285     continue;
286    // getSubRegs() orders by SubRegIndex. We want a topological order.
287    SetVector<CodeGenRegister*> SR;
288    Reg.addSubRegsPreOrder(SR);
289    OS << "  const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
290    for (unsigned j = 0, je = SR.size(); j != je; ++j)
291      OS << getQualifiedName(SR[j]->TheDef) << ", ";
292    OS << "0 };\n";
293  }
294
295  // Emit the empty super-registers list
296  OS << "  const unsigned Empty_SuperRegsSet[] = { 0 };\n";
297  // Loop over all of the registers which have super-registers, emitting the
298  // super-registers list to memory.
299  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
300    const CodeGenRegister &Reg = *Regs[i];
301    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
302    if (SR.empty())
303      continue;
304    OS << "  const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
305    for (unsigned j = 0, je = SR.size(); j != je; ++j)
306      OS << getQualifiedName(SR[j]->TheDef) << ", ";
307    OS << "0 };\n";
308  }
309  OS << "}\n";       // End of anonymous namespace...
310
311  OS << "\nMCRegisterDesc " << TargetName
312     << "RegDesc[] = { // Descriptors\n";
313  OS << "  { \"NOREG\",\t0,\t0,\t0 },\n";
314
315  // Now that register alias and sub-registers sets have been emitted, emit the
316  // register descriptors now.
317  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
318    const CodeGenRegister &Reg = *Regs[i];
319    OS << "  { \"";
320    OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
321    if (!Reg.getSubRegs().empty())
322      OS << Reg.getName() << "_SubRegsSet,\t";
323    else
324      OS << "Empty_SubRegsSet,\t";
325    if (!Reg.getSuperRegs().empty())
326      OS << Reg.getName() << "_SuperRegsSet";
327    else
328      OS << "Empty_SuperRegsSet";
329    OS << " },\n";
330  }
331  OS << "};\n\n";      // End of register descriptors...
332
333  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
334
335  // Loop over all of the register classes... emitting each one.
336  OS << "namespace {     // Register classes...\n";
337
338  // Emit the register enum value arrays for each RegisterClass
339  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341    ArrayRef<Record*> Order = RC.getOrder();
342
343    // Give the register class a legal C name if it's anonymous.
344    std::string Name = RC.getName();
345
346    // Emit the register list now.
347    OS << "  // " << Name << " Register Class...\n"
348       << "  static const unsigned " << Name
349       << "[] = {\n    ";
350    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
351      Record *Reg = Order[i];
352      OS << getQualifiedName(Reg) << ", ";
353    }
354    OS << "\n  };\n\n";
355
356    OS << "  // " << Name << " Bit set.\n"
357       << "  static const unsigned char " << Name
358       << "Bits[] = {\n    ";
359    BitVectorEmitter BVE;
360    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
361      Record *Reg = Order[i];
362      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
363    }
364    BVE.print(OS);
365    OS << "\n  };\n\n";
366
367  }
368  OS << "}\n\n";
369
370  OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
371
372  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
373    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
374    OS << "  MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
375       << '\"' << RC.getName() << "\", "
376       << RC.SpillSize/8 << ", "
377       << RC.SpillAlignment/8 << ", "
378       << RC.CopyCost << ", "
379       << RC.Allocatable << ", "
380       << RC.getName() << ", " << RC.getName() << " + "
381       << RC.getOrder().size() << ", "
382       << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
383       << "),\n";
384  }
385
386  OS << "};\n\n";
387
388  // MCRegisterInfo initialization routine.
389  OS << "static inline void Init" << TargetName
390     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
391     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
392  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
393     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
394     << RegisterClasses.size() << ");\n\n";
395
396  EmitRegMapping(OS, Regs, false);
397
398  OS << "}\n\n";
399
400
401  OS << "} // End llvm namespace \n";
402  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
403}
404
405void
406RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
407                                     CodeGenRegBank &RegBank) {
408  EmitSourceFileHeader("Register Information Header Fragment", OS);
409
410  OS << "\n#ifdef GET_REGINFO_HEADER\n";
411  OS << "#undef GET_REGINFO_HEADER\n";
412
413  const std::string &TargetName = Target.getName();
414  std::string ClassName = TargetName + "GenRegisterInfo";
415
416  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
417  OS << "#include <string>\n\n";
418
419  OS << "namespace llvm {\n\n";
420
421  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
422     << "  explicit " << ClassName
423     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
424     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
425     << "     { return false; }\n"
426     << "  unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
427     << "  unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
428     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
429     << "};\n\n";
430
431  const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
432  if (!SubRegIndices.empty()) {
433    OS << "\n// Subregister indices\n";
434    std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
435    if (!Namespace.empty())
436      OS << "namespace " << Namespace << " {\n";
437    OS << "enum {\n  NoSubRegister,\n";
438    for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
439      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
440    OS << "  NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
441    OS << "};\n";
442    if (!Namespace.empty())
443      OS << "}\n";
444  }
445
446  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
447
448  if (!RegisterClasses.empty()) {
449    OS << "namespace " << RegisterClasses[0]->Namespace
450       << " { // Register classes\n";
451
452    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
453      const CodeGenRegisterClass &RC = *RegisterClasses[i];
454      const std::string &Name = RC.getName();
455
456      // Output the register class definition.
457      OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
458         << "    " << Name << "Class();\n";
459      if (!RC.AltOrderSelect.empty())
460        OS << "    ArrayRef<unsigned> "
461              "getRawAllocationOrder(const MachineFunction&) const;\n";
462      OS << "  };\n";
463
464      // Output the extern for the instance.
465      OS << "  extern " << Name << "Class\t" << Name << "RegClass;\n";
466      // Output the extern for the pointer to the instance (should remove).
467      OS << "  static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
468         << Name << "RegClass;\n";
469    }
470    OS << "} // end of namespace " << TargetName << "\n\n";
471  }
472  OS << "} // End llvm namespace \n";
473  OS << "#endif // GET_REGINFO_HEADER\n\n";
474}
475
476//
477// runTargetDesc - Output the target register and register file descriptions.
478//
479void
480RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
481                                   CodeGenRegBank &RegBank){
482  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
483
484  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
485  OS << "#undef GET_REGINFO_TARGET_DESC\n";
486
487  OS << "namespace llvm {\n\n";
488
489  // Get access to MCRegisterClass data.
490  OS << "extern MCRegisterClass " << Target.getName()
491    << "MCRegisterClasses[];\n";
492
493  // Start out by emitting each of the register classes.
494  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
495
496  // Collect all registers belonging to any allocatable class.
497  std::set<Record*> AllocatableRegs;
498
499  // Collect allocatable registers.
500  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
501    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
502    ArrayRef<Record*> Order = RC.getOrder();
503
504    if (RC.Allocatable)
505      AllocatableRegs.insert(Order.begin(), Order.end());
506  }
507
508  OS << "namespace {     // Register classes...\n";
509
510  // Emit the ValueType arrays for each RegisterClass
511  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
512    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
513
514    // Give the register class a legal C name if it's anonymous.
515    std::string Name = RC.getName() + "VTs";
516
517    // Emit the register list now.
518    OS << "  // " << Name
519       << " Register Class Value Types...\n"
520       << "  static const EVT " << Name
521       << "[] = {\n    ";
522    for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
523      OS << getEnumName(RC.VTs[i]) << ", ";
524    OS << "MVT::Other\n  };\n\n";
525  }
526  OS << "}  // end anonymous namespace\n\n";
527
528  // Now that all of the structs have been emitted, emit the instances.
529  if (!RegisterClasses.empty()) {
530    OS << "namespace " << RegisterClasses[0]->Namespace
531       << " {   // Register class instances\n";
532    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
533      OS << "  " << RegisterClasses[i]->getName()  << "Class\t"
534         << RegisterClasses[i]->getName() << "RegClass;\n";
535
536    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
537
538    OS << "\n  static const TargetRegisterClass* const "
539      << "NullRegClasses[] = { NULL };\n\n";
540
541    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
542
543    if (NumSubRegIndices) {
544      // Emit the sub-register classes for each RegisterClass
545      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
546        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
547        std::vector<Record*> SRC(NumSubRegIndices);
548        for (DenseMap<Record*,Record*>::const_iterator
549             i = RC.SubRegClasses.begin(),
550             e = RC.SubRegClasses.end(); i != e; ++i) {
551          // Build SRC array.
552          unsigned idx = RegBank.getSubRegIndexNo(i->first);
553          SRC.at(idx-1) = i->second;
554
555          // Find the register class number of i->second for SuperRegClassMap.
556          const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
557          assert(RC2 && "Invalid register class in SubRegClasses");
558          SuperRegClassMap[RC2->EnumValue].insert(rc);
559        }
560
561        // Give the register class a legal C name if it's anonymous.
562        std::string Name = RC.getName();
563
564        OS << "  // " << Name
565           << " Sub-register Classes...\n"
566           << "  static const TargetRegisterClass* const "
567           << Name << "SubRegClasses[] = {\n    ";
568
569        for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
570          if (idx)
571            OS << ", ";
572          if (SRC[idx])
573            OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
574          else
575            OS << "0";
576        }
577        OS << "\n  };\n\n";
578      }
579
580      // Emit the super-register classes for each RegisterClass
581      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
582        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
583
584        // Give the register class a legal C name if it's anonymous.
585        std::string Name = RC.getName();
586
587        OS << "  // " << Name
588           << " Super-register Classes...\n"
589           << "  static const TargetRegisterClass* const "
590           << Name << "SuperRegClasses[] = {\n    ";
591
592        bool Empty = true;
593        std::map<unsigned, std::set<unsigned> >::iterator I =
594          SuperRegClassMap.find(rc);
595        if (I != SuperRegClassMap.end()) {
596          for (std::set<unsigned>::iterator II = I->second.begin(),
597                 EE = I->second.end(); II != EE; ++II) {
598            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
599            if (!Empty)
600              OS << ", ";
601            OS << "&" << RC2.getQualifiedName() << "RegClass";
602            Empty = false;
603          }
604        }
605
606        OS << (!Empty ? ", " : "") << "NULL";
607        OS << "\n  };\n\n";
608      }
609    }
610
611    // Emit the sub-classes array for each RegisterClass
612    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
613      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
614
615      // Give the register class a legal C name if it's anonymous.
616      std::string Name = RC.getName();
617
618      OS << "  static const unsigned " << Name << "SubclassMask[] = { ";
619      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
620      OS << "};\n\n";
621    }
622
623    // Emit NULL terminated super-class lists.
624    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
625      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
626      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
627
628      // Skip classes without supers.  We can reuse NullRegClasses.
629      if (Supers.empty())
630        continue;
631
632      OS << "  static const TargetRegisterClass* const "
633         << RC.getName() << "Superclasses[] = {\n";
634      for (unsigned i = 0; i != Supers.size(); ++i)
635        OS << "    &" << Supers[i]->getQualifiedName() << "RegClass,\n";
636      OS << "    NULL\n  };\n\n";
637    }
638
639    // Emit methods.
640    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
641      const CodeGenRegisterClass &RC = *RegisterClasses[i];
642      OS << RC.getName() << "Class::" << RC.getName()
643         << "Class()  : TargetRegisterClass(&"
644         << Target.getName() << "MCRegisterClasses["
645         << RC.getName() + "RegClassID" << "], "
646         << RC.getName() + "VTs" << ", "
647         << RC.getName() + "SubclassMask" << ", ";
648      if (RC.getSuperClasses().empty())
649        OS << "NullRegClasses, ";
650      else
651        OS << RC.getName() + "Superclasses, ";
652      OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
653         << "RegClasses, "
654         << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
655         << "RegClasses"
656         << ") {}\n";
657      if (!RC.AltOrderSelect.empty()) {
658        OS << "\nstatic inline unsigned " << RC.getName()
659           << "AltOrderSelect(const MachineFunction &MF) {"
660           << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
661           << RC.getName() << "Class::"
662           << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
663        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
664          ArrayRef<Record*> Elems = RC.getOrder(oi);
665          OS << "  static const unsigned AltOrder" << oi << "[] = {";
666          for (unsigned elem = 0; elem != Elems.size(); ++elem)
667            OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
668          OS << " };\n";
669        }
670        OS << "  const MCRegisterClass &MCR = " << Target.getName()
671           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];"
672           << "  static const ArrayRef<unsigned> Order[] = {\n"
673           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
674        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
675          OS << "),\n    makeArrayRef(AltOrder" << oi;
676        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
677           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
678           << ");\n  return Order[Select];\n}\n";
679        }
680    }
681
682    OS << "}\n";
683  }
684
685  OS << "\nnamespace {\n";
686  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
687  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
688    OS << "    &" << RegisterClasses[i]->getQualifiedName()
689       << "RegClass,\n";
690  OS << "  };\n";
691  OS << "}\n";       // End of anonymous namespace...
692
693  // Emit extra information about registers.
694  const std::string &TargetName = Target.getName();
695  OS << "\n  static const TargetRegisterInfoDesc "
696     << TargetName << "RegInfoDesc[] = "
697     << "{ // Extra Descriptors\n";
698  OS << "    { 0, 0 },\n";
699
700  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
701  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
702    const CodeGenRegister &Reg = *Regs[i];
703    OS << "    { ";
704    OS << Reg.CostPerUse << ", "
705       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
706  }
707  OS << "  };\n";      // End of register descriptors...
708
709
710  // Calculate the mapping of subregister+index pairs to physical registers.
711  // This will also create further anonymous indexes.
712  unsigned NamedIndices = RegBank.getNumNamedIndices();
713
714  // Emit SubRegIndex names, skipping 0
715  const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
716  OS << "\n  static const char *const " << TargetName
717     << "SubRegIndexTable[] = { \"";
718  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
719    OS << SubRegIndices[i]->getName();
720    if (i+1 != e)
721      OS << "\", \"";
722  }
723  OS << "\" };\n\n";
724
725  // Emit names of the anonymus subreg indexes.
726  if (SubRegIndices.size() > NamedIndices) {
727    OS << "  enum {";
728    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
729      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
730      if (i+1 != e)
731        OS << ',';
732    }
733    OS << "\n  };\n\n";
734  }
735  OS << "\n";
736
737  std::string ClassName = Target.getName() + "GenRegisterInfo";
738
739  // Emit the subregister + index mapping function based on the information
740  // calculated above.
741  OS << "unsigned " << ClassName
742     << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
743     << "  switch (RegNo) {\n"
744     << "  default:\n    return 0;\n";
745  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
746    const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
747    if (SRM.empty())
748      continue;
749    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
750    OS << "    switch (Index) {\n";
751    OS << "    default: return 0;\n";
752    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
753         ie = SRM.end(); ii != ie; ++ii)
754      OS << "    case " << getQualifiedName(ii->first)
755         << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
756    OS << "    };\n" << "    break;\n";
757  }
758  OS << "  };\n";
759  OS << "  return 0;\n";
760  OS << "}\n\n";
761
762  OS << "unsigned " << ClassName
763     << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
764     << "  switch (RegNo) {\n"
765     << "  default:\n    return 0;\n";
766   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
767     const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
768     if (SRM.empty())
769       continue;
770    OS << "  case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
771    for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
772         ie = SRM.end(); ii != ie; ++ii)
773      OS << "    if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
774         << ")  return " << getQualifiedName(ii->first) << ";\n";
775    OS << "    return 0;\n";
776  }
777  OS << "  };\n";
778  OS << "  return 0;\n";
779  OS << "}\n\n";
780
781  // Emit composeSubRegIndices
782  OS << "unsigned " << ClassName
783     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
784     << "  switch (IdxA) {\n"
785     << "  default:\n    return IdxB;\n";
786  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
787    bool Open = false;
788    for (unsigned j = 0; j != e; ++j) {
789      if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
790                                                         SubRegIndices[j])) {
791        if (!Open) {
792          OS << "  case " << getQualifiedName(SubRegIndices[i])
793             << ": switch(IdxB) {\n    default: return IdxB;\n";
794          Open = true;
795        }
796        OS << "    case " << getQualifiedName(SubRegIndices[j])
797           << ": return " << getQualifiedName(Comp) << ";\n";
798      }
799    }
800    if (Open)
801      OS << "    }\n";
802  }
803  OS << "  }\n}\n\n";
804
805  // Emit the constructor of the class...
806  OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
807
808  OS << ClassName << "::" << ClassName
809     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
810     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
811     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
812     << "                 " << TargetName << "SubRegIndexTable) {\n"
813     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
814     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
815     << RegisterClasses.size() << ");\n\n";
816
817  EmitRegMapping(OS, Regs, true);
818
819  OS << "}\n\n";
820
821  OS << "} // End llvm namespace \n";
822  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
823}
824
825void RegisterInfoEmitter::run(raw_ostream &OS) {
826  CodeGenTarget Target(Records);
827  CodeGenRegBank &RegBank = Target.getRegBank();
828  RegBank.computeDerivedInfo();
829
830  runEnums(OS, Target, RegBank);
831  runMCDesc(OS, Target, RegBank);
832  runTargetHeader(OS, Target, RegBank);
833  runTargetDesc(OS, Target, RegBank);
834}
835