RegisterInfoEmitter.cpp revision 3cbcffc4e5990209ce80a54e615f55245fe3b824 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "SequenceToOffsetTable.h"
20#include "llvm/TableGen/Error.h"
21#include "llvm/TableGen/Record.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/StringExtras.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/Twine.h"
26#include "llvm/Support/Format.h"
27#include <algorithm>
28#include <set>
29using namespace llvm;
30
31// runEnums - Print out enum values for all of the registers.
32void RegisterInfoEmitter::runEnums(raw_ostream &OS,
33                                   CodeGenTarget &Target, CodeGenRegBank &Bank) {
34  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
35
36  // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
37  assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
38
39  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
40
41  EmitSourceFileHeader("Target Register Enum Values", OS);
42
43  OS << "\n#ifdef GET_REGINFO_ENUM\n";
44  OS << "#undef GET_REGINFO_ENUM\n";
45
46  OS << "namespace llvm {\n\n";
47
48  OS << "class MCRegisterClass;\n"
49     << "extern const MCRegisterClass " << Namespace
50     << "MCRegisterClasses[];\n\n";
51
52  if (!Namespace.empty())
53    OS << "namespace " << Namespace << " {\n";
54  OS << "enum {\n  NoRegister,\n";
55
56  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
57    OS << "  " << Registers[i]->getName() << " = " <<
58      Registers[i]->EnumValue << ",\n";
59  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
60         "Register enum value mismatch!");
61  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
62  OS << "};\n";
63  if (!Namespace.empty())
64    OS << "}\n";
65
66  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
67  if (!RegisterClasses.empty()) {
68
69    // RegisterClass enums are stored as uint16_t in the tables.
70    assert(RegisterClasses.size() <= 0xffff &&
71           "Too many register classes to fit in tables");
72
73    OS << "\n// Register classes\n";
74    if (!Namespace.empty())
75      OS << "namespace " << Namespace << " {\n";
76    OS << "enum {\n";
77    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
78      if (i) OS << ",\n";
79      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
80      OS << " = " << i;
81    }
82    OS << "\n  };\n";
83    if (!Namespace.empty())
84      OS << "}\n";
85  }
86
87  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
88  // If the only definition is the default NoRegAltName, we don't need to
89  // emit anything.
90  if (RegAltNameIndices.size() > 1) {
91    OS << "\n// Register alternate name indices\n";
92    if (!Namespace.empty())
93      OS << "namespace " << Namespace << " {\n";
94    OS << "enum {\n";
95    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
96      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
97    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
98    OS << "};\n";
99    if (!Namespace.empty())
100      OS << "}\n";
101  }
102
103  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
104  if (!SubRegIndices.empty()) {
105    OS << "\n// Subregister indices\n";
106    std::string Namespace =
107      SubRegIndices[0]->getNamespace();
108    if (!Namespace.empty())
109      OS << "namespace " << Namespace << " {\n";
110    OS << "enum {\n  NoSubRegister,\n";
111    for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
112      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
113    OS << "  NUM_TARGET_NAMED_SUBREGS\n};\n";
114    if (!Namespace.empty())
115      OS << "}\n";
116  }
117
118  OS << "} // End llvm namespace \n";
119  OS << "#endif // GET_REGINFO_ENUM\n\n";
120}
121
122void RegisterInfoEmitter::
123EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
124                    const std::string &ClassName) {
125  unsigned NumRCs = RegBank.getRegClasses().size();
126  unsigned NumSets = RegBank.getNumRegPressureSets();
127
128  OS << "/// Get the weight in units of pressure for this register class.\n"
129     << "const RegClassWeight &" << ClassName << "::\n"
130     << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
131     << "  static const RegClassWeight RCWeightTable[] = {\n";
132  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
133    const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134    const CodeGenRegister::Set &Regs = RC.getMembers();
135    if (Regs.empty())
136      OS << "    {0, 0";
137    else {
138      std::vector<unsigned> RegUnits;
139      RC.buildRegUnitSet(RegUnits);
140      OS << "    {" << (*Regs.begin())->getWeight(RegBank)
141         << ", " << RegBank.getRegUnitSetWeight(RegUnits);
142    }
143    OS << "},  \t// " << RC.getName() << "\n";
144  }
145  OS << "    {0, 0} };\n"
146     << "  return RCWeightTable[RC->getID()];\n"
147     << "}\n\n";
148
149  OS << "\n"
150     << "// Get the number of dimensions of register pressure.\n"
151     << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
152     << "  return " << NumSets << ";\n}\n\n";
153
154  OS << "// Get the register unit pressure limit for this dimension.\n"
155     << "// This limit must be adjusted dynamically for reserved registers.\n"
156     << "unsigned " << ClassName << "::\n"
157     << "getRegPressureSetLimit(unsigned Idx) const {\n"
158     << "  static const unsigned PressureLimitTable[] = {\n";
159  for (unsigned i = 0; i < NumSets; ++i ) {
160    const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
161    OS << "    " << RegBank.getRegUnitSetWeight(RegUnits.Units)
162       << ",  \t// " << i << ": " << RegBank.getRegPressureSet(i).Name << "\n";
163  }
164  OS << "    0 };\n"
165     << "  return PressureLimitTable[Idx];\n"
166     << "}\n\n";
167
168  OS << "/// Get the dimensions of register pressure "
169     << "impacted by this register class.\n"
170     << "/// Returns a -1 terminated array of pressure set IDs\n"
171     << "const int* " << ClassName << "::\n"
172     << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
173     << "  static const int RCSetsTable[] = {\n    ";
174  std::vector<unsigned> RCSetStarts(NumRCs);
175  for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
176    RCSetStarts[i] = StartIdx;
177    ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
178    for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
179           PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
180      OS << *PSetI << ",  ";
181      ++StartIdx;
182    }
183    OS << "-1,  \t// " << RegBank.getRegClasses()[i]->getName() << "\n    ";
184    ++StartIdx;
185  }
186  OS << "-1 };\n";
187  OS << "  static const unsigned RCSetStartTable[] = {\n    ";
188  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
189    OS << RCSetStarts[i] << ",";
190  }
191  OS << "0 };\n"
192     << "  unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
193     << "  return &RCSetsTable[SetListStart];\n"
194     << "}\n\n";
195}
196
197void
198RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
199                                       const std::vector<CodeGenRegister*> &Regs,
200                                          bool isCtor) {
201  // Collect all information about dwarf register numbers
202  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
203  DwarfRegNumsMapTy DwarfRegNums;
204
205  // First, just pull all provided information to the map
206  unsigned maxLength = 0;
207  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
208    Record *Reg = Regs[i]->TheDef;
209    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
210    maxLength = std::max((size_t)maxLength, RegNums.size());
211    if (DwarfRegNums.count(Reg))
212      PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
213                   getQualifiedName(Reg) + "specified multiple times");
214    DwarfRegNums[Reg] = RegNums;
215  }
216
217  if (!maxLength)
218    return;
219
220  // Now we know maximal length of number list. Append -1's, where needed
221  for (DwarfRegNumsMapTy::iterator
222       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
223    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
224      I->second.push_back(-1);
225
226  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
227
228  OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
229
230  // Emit reverse information about the dwarf register numbers.
231  for (unsigned j = 0; j < 2; ++j) {
232    for (unsigned i = 0, e = maxLength; i != e; ++i) {
233      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
234      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
235      OS << i << "Dwarf2L[]";
236
237      if (!isCtor) {
238        OS << " = {\n";
239
240        // Store the mapping sorted by the LLVM reg num so lookup can be done
241        // with a binary search.
242        std::map<uint64_t, Record*> Dwarf2LMap;
243        for (DwarfRegNumsMapTy::iterator
244               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
245          int DwarfRegNo = I->second[i];
246          if (DwarfRegNo < 0)
247            continue;
248          Dwarf2LMap[DwarfRegNo] = I->first;
249        }
250
251        for (std::map<uint64_t, Record*>::iterator
252               I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
253          OS << "  { " << I->first << "U, " << getQualifiedName(I->second)
254             << " },\n";
255
256        OS << "};\n";
257      } else {
258        OS << ";\n";
259      }
260
261      // We have to store the size in a const global, it's used in multiple
262      // places.
263      OS << "extern const unsigned " << Namespace
264         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
265      if (!isCtor)
266        OS << " = sizeof(" << Namespace
267           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
268           << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
269      else
270        OS << ";\n\n";
271    }
272  }
273
274  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
275    Record *Reg = Regs[i]->TheDef;
276    const RecordVal *V = Reg->getValue("DwarfAlias");
277    if (!V || !V->getValue())
278      continue;
279
280    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
281    Record *Alias = DI->getDef();
282    DwarfRegNums[Reg] = DwarfRegNums[Alias];
283  }
284
285  // Emit information about the dwarf register numbers.
286  for (unsigned j = 0; j < 2; ++j) {
287    for (unsigned i = 0, e = maxLength; i != e; ++i) {
288      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
289      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
290      OS << i << "L2Dwarf[]";
291      if (!isCtor) {
292        OS << " = {\n";
293        // Store the mapping sorted by the Dwarf reg num so lookup can be done
294        // with a binary search.
295        for (DwarfRegNumsMapTy::iterator
296               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
297          int RegNo = I->second[i];
298          if (RegNo == -1) // -1 is the default value, don't emit a mapping.
299            continue;
300
301          OS << "  { " << getQualifiedName(I->first) << ", " << RegNo
302             << "U },\n";
303        }
304        OS << "};\n";
305      } else {
306        OS << ";\n";
307      }
308
309      // We have to store the size in a const global, it's used in multiple
310      // places.
311      OS << "extern const unsigned " << Namespace
312         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
313      if (!isCtor)
314        OS << " = sizeof(" << Namespace
315           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
316           << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
317      else
318        OS << ";\n\n";
319    }
320  }
321}
322
323void
324RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
325                                    const std::vector<CodeGenRegister*> &Regs,
326                                    bool isCtor) {
327  // Emit the initializer so the tables from EmitRegMappingTables get wired up
328  // to the MCRegisterInfo object.
329  unsigned maxLength = 0;
330  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
331    Record *Reg = Regs[i]->TheDef;
332    maxLength = std::max((size_t)maxLength,
333                         Reg->getValueAsListOfInts("DwarfNumbers").size());
334  }
335
336  if (!maxLength)
337    return;
338
339  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
340
341  // Emit reverse information about the dwarf register numbers.
342  for (unsigned j = 0; j < 2; ++j) {
343    OS << "  switch (";
344    if (j == 0)
345      OS << "DwarfFlavour";
346    else
347      OS << "EHFlavour";
348    OS << ") {\n"
349     << "  default:\n"
350     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
351
352    for (unsigned i = 0, e = maxLength; i != e; ++i) {
353      OS << "  case " << i << ":\n";
354      OS << "    ";
355      if (!isCtor)
356        OS << "RI->";
357      std::string Tmp;
358      raw_string_ostream(Tmp) << Namespace
359                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
360                              << "Dwarf2L";
361      OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
362      if (j == 0)
363          OS << "false";
364        else
365          OS << "true";
366      OS << ");\n";
367      OS << "    break;\n";
368    }
369    OS << "  }\n";
370  }
371
372  // Emit information about the dwarf register numbers.
373  for (unsigned j = 0; j < 2; ++j) {
374    OS << "  switch (";
375    if (j == 0)
376      OS << "DwarfFlavour";
377    else
378      OS << "EHFlavour";
379    OS << ") {\n"
380       << "  default:\n"
381       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
382
383    for (unsigned i = 0, e = maxLength; i != e; ++i) {
384      OS << "  case " << i << ":\n";
385      OS << "    ";
386      if (!isCtor)
387        OS << "RI->";
388      std::string Tmp;
389      raw_string_ostream(Tmp) << Namespace
390                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
391                              << "L2Dwarf";
392      OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
393      if (j == 0)
394          OS << "false";
395        else
396          OS << "true";
397      OS << ");\n";
398      OS << "    break;\n";
399    }
400    OS << "  }\n";
401  }
402}
403
404// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
405// Width is the number of bits per hex number.
406static void printBitVectorAsHex(raw_ostream &OS,
407                                const BitVector &Bits,
408                                unsigned Width) {
409  assert(Width <= 32 && "Width too large");
410  unsigned Digits = (Width + 3) / 4;
411  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
412    unsigned Value = 0;
413    for (unsigned j = 0; j != Width && i + j != e; ++j)
414      Value |= Bits.test(i + j) << j;
415    OS << format("0x%0*x, ", Digits, Value);
416  }
417}
418
419// Helper to emit a set of bits into a constant byte array.
420class BitVectorEmitter {
421  BitVector Values;
422public:
423  void add(unsigned v) {
424    if (v >= Values.size())
425      Values.resize(((v/8)+1)*8); // Round up to the next byte.
426    Values[v] = true;
427  }
428
429  void print(raw_ostream &OS) {
430    printBitVectorAsHex(OS, Values, 8);
431  }
432};
433
434static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
435  OS << getQualifiedName(Reg->TheDef);
436}
437
438static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
439  OS << getEnumName(VT);
440}
441
442//
443// runMCDesc - Print out MC register descriptions.
444//
445void
446RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
447                               CodeGenRegBank &RegBank) {
448  EmitSourceFileHeader("MC Register Information", OS);
449
450  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
451  OS << "#undef GET_REGINFO_MC_DESC\n";
452
453  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
454  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
455  RegBank.computeOverlaps(Overlaps);
456
457  // The lists of sub-registers, super-registers, and overlaps all go in the
458  // same array. That allows us to share suffixes.
459  typedef std::vector<const CodeGenRegister*> RegVec;
460  SmallVector<RegVec, 4> SubRegLists(Regs.size());
461  SmallVector<RegVec, 4> OverlapLists(Regs.size());
462  SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
463
464  // Precompute register lists for the SequenceToOffsetTable.
465  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
466    const CodeGenRegister *Reg = Regs[i];
467
468    // Compute the ordered sub-register list.
469    SetVector<const CodeGenRegister*> SR;
470    Reg->addSubRegsPreOrder(SR, RegBank);
471    RegVec &SubRegList = SubRegLists[i];
472    SubRegList.assign(SR.begin(), SR.end());
473    RegSeqs.add(SubRegList);
474
475    // Super-registers are already computed.
476    const RegVec &SuperRegList = Reg->getSuperRegs();
477    RegSeqs.add(SuperRegList);
478
479    // The list of overlaps doesn't need to have any particular order, except
480    // Reg itself must be the first element. Pick an ordering that has one of
481    // the other lists as a suffix.
482    RegVec &OverlapList = OverlapLists[i];
483    const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
484                           SubRegList : SuperRegList;
485    CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
486
487    // First element is Reg itself.
488    OverlapList.push_back(Reg);
489    Omit.insert(Reg);
490
491    // Any elements not in Suffix.
492    const CodeGenRegister::Set &OSet = Overlaps[Reg];
493    std::set_difference(OSet.begin(), OSet.end(),
494                        Omit.begin(), Omit.end(),
495                        std::back_inserter(OverlapList),
496                        CodeGenRegister::Less());
497
498    // Finally, Suffix itself.
499    OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
500    RegSeqs.add(OverlapList);
501  }
502
503  // Compute the final layout of the sequence table.
504  RegSeqs.layout();
505
506  OS << "namespace llvm {\n\n";
507
508  const std::string &TargetName = Target.getName();
509
510  // Emit the shared table of register lists.
511  OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
512  RegSeqs.emit(OS, printRegister);
513  OS << "};\n\n";
514
515  OS << "extern const MCRegisterDesc " << TargetName
516     << "RegDesc[] = { // Descriptors\n";
517  OS << "  { \"NOREG\", 0, 0, 0 },\n";
518
519  // Emit the register descriptors now.
520  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
521    const CodeGenRegister *Reg = Regs[i];
522    OS << "  { \"" << Reg->getName() << "\", "
523       << RegSeqs.get(OverlapLists[i]) << ", "
524       << RegSeqs.get(SubRegLists[i]) << ", "
525       << RegSeqs.get(Reg->getSuperRegs()) << " },\n";
526  }
527  OS << "};\n\n";      // End of register descriptors...
528
529  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
530
531  // Loop over all of the register classes... emitting each one.
532  OS << "namespace {     // Register classes...\n";
533
534  // Emit the register enum value arrays for each RegisterClass
535  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
536    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
537    ArrayRef<Record*> Order = RC.getOrder();
538
539    // Give the register class a legal C name if it's anonymous.
540    std::string Name = RC.getName();
541
542    // Emit the register list now.
543    OS << "  // " << Name << " Register Class...\n"
544       << "  const uint16_t " << Name
545       << "[] = {\n    ";
546    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
547      Record *Reg = Order[i];
548      OS << getQualifiedName(Reg) << ", ";
549    }
550    OS << "\n  };\n\n";
551
552    OS << "  // " << Name << " Bit set.\n"
553       << "  const uint8_t " << Name
554       << "Bits[] = {\n    ";
555    BitVectorEmitter BVE;
556    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
557      Record *Reg = Order[i];
558      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
559    }
560    BVE.print(OS);
561    OS << "\n  };\n\n";
562
563  }
564  OS << "}\n\n";
565
566  OS << "extern const MCRegisterClass " << TargetName
567     << "MCRegisterClasses[] = {\n";
568
569  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
570    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
571
572    // Asserts to make sure values will fit in table assuming types from
573    // MCRegisterInfo.h
574    assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
575    assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
576    assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
577
578    OS << "  { " << '\"' << RC.getName() << "\", "
579       << RC.getName() << ", " << RC.getName() << "Bits, "
580       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
581       << RC.getQualifiedName() + "RegClassID" << ", "
582       << RC.SpillSize/8 << ", "
583       << RC.SpillAlignment/8 << ", "
584       << RC.CopyCost << ", "
585       << RC.Allocatable << " },\n";
586  }
587
588  OS << "};\n\n";
589
590  // Emit the data table for getSubReg().
591  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
592  if (SubRegIndices.size()) {
593    OS << "const uint16_t " << TargetName << "SubRegTable[]["
594       << SubRegIndices.size() << "] = {\n";
595    for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
596      const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
597      OS << "  /* " << Regs[i]->TheDef->getName() << " */\n";
598      if (SRM.empty()) {
599        OS << "  {0},\n";
600        continue;
601      }
602      OS << "  {";
603      for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
604        // FIXME: We really should keep this to 80 columns...
605        CodeGenRegister::SubRegMap::const_iterator SubReg =
606          SRM.find(SubRegIndices[j]);
607        if (SubReg != SRM.end())
608          OS << getQualifiedName(SubReg->second->TheDef);
609        else
610          OS << "0";
611        if (j != je - 1)
612          OS << ", ";
613      }
614      OS << "}" << (i != e ? "," : "") << "\n";
615    }
616    OS << "};\n\n";
617    OS << "const uint16_t *get" << TargetName
618       << "SubRegTable() {\n  return (const uint16_t *)" << TargetName
619       << "SubRegTable;\n}\n\n";
620  }
621
622  EmitRegMappingTables(OS, Regs, false);
623
624  // MCRegisterInfo initialization routine.
625  OS << "static inline void Init" << TargetName
626     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
627     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
628  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
629     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
630     << RegisterClasses.size() << ", " << TargetName << "RegLists, ";
631  if (SubRegIndices.size() != 0)
632    OS << "(uint16_t*)" << TargetName << "SubRegTable, "
633       << SubRegIndices.size() << ");\n\n";
634  else
635    OS << "NULL, 0);\n\n";
636
637  EmitRegMapping(OS, Regs, false);
638
639  OS << "}\n\n";
640
641  OS << "} // End llvm namespace \n";
642  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
643}
644
645void
646RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
647                                     CodeGenRegBank &RegBank) {
648  EmitSourceFileHeader("Register Information Header Fragment", OS);
649
650  OS << "\n#ifdef GET_REGINFO_HEADER\n";
651  OS << "#undef GET_REGINFO_HEADER\n";
652
653  const std::string &TargetName = Target.getName();
654  std::string ClassName = TargetName + "GenRegisterInfo";
655
656  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
657
658  OS << "namespace llvm {\n\n";
659
660  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
661     << "  explicit " << ClassName
662     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
663     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
664     << "     { return false; }\n"
665     << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
666     << "  const TargetRegisterClass *"
667        "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
668     << "  const TargetRegisterClass *getMatchingSuperRegClass("
669        "const TargetRegisterClass*, const TargetRegisterClass*, "
670        "unsigned) const;\n"
671     << "  const RegClassWeight &getRegClassWeight("
672     << "const TargetRegisterClass *RC) const;\n"
673     << "  unsigned getNumRegPressureSets() const;\n"
674     << "  unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
675     << "  const int *getRegClassPressureSets("
676     << "const TargetRegisterClass *RC) const;\n"
677     << "};\n\n";
678
679  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
680
681  if (!RegisterClasses.empty()) {
682    OS << "namespace " << RegisterClasses[0]->Namespace
683       << " { // Register classes\n";
684
685    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
686      const CodeGenRegisterClass &RC = *RegisterClasses[i];
687      const std::string &Name = RC.getName();
688
689      // Output the extern for the instance.
690      OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
691      // Output the extern for the pointer to the instance (should remove).
692      OS << "  static const TargetRegisterClass * const " << Name
693         << "RegisterClass = &" << Name << "RegClass;\n";
694    }
695    OS << "} // end of namespace " << TargetName << "\n\n";
696  }
697  OS << "} // End llvm namespace \n";
698  OS << "#endif // GET_REGINFO_HEADER\n\n";
699}
700
701//
702// runTargetDesc - Output the target register and register file descriptions.
703//
704void
705RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
706                                   CodeGenRegBank &RegBank){
707  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
708
709  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
710  OS << "#undef GET_REGINFO_TARGET_DESC\n";
711
712  OS << "namespace llvm {\n\n";
713
714  // Get access to MCRegisterClass data.
715  OS << "extern const MCRegisterClass " << Target.getName()
716     << "MCRegisterClasses[];\n";
717
718  // Start out by emitting each of the register classes.
719  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
720
721  // Collect all registers belonging to any allocatable class.
722  std::set<Record*> AllocatableRegs;
723
724  // Collect allocatable registers.
725  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
726    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
727    ArrayRef<Record*> Order = RC.getOrder();
728
729    if (RC.Allocatable)
730      AllocatableRegs.insert(Order.begin(), Order.end());
731  }
732
733  // Build a shared array of value types.
734  SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
735  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
736    VTSeqs.add(RegisterClasses[rc]->VTs);
737  VTSeqs.layout();
738  OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
739  VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
740  OS << "};\n";
741
742  // Now that all of the structs have been emitted, emit the instances.
743  if (!RegisterClasses.empty()) {
744    std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
745
746    OS << "\nstatic const TargetRegisterClass *const "
747       << "NullRegClasses[] = { NULL };\n\n";
748
749    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
750
751    if (NumSubRegIndices) {
752      // Compute the super-register classes for each RegisterClass
753      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
754        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
755        for (DenseMap<Record*,Record*>::const_iterator
756             i = RC.SubRegClasses.begin(),
757             e = RC.SubRegClasses.end(); i != e; ++i) {
758          // Find the register class number of i->second for SuperRegClassMap.
759          const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
760          assert(RC2 && "Invalid register class in SubRegClasses");
761          SuperRegClassMap[RC2->EnumValue].insert(rc);
762        }
763      }
764
765      // Emit the super-register classes for each RegisterClass
766      for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
767        const CodeGenRegisterClass &RC = *RegisterClasses[rc];
768
769        // Give the register class a legal C name if it's anonymous.
770        std::string Name = RC.getName();
771
772        OS << "// " << Name
773           << " Super-register Classes...\n"
774           << "static const TargetRegisterClass *const "
775           << Name << "SuperRegClasses[] = {\n  ";
776
777        bool Empty = true;
778        std::map<unsigned, std::set<unsigned> >::iterator I =
779          SuperRegClassMap.find(rc);
780        if (I != SuperRegClassMap.end()) {
781          for (std::set<unsigned>::iterator II = I->second.begin(),
782                 EE = I->second.end(); II != EE; ++II) {
783            const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
784            if (!Empty)
785              OS << ", ";
786            OS << "&" << RC2.getQualifiedName() << "RegClass";
787            Empty = false;
788          }
789        }
790
791        OS << (!Empty ? ", " : "") << "NULL";
792        OS << "\n};\n\n";
793      }
794    }
795
796    // Emit the sub-classes array for each RegisterClass
797    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
798      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
799
800      // Give the register class a legal C name if it's anonymous.
801      std::string Name = RC.getName();
802
803      OS << "static const uint32_t " << Name << "SubclassMask[] = {\n  ";
804      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
805      OS << "\n};\n\n";
806    }
807
808    // Emit NULL terminated super-class lists.
809    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
810      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
811      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
812
813      // Skip classes without supers.  We can reuse NullRegClasses.
814      if (Supers.empty())
815        continue;
816
817      OS << "static const TargetRegisterClass *const "
818         << RC.getName() << "Superclasses[] = {\n";
819      for (unsigned i = 0; i != Supers.size(); ++i)
820        OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
821      OS << "  NULL\n};\n\n";
822    }
823
824    // Emit methods.
825    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
826      const CodeGenRegisterClass &RC = *RegisterClasses[i];
827      if (!RC.AltOrderSelect.empty()) {
828        OS << "\nstatic inline unsigned " << RC.getName()
829           << "AltOrderSelect(const MachineFunction &MF) {"
830           << RC.AltOrderSelect << "}\n\n"
831           << "static ArrayRef<uint16_t> " << RC.getName()
832           << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
833        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
834          ArrayRef<Record*> Elems = RC.getOrder(oi);
835          if (!Elems.empty()) {
836            OS << "  static const uint16_t AltOrder" << oi << "[] = {";
837            for (unsigned elem = 0; elem != Elems.size(); ++elem)
838              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
839            OS << " };\n";
840          }
841        }
842        OS << "  const MCRegisterClass &MCR = " << Target.getName()
843           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
844           << "  const ArrayRef<uint16_t> Order[] = {\n"
845           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
846        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
847          if (RC.getOrder(oi).empty())
848            OS << "),\n    ArrayRef<uint16_t>(";
849          else
850            OS << "),\n    makeArrayRef(AltOrder" << oi;
851        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
852           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
853           << ");\n  return Order[Select];\n}\n";
854        }
855    }
856
857    // Now emit the actual value-initialized register class instances.
858    OS << "namespace " << RegisterClasses[0]->Namespace
859       << " {   // Register class instances\n";
860
861    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
862      const CodeGenRegisterClass &RC = *RegisterClasses[i];
863      OS << "  extern const TargetRegisterClass "
864         << RegisterClasses[i]->getName() << "RegClass = {\n    "
865         << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
866         << "RegClassID],\n    "
867         << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
868         << RC.getName() << "SubclassMask,\n    ";
869      if (RC.getSuperClasses().empty())
870        OS << "NullRegClasses,\n    ";
871      else
872        OS << RC.getName() << "Superclasses,\n    ";
873      OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
874         << "RegClasses,\n    ";
875      if (RC.AltOrderSelect.empty())
876        OS << "0\n";
877      else
878        OS << RC.getName() << "GetRawAllocationOrder\n";
879      OS << "  };\n\n";
880    }
881
882    OS << "}\n";
883  }
884
885  OS << "\nnamespace {\n";
886  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
887  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
888    OS << "    &" << RegisterClasses[i]->getQualifiedName()
889       << "RegClass,\n";
890  OS << "  };\n";
891  OS << "}\n";       // End of anonymous namespace...
892
893  // Emit extra information about registers.
894  const std::string &TargetName = Target.getName();
895  OS << "\nstatic const TargetRegisterInfoDesc "
896     << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
897  OS << "  { 0, 0 },\n";
898
899  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
900  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
901    const CodeGenRegister &Reg = *Regs[i];
902    OS << "  { ";
903    OS << Reg.CostPerUse << ", "
904       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
905  }
906  OS << "};\n";      // End of register descriptors...
907
908
909  // Calculate the mapping of subregister+index pairs to physical registers.
910  // This will also create further anonymous indices.
911  unsigned NamedIndices = RegBank.getNumNamedIndices();
912
913  // Emit SubRegIndex names, skipping 0
914  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
915  OS << "\nstatic const char *const " << TargetName
916     << "SubRegIndexTable[] = { \"";
917  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
918    OS << SubRegIndices[i]->getName();
919    if (i+1 != e)
920      OS << "\", \"";
921  }
922  OS << "\" };\n\n";
923
924  // Emit names of the anonymous subreg indices.
925  if (SubRegIndices.size() > NamedIndices) {
926    OS << "  enum {";
927    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
928      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
929      if (i+1 != e)
930        OS << ',';
931    }
932    OS << "\n  };\n\n";
933  }
934  OS << "\n";
935
936  std::string ClassName = Target.getName() + "GenRegisterInfo";
937
938  // Emit composeSubRegIndices
939  OS << "unsigned " << ClassName
940     << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
941     << "  switch (IdxA) {\n"
942     << "  default:\n    return IdxB;\n";
943  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
944    bool Open = false;
945    for (unsigned j = 0; j != e; ++j) {
946      if (CodeGenSubRegIndex *Comp =
947            SubRegIndices[i]->compose(SubRegIndices[j])) {
948        if (!Open) {
949          OS << "  case " << SubRegIndices[i]->getQualifiedName()
950             << ": switch(IdxB) {\n    default: return IdxB;\n";
951          Open = true;
952        }
953        OS << "    case " << SubRegIndices[j]->getQualifiedName()
954           << ": return " << Comp->getQualifiedName() << ";\n";
955      }
956    }
957    if (Open)
958      OS << "    }\n";
959  }
960  OS << "  }\n}\n\n";
961
962  // Emit getSubClassWithSubReg.
963  OS << "const TargetRegisterClass *" << ClassName
964     << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
965        " const {\n";
966  if (SubRegIndices.empty()) {
967    OS << "  assert(Idx == 0 && \"Target has no sub-registers\");\n"
968       << "  return RC;\n";
969  } else {
970    // Use the smallest type that can hold a regclass ID with room for a
971    // sentinel.
972    if (RegisterClasses.size() < UINT8_MAX)
973      OS << "  static const uint8_t Table[";
974    else if (RegisterClasses.size() < UINT16_MAX)
975      OS << "  static const uint16_t Table[";
976    else
977      throw "Too many register classes.";
978    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
979    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
980      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
981      OS << "    {\t// " << RC.getName() << "\n";
982      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
983        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
984        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
985          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
986             << " -> " << SRC->getName() << "\n";
987        else
988          OS << "      0,\t// " << Idx->getName() << "\n";
989      }
990      OS << "    },\n";
991    }
992    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
993       << "  if (!Idx) return RC;\n  --Idx;\n"
994       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
995       << "  unsigned TV = Table[RC->getID()][Idx];\n"
996       << "  return TV ? getRegClass(TV - 1) : 0;\n";
997  }
998  OS << "}\n\n";
999
1000  // Emit getMatchingSuperRegClass.
1001  OS << "const TargetRegisterClass *" << ClassName
1002     << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
1003        " const TargetRegisterClass *B, unsigned Idx) const {\n";
1004  if (SubRegIndices.empty()) {
1005    OS << "  llvm_unreachable(\"Target has no sub-registers\");\n";
1006  } else {
1007    // We need to find the largest sub-class of A such that every register has
1008    // an Idx sub-register in B.  Map (B, Idx) to a bit-vector of
1009    // super-register classes that map into B. Then compute the largest common
1010    // sub-class with A by taking advantage of the register class ordering,
1011    // like getCommonSubClass().
1012
1013    // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
1014    // the number of 32-bit words required to represent all register classes.
1015    const unsigned BVWords = (RegisterClasses.size()+31)/32;
1016    BitVector BV(RegisterClasses.size());
1017
1018    OS << "  static const uint32_t Table[" << RegisterClasses.size()
1019       << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
1020    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1021      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1022      OS << "    {\t// " << RC.getName() << "\n";
1023      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1024        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1025        BV.reset();
1026        RC.getSuperRegClasses(Idx, BV);
1027        OS << "      { ";
1028        printBitVectorAsHex(OS, BV, 32);
1029        OS << "},\t// " << Idx->getName() << '\n';
1030      }
1031      OS << "    },\n";
1032    }
1033    OS << "  };\n  assert(A && B && \"Missing regclass\");\n"
1034       << "  --Idx;\n"
1035       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1036       << "  const uint32_t *TV = Table[B->getID()][Idx];\n"
1037       << "  const uint32_t *SC = A->getSubClassMask();\n"
1038       << "  for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
1039       << "    if (unsigned Common = TV[i] & SC[i])\n"
1040       << "      return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
1041       << "  return 0;\n";
1042  }
1043  OS << "}\n\n";
1044
1045  EmitRegUnitPressure(OS, RegBank, ClassName);
1046
1047  // Emit the constructor of the class...
1048  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1049  OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
1050  if (SubRegIndices.size() != 0)
1051    OS << "extern const uint16_t *get" << TargetName
1052       << "SubRegTable();\n";
1053
1054  EmitRegMappingTables(OS, Regs, true);
1055
1056  OS << ClassName << "::\n" << ClassName
1057     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1058     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1059     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1060     << "             " << TargetName << "SubRegIndexTable) {\n"
1061     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
1062     << Regs.size()+1 << ", RA,\n                     " << TargetName
1063     << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1064     << "                     " << TargetName << "RegLists,\n"
1065     << "                     ";
1066  if (SubRegIndices.size() != 0)
1067    OS << "get" << TargetName << "SubRegTable(), "
1068       << SubRegIndices.size() << ");\n\n";
1069  else
1070    OS << "NULL, 0);\n\n";
1071
1072  EmitRegMapping(OS, Regs, true);
1073
1074  OS << "}\n\n";
1075
1076
1077  // Emit CalleeSavedRegs information.
1078  std::vector<Record*> CSRSets =
1079    Records.getAllDerivedDefinitions("CalleeSavedRegs");
1080  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1081    Record *CSRSet = CSRSets[i];
1082    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1083    assert(Regs && "Cannot expand CalleeSavedRegs instance");
1084
1085    // Emit the *_SaveList list of callee-saved registers.
1086    OS << "static const uint16_t " << CSRSet->getName()
1087       << "_SaveList[] = { ";
1088    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1089      OS << getQualifiedName((*Regs)[r]) << ", ";
1090    OS << "0 };\n";
1091
1092    // Emit the *_RegMask bit mask of call-preserved registers.
1093    OS << "static const uint32_t " << CSRSet->getName()
1094       << "_RegMask[] = { ";
1095    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1096    OS << "};\n";
1097  }
1098  OS << "\n\n";
1099
1100  OS << "} // End llvm namespace \n";
1101  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1102}
1103
1104void RegisterInfoEmitter::run(raw_ostream &OS) {
1105  CodeGenTarget Target(Records);
1106  CodeGenRegBank &RegBank = Target.getRegBank();
1107  RegBank.computeDerivedInfo();
1108
1109  runEnums(OS, Target, RegBank);
1110  runMCDesc(OS, Target, RegBank);
1111  runTargetHeader(OS, Target, RegBank);
1112  runTargetDesc(OS, Target, RegBank);
1113}
1114