/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 836 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 864 SETLT, // 1 X 1 0 0 True if less than enumerator in enum:llvm::ISD::CondCode 875 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 601 ISD::SETLT); 608 ISD::SETLT); 707 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT); 710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
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/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 189 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; 208 case ICmpInst::ICMP_SLT: return ISD::SETLT;
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H A D | TargetLoweringBase.cpp | 707 CCs[RTLIB::OLT_F32] = ISD::SETLT; 708 CCs[RTLIB::OLT_F64] = ISD::SETLT; 709 CCs[RTLIB::OLT_F128] = ISD::SETLT;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 149 case ISD::SETLT: 1470 case ISD::SETLT: 1650 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 1661 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1674 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1678 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1691 // SETUGT X, SINTMAX -> SETLT X, 0 1696 ISD::SETLT); 2058 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X 3055 DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT); [all...] |
H A D | LegalizeIntegerTypes.cpp | 977 case ISD::SETLT: 2731 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2742 case ISD::SETLT: 2784 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2811 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break; 3080 ISD::SETLT);
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H A D | SelectionDAGDumper.cpp | 349 case ISD::SETLT: return "setlt";
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H A D | LegalizeDAG.cpp | 1879 case ISD::SETLT: 2636 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT); 2679 ISD::SETLT); 3166 Tmp1, ISD::SETLT); 3357 case ISD::SMIN: Pred = ISD::SETLT; break;
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H A D | DAGCombiner.cpp | 3594 if (isNullConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 4990 case ISD::SETLT: 5590 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && 13853 CC == ISD::SETULT || CC == ISD::SETLT)) { 14008 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 14072 if (isNullConstant(N3) && CC == ISD::SETLT && 14199 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 14200 (N1C->isOne() && CC == ISD::SETLT)) &&
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H A D | SelectionDAG.cpp | 281 case ISD::SETLT: 1960 case ISD::SETLT: return getConstant(C1.slt(C2), dl, VT); 1981 case ISD::SETLT: if (R==APFloat::cmpUnordered)
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H A D | LegalizeFloatTypes.cpp | 1455 Lo, Hi, ISD::SETLT);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2105 case ISD::SETLT: return PPC::PRED_LT; 2128 case ISD::SETLT: return 0; // Bit #0 = SETOLT 2164 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; 2210 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break; 2294 case ISD::SETLT: { 2329 case ISD::SETLT: {
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H A D | PPCISelLowering.cpp | 2361 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); 6054 case ISD::SETLT: 6087 case ISD::SETLT:
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/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 470 case ISD::SETLT:
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/external/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 1684 X86_INTRINSIC_DATA(sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT), 1727 X86_INTRINSIC_DATA(sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT), 1756 X86_INTRINSIC_DATA(sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT), 1767 X86_INTRINSIC_DATA(sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT),
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H A D | X86ISelLowering.cpp | 4050 case ISD::SETLT: return X86::COND_L; 4072 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 4076 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 4123 case ISD::SETLT: return X86::COND_B; 12946 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT); 13079 Value, ThreshVal, ISD::SETLT); 13086 Value, ThreshVal, ISD::SETLT); 14219 case ISD::SETLT: 14301 case ISD::SETLT: 14337 case ISD::SETLT [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 1123 case ISD::SETLT: { 1873 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT); 1874 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT); 1996 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT); 2108 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
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H A D | R600ISelLowering.cpp | 48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); 60 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 959 case ISD::SETLT: 989 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 991 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 998 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 1008 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 1728 Op->getOperand(2), ISD::SETLT); 1734 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
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H A D | MipsISelLowering.cpp | 513 case ISD::SETLT:
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 875 case ISD::SETLT:
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1062 case ISD::SETLT: 1123 case ISD::SETLT: 1445 case ISD::SETLT: 1451 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1472 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 3664 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) { 7393 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL); 8980 (Op == ISD::SMIN && CC != ISD::SETLT && CC != ISD::SETLE) || 8986 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1319 case ISD::SETLT: return ARMCC::LT; 1348 case ISD::SETLT: 3300 case ISD::SETLT: 3303 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 3317 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 4635 case ISD::SETLT: Swap = true; // Fallthrough 4671 case ISD::SETLT: Swap = true;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1385 case ISD::SETLT: return SPCC::ICC_L; 1405 case ISD::SETLT:
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 4051 case ISD::SETLT:
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