Searched refs:SETULE (Results 1 - 24 of 24) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h837 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
856 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator in enum:llvm::ISD::CondCode
881 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
/external/llvm/lib/CodeGen/
H A DAnalysis.cpp178 case FCmpInst::FCMP_ULE: return ISD::SETULE;
190 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE;
205 case ICmpInst::ICMP_ULE: return ISD::SETULE;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp193 case ISD::SETULE:
1464 case ISD::SETULE:
1486 case ISD::SETULE: {
1646 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1667 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1762 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1763 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1774 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1835 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2065 case ISD::SETULE
[all...]
H A DSelectionDAGDumper.cpp343 case ISD::SETULE: return "setule";
H A DLegalizeIntegerTypes.cpp967 case ISD::SETULE:
2747 case ISD::SETULE: LowCC = ISD::SETULE; break;
2782 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2814 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
H A DSelectionDAG.cpp286 case ISD::SETULE:
335 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
1958 case ISD::SETULE: return getConstant(C1.ule(C2), dl, VT);
2008 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, dl, VT);
H A DLegalizeDAG.cpp1865 case ISD::SETULE:
H A DSelectionDAGBuilder.cpp1802 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
H A DDAGCombiner.cpp4993 case ISD::SETULE: {
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2106 case ISD::SETULE:
2136 case ISD::SETULE:
2137 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2167 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2175 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2211 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2220 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
/external/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp469 case ISD::SETULE:
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp132 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDILISelLowering.cpp138 setOperationAction(ISD::SETULE, VT, Expand);
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp964 case ISD::SETULE:
994 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
996 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
998 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1716 Op->getOperand(2), ISD::SETULE);
1722 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1826 Op->getOperand(2), ISD::SETULE);
H A DMipsISelLowering.cpp522 case ISD::SETULE: return Mips::FCOND_ULE;
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1324 case ISD::SETULE: return ARMCC::LS;
1351 case ISD::SETULE: CondCode = ARMCC::LE; break;
3310 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3321 case ISD::SETULE:
3324 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3524 CC == ISD::SETULE)
3534 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3546 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4643 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4677 case ISD::SETULE
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/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp834 case ISD::SETULE:
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1072 case ISD::SETULE:
1128 case ISD::SETULE:
1160 case ISD::SETULE:
1461 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1477 case ISD::SETULE:
1483 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
8981 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) ||
8986 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
/external/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp57 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
H A DAMDGPUISelLowering.cpp1114 case ISD::SETULE:
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1390 case ISD::SETULE: return SPCC::ICC_LEU;
1414 case ISD::SETULE: return SPCC::FCC_ULE;
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4055 case ISD::SETULE: return X86::COND_BE;
4125 case ISD::SETULE:
14228 case ISD::SETULE: Swap = true; // Fallthrough
14304 case ISD::SETULE:
14342 case ISD::SETULE: Unsigned = true; //fall-through
14493 case ISD::SETULE:
14531 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14535 // Special case: Use min/max operations for SETULE/SETUGE
14544 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14576 case ISD::SETULE
[all...]
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4050 case ISD::SETULE:
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2024 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)

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