/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 837 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 855 SETULT, // 1 1 0 0 True if unordered or less than enumerator in enum:llvm::ISD::CondCode 881 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
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/external/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 177 case FCmpInst::FCMP_ULT: return ISD::SETULT; 189 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; 209 case ICmpInst::ICMP_ULT: return ISD::SETULT;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 189 case ISD::SETULT: 1327 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ 1331 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; 1463 case ISD::SETULT: 1485 case ISD::SETULT: 1650 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 1661 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1674 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 1678 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1698 // SETULT [all...] |
H A D | LegalizeIntegerTypes.cpp | 968 case ISD::SETULT: 1616 Amt, NVBitsNode, ISD::SETULT); 1747 ISD::SETULT); 1752 ISD::SETULT); 1761 LoOps[0], LoOps[1], ISD::SETULT); 2445 ISD::SETULT : ISD::SETUGT); 2743 case ISD::SETULT: LowCC = ISD::SETULT; break; 2785 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2812 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperand [all...] |
H A D | SelectionDAGDumper.cpp | 342 case ISD::SETULT: return "setult";
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H A D | LegalizeDAG.cpp | 1864 case ISD::SETULT: 3359 case ISD::UMIN: Pred = ISD::SETULT; break; 3588 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
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H A D | SelectionDAG.cpp | 285 case ISD::SETULT: 310 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT 333 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT 336 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE 1956 case ISD::SETULT: return getConstant(C1.ult(C2), dl, VT); 2004 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
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H A D | DAGCombiner.cpp | 4992 case ISD::SETULT: 13853 CC == ISD::SETULT || CC == ISD::SETLT)) {
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/external/llvm/lib/Target/AMDGPU/ |
H A D | R600ISelLowering.cpp | 56 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 62 setCondCodeAction(ISD::SETULT, MVT::i32, Expand); 1017 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); 1018 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); 1055 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); 1056 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT);
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H A D | AMDGPUISelLowering.cpp | 1115 case ISD::SETULT: {
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 2115 case ISD::SETULT: return PPC::PRED_LT; 2147 case ISD::SETULT: return 0; 2168 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; 2176 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; 2212 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; 3153 // post-legalization uses SETULT in the SELECT_CC for the 3160 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
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H A D | PPCISelLowering.cpp | 347 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); 348 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); 6053 case ISD::SETULT: 6086 case ISD::SETULT:
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/external/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 468 case ISD::SETULT:
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 132 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 135 setOperationAction(ISD::SETULT, VT, Expand);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 963 case ISD::SETULT: 993 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 995 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 998 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 1740 Op->getOperand(2), ISD::SETULT); 1746 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1830 Op->getOperand(2), ISD::SETULT);
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H A D | MipsISelLowering.cpp | 521 case ISD::SETULT: return Mips::FCOND_ULT;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 1323 case ISD::SETULT: return ARMCC::LO; 1349 case ISD::SETULT: CondCode = ARMCC::LT; break; 3307 case ISD::SETULT: 3310 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 3324 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 3529 CC == ISD::SETULT) 3535 CC == ISD::SETULT) 3546 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE || 4645 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 4675 case ISD::SETULT [all...] |
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 849 case ISD::SETULT:
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 1070 case ISD::SETULT: 1124 case ISD::SETULT: 1159 case ISD::SETULT: 1456 case ISD::SETULT: 1461 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1483 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 8981 (Op == ISD::UMIN && CC != ISD::SETULT && CC != ISD::SETULE) || 8986 CC != ISD::SETULT && CC != ISD::SETULE && CC != ISD::SETLT &&
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 1389 case ISD::SETULT: return SPCC::ICC_CS; 1413 case ISD::SETULT: return SPCC::FCC_UL;
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 4053 case ISD::SETULT: return X86::COND_B; 4122 case ISD::SETULT: 14230 case ISD::SETULT: Swap = true; // Fallthrough 14300 case ISD::SETULT: 14339 case ISD::SETULT: SSECC = 1; Unsigned = true; break; 14491 case ISD::SETULT: 14527 case ISD::SETULT: Swap = true; 14559 case ISD::SETULT: { 23989 case ISD::SETULT: 24083 case ISD::SETULT [all...] |
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 4049 case ISD::SETULT:
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 2017 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
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