| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 197 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
200 SMUL_LOHI, UMUL_LOHI, enumerator in enum:llvm::ISD::NodeType
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| H A D | SelectionDAG.h | 1089 case ISD::SMUL_LOHI:
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 295 case ISD::SMUL_LOHI:
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| H A D | MipsSEISelLowering.cpp | 114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
205 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
410 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
482 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 120 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
148 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
168 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2769 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2770 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2771 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2900 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2943 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
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| H A D | SelectionDAGDumper.cpp | 184 case ISD::SMUL_LOHI: return "smul_lohi";
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| H A D | LegalizeDAG.cpp | 3486 ISD::SMUL_LOHI;
3501 // and unsigned forms. If the target supports both SMUL_LOHI and
3504 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3510 OpToUse = ISD::SMUL_LOHI;
3514 OpToUse = ISD::SMUL_LOHI;
3604 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
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| H A D | DAGCombiner.cpp | 1374 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 101 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
216 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
571 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 142 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
147 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
|
| /external/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 151 {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1234 case ISD::SMUL_LOHI:
2446 case ISD::SMUL_LOHI:
2451 bool isSigned = Opcode == ISD::SMUL_LOHI;
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| H A D | X86ISelLowering.cpp | 718 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
1189 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
18214 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
20123 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1693 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1751 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 250 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
315 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1651 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1655 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 453 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
727 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
8471 V->getOpcode() == ISD::SMUL_LOHI)
8489 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8517 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8519 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8555 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8562 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
8572 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
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| H A D | ARMISelDAGToDAG.cpp | 2672 case ISD::SMUL_LOHI: {
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 194 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
2827 // result in the even register. SMUL_LOHI is defined to return the
4339 case ISD::SMUL_LOHI:
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 150 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
476 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 225 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
601 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
|