Searched refs:ShiftAmt (Results 1 - 25 of 31) sorted by relevance

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/external/llvm/lib/Analysis/
H A DDemandedBits.cpp145 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); local
146 AB = AOut.lshr(ShiftAmt);
152 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
154 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
161 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); local
162 AB = AOut.shl(ShiftAmt);
167 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
174 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1); local
175 AB = AOut.shl(ShiftAmt);
179 if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
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H A DValueTracking.cpp992 unsigned ShiftAmt = SA->getLimitedValue(BitWidth-1); local
995 KnownZero = KZF(KnownZero, ShiftAmt);
996 KnownOne = KOF(KnownOne, ShiftAmt);
1028 for (unsigned ShiftAmt = 0; ShiftAmt < BitWidth; ++ShiftAmt) {
1031 if ((ShiftAmt & ~ShiftAmtKZ) != ShiftAmt)
1033 if ((ShiftAmt | ShiftAmtKO) != ShiftAmt)
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H A DConstantFolding.cpp176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); local
187 ConstantInt::get(Src->getType(), ShiftAmt));
188 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); local
213 ConstantInt::get(Src->getType(), ShiftAmt));
214 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp567 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
568 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
573 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
575 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
581 KnownZero <<= ShiftAmt; local
582 KnownOne <<= ShiftAmt; local
584 if (ShiftAmt)
585 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
591 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
594 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
632 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1); local
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H A DInstCombineCasts.cpp642 uint32_t ShiftAmt = KnownZeroMask.logBase2(); local
644 if (ShiftAmt) {
647 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
784 uint64_t ShiftAmt = Amt->getZExtValue();
785 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0;
1018 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); local
1020 if (ShiftAmt)
1022 ConstantInt::get(In->getType(), ShiftAmt));
1032 unsigned ShiftAmt local
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H A DInstCombineCalls.cpp298 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth)); local
299 auto ShiftVec = Builder.CreateVectorSplat(VWidth, ShiftAmt);
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp87 const unsigned ShiftAmt = ToIdx * 16; local
90 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
92 Imm &= ~(0xFFFFLL << ShiftAmt);
104 const unsigned ShiftAmt = ChunkIdx * 16;
124 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
185 unsigned ShiftAmt = 0;
188 for (; ShiftAmt < 64; ShiftAmt += 16) {
189 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
202 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
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H A DAArch64ConditionOptimizer.cpp158 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm()); local
162 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
H A DAArch64ISelDAGToDAG.cpp260 unsigned ShiftAmt; local
263 ShiftAmt = 0;
265 ShiftAmt = 12;
270 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
1779 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local
1780 Mask = Mask.shl(ShiftAmt);
1782 Mask = Mask.lshr(ShiftAmt);
1787 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); local
1788 Mask = Mask.lshr(ShiftAmt);
1790 Mask = Mask.shl(ShiftAmt);
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/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1190 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); local
1244 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1249 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1254 .addReg(MaskUpper).addReg(ShiftAmt);
1256 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1317 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1428 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); local
1489 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1494 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1499 .addReg(MaskUpper).addReg(ShiftAmt);
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H A DMipsFastISel.cpp1564 unsigned ShiftAmt; local
1569 ShiftAmt = 24;
1572 ShiftAmt = 16;
1576 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1577 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp975 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local
976 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
981 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
995 AM.Scale = 1 << ShiftAmt;
1035 unsigned ShiftAmt = Shift.getConstantOperandVal(1); local
1052 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
1087 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
H A DX86ISelLowering.cpp7454 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7468 DAG.getConstant(ShiftAmt, DL, MVT::i8));
15973 SDValue SrcOp, uint64_t ShiftAmt,
15977 // Fold this packed shift into its first operand if ShiftAmt is 0.
15978 if (ShiftAmt == 0)
15981 // Check for ShiftAmt >= element width
15982 if (ShiftAmt >= ElementType.getSizeInBits()) {
15984 ShiftAmt = ElementType.getSizeInBits() - 1;
16011 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
16023 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), d
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/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp940 unsigned ShiftAmt = V.getConstantOperandVal(1); local
945 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
946 Bits[i] = LHSBits[i - ShiftAmt];
948 for (unsigned i = 0; i < ShiftAmt; ++i)
956 unsigned ShiftAmt = V.getConstantOperandVal(1); local
961 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
962 Bits[i] = LHSBits[i + ShiftAmt];
964 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
2468 SDValue ShiftAmt = local
2475 N0, ShiftAmt);
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H A DPPCISelLowering.cpp1423 unsigned ShiftAmt = SVOp->getMaskElt(i); local
1424 if (ShiftAmt < i) return -1;
1426 ShiftAmt -= i;
1432 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1437 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1443 ShiftAmt = 16 - ShiftAmt;
1445 return ShiftAmt;
1618 unsigned ShiftAmt = SVOp->getMaskElt(i); local
1619 if (ShiftAmt <
10735 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT); local
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/external/llvm/lib/Transforms/Scalar/
H A DGVN.cpp1150 unsigned ShiftAmt; local
1152 ShiftAmt = Offset*8;
1154 ShiftAmt = (StoreSize-LoadSize-Offset)*8;
1156 if (ShiftAmt)
1157 SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt);
/external/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1285 unsigned ShiftAmt = isShiftedImm() ? ShiftedImm.ShiftAmount : 0; local
1288 Inst.addOperand(MCOperand::createImm(ShiftAmt));
3287 uint32_t ShiftAmt = 0, MaxShiftAmt = IsXReg ? 48 : 16; local
3289 ShiftAmt += 16;
3292 if (ShiftAmt <= MaxShiftAmt && Imm <= 0xFFFF) {
3296 if (ShiftAmt)
3298 ShiftAmt, true, S, E, Ctx));
3301 APInt Simm = APInt(64, Imm << ShiftAmt);
/external/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp1563 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize * (Ratio - 1);
1569 Tmp = Tmp.shl(ShiftAmt);
1570 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
1579 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize * (Ratio - 1);
1584 Elt.IntVal = Elt.IntVal.lshr(ShiftAmt);
1588 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp2189 int ShiftAmt = cast<ConstantInt>(Shift)->getSExtValue(); local
2196 if (ShiftAmt == EltSize) {
2203 --ShiftAmt;
2204 Shift = ConstantInt::get(VTy->getElementType(), ShiftAmt);
2970 Constant *ShiftAmt = local
2972 Ops[0] = Builder.CreateLShr(Ops[0], ShiftAmt, "vaddhn");
3266 Constant *ShiftAmt = local
3268 Ops[0] = Builder.CreateLShr(Ops[0], ShiftAmt, "vsubhn");
4965 uint64_t ShiftAmt = Amt->getZExtValue(); local
4967 if (ShiftAmt
4982 uint64_t ShiftAmt = Amt->getZExtValue(); local
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp842 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl, local
846 ShiftAmt));
2960 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits(); local
2961 SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT, DL));
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1453 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local
1457 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1517 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, local
1526 MaskedValue, ShiftAmt);
1530 ShiftAmt);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp4863 uint64_t ShiftAmt = ShiftCnst->getZExtValue(); local
4886 NumBits = countTrailingOnes(MaskVal) - ShiftAmt;
4893 NumBits = NumZeros + NumOnes - ShiftAmt;
4899 if (ShiftAmt < NumZeros) {
4906 Start = CurDAG->getTargetConstant(ShiftAmt, DL, MVT::i32);
H A DNVPTXISelLowering.cpp4187 APInt ShiftAmt = ShlRHS->getAPIntValue(); local
4189 if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4190 APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
/external/llvm/lib/Support/
H A DAPInt.cpp2236 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1));
2242 Tmp = Tmp.lshr(ShiftAmt);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2877 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2880 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2881 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2892 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);

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