Searched refs:ShiftBits (Results 1 - 4 of 4) sorted by relevance
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 491 // rlwinm rA, rA, ShiftBits, 0, 31. 536 unsigned ShiftBits = getEncodingValue(DestReg)*4; local 537 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 539 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 580 // rlwinm rA, rA, ShiftBits, 0, 0. 623 unsigned ShiftBits = getEncodingValue(DestReg); local 624 // rlwimi r11, r10, 32-ShiftBits, ..., ... 628 .addImm(ShiftBits ? 32 - ShiftBits : 0) 629 .addImm(ShiftBits) [all...] |
/external/llvm/lib/Analysis/ |
H A D | BasicAliasAnalysis.cpp | 448 if (unsigned ShiftBits = 64 - PointerSize) { 449 Scale <<= ShiftBits; local 450 Scale = (int64_t)Scale >> ShiftBits;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 1748 unsigned ShiftBits = AndRHSC.countTrailingZeros(); local 1755 DAG.getConstant(ShiftBits, dl, 1757 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy); 1768 unsigned ShiftBits; local 1772 ShiftBits = C1.countTrailingOnes(); 1776 ShiftBits = C1.countTrailingZeros(); 1778 NewC = NewC.lshr(ShiftBits); 1779 if (ShiftBits && NewC.getMinSignedBits() <= 64 && 1787 DAG.getConstant(ShiftBits, dl, ShiftTy));
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 4619 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8); local 4620 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); 4621 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits); 4631 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8); local 4632 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits); 4633 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); [all...] |
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