Searched refs:getNumMicroOps (Results 1 - 9 of 9) sorted by relevance

/external/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h97 unsigned getNumMicroOps(const MachineInstr *MI,
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp76 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, function in class:TargetSchedModel
79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
80 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
H A DMachineScheduler.cpp1700 RemIssueCount += SchedModel->getNumMicroOps(I->getInstr(), SC)
1773 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
1776 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
1984 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr());
H A DTargetInstrInfo.cpp1014 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, function in class:TargetInstrInfo
/external/llvm/include/llvm/MC/
H A DMCInstrItineraries.h230 int getNumMicroOps(unsigned ItinClassIndx) const { function in class:llvm::InstrItineraryData
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
347 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h281 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
H A DARMBaseInstrInfo.cpp2757 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2984 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3007 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, function in class:ARMBaseInstrInfo
3014 int ItinUOps = ItinData->getNumMicroOps(Class);
4001 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4002 return getNumMicroOps(ItinData, MI);
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h1141 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,

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