Searched refs:v1i64 (Results 1 - 13 of 13) sorted by relevance

/external/clang/test/CodeGen/
H A Dconst-init.c137 typedef long long v1i64 __attribute((vector_size(8))); typedef
143 static v1i64 a = (v1i64)10LL;
H A Dsystemz-abi-vector.c23 typedef __attribute__((vector_size(8))) long long v1i64; typedef
94 v1i64 pass_v1i64(v1i64 arg) { return arg; }
H A Dx86_64-arguments.c261 typedef unsigned long long v1i64 __attribute__((__vector_size__(8))); typedef
265 v1i64 f34(v1i64 arg) { return arg; }
/external/llvm/include/llvm/CodeGen/
H A DMachineValueType.h95 v1i64 = 45, // 1 x i64 enumerator in enum:llvm::MVT::SimpleValueType
235 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||
342 case v1i64:
415 case v1i64:
467 case v1i64:
626 if (NumElements == 1) return MVT::v1i64;
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2489 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2507 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2525 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2543 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2561 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2579 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2597 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2615 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2633 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2647 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || V
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H A DAArch64ISelLowering.cpp95 addDRTypeForNEON(MVT::v1i64);
556 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
557 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
558 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
559 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
562 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
696 VT.getSimpleVT() != MVT::v2i64 && VT.getSimpleVT() != MVT::v1i64)
6372 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6406 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
7948 // (concat_vectors LHS, (v1i64 (bitconver
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/external/llvm/lib/IR/
H A DValueTypes.cpp172 case MVT::v1i64: return "v1i64";
250 case MVT::v1i64: return VectorType::get(Type::getInt64Ty(Context), 1);
/external/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp402 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
403 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
404 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
405 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
H A DARMISelLowering.cpp147 VT != MVT::v2i64 && VT != MVT::v1i64)
471 addDRTypeForNEON(MVT::v1i64);
552 // Neon does not support some operations on v1i64 and v2i64 types.
553 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
563 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
589 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
599 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
1073 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
3995 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4009 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
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H A DARMISelDAGToDAG.cpp1829 case MVT::v1i64: OpcodeIndex = 3; break;
1873 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1966 case MVT::v1i64: OpcodeIndex = 3; break;
2024 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
/external/llvm/utils/TableGen/
H A DCodeGenTarget.cpp105 case MVT::v1i64: return "MVT::v1i64";
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1790 MVT::v2i32, MVT::v1i64}) {
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp782 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
791 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
2263 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
11862 if (OpVT == MVT::v1i64 &&
11864 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
23787 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23792 MMXSrcOp.getValueType() == MVT::v1i64 &&
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