/art/compiler/linker/arm64/ |
H A D | relative_patcher_arm64.cc | 174 uint32_t shift = wide ? 3u : 2u; local 190 insn = (out_disp & 0x0fffffffu) >> shift; 214 shift = 0u; // No shift for ADD. 241 uint32_t imm12 = (disp & 0xfffu) >> shift;
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/art/compiler/optimizing/ |
H A D | code_generator_arm.cc | 2770 int shift; local 2771 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 2782 if (shift != 0) { 2783 __ Asr(temp1, temp1, shift); 3317 // ARM doesn't mask the shift count so we need to do it ourselves. 3361 // If the shift is > 32 bits, override the high part 3375 // If the shift is > 32 bits, override the low part
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H A D | code_generator_arm64.cc | 1741 uint32_t shift = rhs.immediate() & (lhs.SizeInBits() - 1); local 1742 __ Ror(dst, lhs, shift); 1744 // Ensure shift distance is in the same size register as the result. If 1745 // we are rotating a long and the shift comes in a w register originally, 1746 // we don't need to sxtw for use as an x since the shift distances are 1789 LOG(FATAL) << "Unexpected shift type " << type; 1827 LOG(FATAL) << "Unexpected shift operation type " << type; 2590 int shift; local 2591 CalculateMagicAndShiftForDivRem(imm, type == Primitive::kPrimLong /* is_long */, &magic, &shift); 2611 if (shift ! [all...] |
H A D | code_generator_mips.cc | 1418 LOG(FATAL) << "Unexpected shift type " << type; 1475 // 32-bit shift instructions use the 5 least significant bits of the shift count, so 1477 // when `rhs_reg & 31 == 0` is OK even though we don't shift `lhs` left all the way out 1632 LOG(FATAL) << "Unexpected shift operation type " << type; 2348 int shift; local 2349 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 2366 if (shift != 0) { 2367 __ Sra(TMP, TMP, shift);
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H A D | code_generator_mips64.cc | 1161 LOG(FATAL) << "Unexpected shift type " << type; 1254 LOG(FATAL) << "Unexpected shift operation type " << type; 1994 int shift; local 1998 &shift); 2010 if (shift != 0) { 2011 __ Sra(TMP, TMP, shift); 2034 if (shift >= 32) { 2035 __ Dsra32(TMP, TMP, shift - 32); 2036 } else if (shift > 0) { 2037 __ Dsra(TMP, TMP, shift); [all...] |
H A D | code_generator_utils.cc | 25 int64_t* magic, int* shift) { 26 // It does not make sense to calculate magic and shift for zero divisor. 32 * The magic number M and shift S can be calculated in the following way: 41 * So the shift p is the smallest p satisfying 50 * (resp. 64 - p) as the shift number S. 95 *shift = is_long ? p - 64 : p - 32; 24 CalculateMagicAndShiftForDivRem(int64_t divisor, bool is_long, int64_t* magic, int* shift) argument
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H A D | code_generator_utils.h | 26 // Computes the magic number and the shift needed in the div/rem by constant algorithm, as out 27 // arguments `magic` and `shift` 28 void CalculateMagicAndShiftForDivRem(int64_t divisor, bool is_long, int64_t* magic, int* shift);
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H A D | code_generator_x86.cc | 3268 int shift = CTZ(imm); local 3269 __ sarl(num, Immediate(shift)); 3306 int shift; local 3307 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 3337 if (shift != 0) { 3338 __ sarl(edx, Immediate(shift)); 3686 // The shift count needs to be in CL or a constant. 3719 int32_t shift = second.GetConstant()->AsIntConstant()->GetValue() & kMaxIntShiftDistance; local 3720 if (shift == 0) { 3723 Immediate imm(shift); 3747 int32_t shift = second.GetConstant()->AsIntConstant()->GetValue() & kMaxLongShiftDistance; local 3766 GenerateShlLong(const Location& loc, int shift) argument 3805 GenerateShrLong(const Location& loc, int shift) argument 3837 GenerateUShrLong(const Location& loc, int shift) argument [all...] |
H A D | code_generator_x86.h | 222 void GenerateShlLong(const Location& loc, int shift); 223 void GenerateShrLong(const Location& loc, int shift); 224 void GenerateUShrLong(const Location& loc, int shift);
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H A D | code_generator_x86_64.cc | 3338 int shift = CTZ(imm); local 3339 __ sarl(tmp, Immediate(shift)); 3354 int shift = CTZ(imm); local 3355 __ sarq(rdx, Immediate(shift)); 3387 int shift; local 3393 CalculateMagicAndShiftForDivRem(imm, false /* is_long */, &magic, &shift); 3416 if (shift != 0) { 3417 __ sarl(edx, Immediate(shift)); 3441 CalculateMagicAndShiftForDivRem(imm, true /* is_long */, &magic, &shift); 3461 if (shift ! [all...] |
H A D | common_arm64.h | 157 vixl::Shift shift = vixl::LSL, 161 return vixl::MemOperand(base.X(), regoffset, shift, shift_amount); 187 } else if (mem_op.shift() != vixl::NO_SHIFT) { 188 return vixl::Operand(mem_op.regoffset(), mem_op.shift(), mem_op.shift_amount()); 206 // Our code generator ensures shift distances are within an encodable range.
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H A D | constant_folding.cc | 48 void VisitShift(HBinaryOperation* shift);
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H A D | instruction_simplifier.cc | 57 void VisitShift(HBinaryOperation* shift); 358 // And the shift distance being negated is the distance being shifted the other way. 967 size_t shift = Int64FromConstant(input_other->InputAt(1)->AsConstant()) & (reg_bits - 1); local 969 if ((num_tail_bits_set >= reg_bits - shift) && input_other->IsUShr()) { 975 } else if ((num_tail_bits_set == reg_bits - shift) && IsPowerOfTwo(value + 1) && 1223 HIntConstant* shift = GetGraph()->GetIntConstant(WhichPowerOf2(factor)); local 1224 HShl* shl = new (allocator) HShl(type, input_other, shift); 1533 // as shift and rotate operations expect a 32-bit (or narrower)
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H A D | intrinsics_x86.cc | 2292 static void SwapBits(Register reg, Register temp, int32_t shift, int32_t mask, argument 2294 Immediate imm_shift(shift);
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H A D | intrinsics_x86_64.cc | 2308 static void SwapBits(CpuRegister reg, CpuRegister temp, int32_t shift, int32_t mask, argument 2310 Immediate imm_shift(shift); 2353 int32_t shift, int64_t mask, X86_64Assembler* assembler) { 2354 Immediate imm_shift(shift); 2352 SwapBits64(CpuRegister reg, CpuRegister temp, CpuRegister temp_mask, int32_t shift, int64_t mask, X86_64Assembler* assembler) argument
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H A D | nodes.h | 75 // The maximum (meaningful) distance (31) that can be used in an integer shift/rotate operation. 77 // The maximum (meaningful) distance (63) that can be used in a long shift/rotate operation. 1633 const int shift = type; // 0-based consecutive enum local 1634 DCHECK_LE(kFieldWriteOffset, shift); 1635 DCHECK_LT(shift, kArrayWriteOffset);
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H A D | nodes_arm64.h | 27 kLSL, // Logical shift left. 28 kLSR, // Logical shift right. 29 kASR, // Arithmetic shift right. 47 // The shift argument is unused if the operation 49 int shift = 0, 52 instr_kind_(instr->GetKind()), op_kind_(op), shift_amount_(shift) { 74 // Find the operation kind and shift amount from a bitfield move instruction.
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/art/compiler/utils/arm/ |
H A D | assembler_arm.cc | 111 // Immediate shift. 116 // Register shift. 140 // Immediate shift. 180 uint32_t shift = shift_; 181 if (shift == RRX) { 183 shift = ROR; 185 encoding = am_ | static_cast<uint32_t>(rm_) | shift << 5 | offset_ << 7 | B25;
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H A D | assembler_arm.h | 140 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), argument 142 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(shift_imm) { 145 // Data-processing operands - Logical shift/rotate by register 146 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument 148 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(0) { 281 Address(Register rn, Register rm, Shift shift, uint32_t count, Mode am = Offset) : argument 283 am_(am), is_immed_offset_(false), shift_(shift) { 339 const int32_t offset_; // Used as shift amount for register offset. 817 // Convenience shift instructions. Use mov instruction with shifter operand 818 // for variants setting the status flags or using a register shift coun [all...] |
H A D | assembler_arm32_test.cc | 40 // To speed up tests, don't use all shift immediates. 173 // ShifterOperands of form "reg shift-type imm." 174 for (arm::Shift shift : shifts) { 179 if (shift != arm::Shift::RRX) { 182 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, imm)); 185 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 1)); 186 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 2)); 187 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 3)); 188 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 7)); 189 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 1 [all...] |
H A D | assembler_arm_test.h | 413 for (const SOp& shift : shifts) { 416 std::string shift_string = GetShiftString(shift); 438 (Base::GetAssembler()->*f)(*reg, shift, c); 469 for (const SOp& shift : shifts) { 472 std::string shift_string = GetShiftString(shift); 503 (Base::GetAssembler()->*f)(*reg1, *reg2, shift, c); 547 static constexpr const char* SHIFT_TOKEN = "{shift}";
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H A D | assembler_thumb2.cc | 1210 // However, there is no actual shift available, neither for ADD nor for MOV (ASR/LSR/LSL/ROR). 1284 // Shift operand - check if it is a MOV convertible to a 16-bit shift instruction. 1298 // Register operand without shift. 1474 LOG(FATAL) << "Unexpected shift: " << so.GetShift(); 1794 Shift shift, 1799 if ((IsHighRegister(rd) || IsHighRegister(rm) || shift == ROR || shift == RRX) || 1802 switch (shift) { 1809 LOG(FATAL) << "Unsupported thumb2 shift opcode"; 1821 // 16 bit shift 1792 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, Condition cond, SetCc set_cc) argument 1837 EmitShift(Register rd, Register rn, Shift shift, Register rm, Condition cond, SetCc set_cc) argument 3140 ToItMask(ItState s, uint8_t firstcond0, uint8_t shift) argument [all...] |
H A D | assembler_thumb2.h | 769 void EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, 771 void EmitShift(Register rd, Register rn, Shift shift, Register rm,
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H A D | constants_arm.h | 159 LSL = 0, // Logical shift left 160 LSR = 1, // Logical shift right 161 ASR = 2, // Arithmetic shift right 265 int Bits(int shift, int count) const { argument 266 return (InstructionBits() >> shift) & ((1 << count) - 1);
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/art/runtime/arch/mips64/ |
H A D | quick_entrypoints_mips64.S | 776 dsrl $t3, $t3, 4 # shift the frame size right 4 777 dsll $t3, $t3, 4 # shift the frame size left 4 to align to 16 bytes 879 dsrl $t3, $t3, 4 # shift the frame size right 4 880 dsll $t3, $t3, 4 # shift the frame size left 4 to align to 16 bytes 1570 daddiu $t1, $t1, -1 # Decrease obj size and shift right by
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