1%default {"instr":"","load":"","store":"","wide":"0"}
2/*
3 * Generic 32-bit FP conversion operation.
4 */
5    /* unop vA, vB */
6    movzbl  rINSTbl, %ecx                   # ecx <- A+
7    sarl    $$4, rINST                      # rINST <- B
8    $load   VREG_ADDRESS(rINST)             # %st0 <- vB
9    andb    $$0xf, %cl                      # ecx <- A
10    $instr
11    $store  VREG_ADDRESS(%ecx)              # vA <- %st0
12    .if $wide
13    CLEAR_WIDE_REF %ecx
14    .else
15    CLEAR_REF %ecx
16    .endif
17    ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
18