1// REQUIRES: arm-registered-target 2// RUN: %clang_cc1 -Wall -Werror -triple thumbv7-eabi -target-cpu cortex-a8 -O3 -emit-llvm -o - %s | FileCheck %s 3 4void *f0() 5{ 6 return __builtin_thread_pointer(); 7} 8 9void f1(char *a, char *b) { 10 __clear_cache(a,b); 11} 12 13// CHECK: call {{.*}} @__clear_cache 14 15void test_eh_return_data_regno() 16{ 17 volatile int res; 18 res = __builtin_eh_return_data_regno(0); // CHECK: store volatile i32 0 19 res = __builtin_eh_return_data_regno(1); // CHECK: store volatile i32 1 20} 21 22void nop() { 23 __builtin_arm_nop(); 24} 25 26// CHECK: call {{.*}} @llvm.arm.hint(i32 0) 27 28void yield() { 29 __builtin_arm_yield(); 30} 31 32// CHECK: call {{.*}} @llvm.arm.hint(i32 1) 33 34void wfe() { 35 __builtin_arm_wfe(); 36} 37 38// CHECK: call {{.*}} @llvm.arm.hint(i32 2) 39 40void wfi() { 41 __builtin_arm_wfi(); 42} 43 44// CHECK: call {{.*}} @llvm.arm.hint(i32 3) 45 46void sev() { 47 __builtin_arm_sev(); 48} 49 50// CHECK: call {{.*}} @llvm.arm.hint(i32 4) 51 52void sevl() { 53 __builtin_arm_sevl(); 54} 55 56// CHECK: call {{.*}} @llvm.arm.hint(i32 5) 57 58void dbg() { 59 __builtin_arm_dbg(0); 60} 61 62// CHECK: call {{.*}} @llvm.arm.dbg(i32 0) 63 64void test_barrier() { 65 __builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.arm.dmb(i32 1) 66 __builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.arm.dsb(i32 2) 67 __builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.arm.isb(i32 3) 68} 69 70// CHECK: call {{.*}} @llvm.arm.rbit(i32 %a) 71 72unsigned rbit(unsigned a) { 73 return __builtin_arm_rbit(a); 74} 75 76void prefetch(int i) { 77 __builtin_arm_prefetch(&i, 0, 1); 78// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 0, i32 3, i32 1) 79 80 __builtin_arm_prefetch(&i, 1, 1); 81// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 1) 82 83 84 __builtin_arm_prefetch(&i, 1, 0); 85// CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 0) 86} 87 88unsigned mrc() { 89 // CHECK: define i32 @mrc() 90 // CHECK: [[R:%.*]] = {{.*}} call i32 @llvm.arm.mrc(i32 15, i32 0, i32 13, i32 0, i32 3) 91 // CHECK-NEXT: ret i32 [[R]] 92 return __builtin_arm_mrc(15, 0, 13, 0, 3); 93} 94 95unsigned mrc2() { 96 // CHECK: define i32 @mrc2() 97 // CHECK: [[R:%.*]] = {{.*}} call i32 @llvm.arm.mrc2(i32 15, i32 0, i32 13, i32 0, i32 3) 98 // CHECK-NEXT: ret i32 [[R]] 99 return __builtin_arm_mrc2(15, 0, 13, 0, 3); 100} 101 102void mcr(unsigned a) { 103 // CHECK: define void @mcr(i32 [[A:%.*]]) 104 // CHECK: call void @llvm.arm.mcr(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) 105 __builtin_arm_mcr(15, 0, a, 13, 0, 3); 106} 107 108void mcr2(unsigned a) { 109 // CHECK: define void @mcr2(i32 [[A:%.*]]) 110 // CHECK: call void @llvm.arm.mcr2(i32 15, i32 0, i32 [[A]], i32 13, i32 0, i32 3) 111 __builtin_arm_mcr2(15, 0, a, 13, 0, 3); 112} 113 114void mcrr(unsigned a, unsigned b) { 115 // CHECK: define void @mcrr(i32 [[A:%.*]], i32 [[B:%.*]]) 116 // CHECK: call void @llvm.arm.mcrr(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0) 117 __builtin_arm_mcrr(15, 0, a, b, 0); 118} 119 120void mcrr2(unsigned a, unsigned b) { 121 // CHECK: define void @mcrr2(i32 [[A:%.*]], i32 [[B:%.*]]) 122 // CHECK: call void @llvm.arm.mcrr2(i32 15, i32 0, i32 [[A]], i32 [[B]], i32 0) 123 __builtin_arm_mcrr2(15, 0, a, b, 0); 124} 125 126unsigned rsr() { 127 // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !7) 128 // CHECK-NEXT: ret i32 [[V0]] 129 return __builtin_arm_rsr("cp1:2:c3:c4:5"); 130} 131 132unsigned long long rsr64() { 133 // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !8) 134 // CHECK-NEXT: ret i64 [[V0]] 135 return __builtin_arm_rsr64("cp1:2:c3"); 136} 137 138void *rsrp() { 139 // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i32 @llvm.read_register.i32(metadata !9) 140 // CHECK-NEXT: [[V1:[%A-Za-z0-9.]+]] = inttoptr i32 [[V0]] to i8* 141 // CHECK-NEXT: ret i8* [[V1]] 142 return __builtin_arm_rsrp("sysreg"); 143} 144 145void wsr(unsigned v) { 146 // CHECK: call void @llvm.write_register.i32(metadata !7, i32 %v) 147 __builtin_arm_wsr("cp1:2:c3:c4:5", v); 148} 149 150void wsr64(unsigned long long v) { 151 // CHECK: call void @llvm.write_register.i64(metadata !8, i64 %v) 152 __builtin_arm_wsr64("cp1:2:c3", v); 153} 154 155void wsrp(void *v) { 156 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i32 157 // CHECK-NEXT: call void @llvm.write_register.i32(metadata !9, i32 [[V0]]) 158 __builtin_arm_wsrp("sysreg", v); 159} 160 161// CHECK: !7 = !{!"cp1:2:c3:c4:5"} 162// CHECK: !8 = !{!"cp1:2:c3"} 163// CHECK: !9 = !{!"sysreg"} 164