1//===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements routines for translating functions from LLVM IR into
11// Machine IR.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
17
18#include "llvm/ADT/APInt.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/IndexedMap.h"
21#include "llvm/ADT/Optional.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/CodeGen/ISDOpcodes.h"
25#include "llvm/CodeGen/MachineBasicBlock.h"
26#include "llvm/IR/InlineAsm.h"
27#include "llvm/IR/Instructions.h"
28#include "llvm/Target/TargetRegisterInfo.h"
29#include <vector>
30
31namespace llvm {
32
33class AllocaInst;
34class BasicBlock;
35class BranchProbabilityInfo;
36class CallInst;
37class Function;
38class GlobalVariable;
39class Instruction;
40class MachineInstr;
41class MachineBasicBlock;
42class MachineFunction;
43class MachineModuleInfo;
44class MachineRegisterInfo;
45class SelectionDAG;
46class MVT;
47class TargetLowering;
48class Value;
49
50//===--------------------------------------------------------------------===//
51/// FunctionLoweringInfo - This contains information that is global to a
52/// function that is used when lowering a region of the function.
53///
54class FunctionLoweringInfo {
55public:
56  const Function *Fn;
57  MachineFunction *MF;
58  const TargetLowering *TLI;
59  MachineRegisterInfo *RegInfo;
60  BranchProbabilityInfo *BPI;
61  /// CanLowerReturn - true iff the function's return value can be lowered to
62  /// registers.
63  bool CanLowerReturn;
64
65  /// True if part of the CSRs will be handled via explicit copies.
66  bool SplitCSR;
67
68  /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
69  /// allocated to hold a pointer to the hidden sret parameter.
70  unsigned DemoteRegister;
71
72  /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
73  DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
74
75  /// ValueMap - Since we emit code for the function a basic block at a time,
76  /// we must remember which virtual registers hold the values for
77  /// cross-basic-block values.
78  DenseMap<const Value *, unsigned> ValueMap;
79
80  /// Track virtual registers created for exception pointers.
81  DenseMap<const Value *, unsigned> CatchPadExceptionPointers;
82
83  // Keep track of frame indices allocated for statepoints as they could be used
84  // across basic block boundaries.
85  // Key of the map is statepoint instruction, value is a map from spilled
86  // llvm Value to the optional stack stack slot index.
87  // If optional is unspecified it means that we have visited this value
88  // but didn't spill it.
89  typedef DenseMap<const Value*, Optional<int>> StatepointSpilledValueMapTy;
90  DenseMap<const Instruction*, StatepointSpilledValueMapTy>
91    StatepointRelocatedValues;
92
93  /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
94  /// the entry block.  This allows the allocas to be efficiently referenced
95  /// anywhere in the function.
96  DenseMap<const AllocaInst*, int> StaticAllocaMap;
97
98  /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
99  DenseMap<const Argument*, int> ByValArgFrameIndexMap;
100
101  /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
102  /// function arguments that are inserted after scheduling is completed.
103  SmallVector<MachineInstr*, 8> ArgDbgValues;
104
105  /// RegFixups - Registers which need to be replaced after isel is done.
106  DenseMap<unsigned, unsigned> RegFixups;
107
108  /// StatepointStackSlots - A list of temporary stack slots (frame indices)
109  /// used to spill values at a statepoint.  We store them here to enable
110  /// reuse of the same stack slots across different statepoints in different
111  /// basic blocks.
112  SmallVector<unsigned, 50> StatepointStackSlots;
113
114  /// MBB - The current block.
115  MachineBasicBlock *MBB;
116
117  /// MBB - The current insert position inside the current block.
118  MachineBasicBlock::iterator InsertPt;
119
120  struct LiveOutInfo {
121    unsigned NumSignBits : 31;
122    bool IsValid : 1;
123    APInt KnownOne, KnownZero;
124    LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
125                    KnownZero(1, 0) {}
126  };
127
128  /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
129  /// for a value.
130  DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
131
132  /// VisitedBBs - The set of basic blocks visited thus far by instruction
133  /// selection.
134  SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
135
136  /// PHINodesToUpdate - A list of phi instructions whose operand list will
137  /// be updated after processing the current basic block.
138  /// TODO: This isn't per-function state, it's per-basic-block state. But
139  /// there's no other convenient place for it to live right now.
140  std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
141  unsigned OrigNumPHINodesToUpdate;
142
143  /// If the current MBB is a landing pad, the exception pointer and exception
144  /// selector registers are copied into these virtual registers by
145  /// SelectionDAGISel::PrepareEHLandingPad().
146  unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
147
148  /// set - Initialize this FunctionLoweringInfo with the given Function
149  /// and its associated MachineFunction.
150  ///
151  void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
152
153  /// clear - Clear out all the function-specific state. This returns this
154  /// FunctionLoweringInfo to an empty state, ready to be used for a
155  /// different function.
156  void clear();
157
158  /// isExportedInst - Return true if the specified value is an instruction
159  /// exported from its block.
160  bool isExportedInst(const Value *V) {
161    return ValueMap.count(V);
162  }
163
164  unsigned CreateReg(MVT VT);
165
166  unsigned CreateRegs(Type *Ty);
167
168  unsigned InitializeRegForValue(const Value *V) {
169    // Tokens never live in vregs.
170    if (V->getType()->isTokenTy())
171      return 0;
172    unsigned &R = ValueMap[V];
173    assert(R == 0 && "Already initialized this value register!");
174    return R = CreateRegs(V->getType());
175  }
176
177  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
178  /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
179  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
180    if (!LiveOutRegInfo.inBounds(Reg))
181      return nullptr;
182
183    const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
184    if (!LOI->IsValid)
185      return nullptr;
186
187    return LOI;
188  }
189
190  /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
191  /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
192  /// the register's LiveOutInfo is for a smaller bit width, it is extended to
193  /// the larger bit width by zero extension. The bit width must be no smaller
194  /// than the LiveOutInfo's existing bit width.
195  const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
196
197  /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
198  void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
199                         const APInt &KnownZero, const APInt &KnownOne) {
200    // Only install this information if it tells us something.
201    if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
202      return;
203
204    LiveOutRegInfo.grow(Reg);
205    LiveOutInfo &LOI = LiveOutRegInfo[Reg];
206    LOI.NumSignBits = NumSignBits;
207    LOI.KnownOne = KnownOne;
208    LOI.KnownZero = KnownZero;
209  }
210
211  /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
212  /// register based on the LiveOutInfo of its operands.
213  void ComputePHILiveOutRegInfo(const PHINode*);
214
215  /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
216  /// called when a block is visited before all of its predecessors.
217  void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
218    // PHIs with no uses have no ValueMap entry.
219    DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
220    if (It == ValueMap.end())
221      return;
222
223    unsigned Reg = It->second;
224    if (Reg == 0)
225      return;
226
227    LiveOutRegInfo.grow(Reg);
228    LiveOutRegInfo[Reg].IsValid = false;
229  }
230
231  /// setArgumentFrameIndex - Record frame index for the byval
232  /// argument.
233  void setArgumentFrameIndex(const Argument *A, int FI);
234
235  /// getArgumentFrameIndex - Get frame index for the byval argument.
236  int getArgumentFrameIndex(const Argument *A);
237
238  unsigned getCatchPadExceptionPointerVReg(const Value *CPI,
239                                           const TargetRegisterClass *RC);
240
241private:
242  void addSEHHandlersForLPads(ArrayRef<const LandingPadInst *> LPads);
243
244  /// LiveOutRegInfo - Information about live out vregs.
245  IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
246};
247
248/// ComputeUsesVAFloatArgument - Determine if any floating-point values are
249/// being passed to this variadic function, and set the MachineModuleInfo's
250/// usesVAFloatArgument flag if so. This flag is used to emit an undefined
251/// reference to _fltused on Windows, which will link in MSVCRT's
252/// floating-point support.
253void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);
254
255/// AddLandingPadInfo - Extract the exception handling information from the
256/// landingpad instruction and add them to the specified machine module info.
257void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
258                       MachineBasicBlock *MBB);
259
260} // end namespace llvm
261
262#endif
263