1//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CriticalAntiDepBreaker class, which
11// implements register anti-dependence breaking along a blocks
12// critical path during post-RA scheduler.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
17#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
18
19#include "AntiDepBreaker.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/RegisterClassInfo.h"
26#include "llvm/CodeGen/ScheduleDAG.h"
27#include <map>
28
29namespace llvm {
30class RegisterClassInfo;
31class TargetInstrInfo;
32class TargetRegisterInfo;
33
34class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
35    MachineFunction& MF;
36    MachineRegisterInfo &MRI;
37    const TargetInstrInfo *TII;
38    const TargetRegisterInfo *TRI;
39    const RegisterClassInfo &RegClassInfo;
40
41    /// The set of allocatable registers.
42    /// We'll be ignoring anti-dependencies on non-allocatable registers,
43    /// because they may not be safe to break.
44    const BitVector AllocatableSet;
45
46    /// For live regs that are only used in one register class in a
47    /// live range, the register class. If the register is not live, the
48    /// corresponding value is null. If the register is live but used in
49    /// multiple register classes, the corresponding value is -1 casted to a
50    /// pointer.
51    std::vector<const TargetRegisterClass*> Classes;
52
53    /// Map registers to all their references within a live range.
54    std::multimap<unsigned, MachineOperand *> RegRefs;
55    typedef std::multimap<unsigned, MachineOperand *>::const_iterator
56      RegRefIter;
57
58    /// The index of the most recent kill (proceeding bottom-up),
59    /// or ~0u if the register is not live.
60    std::vector<unsigned> KillIndices;
61
62    /// The index of the most recent complete def (proceeding
63    /// bottom up), or ~0u if the register is live.
64    std::vector<unsigned> DefIndices;
65
66    /// A set of registers which are live and cannot be changed to
67    /// break anti-dependencies.
68    BitVector KeepRegs;
69
70  public:
71    CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo&);
72    ~CriticalAntiDepBreaker() override;
73
74    /// Initialize anti-dep breaking for a new basic block.
75    void StartBlock(MachineBasicBlock *BB) override;
76
77    /// Identifiy anti-dependencies along the critical path
78    /// of the ScheduleDAG and break them by renaming registers.
79    unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
80                                   MachineBasicBlock::iterator Begin,
81                                   MachineBasicBlock::iterator End,
82                                   unsigned InsertPosIndex,
83                                   DbgValueVector &DbgValues) override;
84
85    /// Update liveness information to account for the current
86    /// instruction, which will not be scheduled.
87    void Observe(MachineInstr *MI, unsigned Count,
88                 unsigned InsertPosIndex) override;
89
90    /// Finish anti-dep breaking for a basic block.
91    void FinishBlock() override;
92
93  private:
94    void PrescanInstruction(MachineInstr *MI);
95    void ScanInstruction(MachineInstr *MI, unsigned Count);
96    bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
97                                 RegRefIter RegRefEnd,
98                                 unsigned NewReg);
99    unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
100                                      RegRefIter RegRefEnd,
101                                      unsigned AntiDepReg,
102                                      unsigned LastNewReg,
103                                      const TargetRegisterClass *RC,
104                                      SmallVectorImpl<unsigned> &Forbid);
105  };
106}
107
108#endif
109