ARMInstrThumb2.td revision 3583df7676bd194faf21eb24ff7790928502852a
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Shifted operands. No register controlled shifts for Thumb2. 25// Note: We do not support rrx shifted operands yet. 26def t2_so_reg : Operand<i32>, // reg imm 27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 28 [shl,srl,sra,rotr]> { 29 let PrintMethod = "printT2SOOperand"; 30 let MIOperandInfo = (ops GPR, i32imm); 31} 32 33// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 34def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 36}]>; 37 38// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 39def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm - Match a 32-bit immediate operand, which is an 44// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 45// immediate splatted into multiple bytes of the word. t2_so_imm values are 46// represented in the imm field in the same 12-bit form that they are encoded 47// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 48// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 49def t2_so_imm : Operand<i32>, 50 PatLeaf<(imm), [{ 51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 52}]>; 53 54// t2_so_imm_not - Match an immediate that is a complement 55// of a t2_so_imm. 56def t2_so_imm_not : Operand<i32>, 57 PatLeaf<(imm), [{ 58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 59}], t2_so_imm_not_XFORM>; 60 61// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 62def t2_so_imm_neg : Operand<i32>, 63 PatLeaf<(imm), [{ 64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 65}], t2_so_imm_neg_XFORM>; 66 67/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 68def imm1_31 : PatLeaf<(i32 imm), [{ 69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 70}]>; 71 72/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 73def imm0_4095 : PatLeaf<(i32 imm), [{ 74 return (uint32_t)N->getZExtValue() < 4096; 75}]>; 76 77def imm0_4095_neg : PatLeaf<(i32 imm), [{ 78 return (uint32_t)(-N->getZExtValue()) < 4096; 79}], imm_neg_XFORM>; 80 81/// imm0_65535 predicate - True if the 32-bit immediate is in the range 82/// [0.65535]. 83def imm0_65535 : PatLeaf<(i32 imm), [{ 84 return (uint32_t)N->getZExtValue() < 65536; 85}]>; 86 87/// Split a 32-bit immediate into two 16 bit parts. 88def t2_lo16 : SDNodeXForm<imm, [{ 89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, 90 MVT::i32); 91}]>; 92 93def t2_hi16 : SDNodeXForm<imm, [{ 94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 95}]>; 96 97def t2_lo16AllZero : PatLeaf<(i32 imm), [{ 98 // Returns true if all low 16-bits are 0. 99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 100 }], t2_hi16>; 101 102 103// Define Thumb2 specific addressing modes. 104 105// t2addrmode_imm12 := reg + imm12 106def t2addrmode_imm12 : Operand<i32>, 107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 108 let PrintMethod = "printT2AddrModeImm12Operand"; 109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 110} 111 112// t2addrmode_imm8 := reg - imm8 113def t2addrmode_imm8 : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 115 let PrintMethod = "printT2AddrModeImm8Operand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119def t2am_imm8_offset : Operand<i32>, 120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 121 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 122} 123 124// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 125def t2addrmode_imm8s4 : Operand<i32>, 126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 127 let PrintMethod = "printT2AddrModeImm8s4Operand"; 128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 129} 130 131// t2addrmode_so_reg := reg + (reg << imm2) 132def t2addrmode_so_reg : Operand<i32>, 133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 134 let PrintMethod = "printT2AddrModeSoRegOperand"; 135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 136} 137 138 139//===----------------------------------------------------------------------===// 140// Multiclass helpers... 141// 142 143/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 144/// unary operation that produces a value. These are predicable and can be 145/// changed to modify CPSR. 146multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 147 // shifted imm 148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 149 opc, " $dst, $src", 150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 151 let isAsCheapAsAMove = Cheap; 152 let isReMaterializable = ReMat; 153 } 154 // register 155 def r : T2I<(outs GPR:$dst), (ins GPR:$src), 156 opc, ".w $dst, $src", 157 [(set GPR:$dst, (opnode GPR:$src))]>; 158 // shifted register 159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), 160 opc, ".w $dst, $src", 161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 162} 163 164/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 165// binary operation that produces a value. These are predicable and can be 166/// changed to modify CPSR. 167multiclass T2I_bin_irs<string opc, PatFrag opnode, 168 bit Commutable = 0, string wide =""> { 169 // shifted imm 170 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 171 opc, " $dst, $lhs, $rhs", 172 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 173 // register 174 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 175 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 176 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 177 let isCommutable = Commutable; 178 } 179 // shifted register 180 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 181 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 182 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 183} 184 185/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 186// the ".w" prefix to indicate that they are wide. 187multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> : 188 T2I_bin_irs<opc, opnode, Commutable, ".w">; 189 190/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 191/// reversed. It doesn't define the 'rr' form since it's handled by its 192/// T2I_bin_irs counterpart. 193multiclass T2I_rbin_is<string opc, PatFrag opnode> { 194 // shifted imm 195 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), 196 opc, ".w $dst, $rhs, $lhs", 197 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 198 // shifted register 199 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), 200 opc, " $dst, $rhs, $lhs", 201 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 202} 203 204/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 205/// instruction modifies the CPSR register. 206let Defs = [CPSR] in { 207multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 208 // shifted imm 209 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 210 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 211 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 212 // register 213 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 214 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 215 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 216 let isCommutable = Commutable; 217 } 218 // shifted register 219 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 220 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 221 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 222} 223} 224 225/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 226/// patterns for a binary operation that produces a value. 227multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 228 // shifted imm 229 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 230 opc, ".w $dst, $lhs, $rhs", 231 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 232 // 12-bit imm 233 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 234 !strconcat(opc, "w"), " $dst, $lhs, $rhs", 235 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 236 // register 237 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 238 opc, ".w $dst, $lhs, $rhs", 239 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 240 let isCommutable = Commutable; 241 } 242 // shifted register 243 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 244 opc, ".w $dst, $lhs, $rhs", 245 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 246} 247 248/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 249/// binary operation that produces a value and use and define the carry bit. 250/// It's not predicable. 251let Uses = [CPSR] in { 252multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 253 // shifted imm 254 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 255 opc, " $dst, $lhs, $rhs", 256 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 257 Requires<[IsThumb2, CarryDefIsUnused]>; 258 // register 259 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 260 opc, ".w $dst, $lhs, $rhs", 261 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 262 Requires<[IsThumb2, CarryDefIsUnused]> { 263 let isCommutable = Commutable; 264 } 265 // shifted register 266 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 267 opc, ".w $dst, $lhs, $rhs", 268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 269 Requires<[IsThumb2, CarryDefIsUnused]>; 270 // Carry setting variants 271 // shifted imm 272 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 273 !strconcat(opc, "s $dst, $lhs, $rhs"), 274 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 275 Requires<[IsThumb2, CarryDefIsUsed]> { 276 let Defs = [CPSR]; 277 } 278 // register 279 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 280 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 281 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 282 Requires<[IsThumb2, CarryDefIsUsed]> { 283 let Defs = [CPSR]; 284 let isCommutable = Commutable; 285 } 286 // shifted register 287 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 288 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 289 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 290 Requires<[IsThumb2, CarryDefIsUsed]> { 291 let Defs = [CPSR]; 292 } 293} 294} 295 296/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 297let Defs = [CPSR] in { 298multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 299 // shifted imm 300 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 301 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"), 302 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 303 // shifted register 304 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 305 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 306 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 307} 308} 309 310/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 311// rotate operation that produces a value. 312multiclass T2I_sh_ir<string opc, PatFrag opnode> { 313 // 5-bit imm 314 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 315 opc, ".w $dst, $lhs, $rhs", 316 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 317 // register 318 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 319 opc, ".w $dst, $lhs, $rhs", 320 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 321} 322 323/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 324/// patterns. Similar to T2I_bin_irs except the instruction does not produce 325/// a explicit result, only implicitly set CPSR. 326let Defs = [CPSR] in { 327multiclass T2I_cmp_is<string opc, PatFrag opnode> { 328 // shifted imm 329 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), 330 opc, ".w $lhs, $rhs", 331 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 332 // register 333 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), 334 opc, ".w $lhs, $rhs", 335 [(opnode GPR:$lhs, GPR:$rhs)]>; 336 // shifted register 337 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), 338 opc, ".w $lhs, $rhs", 339 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 340} 341} 342 343/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 344multiclass T2I_ld<string opc, PatFrag opnode> { 345 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), 346 opc, ".w $dst, $addr", 347 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 348 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), 349 opc, " $dst, $addr", 350 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 351 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), 352 opc, ".w $dst, $addr", 353 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 354 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), 355 opc, ".w $dst, $addr", 356 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; 357} 358 359/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 360multiclass T2I_st<string opc, PatFrag opnode> { 361 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), 362 opc, ".w $src, $addr", 363 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 364 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), 365 opc, " $src, $addr", 366 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 367 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), 368 opc, ".w $src, $addr", 369 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 370} 371 372/// T2I_picld - Defines the PIC load pattern. 373class T2I_picld<string opc, PatFrag opnode> : 374 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), 375 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr", 376 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 377 378/// T2I_picst - Defines the PIC store pattern. 379class T2I_picst<string opc, PatFrag opnode> : 380 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), 381 !strconcat("${addr:label}:\n\t", opc), " $src, $addr", 382 [(opnode GPR:$src, addrmodepc:$addr)]>; 383 384 385/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 386/// register and one whose operand is a register rotated by 8/16/24. 387multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 388 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), 389 opc, ".w $dst, $Src", 390 [(set GPR:$dst, (opnode GPR:$Src))]>; 391 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), 392 opc, ".w $dst, $Src, ror $rot", 393 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>; 394} 395 396/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 397/// register and one whose operand is a register rotated by 8/16/24. 398multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 399 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 400 opc, " $dst, $LHS, $RHS", 401 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 402 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 403 opc, " $dst, $LHS, $RHS, ror $rot", 404 [(set GPR:$dst, (opnode GPR:$LHS, 405 (rotr GPR:$RHS, rot_imm:$rot)))]>; 406} 407 408//===----------------------------------------------------------------------===// 409// Instructions 410//===----------------------------------------------------------------------===// 411 412//===----------------------------------------------------------------------===// 413// Miscellaneous Instructions. 414// 415 416let isNotDuplicable = 1 in 417def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), 418 "$cp:\n\tadd.w $dst, $lhs, pc", 419 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; 420 421 422// LEApcrel - Load a pc-relative address into a register without offending the 423// assembler. 424def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), 425 "adr$p.w $dst, #$label", []>; 426 427def t2LEApcrelJT : T2XI<(outs GPR:$dst), 428 (ins i32imm:$label, i32imm:$id, pred:$p), 429 "adr$p.w $dst, #${label}_${id:no_hash}", []>; 430 431//===----------------------------------------------------------------------===// 432// Load / store Instructions. 433// 434 435// Load 436let canFoldAsLoad = 1 in 437defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 438 439// Loads with zero extension 440defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 441defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 442 443// Loads with sign extension 444defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 445defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 446 447let mayLoad = 1 in { 448// Load doubleword 449def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), 450 "ldrd", " $dst, $addr", []>; 451def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), 452 "ldrd", " $dst, $addr", []>; 453} 454 455// zextload i1 -> zextload i8 456def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 457 (t2LDRBi12 t2addrmode_imm12:$addr)>; 458def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 459 (t2LDRBi8 t2addrmode_imm8:$addr)>; 460def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 461 (t2LDRBs t2addrmode_so_reg:$addr)>; 462def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 463 (t2LDRBpci tconstpool:$addr)>; 464 465// extload -> zextload 466// FIXME: Reduce the number of patterns by legalizing extload to zextload 467// earlier? 468def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 469 (t2LDRBi12 t2addrmode_imm12:$addr)>; 470def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 471 (t2LDRBi8 t2addrmode_imm8:$addr)>; 472def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 473 (t2LDRBs t2addrmode_so_reg:$addr)>; 474def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 475 (t2LDRBpci tconstpool:$addr)>; 476 477def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 478 (t2LDRBi12 t2addrmode_imm12:$addr)>; 479def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 480 (t2LDRBi8 t2addrmode_imm8:$addr)>; 481def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 482 (t2LDRBs t2addrmode_so_reg:$addr)>; 483def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 484 (t2LDRBpci tconstpool:$addr)>; 485 486def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 487 (t2LDRHi12 t2addrmode_imm12:$addr)>; 488def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 489 (t2LDRHi8 t2addrmode_imm8:$addr)>; 490def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 491 (t2LDRHs t2addrmode_so_reg:$addr)>; 492def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 493 (t2LDRHpci tconstpool:$addr)>; 494 495// Indexed loads 496let mayLoad = 1 in { 497def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 498 (ins t2addrmode_imm8:$addr), 499 AddrModeT2_i8, IndexModePre, 500 "ldr", " $dst, $addr!", "$addr.base = $base_wb", 501 []>; 502 503def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 504 (ins GPR:$base, t2am_imm8_offset:$offset), 505 AddrModeT2_i8, IndexModePost, 506 "ldr", " $dst, [$base], $offset", "$base = $base_wb", 507 []>; 508 509def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 510 (ins t2addrmode_imm8:$addr), 511 AddrModeT2_i8, IndexModePre, 512 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", 513 []>; 514def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 515 (ins GPR:$base, t2am_imm8_offset:$offset), 516 AddrModeT2_i8, IndexModePost, 517 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", 518 []>; 519 520def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 521 (ins t2addrmode_imm8:$addr), 522 AddrModeT2_i8, IndexModePre, 523 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", 524 []>; 525def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 526 (ins GPR:$base, t2am_imm8_offset:$offset), 527 AddrModeT2_i8, IndexModePost, 528 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", 529 []>; 530 531def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 532 (ins t2addrmode_imm8:$addr), 533 AddrModeT2_i8, IndexModePre, 534 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", 535 []>; 536def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 537 (ins GPR:$base, t2am_imm8_offset:$offset), 538 AddrModeT2_i8, IndexModePost, 539 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", 540 []>; 541 542def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 543 (ins t2addrmode_imm8:$addr), 544 AddrModeT2_i8, IndexModePre, 545 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", 546 []>; 547def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 548 (ins GPR:$base, t2am_imm8_offset:$offset), 549 AddrModeT2_i8, IndexModePost, 550 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", 551 []>; 552} 553 554// Store 555defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 556defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 557defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 558 559// Store doubleword 560let mayLoad = 1 in 561def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), 562 "strd", " $src, $addr", []>; 563 564// Indexed stores 565def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 566 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 567 AddrModeT2_i8, IndexModePre, 568 "str", " $src, [$base, $offset]!", "$base = $base_wb", 569 [(set GPR:$base_wb, 570 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 571 572def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 573 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 574 AddrModeT2_i8, IndexModePost, 575 "str", " $src, [$base], $offset", "$base = $base_wb", 576 [(set GPR:$base_wb, 577 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 578 579def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 580 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 581 AddrModeT2_i8, IndexModePre, 582 "strh", " $src, [$base, $offset]!", "$base = $base_wb", 583 [(set GPR:$base_wb, 584 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 585 586def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 587 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 588 AddrModeT2_i8, IndexModePost, 589 "strh", " $src, [$base], $offset", "$base = $base_wb", 590 [(set GPR:$base_wb, 591 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 592 593def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 594 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 595 AddrModeT2_i8, IndexModePre, 596 "strb", " $src, [$base, $offset]!", "$base = $base_wb", 597 [(set GPR:$base_wb, 598 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 599 600def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 601 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 602 AddrModeT2_i8, IndexModePost, 603 "strb", " $src, [$base], $offset", "$base = $base_wb", 604 [(set GPR:$base_wb, 605 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 606 607 608// FIXME: ldrd / strd pre / post variants 609 610//===----------------------------------------------------------------------===// 611// Load / store multiple Instructions. 612// 613 614let mayLoad = 1 in 615def t2LDM : T2XI<(outs), 616 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 617 "ldm${addr:submode}${p}.w $addr, $dst1", []>; 618 619let mayStore = 1 in 620def t2STM : T2XI<(outs), 621 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 622 "stm${addr:submode}${p}.w $addr, $src1", []>; 623 624//===----------------------------------------------------------------------===// 625// Move Instructions. 626// 627 628let neverHasSideEffects = 1 in 629def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), 630 "mov", ".w $dst, $src", []>; 631 632let isReMaterializable = 1, isAsCheapAsAMove = 1 in 633def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 634 "mov", ".w $dst, $src", 635 [(set GPR:$dst, t2_so_imm:$src)]>; 636 637let isReMaterializable = 1, isAsCheapAsAMove = 1 in 638def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), 639 "movw", " $dst, $src", 640 [(set GPR:$dst, imm0_65535:$src)]>; 641 642// FIXME: Also available in ARM mode. 643let Constraints = "$src = $dst" in 644def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), 645 "movt", " $dst, $imm", 646 [(set GPR:$dst, 647 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; 648 649//===----------------------------------------------------------------------===// 650// Extend Instructions. 651// 652 653// Sign extenders 654 655defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 656defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 657 658defm t2SXTAB : T2I_bin_rrot<"sxtab", 659 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 660defm t2SXTAH : T2I_bin_rrot<"sxtah", 661 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 662 663// TODO: SXT(A){B|H}16 664 665// Zero extenders 666 667let AddedComplexity = 16 in { 668defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 669defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 670defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 671 672def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 673 (t2UXTB16r_rot GPR:$Src, 24)>; 674def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 675 (t2UXTB16r_rot GPR:$Src, 8)>; 676 677defm t2UXTAB : T2I_bin_rrot<"uxtab", 678 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 679defm t2UXTAH : T2I_bin_rrot<"uxtah", 680 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 681} 682 683//===----------------------------------------------------------------------===// 684// Arithmetic Instructions. 685// 686 687defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 688defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 689 690// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 691defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 692defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 693 694defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 695defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 696 697// RSB 698defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 699defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 700 701// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 702def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 703 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 704def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 705 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 706 707 708//===----------------------------------------------------------------------===// 709// Shift and rotate Instructions. 710// 711 712defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 713defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 714defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 715defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 716 717def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), 718 "rrx", " $dst, $src", 719 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 720 721let Defs = [CPSR] in { 722def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), 723 "lsrs.w $dst, $src, #1", 724 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 725def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), 726 "asrs.w $dst, $src, #1", 727 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 728} 729 730//===----------------------------------------------------------------------===// 731// Bitwise Instructions. 732// 733 734defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 735defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 736defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 737 738defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 739 740let Constraints = "$src = $dst" in 741def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 742 "bfc", " $dst, $imm", 743 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 744 745// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 746 747defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 748 749// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 750let AddedComplexity = 1 in 751defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 752 753 754def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 755 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 756 757def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 758 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>; 759 760def : T2Pat<(t2_so_imm_not:$src), 761 (t2MVNi t2_so_imm_not:$src)>; 762 763//===----------------------------------------------------------------------===// 764// Multiply Instructions. 765// 766let isCommutable = 1 in 767def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 768 "mul", " $dst, $a, $b", 769 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 770 771def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 772 "mla", " $dst, $a, $b, $c", 773 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 774 775def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 776 "mls", " $dst, $a, $b, $c", 777 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 778 779// Extra precision multiplies with low / high results 780let neverHasSideEffects = 1 in { 781let isCommutable = 1 in { 782def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 783 "smull", " $ldst, $hdst, $a, $b", []>; 784 785def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 786 "umull", " $ldst, $hdst, $a, $b", []>; 787} 788 789// Multiply + accumulate 790def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 791 "smlal", " $ldst, $hdst, $a, $b", []>; 792 793def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 794 "umlal", " $ldst, $hdst, $a, $b", []>; 795 796def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 797 "umaal", " $ldst, $hdst, $a, $b", []>; 798} // neverHasSideEffects 799 800// Most significant word multiply 801def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 802 "smmul", " $dst, $a, $b", 803 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 804 805def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 806 "smmla", " $dst, $a, $b, $c", 807 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 808 809 810def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 811 "smmls", " $dst, $a, $b, $c", 812 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 813 814multiclass T2I_smul<string opc, PatFrag opnode> { 815 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 816 !strconcat(opc, "bb"), " $dst, $a, $b", 817 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 818 (sext_inreg GPR:$b, i16)))]>; 819 820 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 821 !strconcat(opc, "bt"), " $dst, $a, $b", 822 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 823 (sra GPR:$b, (i32 16))))]>; 824 825 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 826 !strconcat(opc, "tb"), " $dst, $a, $b", 827 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 828 (sext_inreg GPR:$b, i16)))]>; 829 830 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 831 !strconcat(opc, "tt"), " $dst, $a, $b", 832 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 833 (sra GPR:$b, (i32 16))))]>; 834 835 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 836 !strconcat(opc, "wb"), " $dst, $a, $b", 837 [(set GPR:$dst, (sra (opnode GPR:$a, 838 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 839 840 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 841 !strconcat(opc, "wt"), " $dst, $a, $b", 842 [(set GPR:$dst, (sra (opnode GPR:$a, 843 (sra GPR:$b, (i32 16))), (i32 16)))]>; 844} 845 846 847multiclass T2I_smla<string opc, PatFrag opnode> { 848 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 849 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 850 [(set GPR:$dst, (add GPR:$acc, 851 (opnode (sext_inreg GPR:$a, i16), 852 (sext_inreg GPR:$b, i16))))]>; 853 854 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 855 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 856 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 857 (sra GPR:$b, (i32 16)))))]>; 858 859 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 860 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 861 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 862 (sext_inreg GPR:$b, i16))))]>; 863 864 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 865 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 866 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 867 (sra GPR:$b, (i32 16)))))]>; 868 869 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 870 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 871 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 872 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 873 874 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 875 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 876 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 877 (sra GPR:$b, (i32 16))), (i32 16))))]>; 878} 879 880defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 881defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 882 883// TODO: Halfword multiple accumulate long: SMLAL<x><y> 884// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 885 886 887//===----------------------------------------------------------------------===// 888// Misc. Arithmetic Instructions. 889// 890 891def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), 892 "clz", " $dst, $src", 893 [(set GPR:$dst, (ctlz GPR:$src))]>; 894 895def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), 896 "rev", ".w $dst, $src", 897 [(set GPR:$dst, (bswap GPR:$src))]>; 898 899def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), 900 "rev16", ".w $dst, $src", 901 [(set GPR:$dst, 902 (or (and (srl GPR:$src, (i32 8)), 0xFF), 903 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 904 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 905 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 906 907def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), 908 "revsh", ".w $dst, $src", 909 [(set GPR:$dst, 910 (sext_inreg 911 (or (srl (and GPR:$src, 0xFFFF), (i32 8)), 912 (shl GPR:$src, (i32 8))), i16))]>; 913 914def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 915 "pkhbt", " $dst, $src1, $src2, LSL $shamt", 916 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 917 (and (shl GPR:$src2, (i32 imm:$shamt)), 918 0xFFFF0000)))]>; 919 920// Alternate cases for PKHBT where identities eliminate some nodes. 921def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 922 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 923def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 924 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 925 926def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 927 "pkhtb", " $dst, $src1, $src2, ASR $shamt", 928 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 929 (and (sra GPR:$src2, imm16_31:$shamt), 930 0xFFFF)))]>; 931 932// Alternate cases for PKHTB where identities eliminate some nodes. Note that 933// a shift amount of 0 is *not legal* here, it is PKHBT instead. 934def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 935 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 936def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 937 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 938 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 939 940//===----------------------------------------------------------------------===// 941// Comparison Instructions... 942// 943 944defm t2CMP : T2I_cmp_is<"cmp", 945 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 946defm t2CMPz : T2I_cmp_is<"cmp", 947 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 948 949defm t2CMN : T2I_cmp_is<"cmn", 950 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 951defm t2CMNz : T2I_cmp_is<"cmn", 952 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 953 954def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 955 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 956 957def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 958 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 959 960defm t2TST : T2I_cmp_is<"tst", 961 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 962defm t2TEQ : T2I_cmp_is<"teq", 963 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 964 965// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 966// Short range conditional branch. Looks awesome for loops. Need to figure 967// out how to use this one. 968 969 970// Conditional moves 971// FIXME: should be able to write a pattern for ARMcmov, but can't use 972// a two-value operand where a dag node expects two operands. :( 973def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), 974 "mov", " $dst, $true", 975 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 976 RegConstraint<"$false = $dst">; 977 978def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true), 979 "mov", " $dst, $true", 980[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 981 RegConstraint<"$false = $dst">; 982 983def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 984 "mov", " $dst, $true", 985[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 986 RegConstraint<"$false = $dst">; 987 988//===----------------------------------------------------------------------===// 989// TLS Instructions 990// 991 992// __aeabi_read_tp preserves the registers r1-r3. 993let isCall = 1, 994 Defs = [R0, R12, LR, CPSR] in { 995 def t2TPsoft : T2XI<(outs), (ins), 996 "bl __aeabi_read_tp", 997 [(set R0, ARMthread_pointer)]>; 998} 999 1000//===----------------------------------------------------------------------===// 1001// Control-Flow Instructions 1002// 1003 1004// FIXME: remove when we have a way to marking a MI with these properties. 1005// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1006// operand list. 1007// FIXME: Should pc be an implicit operand like PICADD, etc? 1008let isReturn = 1, isTerminator = 1, mayLoad = 1 in 1009 def t2LDM_RET : T2XI<(outs), 1010 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 1011 "ldm${addr:submode}${p} $addr, $dst1", 1012 []>; 1013 1014// On non-Darwin platforms R9 is callee-saved. 1015let isCall = 1, 1016 Defs = [R0, R1, R2, R3, R12, LR, 1017 D0, D1, D2, D3, D4, D5, D6, D7, 1018 D16, D17, D18, D19, D20, D21, D22, D23, 1019 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in { 1020def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops), 1021 "bl ${func:call}", 1022 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; 1023 1024def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops), 1025 "blx $func", 1026 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>; 1027} 1028 1029// On Darwin R9 is call-clobbered. 1030let isCall = 1, 1031 Defs = [R0, R1, R2, R3, R9, R12, LR, 1032 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 1033def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops), 1034 "bl ${func:call}", 1035 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>; 1036 1037def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops), 1038 "blx $func", 1039 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>; 1040} 1041 1042let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1043let isPredicable = 1 in 1044def t2B : T2XI<(outs), (ins brtarget:$target), 1045 "b.w $target", 1046 [(br bb:$target)]>; 1047 1048let isNotDuplicable = 1, isIndirectBranch = 1 in 1049def t2BR_JT : 1050 T2JTI<(outs), 1051 (ins GPR:$base, GPR:$idx, jt2block_operand:$jt, i32imm:$id), 1052 "add.w pc, $base, $idx, lsl #2\n$jt", 1053 [(ARMbr2jt GPR:$base, GPR:$idx, tjumptable:$jt, imm:$id)]>; 1054} // isBranch, isTerminator, isBarrier 1055 1056// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1057// a two-value operand where a dag node expects two operands. :( 1058let isBranch = 1, isTerminator = 1 in 1059def t2Bcc : T2I<(outs), (ins brtarget:$target), 1060 "b", ".w $target", 1061 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1062 1063 1064// IT block 1065def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1066 AddrModeNone, Size2Bytes, 1067 "it$mask $cc", "", []>; 1068 1069//===----------------------------------------------------------------------===// 1070// Non-Instruction Patterns 1071// 1072 1073// ConstantPool, GlobalAddress, and JumpTable 1074def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1075def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1076def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1077 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1078 1079// Large immediate handling. 1080 1081def : T2Pat<(i32 imm:$src), 1082 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>; 1083