| cddc3e03e4ec99c0268c03a126195173e519ed58 |
|
04-Mar-2016 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r256229
http://b/26987366
(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)
Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6948897e478cbd66626159776a8017b3c18579b9 |
|
01-Jul-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r239765
Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.
Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0c7f116bb6950ef819323d855415b2f2b0aad987 |
|
06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2b01682aa7b9509e9fa1865ebed3d0a7928f5b7a |
|
08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f635ab8eabb06a41fa791d897ebf32eb338688a0 |
|
05-Nov-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 47c6d17b1cce85ba30471b2270419e35ba3d5653 |
|
29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
ARM: Add subtarget feature for CRC
Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend.
Differential Revision: http://llvm-reviews.chandlerc.com/D2036
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b161955ffbda5ccb5293e0c76ef982acb6ec6661 |
|
23-Oct-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
Make ARM hint ranges consistent, and add tests for these ranges
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 485333df7157d6e8681d910d85b271b0bc96b48e |
|
18-Oct-2013 |
Richard Barton <richard.barton@arm.com> |
Add hint disassembly syntax for 16-bit Thumb hint instructions.
Patch by Artyom Skrobov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6eef361b73b457896b310d411251aedd5e72476a |
|
03-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bba9390fc6c0d536172c6bb4a9c93db557c1aff4 |
|
01-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.
rdar://problem/14207019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d1311ac171f9cb90cab4906a6c0e091b6b65b862 |
|
01-Oct-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 268c743a3ba44ada364938bc5ff9b1be219df54f |
|
26-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0f22c134be40a337b30e30bdafb9e8b6880dea1e |
|
23-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Split A/R class into separate subtarget features.
Patch by Bradley Smith.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a4d46d7fc6431ec3576839f11cb61862b784cb3e |
|
18-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add CRC instructions.
Patch by Bradley Smith!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dc0de80f24a83336cb26dcb9ed1fa030142a504d |
|
17-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4897151df698197f0eb5c4085545312dbb20c94d |
|
05-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Implement the new DMB/DSB operands.
This removes the custom ISD Node: MEMBARRIER and replaces it
with an intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b5523ce1bb50e86942ad5273e3a89872c4d26b73 |
|
05-Sep-2013 |
Richard Barton <richard.barton@arm.com> |
Add AArch32 DCPS{1,2,3} and HLT instructions.
These were pretty straightforward instructions, with some assembly support
required for HLT.
The ARM assembler is keen to split the instruction mnemonic into a
(non-existent) 'H' instruction with the LT condition code. An exception for
HLT is needed.
HLT follows the same rules as BKPT when in IT blocks, so the special BKPT
hadling code has been adapted to handle HLT also.
Regression tests added including diagnostic tests for out of range immediates
and illegal condition codes, as well as negative tests for pre-ARMv8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8f3d54d057007552d0abc37c87a50ef34a7ab9ef |
|
05-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 10b5086e6e945b830ff909821240eff5c4a42bfc |
|
05-Sep-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.
Patch by Daniel Stewart!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b2e5453821ef27306036a9961818cf530a3ca8cb |
|
28-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8]
Fix a few things in one swoop.
# Add some negative tests.
# Fix some formatting issues.
# Add some missing IsThumb / ARMv8
# Fix some outs / ins mistakes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bafb5f8d9f415340d9035ee9430f9480da9a50fb |
|
28-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add a missing IsThumb to t2LDAEXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0b90c6223d9c49b5e0dc4bf4e53796b0714d7b80 |
|
27-Aug-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Add MC support for the new load/store acquire/release instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 |
|
22-Aug-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: use TableGen patterns to select CMOV operations.
Back in the mists of time (2008), it seems TableGen couldn't handle the
patterns necessary to match ARM's CMOV node that we convert select operations
to, so we wrote a lot of fairly hairy C++ to do it for us.
TableGen can deal with it now: there were a few minor differences to CodeGen
(see tests), but nothing obviously worse that I could see, so we should
probably address anything that *does* come up in a localised manner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1a9f21abac47dcea0c62341b0ee4fd35481350b8 |
|
21-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Make "mov" work for all Thumb2 MOV encodings
According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings.
To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 756e89c8c2a3c30ce3a73ed13724aad1b41a5608 |
|
19-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Thumb2 add immediate alias for SP
The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction.
All the patch does is adjust a register constraint on an instruction alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8b36f9e4314ac4d786d2d4fd5fa9e7858487ee9e |
|
16-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix Thumb2 aliasing complementary instructions taking modified immediates
There are many Thumb instructions which take 12-bit immediates encoded in a special
8-byte value + 4-byte rotator form. Not all numbers are represented, and it's legal
to transform an assembly instruction to be able to encode the immediate.
For example: AND and BIC are complementary instructions; one can switch the AND
to a BIC as long as the immediate is complemented.
The intent is to switch one instruction into its complementary one when the immediate
cannot be encoded in the form requested in the original assembly and when the
complementary immediate is encodable.
The patch addresses two issues:
1. definition of t2SOImmNot immediate - it has to check that the orignal value is
not encoded naturally
2. t2AND and t2BIC instruction aliases which should use the Thumb2 SOImm operand
rather than the ARM one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 428715d4e120e6ef6fc898665607a92f3dd02709 |
|
15-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes three issues related to Thumb literal loads:
1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020]
2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed
3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen
and the ASM parser, so this alias rule really does nothing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 04b03fac11f10c92cf7ce63ba2f548a42ee2c448 |
|
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This fixes the Thumb2 CPS assembly syntax.
In Thumb1, only one variant is supported: CPS{effect} {flags}
Thumb2 supports three:
CPS{effect}.W {flags}
CPS{effect} {flags} {mode}
CPS {mode}
Canonically, .W should be used only when ambiguity is present between encodings of different width.
The wide suffix is still accepted for the latter two forms via aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e921f323533ee751b3fa34bd00d10fa72096ffd3 |
|
09-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Fix assembling of Thumb2 branch instructions.
The long encoding for Thumb2 unconditional branches is broken.
Additionally, there is no range checking for target operands; as such
for instructions originating in assembly code, only short Thumb encodings
are generated, regardless of the bitsize needed for the offset.
Adding range checking is non trivial due to the representation of Thumb
branch instructions. There is no true difference between conditional and
unconditional branches in terms of operands and syntax - even unconditional
branches have a predicate which is expected to match that of the IT block
they are in. Yet, the encodings and the permitted size of the offset differ.
Due to this, for any mnemonic there are really 4 encodings to choose for.
The problem cannot be handled in the parser alone or by manipulating td files.
Because the parser builds first a set of match candidates and then checks them
one by one, whatever tablegen-only solution might be found will ultimately be
dependent of the parser's evaluation order. What's worse is that due to the fact
that all branches have the same syntax and the same kinds of operands, that
order is governed by the lexicographical ordering of the names of operand
classes...
To circumvent all this, any necessary disambiguation is added to the instruction
validation pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 868bed99674cf19e5cb475945f3067f0f4cc421e |
|
08-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
The name "tCDP" isn't used anywhere else in the source code, so renaming it for consistency doesn't cause any problems.
This is the only Thumb2 instruction defined with "t" prefix; all other Thumb2 instructions have "t2" prefix (e.g. "t2CDP2" which is defined immediately afterwards).
Patch by Artyom Skrobov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4f7092176c3d3eaae0ea7af26aec2d77b3e4035f |
|
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,
as pldw does not have a literal variant (i.e. pc relative version)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4a378b95aa0f24ba461e512608b8aaeaa803996f |
|
06-Aug-2013 |
Mihai Popa <mihail.popa@gmail.com> |
Support APSR_nzcv as operand for Thumb2 mrc. Deprecate pre-UAL syntax (pc instead of apsr_nzcv)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e38070fc32818a6e412dafbb8b3807b413d0819e |
|
31-Jul-2013 |
Kevin Enderby <enderby@apple.com> |
Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.
While the .td entry is nice and all, it takes a pretty gross hack in
ARMAsmParser::ParseInstruction() because of handling of other "subs"
instructions to get it to match. Ran it by Jim Grosbach and he said it was
about what he expected to make this work given the existing code.
rdar://14214063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 02265382929b0275d7b7b334eab5e2fd34e1b9fe |
|
22-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:
1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1c6e6ce10c61f8db656a04af36e2b374c0fe9566 |
|
22-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: remove now unneeded custom Asm converters
After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cae5d5ea658e05091e66b742b5834f1896ff2f5d |
|
19-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.
Related to <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bbcea55b68fad8116c29b3e831c5df398d558569 |
|
19-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Make sure the instruction alias for PLI uses the right subtarget features.
PLI requires both the Thumb2 and the ARMv7 feature.
Related to <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 898788c6bcc2abfe0e1c7b21c14394352963acd6 |
|
16-Jul-2013 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
ARM: Add support for the Thumb2 PLI alternate literal form.
This adds an instruction alias to make the assembler recognize the alternate literal form: pli [PC, #+/-<imm>]
See A8.8.129 in the ARM ARM (DDI 0406C.b).
Fixes <rdar://problem/14403733>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2f438131f115a3860ee344a827a091790d6dc13d |
|
16-Jul-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: implement ldrex, strex and clrex intrinsics
Intrinsics already existed for the 64-bit variants, so these support operations
of size at most 32-bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 97c37bb4d4ae5e505350091e520a1354069941e0 |
|
10-Jul-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Fix incorrect pack pattern for thumb2
Propagate the fix from r185712 to Thumb2 codegen as well. Original
commit message applies here as well:
A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and
packs them in the bottom half of "x". An arithmetic and logic shift are
only equivalent in this context if the shift amount is 16. We would be
shifting in ones into the bottom 16bits instead of zeros if "y" is
negative.
rdar://14338767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b81b477cd4392a51112c3af0659ea9fc176e74f1 |
|
03-Jul-2013 |
Mihai Popa <mihail.popa@gmail.com> |
This corrects the implementation of Thumb ADR instruction. There are three issues:
1. it should accept only 4-byte aligned addresses
2. the maximum offset should be 1020
3. it should be encoded with the offset scaled by two bits
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c19bd321362166805194cbaf170e06a4790d2da9 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c1a91dd97b000128189421eda6c5bb7905b1f467 |
|
26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0c9f0c047dfba91bc7c0fb66f7e868e917d37c4c |
|
24-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: enable decoding of pc-relative PLD/PLI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| beb920fce6ccc89b4735f280f94cb8c227f4ef5e |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix literal load with positive offset encoding
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly
This patch also makes the assembler look at the .w/.n specifier for
loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f8b60d6f30a8f25c84a71d36ff3a86fe1f52f671 |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: add operands pre-writeback variants when needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ce046b98ed6c351779fc43599a80d588752bc1ca |
|
18-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb literal loads decoding
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a768a4954818456fa6fe2077a3cbe75979025c15 |
|
14-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: fix thumb coprocessor instruction with pre-writeback disassembly
was stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4e9a96d810eb0cc126ebe6f18e536b474c84940c |
|
10-Jun-2013 |
Amaury de la Vieuville <amaury.dlv@gmail.com> |
ARM: ISB cannot be passed the same options as DMB
ISB should only accepts full system sync, other options are reserved
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a6db67719754168c7e491bb814264a3bddbd8534 |
|
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb2 instructions
Reapply 183264.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3ba4778c9579739748810d78befd1752dc71acb6 |
|
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload thumb2 instructions
Reapply 183262.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 826de688b06552125b94a3d1e038f5326d53435f |
|
06-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb2 instructions
Reapply of 183259.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8a227084a5b07fa289c34f2b36e12f75b47473d6 |
|
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 16d915018b303e69c409bed15e29ac6906b1fe92 |
|
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add branch thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fdbca2faac8ebc3fa5c17ffae5e6a0e5d38a4cb8 |
|
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add preload thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1942e3254d2d50ccad3dce247fde4ec1e974a857 |
|
05-Jun-2013 |
Arnold Schwaighofer <aschwaighofer@apple.com> |
ARM sched model: Add more ALU and CMP thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a9a8a128f807d46ce46971abf65578996c50cf2e |
|
29-May-2013 |
JF Bastien <jfb@google.com> |
Tidy some register classes for ARM and Thumb
Tidy up three places where the register class for ARM and Thumb wasn't
restrictive enough:
- No PC dest for reg-reg add/orr/sub.
- No PC dest for shifts.
- No PC or SP for Thumb2 reg-imm add.
I encountered this while combining FastISel with
-verify-machineinstrs. These instructions defined registers whose
classes weren't restrictive enough, and the uses failed
verification. They're also undefined in the ISA, or would produce code
that FastISel wouldn't want. This doesn't fix the register class
narrowing issue (where uses should restrict definitions), and isn't
thorough, but it's a small step in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1ad3a410beff11913db0573942fb51b651d01a13 |
|
26-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Fix encoding of hint instruction for Thumb.
"hint" space for Thumb actually overlaps the encoding space of the CPS
instruction. In actuality, hints can be defined as CPS instructions where imod
and M bits are all nil.
Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe,
sev) in DecodeT2CPSInstruction.
This commit adds a proper diagnostic message for Imm0_4 and updates all tests.
Patch by Mihail Popa <Mihail.Popa@arm.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d64ee4455a9d2fcec7e001c7f4c02d490bed5158 |
|
12-Apr-2013 |
Quentin Colombet <qcolombet@apple.com> |
ARM: Correct printing of pre-indexed operands.
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes.
The MC disassembler was not obeying this when the offset is 0.
It was producing instructions like: str r0, [r1]!.
Correct syntax is: str r0, [r1, #0]!.
This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used.
Patch by Mihail Popa <Mihail.Popa@arm.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 |
|
10-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.
These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.
This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1e8ed2537b3e4b2175cd9e62626f07606c62cfa0 |
|
23-Feb-2013 |
Jim Grosbach <grosbach@apple.com> |
ARM: Convenience aliases for 'srs*' instructions.
Handle an implied 'sp' operand.
rdar://11466783
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 376642ed620ecae05b68c7bc81f79aeb2065abe0 |
|
11-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
if it's not possible to materialize an integer immediate with a single
instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
Also increase the threshold to something reasonable (8 for memset, 4 pairs
for memcpy).
This significantly improves Dhrystone, up to 50% on ARM iOS devices.
rdar://12760078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 50b66387e3eda89ba0097fedc237e41eac5d6808 |
|
14-Nov-2012 |
Nadav Rotem <nrotem@apple.com> |
The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number.
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.
rdar://12028498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b341fac05a890272024dcc5c7e47d10b22d62b92 |
|
10-Nov-2012 |
Evan Cheng <evan.cheng@apple.com> |
Disable the Thumb no-return call optimization:
mov lr, pc
b.w _foo
The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.
rdar://12663632
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8ba1474181fc3997cc8449d75065e1021c72d49b |
|
30-Oct-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Better disassembly for pc-relative LDR.
When the operand is a plain immediate rather than a label, print it
as [pc, #imm] like we do for the Thumb2 wide encoding variant.
rdar://12154503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 445ba85b8d7bc8fb4689ca22131cadc80a034705 |
|
30-Oct-2012 |
Kevin Enderby <enderby@apple.com> |
Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target
is 24 bits not 20 and the decoding needed to correctly handle converting the
J1 and J2 bits to their I1 and I2 values to reconstruct the displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d258eb3ec5cc5c9a28d3a8cd80241c9df24ce3a1 |
|
24-Oct-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a miscompilation caused by a typo. When turning a adde with negative value
into a sbc with a positive number, the immediate should be complemented, not
negated. Also added a missing pattern for ARM codegen.
rdar://12559385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eb1641d54a7eda7717304bc4d55d059208d8ebed |
|
29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f632d80e0c83248909b2dbbe2decef7de84718f9 |
|
06-Sep-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove predicated pseudo-instructions.
These pseudos are no longer needed now that it is possible to represent
predicated instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 67514e90669ec9ffd954c1fcb6f8979bafcabe8a |
|
04-Sep-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cff9baa95273bc279bf5fadb9e27afbd25cca20b |
|
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dd364419ee64cd5bb234af006ce0cb285e4a84ca |
|
28-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.
It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.
Atomic loads are also prevented from participating in rematerialization
and load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7778ee1ed9f9e8a3aa4911ff4adcf15e46588e03 |
|
24-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Explicitly mark LEApcrel pseudos with hasSideEffects.
It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.
This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 083b48af14c8bfa0e96f63ebc889704d09655fd4 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add ADD and SUB to the predicable ARM instructions.
It is not my plan to duplicate the entire ARM instruction set with
predicated versions. We need a way of representing predicated
instructions in SSA form without requiring a separate opcode.
Then the pseudo-instructions can go away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 053b5b0b3c34d4763511b6dcd8e0150f8e9dd083 |
|
17-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle ARM MOVCC optimization in PeepholeOptimizer.
Use the target independent select analysis hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2860b7ea3a1d60213ee7228bd274bc4f8b170772 |
|
16-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fold predicable instructions into MOVCC / t2MOVCC.
The ARM select instructions are just predicated moves. If the select is
the only use of an operand, the instruction defining the operand can be
predicated instead, saving one instruction and decreasing register
pressure.
This implementation can turn AND/ORR/EOR instructions into their
corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to
predicate any instruction, but we don't yet support predicated
instructions in SSA form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161994 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 65bf80e2b7d3c839331be63cdd28a8d101936bca |
|
15-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add missing Rfalse operand to the predicated pseudo-instructions.
When predicating this instruction:
Rd = ADD Rn, Rm
We need an extra operand to represent the value given to Rd when the
predicate is false:
Rd = ADDCC Rfalse, Rn, Rm, pred
The Rd and Rfalse operands are different registers while in SSA form.
Rfalse is tied to Rd to make sure they get the same register during
register allocation.
Previously, Rd and Rn were tied, but that is not required.
Compare to MOVCC:
Rd = MOVCC Rfalse, Rtrue, pred
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161955 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a7016d6fc1c9935ede7b3dc2f39c8cdab14e40e0 |
|
12-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM
architecture
It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7
thumb O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bcc4c1d2d1b6877418de92835c537d79d44363a6 |
|
09-Aug-2012 |
Arnold Schwaighofer <arnolds@codeaurora.org> |
Patch to implement UMLAL/SMLAL instructions for the ARM architecture
This patch corrects the definition of umlal/smlal instructions and adds support
for matching them to the ARM dag combiner.
Bug 12213
Patch by Yin Ma!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9249ef3b994ec94b1a70c0c1f8e60115ec70144b |
|
02-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: More InstAlias refactors to use #NAME#.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5c6c128b8162ab23f6330f8b8b5e66494458ec65 |
|
02-Aug-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Refactor instaliases using TableGen support for #NAME#.
Now that TableGen supports references to NAME w/o it being explicitly
referenced in the definition's own name, use that to simplify
assembly InstAlias definitions in multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
|
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 135fb455b72b1db12d93aa13b13872780db6315b |
|
13-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove variable_ops from ARM call instructions.
Function argument registers are added to the call SDNode, but
InstrEmitter now knows how to make those operands implicit, and the call
instruction doesn't have to be variadic.
Explicit register operands should only be those that are encoded in the
instruction, implicit register operands are for extra dependencies like
call argument and return values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ac03af4ea9f6a33164dbb5a0bc59ccc738939a4c |
|
02-Jul-2012 |
Bob Wilson <bob.wilson@apple.com> |
Do not attempt to use ROR for Thumb1.
Patch by Matt Fischer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fc47253294047a62b30a2347a0bf421d934fb69c |
|
23-Jun-2012 |
Evan Cheng <evan.cheng@apple.com> |
(sub X, imm) gets canonicalized to (add X, -imm)
There are patterns to handle immediates when they fit in the immediate field.
e.g. %sub = add i32 %x, -123
=> sub r0, r0, #123
Add patterns to catch immediates that do not fit but should be materialized
with a single movw instruction rather than movw + movt pair.
e.g. %sub = add i32 %x, -65535
=> movw r1, #65535
sub r0, r0, r1
rdar://11726136
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
|
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 96ef284da415cccd60cf5066929a4683dec5dd79 |
|
18-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
This change handles a another case for generating the bic instruction
when a compile time constant is known. This occurs when implicitly zero
extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't
need to be handled, as the 8 bit constants are encoded directly, thereby
not needing a separate load instruction to form the constant into a register.
<rdar://problem/11481151>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ad5c8808923ed5b24b586cec544e45cee539e529 |
|
11-Jun-2012 |
Bill Wendling <isanbard@gmail.com> |
Re-enable the CMN instruction.
We turned off the CMN instruction because it had semantics which we weren't
getting correct. If we are comparing with an immediate, then it's okay to use
the CMN instruction.
<rdar://problem/7569620>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e061053051a8eaafe020b2d0a81f9e4ee910c1d0 |
|
05-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
Revert commit r157966
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dd52bf2ed806229732115400b2a060204f24dea3 |
|
05-Jun-2012 |
Joel Jones <joel_k_jones@apple.com> |
This change handles a another case for generating the bic instruction
when a compile time constant is known. This occurs when implicitly zero
extending function arguments from 16 bits to 32 bits.
<rdar://problem/11481151>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b551f0cc7882cd9cc9c3a3b2e4d35bc942a9cb44 |
|
21-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: RSB source register should be rGRP not GPRnopc.
t2RSB defined the operand correctly, but tRSBS didn't.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe |
|
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 54319e2a8c22e7ee7044e398fbd8d4287e2b7c4f |
|
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
adds.w r2, #-16
adds.w r2, r2, #-16
addw r2, #-16
addw r2, #-16
addw r2, r2, #-16
rdar://11330769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 97a454317af1903b269d42d368d2263ab79b6ed1 |
|
27-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c92ba4e90501e407c8f71a18e62b8858513085ed |
|
24-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns, whitespace, et. al.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2a7d3a93735f97c2a4cabcc08a88d702c28cb0d4 |
|
13-Apr-2012 |
Kevin Enderby <enderby@apple.com> |
Fix a few more places in the ARM disassembler so that branches get
symbolic operands added when using the C disassembler API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a23ecc2ba945c9685a76552276e5f6f41859b4ab |
|
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f16936e5923156863906c915de657b134db4fb16 |
|
06-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Deduplicate ARM call-related instructions.
We had special instructions for iOS because r9 is call-clobbered, but
that is represented dynamically by the register mask operands now, so
there is no need for the pseudo-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4e53fe8dc61ad48650ac6fe30d7268ec92b7fc1a |
|
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://11192734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c5041cac7d3aeaa7350abadf2a7ada92e8da27dc |
|
04-Apr-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.
<rdar://problem/11182914>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b22e70d835a88753d3ec6d5ee5e85b23fa6834b1 |
|
29-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 03a18525385bafdb6763629aed144b6b8063290d |
|
20-Mar-2012 |
Evan Cheng <evan.cheng@apple.com> |
Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 11d5dc3d50217711462b453ca9592e39d0c879e7 |
|
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix silly typo in optional operand alias.
rdar://11065671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 213d2e7dc31bef3ceeef0cefa703cb4ce52de51a |
|
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM optional operand on MRC/MCR assembly instructions.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9e931f6a64d329276d6253ec1baec9df96f4bbd6 |
|
24-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 asm aliases for wide bitwise w/ immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c54f6348861517398f17e85f41b30c4dd079fc3d |
|
24-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch ARM target to register masks.
I'll let the buildbots determine the compile time improvements from this
change, but 464.h264ref has 5% faster codegen at -O2.
This patch does cause some assembly changes. Branch folding can make
different decisions about calls with dead return values.
CriticalAntiDepBreaker may choose different registers because its
liveness tracking is affected. MachineCopyPropagation may sometimes
leave a dead copy behind.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c892aeb26601cc5109490d30c7e170cb07f84428 |
|
23-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Optimize a couple of common patterns involving conditional moves where the false
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g.
cmp r9, r4
mov r4, #0
moveq r4, #1
orr lr, lr, r4
should be:
cmp r9, r4
orreq lr, lr, #1
That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend
this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y).
It's possible to extend this to ADD and SUB but I don't think they are common.
rdar://8659097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2c6d0f2625b4509d50006b931d053bed08e19fc2 |
|
23-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add missed mayStore flag to STREXD / t2STREXD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 12a8863828879168ffd634df09f3aa91b0b256ee |
|
21-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0b4c6738868e11ba06047a406f79489cb1db8c5a |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5aa5368ccd6b4711d67e00a190e1da1f41b713a0 |
|
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Replace FIXME with explanatory comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ece8b73eb28426b7cec82b1a91e83155a8343ad0 |
|
13-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use RegisterTuples to generate pseudo-registers.
The QQ and QQQQ registers are not 'real', they are pseudo-registers used
to model some vld and vst instructions.
This makes the call clobber lists longer, but I intend to get rid of
those soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2cc5cda464e7c936215281934193658cb799c603 |
|
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| afff941211526a31f931aa9fcac84ae42ff60ef0 |
|
20-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b6744db06f088e1c8a8563c0cb6c202de9ef8aaa |
|
16-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADR assembly parsing w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4677708d4f3a9f2fd76d589a604936b294da309f |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 mov vs. mvn alias goes both ways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8d11c6349f9bf276534907245946518042c1bb60 |
|
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 863d2af9477e331955a9bee8be1969ce658b59b5 |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for "mov(shifted register)"
rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b0659873e6d983eae1e29ecddedcfabb9cdc1eea |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 pre/post indexed stores can be from any non-PC GPR.
rdar://10549786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e91e7bcadc445381adef5c5154e8e2cba074505f |
|
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 840bf7eda7c81059a0aae9abd51262147c60d814 |
|
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3bc8a3d3afe3ddda884a681002e24850099b719e |
|
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8524bca75076a5e94ba3263968fa4b9e4fc6234f |
|
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alias for long-form pop and friends.
rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cf9814ddd277dfcbb4ec5727e2cb510b8a451e04 |
|
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7f1ec9570d673aedd13c5621407085400bab8299 |
|
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 two-operand 'mul' instruction wide encoding parsing.
rdar://10449724
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9588c10b69121d9746b09e868fcc8879cbd98e3a |
|
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactor simple immediate asm operand render methods.
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3c5d6e4df495316c0d2e0a7bca5ec7a88aa400a5 |
|
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 89a633708542de5847e807f98f86edfefc9fc019 |
|
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5d0492cfc4521ccb13b4961227b279991a17c393 |
|
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 88484c00307274568ab068909cb38ecaedd41cbf |
|
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 036a67d670413f8116415b87457f22d256f314ae |
|
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a581328ceb4c9db165d79a4dabd6b28db799d70f |
|
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9c5edc00c41c29be5b088710a4a7ae8507179b64 |
|
26-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f8e74f816df2d0b83e3fe08da3dff4e8c2421e5e |
|
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 LDM instructions can target PC. Make sure to encode it.
PR11220
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 90b7b12f012d9234488277a323231e0b7a8d12ac |
|
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7f5f0dae33c8a105b51532d5ceb3339ac2ce0cbc |
|
18-Oct-2011 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9858a48afcd39d41ad7d424b159422370cffca84 |
|
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0851a29b6d592f6510b5ff17e7607bb3f492fca1 |
|
18-Oct-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix misc warnings. Patch by Joe Abbey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 13a7121858238bc3490b27206a609bf8a2ce1f21 |
|
18-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.
It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.
Neat, huh?
<rdar://problem/10116753>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6f9c28060f3630a1838ca5b0b3cee87d184937cf |
|
17-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Pseudoinstructions should not be less constrained than the instruction they are
lowered to. This fixes a lot of verifier failures on the test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| daada347b550353acbd94fa863bb810854ab6b7b |
|
16-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add flags on Thumb2 indexed stores paralleling the flags on the indexed loads.
These missing flags show up as errors when running -verify-coalescing on
test-suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d575137634377b0aa9f59d3ecb7c82eb2088033c |
|
16-Oct-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix an obvious typo found when looking at nearby code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 |
|
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ef2c86f8760f717882821987664bf5e7604ffe20 |
|
11-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Reapply r141365 now that PR11107 is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eba564ceace5861a321c230acf5df32e55ed9be5 |
|
10-Oct-2011 |
Bill Wendling <isanbard@gmail.com> |
Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to
hang, and possibly SPEC/CINT2006/464_h264ref.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 244455e6d6bb95c5e556ace66adb148dbcd16a27 |
|
07-Oct-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Peephole optimization for ABS on ARM.
Patch by Ana Pazos!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9e5887b17e634b98f7c1cf0ee4f25c218097d08e |
|
05-Oct-2011 |
Kevin Enderby <enderby@apple.com> |
Adding back support for printing operands symbolically to ARM's new disassembler
using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b95ed6ec464c7c675ac71a57dfd9cc8041533a1c |
|
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB can take SP as a destination register.
It's documented as a separate instruction to line up with the Thumb1
encodings, for which it really is a distinct instruction encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
|
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 25ddc2bf7ed69f500dd4d3e003004bda28c3dd95 |
|
28-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2dafe200ca2708ec08656e51a52ce4d718e8a1d6 |
|
27-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove extraneous commit garbage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140581 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0afa0094afdfe589f407feb76948f273b414b278 |
|
26-Sep-2011 |
Owen Anderson <resistor@mac.com> |
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4a713570b60eb5c849d988d68057f6df4d1f3999 |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0781c1f700886f94f5430380a5e82d7ccf6bbdc0 |
|
23-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 61268701931d747fa95e0be8a368101e7f97b83c |
|
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e1368729700f1a51ee5cf33431df985e232bcc68 |
|
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3be654f8082dcbdff011a6716a7c90486e28fc9e |
|
21-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 83a8031336a1155e6b0c3e9a84164324e08d1c8b |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4815d56bb2c356a610f46753c5f1cefafa113b21 |
|
20-Sep-2011 |
Andrew Trick <atrick@apple.com> |
ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 50f1c37123968b7f57068280483ec78f6ff7973e |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8c9898454c1006e6d502e67f22f186f2de88b922 |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect comments. These are not disassmebly only patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0efe213ed5a2c1d2647dc1306e684da6147a611e |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 range check on CPS mode immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 32f36899e942a4bd7e25f61bf3d49a737699c481 |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
|
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bc80e94865d139a60534ac40cbf12f2d214dad56 |
|
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 326efe58918d3f0a431d07938054870fcd0e240f |
|
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 061c3c450660976411ee7ff02774ae491ab3ee79 |
|
19-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8a8d28b0392a27ff8e0c60c04561671023a08dc2 |
|
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f67e8554bf4808ad447ffb5d2deebbb10b810391 |
|
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8a28bdcbcca3328364b86c4010fe96590d1952c8 |
|
17-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ee2c2a4f98c4a6fa575dcdd1bcc3effd1432a7c7 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR.
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 947a24cd64f9471511629e9db84bac2c334c73c2 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 642caea2c624aaeb492a112d60f419ee4d1a10c7 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR(immediate).
Add aliases for STRB/STRH while there. Tests forthcoming for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8213c96655e955a0b63b05580bc2f6a55be26083 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b105b997a49c809bfd464ae7691d5ee45d34f446 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 05ec8f7ac90179cccb476512c872db95bfec418d |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7ff2472b8235d8702bd04bf297d573d06cf6b40d |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 231948f860df79b7f0926305caa065a64d758265 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eeca7582faed76deb3a5ac9216dce6275ac99481 |
|
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 191d33fd6d0a91e89f2a8f719e5adbdccf9effa9 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 689b86ed2e1f1daf9201f0ef83ff3bc1d5167232 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1b69a128d6b98456c666b4031cc46c3d0fbe6177 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 57b21e437a4746e8c3c26531cb233bac953cc5e2 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 push/pop mnemonic recognition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0b69247b10ddbce5f0c476c3471918ffc6091ac5 |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PKH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d32872f9ca446fc48084082fcb88255a55405cc2 |
|
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bf841cf3360558d2939c9f1a244a7a7296f846df |
|
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7782a58b87923cc293d4e4422729ac0a582bb5c1 |
|
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 885f1a0c048e07fca56bc256702c58eae50ae71f |
|
13-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cd00dc6852d17aa24f667a1060d2de83cd6423f0 |
|
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1ad60c2adc9ed765a968747d0c548cda53bfd384 |
|
10-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for MOV(immediate).
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
|
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0811fe13d65c67e4c22d9113795deabbd0daa277 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a77295db19527503d6b290e4f34f273d0a789365 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e64fb28da191bc978ab99ea397e6108a15c364f8 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR post-indexed.
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eeec025cf5a2236ee9527a3312496a6ea42100c6 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f0eee6eca8c39b11b6a41d9b04eba8985655df77 |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ab899c1bcca7f1cc85342c3a686464ba4af035df |
|
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8bb5a861a0efae6b9c8f07936ad9bb3508ada23e |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8a83f71301fdf0e2cea8ecdf413f192ac48ddc5c |
|
07-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a8307dd1c9279cbde1f3497e530d2ed9d014a0c5 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDR(immediate).
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cfbb3a78dbb9f0e5de90ef2032f0ee9a7ceda8f1 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldm/stm 'db' mnemonics don't have a '.w' suffix.
There is no 16-bit wide encoding, so the .w suffix isn't needed (indeed, isn't
documented as allowed). Also add the missing '!' token on the _UPD
variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ffa5a763444e456cee17442af603fb4ef0843bb4 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 use 'ldm' as default mnemonic.
Handle explicit 'ia' suffix via a MnemonicAlias (pre-existing).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 218affc710a0165746ec21a3315c6cc68272cfd5 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ISB is HasDB, not just HasV7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| aa833e53dc74db6cb6789ef7f05c620d28980983 |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 06c1a51241852bd652ae6473afaa71d96d48b0eb |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 77951908b76c00315f1a74d09fb45530029638ec |
|
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ef88a926778b15aa4527a148a514ed0585af7cb1 |
|
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CMN and CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ad2dad930d450d721209531175b0cbfdc8402558 |
|
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4a51708448e8958d8d1a375c055f1b98c8e20926 |
|
06-Sep-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix fall outs from my recent change on how carry bit is modeled during isel.
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6c3e11ea55172def6f9829cc24cc5c3b071208ba |
|
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BXJ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5f25fb01b4061725124e34a942809e9c0c6f681c |
|
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ASR.
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d2990107a9c10e41f4e6256147374afb2118b55f |
|
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5c1ac5554229d5481b772cb017139bdd24d5114d |
|
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for AND (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f0851e5d95a1d1f746a3b1e9633af76496e316e7 |
|
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADD (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 20ed2e7939d6a8e804a51897c3af4588deb48be2 |
|
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ADD(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b45b11bce1fd79b0973d2df8db295583b5477c62 |
|
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 72335d55d972dd7279fe68ed05fa3c4e7fce9345 |
|
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADC(register).
Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eaca928a3798e1fa7072457b94eccdd5b53b5d5f |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 37fefc20d3a1e3934a377567d54a141f67752227 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 342e3161d9dd4fa485b47788aa0266f9c91c3832 |
|
30-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d3765189bfb8c0dd3aa377aaf2d644f321ea8e5a |
|
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert 138781. It's not playing nicely with the immediate forms for ADC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e94a5b1218b9b5646da7f41f2020a1f024e2d0be |
|
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 89df996ab20609676ecc8823f58414d598b09b46 |
|
26-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler parsing and encoding of IT instruction.
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 069e2ed794a90cb5108a35627ee148866795f140 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Atomic load/store on ARM/Thumb.
I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.
I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f44082091c5517a3275c57a8b58e36987c8227f0 |
|
25-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e234d02204e0e546c3555e7e894b8521d22a2121 |
|
24-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Be stricter in enforcing IT instruction predicate values, so that we don't end up trying to print out an illegal predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6153a036f544beb03dfc4d58edc28cf42712743d |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e732cb004379a75efd6d1fd466dbea4cf249de28 |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c6788c83b491b502482bf7d9a06b403d07f9e77e |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
t2SMLAD is a four-register instruction, not a three-register one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 22d35086fec34fa106d844b9b2204d7c3c20d8bc |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct operand naming of t2USAT16 to allow proper decoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2379fc235f8979f7f1218523672a19af1505e29d |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Match operand naming to allow correct decoding of t2LDRSH_POST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 796c3659c97c22e3cf2e7e331861a3944c5b90d5 |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Match operand names to provide correct decoding for Thumb2 SMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2c9f83533baa8802ab1d600fd76854125af53076 |
|
23-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a33b31be451472e72e6dd88851061e239ad54606 |
|
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up predicates on ARM target instruction aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 11cca7a2ea1ea4d19433bf356b55845637561a39 |
|
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 70939ee1415722d7f39f13faf9b3644b96007996 |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9fe72bcd3714d136b371aa85d293e16363c29914 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve operand validation for Thumb2 addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8d7d2e1238fac58c01ccfb719d0cc5680a079561 |
|
09-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6d74631062e4464326eb5c680a4d62d340fa42eb |
|
08-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2cb1dfa4464c8dc551d93e0ce34d7a2f797304db |
|
08-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 14c903a76be7933cea746617d3f787fdf4de8203 |
|
05-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7032741e7bf84d144c408a47591add10f0a394ba |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of remaining extend instructions.
Refactor the rest of the extend instructions to not artificially distinguish
between a rotate of zero and a rotate of any other value. Replace the by-zero
versions with Pat<>'s for ISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c5a8c861c9f008d777f5da6a77c253fea2bfe2f1 |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM extend instructions simplification.
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 45f3929ef0dcdf281a10f23e031ffaba7664e7c0 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM rot_imm printing adjustment.
Allow the rot_imm operand to be optional. This sets the stage for refactoring
away the "rr" versions from the multiclasses and replacing them with Pat<>s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 85bfd3b023d4d70936006eadd86588b03e5f40c0 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f49433523e8a39db6d83503e312ae55160eed90a |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4a5ffb399f841783c201c599b88d576757f1922e |
|
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SSAT instruction 5-bit immediate handling.
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7c9fbc0340aff9e20fd9009be23ffd279c1c0a7d |
|
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1769a3df4a81309ec055a8586c8ac35755fa79a2 |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a0472dc4205d5f2cc4e9cc5a08c51625573a26ce |
|
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ccfd9313d11aa29551f93fe99428946837c97729 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
|
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 16884415db751c75f2133bd04921393c792b1158 |
|
14-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6f9f8845028d4d3b96c33417398034a71137d867 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1cbb0c16a1f2bb0c6163198f626155640d677411 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Revert 135093. Think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135094 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 91eb0aa5de61c76345bb70506c70732a528df36a |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Correct range for thumb co-processor immediate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
|
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e35c5e06fe5b1fd6e754773168ad0281ecda7009 |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0d8dae292a088c3a742f655c1787782abfe7e34c |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Parameterize away the ARM T1Cop class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9bb098ad3a3c93aec50a4a63e6894472727f8d88 |
|
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| af7f2d6b67070eae933402c9115514719d1628cf |
|
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 53e3fc463e3d9ee840510b08ebd6db17694fa2c5 |
|
08-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Use TableGen'erated pseudo lowering for ARM.
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a7603982dbf9e240ecc7ed6eddcd1cdb868107ac |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7M vs. ARMv7E-M support.
The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."
Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.
rdar://9572992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| efeedceb41cc0c5ff7918cad870d5820de84b03d |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize t2MOVCC[ri].
t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ff97eb0cf4394090570feaa327d1237ba4b935e2 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the Thumb tTPsoft instruction.
It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 16f9924000a8d513353cd5c69d1d6307016fe280 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize the t2LDMIA_RET instruction.
It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f6fd90910a552ad9883f031350ae517e26dfdb44 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| adf7366771ebc78b3eee3c86b95e255ff5726da7 |
|
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6b8f1e35eacba34a11e2a7d5f614efc47b43d2e3 |
|
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 734f63bed974a0196e85b0f82c1b6b4e5b891192 |
|
21-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9568e5c3c3f1e25288d2ff375dba0fddbf161fd6 |
|
21-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
=> (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
=> (rotl (bswap x) 16)
This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.
rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6d6c55bc270d1bee8561d3ce00d2ca9ced3bb506 |
|
17-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f60ceac9cd7230e0d5ff911fced396f6b5d8c815 |
|
15-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Another revsh pattern. rdar://9609059
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f921c0fe3418f96bd1e37beb582a368d3ac24295 |
|
14-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up a few 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a1099f184d5d3e88e12957f4ebe1fc4a985dd18d |
|
07-Jun-2011 |
Andrew Trick <atrick@apple.com> |
Fix for setjmp/longjmp exception handling on ARM. setjmp clobbers CPSR.
rdar://problem/9556069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
|
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a0112d0c39aa31fe555ecf7296923ca30f68f811 |
|
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d6ffcd88baa95988c0158151ec1d188a8442bff9 |
|
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Actually, the address operand of the Thumb2 LDREX / STREX instructions *can*
take r13, so we can just make it a GPR. This fixes PR8825.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3c60ff4f3da9671597ed8fadd775255902616b71 |
|
18-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They
were marked as taking a tGPR when in reality they take an rGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2944b4fe059b727b1cbd2b85013610de137fac02 |
|
04-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Mark ultra-super-registers QQQQ as call-clobbered instead of the D sub-registers.
LiveVariables doesn't understand that clobbering D0 and D1 completely overwrites
Q0, so if Q0 is live-in to a function, its live range will extend beyond a
function call that only clobbers D0 and D1. This shows up in the
ARM/2009-11-01-NeonMoves test case.
LiveVariables should probably implement the much stricter rules for physreg
liveness that RAFast imposes - a physreg is killed by the first use of any
alias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0a69ba309f5a30d2dcfa1814eb50635539523304 |
|
03-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
it's possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 54ad87ab786cae4e5b654f4295e9697f0c72dbb1 |
|
03-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add a few ARM coprocessor intrinsics. Testcases included
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c573e2c7ea646d29162a96a0707f4eb0f77f83bc |
|
30-Apr-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d49ffe8284457953db68db063b527ee9c346b67a |
|
29-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Teach Thumb2 isel to fold and->rotr ==> ROR.
Generalization of Nate Begeman's patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8f232d307ace42180961856f69541b95b3278295 |
|
28-Apr-2011 |
Eric Christopher <echristo@apple.com> |
Let the immediate leaf pattern take transforms and switch the signed
immediate patterns in arm to using the pattern.
Handles rdar://9299434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1c3af779fc6b184204efd7e98dc16e475c251e7f |
|
23-Apr-2011 |
Andrew Trick <atrick@apple.com> |
Thumb2 and ARM add/subtract with carry fixes.
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.
Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.
Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3a96122c4ae4e7727ba976a9f658626c18997689 |
|
16-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7a2bdde0a0eebcd2125055e0eacaca040f0b766c |
|
15-Apr-2011 |
Chris Lattner <sabre@nondot.org> |
Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 188ce9c78bdd817f5aa84eff6f1929387ca329e6 |
|
15-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
For t2BFI, both Inst{26} and Inst{5} "should" be 0.
Ref: I.1 Instruction encoding diagrams and pseudocode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 471d73d5d387d52dc854145caca971dfd9fd506a |
|
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.
rdar://problem/9279440
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6e3ccc3c85b960afd843288b701d08756add8e79 |
|
13-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Forgot to add this change for http://llvm.org/viewvc/llvm-project?view=rev&revision=129387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 836a7de15907e0368f7785684f156764ea6b7069 |
|
13-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add @earlyclobber constraints to the writeback register of all ARM store instructions.
The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ec51a6225c59fee9021b8b6c7c813228cb27a3fa |
|
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 RFE instructions need to have their second halfword fully specified.
In addition, the base register is not rGPR, but GPR with th exception that:
if n == 15 then UNPREDICTABLE
rdar://problem/9273836
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f9ce2cba42f76ad82bbb17436902f66a9e5f6367 |
|
12-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
The Thumb2 Ld, St, and Preload instructions with the i12 forms should have its Inst{23}
be specified as '1' (add = TRUE).
Also add a utility function for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
|
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 026a42b170c7724dceec87b1c570360cde68deda |
|
22-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change MRC and MRC2 instructions to model the output register properly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3f30af3f4563fc6987d123a024f05b3e7769d9a1 |
|
18-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Match a few more obvious patterns to revsh. rdar://9147637.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c9bd496aa206746d0bc114d15781650a5b543296 |
|
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Thumb2 PC-relative loads require a fixup rather than just an immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e2189144d45be78a89f0daf3df3cf12e38221d86 |
|
14-Mar-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove some dead patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
|
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
|
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 971b83b67a9812556cdb97bb58aa96fb37af458d |
|
08-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 09989945e204d3d3434ae9f3392c335b25a1ac84 |
|
07-Feb-2011 |
Bob Wilson <bob.wilson@apple.com> |
Remove inaccurate comments: so_imm and t2_so_imm operands are not encoded
until the instructions are emitted or printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1b10d5be40313b4e246e85cf375dfa3452ab306b |
|
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 53519f015e3e84e9f57b677cc8724805a6009b73 |
|
21-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.
It's now enabled by default for Darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 030160073d8ec7d5fc1d928d9c8b6173d3a5e0cc |
|
21-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e47f3751d7770916f250a00a84316d412e959c00 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding and parsing of clrex instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6456121d5c40f56d45ff4b8b183d5468e43b9717 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Change instruction names for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8dd37f7b7dca7907f9f070dc96359f242e102163 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add cdp/cdp2 instructions for thumb/thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6b3a999f227139a3be7df6b5aea7a7d01ce94851 |
|
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr*2 and mr*c2 support to thumb2 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 907276dc4439c04d675fbcdb121cbede7a99ff9d |
|
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Correct itinerary entry for t2MOV_pic_ga_add_pc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
|
20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one.
TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.
Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.
ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
to re-materialize the instruction, allow machine LICM to hoist the set of
instructions out of the loop and make it possible to CSE them. It's a bit
hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.
With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fc8475bde993cc0fa6101427e73e8a9cf7d1c3a4 |
|
19-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e7255a80e308c7f67d25b0b247ed791a99ea3a4e |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix MRS encoding for arm and thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 892fc6d7b64364b230261daa967518a71748c01b |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of t2ISB by using the right class and also parse it correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a461d4222877f43588da38c466145f38dd74e229 |
|
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2e3cea3153ab957af01925580d912be060cb00cf |
|
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Start marking T2 address operands as such, for the benefit of the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 |
|
17-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7597212abced110723f2fee985a7d60557c092ec |
|
13-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8d66b7852afec301a1a667069f8c497da2eec964 |
|
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Mark some T2 ...s instructions as codegen only, they aren't real
instructions but are restricted pseudo forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f0db261e97f9c199e584b2a73095a7e36f4eb3cc |
|
17-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add bits 31-28 to the Thumb2 encoding of TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d481110ef753902447d6b42e09d0ad0718e417cc |
|
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak a few pseudo-inst pattern base classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 41b1d4e4725b34ccf646c706757d8a557ab376e7 |
|
15-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The new t2LEApcrel* pseudo instructions need the size specified.
rdar://8768390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 00f25fa43e5e36912a3302756a77585b810859bd |
|
14-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a838a25d59838adfa91463f6a918ae3adeb352c1 |
|
14-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
process cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6b8719fd7dc527e4c1910ae49ebee61d90907c08 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121721, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e8d02539d7981c07d301d91a6a5b6ad34099b510 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c266600bec4b5ba0ee93ffdfeaafcab8f1295145 |
|
13-Dec-2010 |
Owen Anderson <resistor@mac.com> |
In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 808c7d1482bafdcf1e6b2d759ae98946074b95e2 |
|
10-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 encodings of STREX and LDREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0be099da7937c13794e148ebcafa7880c01ed11a |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 683fc3e9afeda5178ab0644f4ba299715f53a7c8 |
|
10-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
More trivial cleanup. No need to define the EncoderMethod property type. Can
just assign to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6b0fa635d5bfd80940e667cec1662e611f5d270f |
|
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix encoding of the immediate operands on post-indexed LDR and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a0e23c5e95978565b9e5a0cd38f4a0f26555d9be |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
The add/sub SP instructions are really pseudos. The assembler should ignore
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fb20d890756b75d6ccfa7ab17f170a877d425dc6 |
|
09-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 BCC encoding and fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 60fc2ed2bb7e031c95fabaae581583110af8b831 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME
for more thorough cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 20e0fa698d734f5c1b2c96ff5b266e393c82c0b9 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7685ff84ada08d63c8b67618d54ab7eb1fcae365 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 37474e6d68b42b0d1f4299c8588893bfaa3d0d09 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 07e9b26371c1045a5b1dde55fcaa8e2753eb0377 |
|
09-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b76dfe06d9eb42a4b7ffbb02997a2a8eead4faa1 |
|
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Add operand encoding for Thumb2 addw SP + imm. rdar://8745434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121305 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7c6d85a98102add1994b612a707a379b8123c34b |
|
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Parameterize opcode encoding bits for Thumb2 extended precision integer
multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 520820489905c3c9ed268a1c27416f2a726cb66e |
|
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix operand encoding for Thumb2 extended precision multiplies. rdar://8745555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121297 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 86386923625c7ae59e8e3d6ceaf9fdd3b33f7718 |
|
08-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify T2 operand assignment notation a bit. No need to specify a bit range
for the source field when it's the whole thing that's being referenced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bdf714450b70509538aa5a8a676034418ce827b6 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Fix Thumb2 encoding of the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121182 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 97a884d602538705644e296a57a039959cdb6f6e |
|
07-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
possible. They were duplicates for everything exception the source pattern
before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eb6779c5b98383e33542207f062102e79263df16 |
|
07-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c76c59840b7a4491afdcd2f35483f8d6e5ab533a |
|
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Revert r121021, which broke the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4c386fc75488cf8663acf9527e335bbca1fbc0ac |
|
06-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7721e7f279c4c01b29583011eaff48250ec6cdd9 |
|
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9d63d90de5e57ad96f467b270544443a9284eb2b |
|
01-Dec-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 80dd3e06129e2b570cbd65cba850571981df693a |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c7373f8158c162509ce7aef932ccf01aa9419de7 |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for a few miscellaneous instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0e1bcdf4f7547bb5f47ed5ff5f2409a8f72f3609 |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add encoding support for Thumb2 PLD and PLI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120449 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eb05a8d250fb4da51279efc59e99a54eaf5b60ed |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide encodings for a few more load/store variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6af50f7dd12d82f0a80f3158102180eee4c921aa |
|
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Correct Thumb2 encodings for a much wider range of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 75579f739fbc99a92a15f3ce75bbd7628ba00f8c |
|
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for basic loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1e0eab122b6981d7180337aef2856851616c1183 |
|
29-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark Darwin call instructions as using "r7" to prevent the frame-register
assignment instructions from being moved below / above calls.
rdar://8690640
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a0bb25311925079117de74e2e5a5fba8be4e91b4 |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke dead isCodeGenOnly annotation and extraneous comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fbf0cb18cbf74ef551c6e9f1cd8bd2c6541d7171 |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5ca66696e734f963b613de51e3df3684395daf1c |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d092a87ba3f905a6801a0bdf816267329cf0391c |
|
29-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5404c2b36e7f4451c29d1a070fb090c59aee552a |
|
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Improving the factoring of several instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 00a035f74f85e2f05dd641cf7a0eb1d466a270cd |
|
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for MSR and MRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d18a9c9b9d7136c50daee7e5b43dd69da1c0aa52 |
|
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for system instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 05bf595122154b45dfc4e23b459878a4b5224559 |
|
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Thumb2 encodings for branches and IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120306 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7a08864860d68af2fdd70496601378e5e1b1c15d |
|
19-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8b8640a9647ecbd461e20ec8ac823c7e5271835f |
|
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix decoding ambiguities of stdrex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e8e67e13d49219bc0acd73961f3b2dd2ccb90cf4 |
|
19-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix an obvious oversight.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 91a7c59134fa331a8a5560ea0a96dd4ca50fea5b |
|
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for strex and ldrex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 71c11825bf1673baad44274ff71e8df1be938f5e |
|
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8ee9779658d61a426e52a2010522ec8914b8efdd |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119744 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 612fb5b9a6472f8e1cea8a4f771238840f4eaa1c |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 821752e2e601b2e4c0bb83cb341892c853f16d0a |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out the set of Thumb2 multiplication operator encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 99594eb1dec2ddccbfbc995d828ce37ad829ec87 |
|
18-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
the operand to the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119607 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 35141a9ba3ce92281cdbe1ccd0f6b5a42398249c |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Try again at providing Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 424216453fe2d16379fbb6c3310004b997d3771d |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119593 while I figure out my testing disagrees with the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 18333616cd824bee3abecd607d3aa432b5cf507d |
|
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2f7aed39a3082a3e0bb35475e8ed0cb782fef4b5 |
|
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at correct encodings for Thumb2 bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5aba9f694fbfb78df2aa2a228e85ba4c27f3037b |
|
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119551, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 23465a06f4f4fa098f99cf91e81ed8f26f962f3f |
|
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c4af4638dfdab0dc3b6257276cfad2ee45053060 |
|
17-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,
and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.
Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.
Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.
2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.
rdar://8663787, rdar://8241368
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 46c478e80255bb1475e712ebb119808a9d0b9e12 |
|
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3380f6a4d0f88fa27ac7112ffe0ad9b55f589828 |
|
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the correct variable names so that the encodings will be correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119403 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1eeb2806cbfb27db6a842f586d498ef12a933608 |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
L_bit doesn't work here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7b71878d9f490dbdccd39a7f8e813cab58fe8503 |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
- Remove dead patterns.
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 73fe34a3ee866867d5028f4a9afa2c3b8efebcba |
|
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c56dcbf641f1675579e23064b1c7db1c73ca712b |
|
16-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for mov and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| da663f7b51acdc076eb40cbaf197816ca26ff64c |
|
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide encodings for some miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2c4c45deb6a7a8521f6039e3da9688be4cac09d2 |
|
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bb6315d1e48f24e0eefa98b0f572fda8dbb3251f |
|
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for comparison and shift operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a99e778ed894402a4468ad0b695716226471d726 |
|
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for mvn and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2ac190238e88b21e716e2853900b5076c9013410 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 83da6cd5e2d84a7d247f7f8af745763f550c1af5 |
|
14-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at providing correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c93989a0606daff0e96c34790e603b1dd5ca966e |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Comment out the defms until they're activated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119000 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ddc918b379d448d8fc8f249459eee5f3772e07e9 |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add uses of the *_ldst_multi multiclasses. These aren't used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1f4abcfa5cf2a2d929d95714078ac16ebacba7d8 |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Convert the modes to lower case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6c470b806fe8eefae1b7bf180f269a4b120173a4 |
|
13-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c47f7d643eee54c087bbe4c9964aa4d5afb7f6fe |
|
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Conditional moves are slightly more expensive than moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 63f3544a7f6ca09e7515d6b0e1bf9e8e884131e2 |
|
13-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional move of large immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b9a643e2cdfe0ee9f99e1e32ccdbfd3ddf13a46f |
|
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r118939 while I work out why it broke some buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7a6b810dcb3f25634f46462914b3d22985b8559f |
|
13-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Attemt to provide correct encodings for Thumb2 binary operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 875a6ac09a2a4ae2d83dfe262a81d6eb33c24022 |
|
12-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add conditional mvn instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5de6d841a5116152793dcab35a2e534a6a9aaa7a |
|
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
First stab at providing correct Thumb2 encodings, start with adc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 416941d50fec5ebdc4ae3b113a0db1320c3b2a87 |
|
04-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dfed19fe2c34c1209108afa58e8ab014ffd894e2 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bc7deb0f758d2544fc4c36433668340cbf4835cf |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e6913600c723a10ab1f06a43c93d82ee8e26c71c |
|
03-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Break ARM addrmode4 (load/store multiple base address) into its constituent
parts. Represent the operation mode as an optional operand instead.
rdar://8614429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a1ca91af4e01b413cd1d1b3fa9d8d24fa99d9293 |
|
03-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
Completely reject instructions that have an operand in their
ins/outs list that isn't specified by their asmstring. Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right. Mark a bunch of ARM instructions that use this as
isCodeGenOnly. Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9729d2e9989f970724776c3e947cc7244ae45f90 |
|
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the
patterns as such
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6 |
|
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 39ee036f407bd0c94cb993cf9b97348843cfafa4 |
|
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
reapply r117858 with apparent editor malfunction fixed (somehow I
got a dulicated line).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8b2f0822f3e9e5727b2188872a9db76bc6b87cc6 |
|
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
revert r117858 while I check out a failure I missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| efa53760feb23935c29176a94e937f02c3aa5683 |
|
31-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
the asm matcher can't handle operands with modifiers (like ${foo:bar}).
Instead of silently ignoring these instructions, emit a hard error and
force the target author to either refactor the target or mark the
instruction 'isCodeGenOnly'.
Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are
doing this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f74a4298163a7d0b500c7f7a818829c153dc942e |
|
30-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Overhaul memory barriers in the ARM backend. Radar 8601999.
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain. It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions. Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions. Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f38bfd1918aa3d9397e501d5f4a5bd0434fa2742 |
|
30-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove hard tab characters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7e2fe9150f905167f6685c9730911c2abc08293c |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9e08ee5d16b596078e20787f0b5f36121f099333 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0104d9de04f5620ad9f837efbd3d82f31c6ff451 |
|
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Assign load / store with shifter op address modes the right itinerary classes.
- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 458f2dc5d1b0120bd5921582eb1149ea770568bd |
|
25-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
imm12 operands aren't Thumb2 only, so rename the printer helper function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1dd5a2f4e127a99914359cf39f19b3a9916d6be1 |
|
15-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused ARMISD::AND selection DAG node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 792e9796b3dc068d4545e9f5ff927b02731e3836 |
|
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 95369599c61ab1b35ae3afe349763b886225c5be |
|
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
A few 80 column fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a4257162be84d9d606a42e9db5ce2163426949e3 |
|
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3c38f96af2a5443d9f72fd078c2c98dd08746e51 |
|
07-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a0792de66c8364d47b0a688c7f408efb7b10f31b |
|
06-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 78890f41f404fad3663408edd4adf2e13c1e13b5 |
|
02-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Nuke the rest of the :comment references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 71d933a49ef10508f8117a58bab63cb1bb7bdc00 |
|
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
The asm strings are never used at all, so just nuke 'em entirely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7ebc863c156c5ccd127045ddb8d663c3b49ac5f3 |
|
30-Sep-2010 |
Jim Grosbach <grosbach@apple.com> |
Go ahead and jump!
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0e55fd61ae9ab88cf76b30f7e69d168bd7be87d0 |
|
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
ARM instruction itinerary fixes:
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3881cb7a5d54c0011b40997adcd742e1c7b91abd |
|
30-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP
pipeline forwarding path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5d42c567c901508e80ab10ddba1bb30a5007d742 |
|
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7e1bf305cfecbaee859405468b769650efe68f1a |
|
29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bd30ce4311e158f1bfc6c95987ffbbad2193fef3 |
|
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
More pseudo instruction scheduling itinerary fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5be39223216298009799d4a51ed8669934685d58 |
|
25-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix scheduling itinerary for pseudo mov immediate instructions which expand into two real instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f523e476c2e199220306b367b7bd834978fb93d6 |
|
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 71e416ac3aeccfadec2a57150b4f4a243ed6e461 |
|
24-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add isConditionalMove bits to X86 and ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7602acbf3b90af995606e199d68510b856c8e7e7 |
|
09-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix LDM_RET schedule itinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 979b0618192cd99058a7a21c04341c47801dd688 |
|
06-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
remove some dead code. t2addrmode_imm8s4 is never used in a
pattern, so there is no need to define a matching function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5bcb8a6112eca5fb72b39b6b4e608ab1b41e94de |
|
01-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
temporarily revert r112664, it is causing a decoding conflict, and
the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 43a6c5e2fccadb299c35cb3147d112f706922acd |
|
01-Sep-2010 |
Bill Wendling <isanbard@gmail.com> |
We have a chance for an optimization. Consider this code:
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 55c134a26188291f60c44d027a837f05d797194f |
|
31-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 663e339e208a9d54d3731618cb484e8a07c33335 |
|
30-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4822bce4aa395e3e96215e18f5c926c78d4a0e64 |
|
30-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1f7bf0e1f5748a1f8486ebc62fd556eccbe76e1c |
|
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add a parameter to T2I_bin_irs for those patterns which set the S bit.
- Create T2I_bin_sw_irs to be like T2I_bin_w_irs, but that it sets the S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2c4b30ebca87b4578fcf7a45a0bb9dbe956f1ec0 |
|
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Name ANDflag to ANDS, which is less stupid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0b4aa7d11b9a55d602b7398da4495a3b6eba5018 |
|
29-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but
it sets the CPSR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9f134b571310f5591015cb85bbe182890191f837 |
|
26-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
Restrict the register to tGPR to make sure the str instruction will be
encodable as a 16-bit wide instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112195 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4b7dff9a793f3258936c990c8f6a991366d4f55b |
|
26-Aug-2010 |
Dan Gohman <gohman@apple.com> |
Revert r112176; it broke test/CodeGen/Thumb2/thumb2-cmn.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 01b1e1c958d50b79acdf90824f36f7cb8a5be884 |
|
26-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
There seems to be a (potential) hardware bug with the CMN instruction and
comparison with 0. These two pieces of code should give identical results:
rsbs r1, r1, 0
cmp r0, r1
mov r0, #0
it ls
mov r0, #1
and:
cmn r0, r1
mov r0, #0
it ls
mov r0, #1
However, the CMN gives the *opposite* result when r1 is 0. This is because the
carry flag is set in the CMP case but not in the CMN case. In short, the CMP
instruction doesn't perform a truncate of the (logical) NOT of 0 plus the value
of r0 and the carry bit (because the "carry bit" parameter to AddWithCarry is
defined as 1 in this case, the carry flag will always be set when r0 >= 0). The
CMN instruction doesn't perform a NOT of 0 so there is never a "carry" when this
AddWithCarry is performed (because the "carry bit" parameter to AddWithCarry is
defined as 0).
The AddWithCarry in the CMP case seems to be relying upon the identity:
~x + 1 = -x
However when x is 0 and unsigned, this doesn't hold:
x = 0
~x = 0xFFFF FFFF
~x + 1 = 0x1 0000 0000
(-x = 0) != (0x1 0000 0000 = ~x + 1)
Therefore, we should disable *all* versions of CMN, especially when comparing
against zero, until we can limit when the CMN instruction is used (when we know
that the RHS is not 0) or when we have a hardware fix for this.
(See the ARM docs for the "AddWithCarry" pseudo-code.)
This is related to <rdar://problem/7569620>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f0e132c385fa0196e1c9a744ee0aaceec527bc91 |
|
19-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Add the "isCompare" attribute to the defm instead of each individual instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 00d3dda86f825f32277eba8c4206f48fbfc9f584 |
|
17-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't call tablegen'ed Predicate_* functions in the ARM target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c5ed0134a782f16e343892ef7d2faf368fce1ab6 |
|
17-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f955f290c949ff0df7d23cec055efcc4ffeb35d1 |
|
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dc66edaced5dacb56f06f52723dd340d5cfe4eab |
|
17-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee
that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 22f5dc79c05d69391b17e14ed912aa8e98a63027 |
|
16-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Rename sat_shift operand to shift_imm, in preparation for using it for other
instructions besides saturate instructions. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 136e4912806a2182a41e3011e86830a9c77160f0 |
|
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 20d8e4e7aa5645450f3eaedd9f9dbb70423f8ccc |
|
14-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb2 t2RSBrr instruction for disassembly only.
This fixes another part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 38aa2871fc7a37f7a6854744e71fc366ba12888a |
|
13-Aug-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move the Thumb2 SSAT and USAT optional shift operator out of the
instruction opcode. This fixes part of PR7792.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ee34987fd58ed98c6987ed46979ccb46e7420919 |
|
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Really control isel of barrier instructions with cpu feature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 11db068721d44fd5f9b0c2a3a4c90f813d2eae9c |
|
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9db683b06ccdc4e1274257d1458711e0fa2d9b58 |
|
11-Aug-2010 |
Daniel Dunbar <daniel@zuster.org> |
ARM: Quote $p in an asm string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110780 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3611d9e25d8cf79f1d0a608fb5affd6bf2d41598 |
|
11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
CBZ and CBNZ are implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5818032521e9e76873ec82104a7c22ffb9d9b277 |
|
10-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Delete some unused instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c98af3370f899a0d1570b1dff01a2e36632f884f |
|
08-Aug-2010 |
Bill Wendling <isanbard@gmail.com> |
Use the "isCompare" machine instruction attribute instead of calling the
relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.
This pass is will eventually be folded into the Machine CSE pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d4d188e5029801ef2a76ee756dcba49f313004f0 |
|
31-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Move newlines before inline jumptables from the asm strings in .td files to
the jtblock_operand print methods. This avoids extra newlines in the
disassembler's output. PR7757.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6ccfc507dc1f7ad8c8964193a2407264ca644f0d |
|
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0e0a20eb3859affe4626ee75bd5cb32c033d73fb |
|
30-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 692433bc2d3be9c3bb2fd67ab688eda073bafca2 |
|
29-Jul-2010 |
Nate Begeman <natebegeman@mac.com> |
Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7946494ceb506f995f2f11f4ba7390c4481ddeb1 |
|
29-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109693 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f084a5e81d7a0552dca2a144624812bb4547efd2 |
|
20-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Using BIC for immediates needs an extra bump for its complexity to get
instruction selection to prefer it when possible. rdar://7903972
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 469bbdb597f27d6900c95b6d8ae20a45b79ce91b |
|
17-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 502e0aa62833a1648d66c8f7edf5d21cf96c2f56 |
|
14-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Improve 64-subtraction of immediates when parts of the immediate can fit
in the literal field of an instruction. E.g.,
long long foo(long long a) {
return a - 734439407618LL;
}
rdar://7038284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fed76ffa569444596b4e15e2681298c8d7b6be83 |
|
14-Jul-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add missing address register update to t2LDM_RET instruction.
Patch by Brian Lucas. PR7636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c36b5b97308f098beb6c0bdd754bceb39675b049 |
|
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 761fa7af9e883c81da52b27abd0d6971dadbc923 |
|
24-Jun-2010 |
Eli Friedman <eli.friedman@gmail.com> |
Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a967d1121a87dfb6b65eb7e3433c041efd881483 |
|
21-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it
being moved around away from the jump table it references. rdar://8104340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c9792a3c1ffe9656db85e6a042a6205f27d48793 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cosmetic cleanup. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5caeff5c011d9cff5255748b5a0082bca8426554 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0798eddd07b8dc827a4e6e9028c4c3a8d9444286 |
|
28-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Update the saved stack pointer in the sjlj function context following either
an alloca() or an llvm.stackrestore(). rdar://8031573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 54e13eceff09ee79dc6408be990aabdee1a561dc |
|
26-May-2010 |
Jim Grosbach <grosbach@apple.com> |
fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a85df80ed7ff55595ab7982dd1c0543a8dc56efe |
|
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.
I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4876bdb69e3d857df0647b0e16883f55bebafd9f |
|
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix up instruction classes for Thumb2 RSB instructions to be consistent with
Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c21763fd993f37d02c7a495e96c3e8eb4c0b4015 |
|
25-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Allow Thumb2 MVN instructions to set condition codes. The immediate operand
version of t2MVN already allowed that, but not the register versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bb7ecb2bf514e48b3c37afdc43afc8a8fe3a5011 |
|
24-May-2010 |
Bob Wilson <bob.wilson@apple.com> |
Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9085f98b32775aa0190eac221a58350d837ae2c3 |
|
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5fd1c9be2d6ade68a8cf7b38041ebf79624d315c |
|
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ea420b20d4e75af21cfcc1b380a7536c239fb99d |
|
19-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bd91ea53f823fe71c0b67b9a4552984a8b361820 |
|
16-May-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 29402132f3e890a2771818f44987ede213297431 |
|
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b1dc393bd56365ad8fabb51f22c2f3ace707c39a |
|
05-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.
Followup patches will add some tests and adjust to use Subtarget features
for the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ec80e2693ad01262592096d061861e7f1755482e |
|
09-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ab3460519e8013cdba33a416cefd55dfb418999c |
|
16-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Remove the writeback flag from ARM's address mode 4. Now that we have separate
instructions for ld/st with writeback, the flag is completely redundant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 815baebe1c8dc02accf128ae10dff9a1742d3244 |
|
13-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.
There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c0b5dce3fa24202d842cdcd1eff9e02b33e22309 |
|
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm,
instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ae1757b4527715564c8db95049286cc2c3cdece4 |
|
11-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added Thumb2 LDRD/STRD pre/post variants for disassembly only.
Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| dd0f3cf189c34542901178bfca0a319b74d69a05 |
|
10-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a2c618a0f08a331e3f45bd5108423b084c2986ed |
|
09-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
MSR (Move to Special Register from ARM core register) requires a mask to specify
what fields of the CPSR or SPSR are affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f5fd499791bd65a31183324dabc5eefc201f9e2e |
|
08-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fb86d78a45212b66c806a286a56bfd5d0ca77247 |
|
05-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Trivial comment change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 267124cff299922b3d92c5f2878fa285df2f1505 |
|
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit version
of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0635fc5c2726bff3a6cbe91d2ad0f3bcda00671a |
|
04-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions for Preload Data (PLD, PLDW) and Preload
Instruction (PLI) for disassembly only.
According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"]. The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e54a3ef0873f0b298a9369fa0101c11230020cdb |
|
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions LDRT, LDRBT, LDRHT,,LDRSBT, LDRSHT, STRT, STRBT,
and STRHT for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0f7866e796a0fc66bafed36378df274aed18f4ce |
|
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBG
for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bc9d22c99a0a883cce88af37c1bd6746162df543 |
|
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate unused instruction classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97617 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a43398283dcb34568d2283dafbdfe0fa66b05033 |
|
03-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 10a77e14a0b41ebb1c0ee9c07b28550d96acd60c |
|
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b5031ad4c002004c919f9b42d754361cf53b7d51 |
|
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as from
the opc string passed in, since it's a given from the class inheritance of T2sI.
The fixed the extra 's' in adcss & sbcss when disassembly printing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 93042d1dc803b26c7dce7bb75858e6a8c721d9d0 |
|
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9d3acaa1a015c4499595eaff529686a517c14e15 |
|
02-Mar-2010 |
Johnny Chen <johnny.chen@apple.com> |
AL is an optional mnemonic extension for always, except in IT instructions.
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing.
Ref: A8.3 Conditional execution
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bc9d98b52d008d857c7423d7b43fb32022b926a2 |
|
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
The mayHaveSideEffects flag is no longer used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| adc7733a64b65096cbd6066c212a9daa6e278a9a |
|
26-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the follwoing 32-bit Thumb instructions for disassembly only:
o Parallel addition and subtraction, signed/unsigned
o Miscellaneous operations: QADD, QDADD, QSUB, QDSUB
o Unsigned sum of absolute differences [and accumulate]: USAD8, USADA8
o Signed/Unsigned saturate: SSAT, SSAT16, USAT, USAT16
o Signed multiply accumulate long (halfwords): SMLAL<x><y>
o Signed multiply accumulate/subtract [long] (dual): SMLAD[x], SMLALD[X], SMLSD[X], SMLSLD[X]
o Signed dual multiply add/subtract [long]: SMUAD[X], SMUSD[X]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6341c5a4c4019d4ff2a06bd69d4425324d6a7f81 |
|
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the following 32-bit Thumb instructions for disassembly only: SMC, RFE,
and SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ce6275fd2ceae4cae7ac5c249e21de3d7527e9e2 |
|
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (BXJ) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2333655ed04637ffd049b9299685a0752aab8e8d |
|
25-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added the 32-bit Thumb instructions (MRS and MSR) for disassembly only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 80dc116ce3be18be2866db8fe13f03d1d6c4372f |
|
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
80 column cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6417171026447cde57330114e7df2a22bebfc135 |
|
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 39be8fcfdcad1b01997b22739a889d7c819600d5 |
|
16-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
Update Thumb2 to not use CarryDefIsUnused or CarryDefIsUsed predicates, but
to have the predicate on the pattern itself instead. Support for the new
ISel. Remove definitions of CarryDefIsUnused and CarryDefIsUsed since they are
no longer used anywhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96384 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a87ded2695e5bce30dbd0d2d2ac10c571bf1d161 |
|
09-Feb-2010 |
Jim Grosbach <grosbach@apple.com> |
tighten up eh.setjmp sequence a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9474d550ff8d2be251792cf21f777d85e052ed5e |
|
02-Feb-2010 |
Johnny Chen <johnny.chen@apple.com> |
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d5d2baec2609da3ade9ca205e87c88d35e9e6976 |
|
22-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f609bb8466e28ef63eb4db9de485583c6d5b8bc9 |
|
19-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3482c8003ad0c88469b7333aaf658036e3fd0468 |
|
18-Jan-2010 |
Jim Grosbach <grosbach@apple.com> |
Patch by David Conrad:
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
sequence it is now."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d248ffb7d57cc7aa4216b79741b372026936ea0a |
|
08-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Minor change, change the order of two "let Inst{...}" stmts within multiclass
T2I_bin_ii12rs definition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 83142991613730bc857739c6179660ccffebe379 |
|
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Undo r92785, it caused test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92796 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 83f1136cfdbfb6ccbdcd23f1f6e35b72bfaeb306 |
|
05-Jan-2010 |
Johnny Chen <johnny.chen@apple.com> |
Add Rt2 to the asm format string for 32-bit Thumb load/store register dual
instructions. Thumb does not have the restriction that t2 = t+1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 587b072f23789010ee20a487cca458a0e724c6ed |
|
16-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Mark STREX* as earlyclobber for the success result register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| bbc71b2904644bfa85d8785328dc08d61c534467 |
|
16-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Add encoding bits for some Thumb instructions. Plus explicitly set the top two
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d68e119c0fea54f47d0f3f0b5282dcf6cd19d8b9 |
|
15-Dec-2009 |
Johnny Chen <johnny.chen@apple.com> |
Added encoding bits for the Thumb ISA. Initial checkin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7c03dbd8ede6f43063df56eaa6d63f7ae1721892 |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
Add ARMv6 memory and sync barrier instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a623f5a58dd7768b0cf4dbb61b1fffa8b4d07cca |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
correct selection requirements for thumb2 vs. arm versions of the barrier intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c219e4dd5919e2b72b80698fd50aa05e1580a55b |
|
14-Dec-2009 |
Jim Grosbach <grosbach@apple.com> |
add Thumb2 atomic and memory barrier instruction definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5cdc3a949af0cef7f2163f8a7acbf3049c226321 |
|
24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6935efcb667bcd4dd3a00bbd420461e1fadba73a |
|
24-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80 column violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 15e6ef886deedafaf3fcbca8226891ba54dbff9d |
|
23-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4aedb61d039580113982827e397d3ebbd0e0dbba |
|
20-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remat VLDRD from constpool. Clean up some instruction property specifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b9803a8fa65f043c96612fa9c5aeeee12739db2b |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5a1cd36019ca3cbae811f2800631b5b56a9ffdc2 |
|
04-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 907eebd5a6779e8539ef7bf63550a5b72de76ab2 |
|
02-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Put BlockAddresses into ARM constant pools.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2f54a2fd8542aa6280d1c5da18ac314d16550676 |
|
02-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix schedule model for BFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 9eda68988e7772c40f6125750a965ddb85acc25f |
|
31-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ddb16df91257e4c4d2be5343e2c7c7ecbfbe8bf4 |
|
30-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add ARM codegen for indirect branches.
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
|
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 699bebac4f3320b5a9a3c94ac76502caf61dd711 |
|
27-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 65b7f3af76d0ba5bce49b56ab3e18f970b95f9d1 |
|
21-Oct-2009 |
Jim Grosbach <grosbach@apple.com> |
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2095659a8551fb222d145bc8dfa6cf5d15048e42 |
|
21-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Match more patterns to movt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 47eedaa8fa597e3302012b0ef8f24c4886ef6188 |
|
13-Oct-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0d92f5f76884513f8f5e014c61cb7a72ff576fa5 |
|
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d20d6586759fe7a53ec8b1dde80622cda49e31b8 |
|
01-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c732adf3a1718d1b3e08adb11652100cab1efad6 |
|
30-Sep-2009 |
Jim Grosbach <grosbach@apple.com> |
Add "isBarrier = 1" to return instructions.
Patch by Sylvere Teissier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5adb66a646e2ec32265263739f5b01c3f50c176a |
|
28-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6a2fa325c1763a0fb27eceaa78b3a9bf683416bf |
|
28-Sep-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.
This should be better than single load from constpool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e298ab26b11cf6e278b4876bbc5b890e234d4029 |
|
27-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Enable pre-regalloc load / store multiple pass for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ca01a8d4aba723e3b1838e5e2034efbc7efa859d |
|
01-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
RRX reads CPSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d17479e8458d17575e2532d9e8a61057b057a33d |
|
28-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Print a nl before pic labels so they start at a new line. This makes assembly more readable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4f38b383d5089c49489a9a56d8efd0eb76048b3f |
|
21-Aug-2009 |
Bob Wilson <bob.wilson@apple.com> |
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5d598aaf3de7f506749f4a0a142fe0121854e1a6 |
|
19-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Update Cortex-A8 instruction itineraries for integer instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 51f39961c3558ee71b6323d3713e9ddd2354e099 |
|
18-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix revsh pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79318 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| a1efbbdbf3217598f334a6f39dab84ca06f5de41 |
|
14-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrink ADR and LDR from constantpool late during constantpool island pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f35d21617e9c6616eb127355b7c7cd3a5aa7cc58 |
|
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add missing defs of R2 and D1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6d3d9c3fc3b98e9c12ca38acaffa77cf02deffe6 |
|
13-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Finalize itineraries for cortex-a8 integer multiply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8db5cce0217a2b76a954cb97de95c91e76edf59c |
|
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Remove unnecessary newline
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1add659b0a70bf2bdaa3cb93fa5961359fb7df45 |
|
13-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Correct comment wording
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1a8f36e3ce5b9c230781b66600c81536128abfb5 |
|
12-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 378756c0f2d0d5393356ca3711530beceb201e05 |
|
12-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
register naming cleanup (s/ip/r12/)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| ea253b99e907a4171d49547fc5d99c837af5d0b9 |
|
12-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove an Darwin assembler workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78777 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4b322e58b77d16f103d88a3af3a4ebd2675245a0 |
|
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Shrinkify Thumb2 load / store multiple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5aa1684e5da9a85286bf7d29da419d261a70c2f2 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 eh_sjlj_setjmp implementation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1cf5783dd73e72adc60aa2d037728cdcd13938ca |
|
11-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
80 column violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e8af1f9afe5e70e1d4ec4d00a6870428dba88692 |
|
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78550 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8e9ece75db5045ec057efbbdba6550fa0d85e695 |
|
09-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use subclassing to print lane-like immediates (w/o hash) eliminating
'no_hash' modifier. Hopefully this will make Daniel happy :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d77c7aba83bb290b9b62ede38b6ddbc9b790c6ef |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78410 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8b7d7ade85fd0103316295440d4950f39ab08419 |
|
06-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 35d6c41fde95422fb8483be0ac0af2b1425a4b13 |
|
05-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| fa2ea1a8cf2e3fe4dae19032868010e917629d16 |
|
04-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 25f7cfc3cccba6f569f29f79ea533bae960b93c0 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Workaround a couple of Darwin assembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 13f8b36205607ff87ad0c4daf28f63b2660e7c0f |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b620724e614c6594e7b269b6ea7d8483947ea944 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1119776b19872cad8366835f12ee682788879951 |
|
01-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 movcc need .w suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 8f652532365afed2274ec3b8513bb8faef16d2c2 |
|
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now recognizes "orn", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 7c92f3ac99c39d745e909390edb71c72bafecc24 |
|
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Darwin assembler now supports "rrx", so remove workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3e4b22d9836f66ba72dd105567a77be05030f747 |
|
30-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add missing D* register clobbers for Thumb-2 call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 20a2a0aff3221e2c777558d714753bae0f296c8d |
|
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure Thumb2 uses the right call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77507 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0531d04d002c6d9489b4d1a85f49734e5c27e6f7 |
|
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Fix an obvious copy and paste error.
- Darwin Thumb2 call clobbers r9.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5657c01949dca6c012ac60d242d1a8d2ffdf5603 |
|
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e7c329bf4b48ba3a4539183dc2d0804db6f4042a |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6340632d3b32bdf73c390195698ae337cb753e51 |
|
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove support for ORN to workaround <rdar://problem/7096522>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5743854f47c00118f7e667c68c10db5ce76225b3 |
|
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add workaround for <rdar://problem/7098328>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 3583df7676bd194faf21eb24ff7790928502852a |
|
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6495f63945e8dbde81f03a1dc2ab421993b9a495 |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 1f0962756dc46a2909250d242dfa2953eb15e036 |
|
28-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 752aa7d2fe9af9d1bbd027f563e861f854bd40fa |
|
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 does not have RSC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| af0d08d55c58cc34a373ca5f0b45e852c31e59d0 |
|
27-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add ".w" suffix for wide thumb-2 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 66ac53165e17b7c76b8c69e57bde623d44ec492e |
|
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 0b6afa8c71f3ee32d42390c0c46c28ff31aa6325 |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Uh. It would be useful to actually print the operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 789476240d6b6f8ad9366cadf790a82bd41bb0b3 |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Make sure thumb2 jumptable entries are aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5ff58b5c3ab6df332600678798ea5c69c5e943d3 |
|
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eee839dd3c5cb87e51a522b4800674d7680fef70 |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 does not allow the use of "pc" register as part of the load / store address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 81c102ba6639c807825b59df99ac41f3b14d191d |
|
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| b53cc014d0f47b898c9daca34566c16dda6c4c1e |
|
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| eadf04992aea8d3efbc89d8e5920044d7a652e22 |
|
23-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 756da12ae4030259d98fefbe26f840d49f71898e |
|
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c27a4547a369a49e94a02063b097911bffa6ae57 |
|
21-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
CMP and TST define CPSR, not use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 446c428bf394b7113b0f18cbacb5e87b4efd1e14 |
|
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 06e16587ebc81e43b42157fa3afcfd806b59b296 |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add a thumb2 pass to insert IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c50a1cbf5f2b536d396a78a3feb91656a8c8d9f1 |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldm / stm unified syntax; add t2LDM_RET.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5c874172ac8fd563867efc54022ac4c1571e1313 |
|
10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix ldrd / strd address mode matching code. It allows for +/- 8 bit offset. Also change the printer to make the scale 4 explicit.
Note, we are not yet generating these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| cba962dd6b46fce807dfe3ed97da04ec5ad98c34 |
|
09-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Correct comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 |
|
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e7cbe4118b7ddf05032ff8772a98c51e1637bb5c |
|
08-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 77521f5232e679aa3de10aaaed2464aa91d7ff55 |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 334c26473bba3ad8b88341bb0d25d0ac2008bb8d |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e253c951b38e47f14a097db6ac7731c857837ae2 |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 movcc instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 40289b041adb299e4474607066b69b89298e5f70 |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pkhbt / pkhtb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5b9fcd1c8e9f2b7964a82cd383441f568890b561 |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add some more Thumb2 multiplication instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 36a0aebac21bb72328ce72a55df6f3fe62c68b7f |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add bfc to armv6t2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74868 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d27c9fc403ae906c60ca3dfee72001f7e1930492 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 sign / zero extend with rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 2889ccea625942348ea74f51ae2f67d084f44850 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 load / store multiple instructions. Not used yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 78236f8c8a0e6bd966afd7e461599336956f7772 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2LDR_PRE etc are loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6d94f1119644393c0b3e58ad666bb1d020770951 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Added indexed stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 4fbb9960adcd79888acda1869d26032b9ab44a10 |
|
03-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Sign extending pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| e88d5cee9d6b02bc786df806395a718464908064 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Thumb2 pre/post indexed loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d770d9e7d1f5c65b185897dcf226b3fc64598683 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| d1fa120aeec67e94e6ed6056593ccb630fe2db0e |
|
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add PIC load and store patterns for Thumb-2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 6647cea111ab4d83483b28712b5ba8244e6612f2 |
|
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2 load and store double description. But nothing yet creates them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 73b8f16b360544bc0f756d92fa2661028160cef3 |
|
01-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Add thumb-2 store word, halfword, and byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| c9a59b5960088f48c3be234bcc4c79a1ed915d73 |
|
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Improve Thumb-2 jump table support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|
| 5e47a9a6e46bd271eba058fb831da1a1edf8707c |
|
30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| f3c21b857b8449bcde35e499ef8268c0fec9514d |
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30-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
A few more load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| baeb911d60401818dc9fe0db6182cd048e4fdd03 |
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30-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Add Thumb-2 support for TEQ amd TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| c0309b48b560f119982c02a81416c8c1fd208648 |
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29-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 055b0310f862b91f33699037ce67d3ab8137c20c |
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29-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Implement Thumb2 ldr.
After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 9cb9e6778c7d458eee7f3e25d304697ad10d8d46 |
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27-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Renaming for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 8eba8e0ca3497e4f518b5e27117ea22651409c2c |
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27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove outdated comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| dcdaebc592cad9bc23652e3b9fdb552d63bbeb9f |
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27-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has a narrow version and eor(i) does not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 7ce720b448c581b822577aaf44b73a5aa9689dfc |
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26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 93d95bd2c309b1fb8e2a830c441d86556a41038c |
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26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
ADC used to implement adde should use "adcs" opcode instead of "adc".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 83b3593478406b020b7af6ba5402a14507d7d713 |
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26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Currently there is a pattern for the thumb-2 MOV 16-bit immediate instruction. That instruction cannot write the flags so it should use T2I instead of T2sI.
Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 8de898abc8deb46a30973958801e9f9f4e9a7d46 |
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26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Mark a bunch of instructions commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 626742231863db0e9aeef1be1fd48e9f4b7e22f8 |
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26-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 0919a916bf152e08617e67f9d4b03db4769076e2 |
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26-Jun-2009 |
David Goodwin <david_goodwin@apple.com> |
Use MVN for ~t2_so_imm immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 1e249e3705bccd20d72d9131e9f904dc10595c02 |
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25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
ISD::ADDE / ISD::SUBE updates the carry bit so they should isle to ADCS and SBCS / RSCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 0aa1d8c52d34e9ba1e731a21b16606cd6f4f924a |
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25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| b6c29d55123f6b8c3f9e4d56e4be653a1fd2a472 |
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25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add thumb2 add sp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| a09b9ca10fbec13e4ad47d8108e9c6f9a1b53451 |
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25-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Thumb2 pc relative add.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| b8f7706911028508dc2a6c07fa185139f870c059 |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Test instructions operands were printed in the wrong order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| a67efd12263eff2ed0f0a89ce905d59a82d0760a |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Proper patterns for thumb2 shift and rotate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| e499f970585c2462e2de8a38f67f6d11683a6bb0 |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 83a2129332250af4648e0501f93cabfa8873e1f4 |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Obvious typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| f49810c7e60807c43a68ab02c936a4ee77a4d2cf |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 3850a6ae9d1c5f38c94c89237ce87d4270dcac64 |
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23-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Replace isTwoAddress with operand constraint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 7c4f7dd43a84b233f94a1fe44faff42ac46b906d |
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18-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fix asm string from MOVi16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| 52237119a9b41d6d714c96e730d651300b171298 |
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17-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial support for some Thumb2 instructions.
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
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| d4022c3fbb0705abdc8eddc3ee4a5059f5ef8094 |
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30-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add placeholder for thumb2 stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMInstrThumb2.td
|