ARMInstrThumb2.td revision 8bb5a861a0efae6b9c8f07936ad9bb3508ada23e
11dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 21dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 31dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// The LLVM Compiler Infrastructure 41dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 51dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// This file is distributed under the University of Illinois Open Source 61dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// License. See LICENSE.TXT for details. 71dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 81dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris//===----------------------------------------------------------------------===// 91dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// This file describes the Thumb2 instruction set. 111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris//===----------------------------------------------------------------------===// 131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// IT block predicate field 151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef it_pred_asmoperand : AsmOperandClass { 161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Name = "ITCondCode"; 171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMethod = "parseITCondCode"; 181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef it_pred : Operand<i32> { 201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printMandatoryPredicateOperand"; 211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = it_pred_asmoperand; 221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// IT block condition mask 251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef it_mask : Operand<i32> { 271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printThumbITMask"; 281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = it_mask_asmoperand; 291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// Shifted operands. No register controlled shifts for Thumb2. 321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// Note: We do not support rrx shifted operands yet. 331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_reg : Operand<i32>, // reg imm 341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [shl,srl,sra,rotr]> { 361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2SORegOpValue"; 371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2SOOperand"; 381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeSORegImmOperand"; 391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = ShiftedImmAsmOperand; 401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops rGPR, i32imm); 411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}]>; 471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}]>; 521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2_so_imm - Match a 32-bit immediate operand, which is an 541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// immediate splatted into multiple bytes of the word. 561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; } 571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return ARM_AM::getT2SOImmVal(Imm) != -1; 591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris }]> { 601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = t2_so_imm_asmoperand; 611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2SOImmOpValue"; 621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2SOImm"; 631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2_so_imm_not - Match an immediate that is a complement 661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// of a t2_so_imm. 671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm_not : Operand<i32>, 681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatLeaf<(imm), [{ 691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}], t2_so_imm_not_XFORM>; 711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2_so_imm_neg : Operand<i32>, 741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatLeaf<(imm), [{ 751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1; 761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}], t2_so_imm_neg_XFORM>; 771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef imm0_4095 : Operand<i32>, 801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ImmLeaf<i32, [{ 811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return Imm >= 0 && Imm < 4096; 821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}]>; 831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef imm0_4095_neg : PatLeaf<(i32 imm), [{ 851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return (uint32_t)(-N->getZExtValue()) < 4096; 861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}], imm_neg_XFORM>; 871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef imm0_255_neg : PatLeaf<(i32 imm), [{ 891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return (uint32_t)(-N->getZExtValue()) < 255; 901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}], imm_neg_XFORM>; 911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef imm0_255_not : PatLeaf<(i32 imm), [{ 931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return (uint32_t)(~N->getZExtValue()) < 255; 941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}], imm_comp_XFORM>; 951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef lo5AllOne : PatLeaf<(i32 imm), [{ 971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Returns true if all low 5-bits are 1. 981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris}]>; 1001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// Define Thumb2 specific addressing modes. 1021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_imm12 := reg + imm12 1041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 1051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_imm12 : Operand<i32>, 1061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 1071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printAddrModeImm12Operand"; 1081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getAddrModeImm12OpValue"; 1091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2AddrModeImm12"; 1101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = t2addrmode_imm12_asmoperand; 1111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2ldrlabel := imm12 1151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2ldrlabel : Operand<i32> { 1161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getAddrModeImm12OpValue"; 1171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// ADR instruction labels. 1211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2adrlabel : Operand<i32> { 1221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AdrLabelOpValue"; 1231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_negimm8 := reg - imm8 1271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";} 1281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_negimm8 : Operand<i32>, 1291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 1301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeImm8Operand"; 1311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AddrModeImm8OpValue"; 1321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2AddrModeImm8"; 1331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = MemNegImm8OffsetAsmOperand; 1341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_imm8 := reg +/- imm8 1381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } 1391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_imm8 : Operand<i32>, 1401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 1411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeImm8Operand"; 1421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AddrModeImm8OpValue"; 1431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2AddrModeImm8"; 1441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let ParserMatchClass = MemImm8OffsetAsmOperand; 1451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2am_imm8_offset : Operand<i32>, 1491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 1501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [], [SDNPWantRoot]> { 1511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 1521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 1531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2Imm8"; 1541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 1571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_imm8s4 : Operand<i32> { 1581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeImm8s4Operand"; 1591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 1601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2AddrModeImm8s4"; 1611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 1621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2am_imm8s4_offset : Operand<i32> { 1651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 1661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2Imm8S4"; 1671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_so_reg := reg + (reg << imm2) 1701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_so_reg : Operand<i32>, 1711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 1721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printT2AddrModeSoRegOperand"; 1731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let EncoderMethod = "getT2AddrModeSORegOpValue"; 1741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2AddrModeSOReg"; 1751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 1761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// t2addrmode_reg := reg 1791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// Used by load/store exclusive instructions. Useful to enable right assembly 1801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// parsing and printing. Not used for any codegen matching. 1811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 1821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisdef t2addrmode_reg : Operand<i32> { 1831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let PrintMethod = "printAddrMode7Operand"; 1841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeGPRRegisterClass"; 1851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let MIOperandInfo = (ops GPR); 1861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 1871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris//===----------------------------------------------------------------------===// 1891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// Multiclass helpers... 1901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// 1911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 1941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 1951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 1961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 1971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 1981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 1991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 2011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 2021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 2031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 2071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 2091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 2101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 2111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 2121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 2151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 2161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 2171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 2201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 2221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 2231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 2241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 2261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 2271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 2281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 2291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 2331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 2351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 2361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> ShiftedRm; 2371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = ShiftedRm{3-0}; 2401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = ShiftedRm{6-5}; 2411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = ShiftedRm{11-9}; 2421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = ShiftedRm{8-7}; 2431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 2461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 2481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 2491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> ShiftedRm; 2501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = ShiftedRm{3-0}; 2531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = ShiftedRm{6-5}; 2541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = ShiftedRm{11-9}; 2551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = ShiftedRm{8-7}; 2561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 2591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 2611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 2621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> ShiftedRm; 2631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 2651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = ShiftedRm{3-0}; 2661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = ShiftedRm{6-5}; 2671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = ShiftedRm{11-9}; 2681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = ShiftedRm{8-7}; 2691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2TwoReg<dag oops, dag iops, InstrItinClass itin, 2721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 2741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 2751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 2761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 2791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 2821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 2841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 2851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 2861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 2881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 2891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 2901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 2921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 2931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 2941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 2951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 2961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 2971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 2981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 2991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 3031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 3051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 3071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 3081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 3111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 3121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 3131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 3141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 3171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 3191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 3211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 3221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 3251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 3261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 3271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 3281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 3311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 3331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 3351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<5> imm; 3361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 3391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{4-2}; 3401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = imm{1-0}; 3411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 3441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 3461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 3481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<5> imm; 3491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 3521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{4-2}; 3531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = imm{1-0}; 3541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 3571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 3591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 3611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 3621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 3651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 3661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 3691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 3711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 3731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 3741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 3771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 3781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 3811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 3831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 3851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> ShiftedRm; 3861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 3881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 3891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = ShiftedRm{3-0}; 3901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = ShiftedRm{6-5}; 3911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = ShiftedRm{11-9}; 3921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = ShiftedRm{8-7}; 3931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 3941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 3951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 3961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 3971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2sI<oops, iops, itin, opc, asm, pattern> { 3981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 3991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 4001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> ShiftedRm; 4011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 4031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 4041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = ShiftedRm{3-0}; 4051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = ShiftedRm{6-5}; 4061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = ShiftedRm{11-9}; 4071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = ShiftedRm{8-7}; 4081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 4091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2FourReg<dag oops, dag iops, InstrItinClass itin, 4111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 4121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 4131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 4141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 4151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 4161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Ra; 4171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 4191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Ra; 4201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 4211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 4221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 4231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parisclass T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 4251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris dag oops, dag iops, InstrItinClass itin, 4261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string opc, string asm, list<dag> pattern> 4271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris : T2I<oops, iops, itin, opc, asm, pattern> { 4281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> RdLo; 4291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> RdHi; 4301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 4311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rm; 4321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-23} = 0b111110111; 4341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-20} = opc22_20; 4351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 4361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = RdLo; 4371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = RdHi; 4381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-4} = opc7_4; 4391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = Rm; 4401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 4411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 4441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// unary operation that produces a value. These are predicable and can be 4451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// changed to modify CPSR. 4461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_un_irs<bits<4> opcod, string opc, 4471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 4481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { 4491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 4501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 4511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, "\t$Rd, $imm", 4521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> { 4531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isAsCheapAsAMove = Cheap; 4541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isReMaterializable = ReMat; 4551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 4561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 4571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 4581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = 0b1111; // Rn 4591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 4601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 4611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 4621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 4631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rm", 4641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { 4651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 4661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 4671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 4681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = 0b1111; // Rn 4691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 4701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 4711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 4721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 4731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 4741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 4751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $ShiftedRm", 4761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> { 4771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 4781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 4791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 4801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = 0b1111; // Rn 4811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 4821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 4831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 4841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 4851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// binary operation that produces a value. These are predicable and can be 4861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// changed to modify CPSR. 4871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_bin_irs<bits<4> opcod, string opc, 4881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 4891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode, string baseOpc, bit Commutable = 0, 4901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string wide = ""> { 4911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 4921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm< 4931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 4941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, "\t$Rd, $Rn, $imm", 4951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> { 4961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 4971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 4981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 4991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 5001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 5011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 5021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 5031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 5041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 5051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isCommutable = Commutable; 5061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 5071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 5081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 5091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 5101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 5111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 5121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 5131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 5141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 5151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 5161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 5171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> { 5181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 5191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 5201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 5211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 5221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Assembly aliases for optional destination operand when it's the same 5231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // as the source operand. 5241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 5251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 5261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_imm:$imm, pred:$p, 5271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 5291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 5301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 5311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 5331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 5341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_reg:$shift, pred:$p, 5351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 5371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 5381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 5391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// the ".w" suffix to indicate that they are wide. 5401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_bin_w_irs<bits<4> opcod, string opc, 5411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 5421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode, string baseOpc, bit Commutable = 0> : 5431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> { 5441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Assembler aliases w/o the ".w" suffix. 5451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 5461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 5471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 5481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 5501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn, 5511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_reg:$shift, pred:$p, 5521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 5541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // and with the optional destination operand, too. 5551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 5561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 5571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 5581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 5601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 5611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_reg:$shift, pred:$p, 5621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 5631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 5641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 5651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 5661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// reversed. The 'rr' form is only defined for the disassembler; for codegen 5671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// it is equivalent to the T2I_bin_irs counterpart. 5681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { 5691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 5701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm< 5711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 5721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $imm", 5731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { 5741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 5751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 5761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 5771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 5781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 5791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 5801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg< 5811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 5821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, "\t$Rd, $Rn, $Rm", 5831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [/* For disassembly only; pattern left blank */]> { 5841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 5851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 5861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 5871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 5881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 5891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 5901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 5911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 5921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 5931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 5941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 5951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { 5961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 5971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 5981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 5991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 6011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 6021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 6031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// instruction modifies the CPSR register. 6041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parislet hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in { 6051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_bin_s_irs<bits<4> opcod, string opc, 6061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 6071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode, bit Commutable = 0> { 6081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 6091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm< 6101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, 6111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $imm", 6121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> { 6131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 6141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 6151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 6161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 6171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 6191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg< 6201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, 6211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $Rm", 6221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> { 6231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isCommutable = Commutable; 6241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 6251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 6261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 6271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 6281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 6291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 6301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 6321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 6331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, 6341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $ShiftedRm", 6351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> { 6361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 6371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 6381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 6391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 6411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 6421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 6431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 6441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// patterns for a binary operation that produces a value. 6451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 6461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bit Commutable = 0> { 6471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 6481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // The register-immediate version is re-materializable. This is useful 6491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // in particular for taking the address of a local. 6501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isReMaterializable = 1 in { 6511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm< 6521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 6531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $imm", 6541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> { 6551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 6561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 6571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = 1; 6581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23-21} = op23_21; 6591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 6601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // 12-bit imm 6631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri12 : T2I< 6641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 6651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 6661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> { 6671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rd; 6681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rn; 6691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> imm; 6701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 6711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26} = imm{11}; 6721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25-24} = 0b10; 6731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23-21} = op23_21; 6741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 0; // The S bit. 6751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = Rn; 6761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 6771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = imm{10-8}; 6781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = Rd; 6791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = imm{7-0}; 6801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 6821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr, 6831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $Rm", 6841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> { 6851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isCommutable = Commutable; 6861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 6871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 6881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = 1; 6891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23-21} = op23_21; 6901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 6911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 6921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 6931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 6941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 6951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 6961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 6971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 6981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> { 6991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 7001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 7011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = 1; 7021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23-21} = op23_21; 7031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 7051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 7061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 7071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// for a binary operation that produces a value and use the carry 7081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// bit. It's not predicable. 7091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parislet Defs = [CPSR], Uses = [CPSR] in { 7101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 7111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bit Commutable = 0> { 7121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 7131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 7141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 7151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 7161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris Requires<[IsThumb2]> { 7171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 7181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 7191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 7201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 7211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 7231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 7241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $Rm", 7251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 7261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris Requires<[IsThumb2]> { 7271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isCommutable = Commutable; 7281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 7291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 7301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 7311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 7321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 7331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 7341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 7361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 7371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 7381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 7391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 7401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris Requires<[IsThumb2]> { 7411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 7421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 7431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 7441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 7461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 7471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 7481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register 7491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// version is not needed since this is only for codegen. 7501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parislet hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in { 7511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { 7521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 7531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegImm< 7541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 7551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $imm", 7561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { 7571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 7581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 7591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 7601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 7611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 7631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2sTwoRegShiftedReg< 7641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 7651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm", 7661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { 7671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 7681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 7691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 7701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 7721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 7731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 7741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 7751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris// rotate operation that produces a value. 7761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode, 7771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris string baseOpc> { 7781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // 5-bit imm 7791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2sTwoRegShiftImm< 7801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 7811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rm, $imm", 7821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> { 7831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 7841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-21} = 0b010010; 7851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = 0b1111; // Rn 7861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = opcod; 7871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 7891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2sThreeReg< 7901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 7911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rd, $Rn, $Rm", 7921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 7931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 7941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-23} = 0b0100; 7951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 7961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = 0b1111; 7971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-4} = 0b0000; 7981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 7991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Optional destination register 8011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 8021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 8031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ty:$imm, pred:$p, 8041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 8061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 8071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 8081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Assembler aliases w/o the ".w" suffix. 8111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 8121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn, 8131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ty:$imm, pred:$p, 8141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 8161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 8171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 8181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // and with the optional destination operand, too. 8211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 8221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 8231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris ty:$imm, pred:$p, 8241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 8261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 8271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris rGPR:$Rm, pred:$p, 8281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris cc_out:$s)>; 8291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 8301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 8321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// patterns. Similar to T2I_bin_irs except the instruction does not produce 8331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// a explicit result, only implicitly set CPSR. 8341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_cmp_irs<bits<4> opcod, string opc, 8351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 8361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode, string baseOpc> { 8371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parislet isCompare = 1, Defs = [CPSR] in { 8381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted imm 8391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def ri : T2OneRegCmpImm< 8401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, 8411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rn, $imm", 8421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> { 8431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11110; 8441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{25} = 0; 8451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 8461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // The S bit. 8471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15} = 0; 8481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = 0b1111; // Rd 8491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 8501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // register 8511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rr : T2TwoRegCmp< 8521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir, 8531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rn, $Rm", 8541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode GPRnopc:$Rn, rGPR:$Rm)]> { 8551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 8561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 8571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 8581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // The S bit. 8591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{14-12} = 0b000; // imm3 8601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = 0b1111; // Rd 8611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-6} = 0b00; // imm2 8621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = 0b00; // type 8631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 8641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // shifted register 8651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def rs : T2OneRegCmpShiftedReg< 8661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, 8671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rn, $ShiftedRm", 8681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> { 8691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11101; 8701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b01; 8711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24-21} = opcod; 8721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // The S bit. 8731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-8} = 0b1111; // Rd 8741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 8751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 8761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Assembler aliases w/o the ".w" suffix. 8781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // No alias here for 'rr' version as not all instantiations of this 8791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // multiclass want one (CMP in particular, does not). 8801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 8811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn, 8821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_imm:$imm, pred:$p)>; 8831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 8841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn, 8851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris t2_so_reg:$shift, 8861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris pred:$p)>; 8871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 8881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 8891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 8901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_ld<bit signed, bits<2> opcod, string opc, 8911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iis, RegisterClass target, 8921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode> { 8931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 8941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rt, $addr", 8951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> { 8961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 8971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<17> addr; 8981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-25} = 0b1111100; 8991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = signed; 9001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23} = 1; 9011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // load 9031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{16-13}; // Rn 9041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 9051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-0} = addr{11-0}; // imm 9061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 9071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 9081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, "\t$Rt, $addr", 9091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> { 9101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 9111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<13> addr; 9121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 9131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b00; 9141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = signed; 9151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23} = 0; 9161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // load 9181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{12-9}; // Rn 9191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 9201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11} = 1; 9211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Offset: index==TRUE, wback==FALSE 9221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{10} = 1; // The P bit. 9231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{9} = addr{8}; // U 9241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{8} = 0; // The W bit. 9251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = addr{7-0}; // imm 9261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 9271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 9281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rt, $addr", 9291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> { 9301dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 9311dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b00; 9321dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = signed; 9331dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23} = 0; 9341dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9351dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // load 9361dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-6} = 0b000000; 9371dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9381dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 9391dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 9401dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9411dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<10> addr; 9421dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{9-6}; // Rn 9431dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = addr{5-2}; // Rm 9441dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = addr{1-0}; // imm 9451dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9461dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let DecoderMethod = "DecodeT2LoadShift"; 9471dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 9481dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9491dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // FIXME: Is the pci variant actually needed? 9501dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 9511dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rt, $addr", 9521dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { 9531dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let isReMaterializable = 1; 9541dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 9551dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-25} = 0b00; 9561dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{24} = signed; 9571dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23} = ?; // add = (U == '1') 9581dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9591dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 1; // load 9601dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = 0b1111; // Rn 9611dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 9621dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<12> addr; 9631dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt{3-0}; 9641dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-0} = addr{11-0}; 9651dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 9661dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 9671dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9681dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 9691dce0bf16d6300d4858d611cb29de336bfd85f9aEric Parismulticlass T2I_st<bits<2> opcod, string opc, 9701dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris InstrItinClass iii, InstrItinClass iis, RegisterClass target, 9711dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris PatFrag opnode> { 9721dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 9731dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rt, $addr", 9741dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode target:$Rt, t2addrmode_imm12:$addr)]> { 9751dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 9761dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-23} = 0b0001; 9771dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9781dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 0; // !load 9791dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9801dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 9811dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 9821dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 9831dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<17> addr; 9841dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let addr{12} = 1; // add = TRUE 9851dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{16-13}; // Rn 9861dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{23} = addr{12}; // U 9871dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-0} = addr{11-0}; // imm 9881dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 9891dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 9901dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, "\t$Rt, $addr", 9911dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> { 9921dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 9931dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-23} = 0b0000; 9941dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 9951dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 0; // !load 9961dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11} = 1; 9971dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris // Offset: index==TRUE, wback==FALSE 9981dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{10} = 1; // The P bit. 9991dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{8} = 0; // The W bit. 10001dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 10011dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 10021dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 10031dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 10041dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<13> addr; 10051dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{12-9}; // Rn 10061dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{9} = addr{8}; // U 10071dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{7-0} = addr{7-0}; // imm 10081dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 10091dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 10101dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris opc, ".w\t$Rt, $addr", 10111dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> { 10121dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{31-27} = 0b11111; 10131dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{26-23} = 0b0000; 10141dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{22-21} = opcod; 10151dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{20} = 0; // !load 10161dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{11-6} = 0b000000; 10171dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 10181dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<4> Rt; 10191dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{15-12} = Rt; 10201dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 10211dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris bits<10> addr; 10221dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{19-16} = addr{9-6}; // Rn 10231dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{3-0} = addr{5-2}; // Rm 10241dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris let Inst{5-4} = addr{1-0}; // imm 10251dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris } 10261dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris} 10271dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris 10281dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 10291dce0bf16d6300d4858d611cb29de336bfd85f9aEric Paris/// register and one whose operand is a register rotated by 8/16/24. 1030class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> 1031 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1032 opc, ".w\t$Rd, $Rm$rot", 1033 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1034 Requires<[IsThumb2]> { 1035 let Inst{31-27} = 0b11111; 1036 let Inst{26-23} = 0b0100; 1037 let Inst{22-20} = opcod; 1038 let Inst{19-16} = 0b1111; // Rn 1039 let Inst{15-12} = 0b1111; 1040 let Inst{7} = 1; 1041 1042 bits<2> rot; 1043 let Inst{5-4} = rot{1-0}; // rotate 1044} 1045 1046// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 1047class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> 1048 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), 1049 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1050 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1051 Requires<[HasT2ExtractPack, IsThumb2]> { 1052 bits<2> rot; 1053 let Inst{31-27} = 0b11111; 1054 let Inst{26-23} = 0b0100; 1055 let Inst{22-20} = opcod; 1056 let Inst{19-16} = 0b1111; // Rn 1057 let Inst{15-12} = 0b1111; 1058 let Inst{7} = 1; 1059 let Inst{5-4} = rot; 1060} 1061 1062// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 1063// supported yet. 1064class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> 1065 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1066 opc, "\t$Rd, $Rm$rot", []>, 1067 Requires<[IsThumb2, HasT2ExtractPack]> { 1068 bits<2> rot; 1069 let Inst{31-27} = 0b11111; 1070 let Inst{26-23} = 0b0100; 1071 let Inst{22-20} = opcod; 1072 let Inst{19-16} = 0b1111; // Rn 1073 let Inst{15-12} = 0b1111; 1074 let Inst{7} = 1; 1075 let Inst{5-4} = rot; 1076} 1077 1078/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1079/// register and one whose operand is a register rotated by 8/16/24. 1080class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> 1081 : T2ThreeReg<(outs rGPR:$Rd), 1082 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1083 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", 1084 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, 1085 Requires<[HasT2ExtractPack, IsThumb2]> { 1086 bits<2> rot; 1087 let Inst{31-27} = 0b11111; 1088 let Inst{26-23} = 0b0100; 1089 let Inst{22-20} = opcod; 1090 let Inst{15-12} = 0b1111; 1091 let Inst{7} = 1; 1092 let Inst{5-4} = rot; 1093} 1094 1095class T2I_exta_rrot_np<bits<3> opcod, string opc> 1096 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), 1097 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { 1098 bits<2> rot; 1099 let Inst{31-27} = 0b11111; 1100 let Inst{26-23} = 0b0100; 1101 let Inst{22-20} = opcod; 1102 let Inst{15-12} = 0b1111; 1103 let Inst{7} = 1; 1104 let Inst{5-4} = rot; 1105} 1106 1107//===----------------------------------------------------------------------===// 1108// Instructions 1109//===----------------------------------------------------------------------===// 1110 1111//===----------------------------------------------------------------------===// 1112// Miscellaneous Instructions. 1113// 1114 1115class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1116 string asm, list<dag> pattern> 1117 : T2XI<oops, iops, itin, asm, pattern> { 1118 bits<4> Rd; 1119 bits<12> label; 1120 1121 let Inst{11-8} = Rd; 1122 let Inst{26} = label{11}; 1123 let Inst{14-12} = label{10-8}; 1124 let Inst{7-0} = label{7-0}; 1125} 1126 1127// LEApcrel - Load a pc-relative address into a register without offending the 1128// assembler. 1129def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1130 (ins t2adrlabel:$addr, pred:$p), 1131 IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> { 1132 let Inst{31-27} = 0b11110; 1133 let Inst{25-24} = 0b10; 1134 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1135 let Inst{22} = 0; 1136 let Inst{20} = 0; 1137 let Inst{19-16} = 0b1111; // Rn 1138 let Inst{15} = 0; 1139 1140 bits<4> Rd; 1141 bits<13> addr; 1142 let Inst{11-8} = Rd; 1143 let Inst{23} = addr{12}; 1144 let Inst{21} = addr{12}; 1145 let Inst{26} = addr{11}; 1146 let Inst{14-12} = addr{10-8}; 1147 let Inst{7-0} = addr{7-0}; 1148} 1149 1150let neverHasSideEffects = 1, isReMaterializable = 1 in 1151def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1152 4, IIC_iALUi, []>; 1153def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1154 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1155 4, IIC_iALUi, 1156 []>; 1157 1158 1159//===----------------------------------------------------------------------===// 1160// Load / store Instructions. 1161// 1162 1163// Load 1164let canFoldAsLoad = 1, isReMaterializable = 1 in 1165defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, 1166 UnOpFrag<(load node:$Src)>>; 1167 1168// Loads with zero extension 1169defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1170 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>; 1171defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1172 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>; 1173 1174// Loads with sign extension 1175defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1176 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>; 1177defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1178 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>; 1179 1180let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1181// Load doubleword 1182def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1183 (ins t2addrmode_imm8s4:$addr), 1184 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>; 1185} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1186 1187// zextload i1 -> zextload i8 1188def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1189 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1190def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1191 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1192def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1193 (t2LDRBs t2addrmode_so_reg:$addr)>; 1194def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1195 (t2LDRBpci tconstpool:$addr)>; 1196 1197// extload -> zextload 1198// FIXME: Reduce the number of patterns by legalizing extload to zextload 1199// earlier? 1200def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1201 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1202def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1203 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1204def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1205 (t2LDRBs t2addrmode_so_reg:$addr)>; 1206def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1207 (t2LDRBpci tconstpool:$addr)>; 1208 1209def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1210 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1211def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1212 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1213def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1214 (t2LDRBs t2addrmode_so_reg:$addr)>; 1215def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1216 (t2LDRBpci tconstpool:$addr)>; 1217 1218def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1219 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1220def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1221 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1222def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1223 (t2LDRHs t2addrmode_so_reg:$addr)>; 1224def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1225 (t2LDRHpci tconstpool:$addr)>; 1226 1227// FIXME: The destination register of the loads and stores can't be PC, but 1228// can be SP. We need another regclass (similar to rGPR) to represent 1229// that. Not a pressing issue since these are selected manually, 1230// not via pattern. 1231 1232// Indexed loads 1233 1234let mayLoad = 1, neverHasSideEffects = 1 in { 1235def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn), 1236 (ins t2addrmode_imm8:$addr), 1237 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1238 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn", 1239 []>; 1240 1241def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn), 1242 (ins GPR:$base, t2am_imm8_offset:$addr), 1243 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1244 "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn", 1245 []>; 1246 1247def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn), 1248 (ins t2addrmode_imm8:$addr), 1249 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1250 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn", 1251 []>; 1252def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn), 1253 (ins GPR:$base, t2am_imm8_offset:$addr), 1254 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1255 "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn", 1256 []>; 1257 1258def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn), 1259 (ins t2addrmode_imm8:$addr), 1260 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1261 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn", 1262 []>; 1263def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn), 1264 (ins GPR:$base, t2am_imm8_offset:$addr), 1265 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1266 "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn", 1267 []>; 1268 1269def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn), 1270 (ins t2addrmode_imm8:$addr), 1271 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1272 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn", 1273 []>; 1274def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn), 1275 (ins GPR:$base, t2am_imm8_offset:$addr), 1276 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1277 "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn", 1278 []>; 1279 1280def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn), 1281 (ins t2addrmode_imm8:$addr), 1282 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1283 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn", 1284 []>; 1285def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn), 1286 (ins GPR:$base, t2am_imm8_offset:$addr), 1287 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1288 "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn", 1289 []>; 1290} // mayLoad = 1, neverHasSideEffects = 1 1291 1292// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are 1293// for disassembly only. 1294// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1295class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1296 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1297 "\t$Rt, $addr", []> { 1298 let Inst{31-27} = 0b11111; 1299 let Inst{26-25} = 0b00; 1300 let Inst{24} = signed; 1301 let Inst{23} = 0; 1302 let Inst{22-21} = type; 1303 let Inst{20} = 1; // load 1304 let Inst{11} = 1; 1305 let Inst{10-8} = 0b110; // PUW. 1306 1307 bits<4> Rt; 1308 bits<13> addr; 1309 let Inst{15-12} = Rt; 1310 let Inst{19-16} = addr{12-9}; 1311 let Inst{7-0} = addr{7-0}; 1312} 1313 1314def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1315def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1316def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1317def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1318def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1319 1320// Store 1321defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, 1322 BinOpFrag<(store node:$LHS, node:$RHS)>>; 1323defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1324 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1325defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1326 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1327 1328// Store doubleword 1329let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1330def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1331 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr), 1332 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>; 1333 1334// Indexed stores 1335def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb), 1336 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1337 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1338 "str", "\t$Rt, [$Rn, $addr]!", 1339 "$Rn = $base_wb,@earlyclobber $base_wb", 1340 [(set GPRnopc:$base_wb, 1341 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1342 1343def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb), 1344 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1345 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1346 "str", "\t$Rt, [$Rn], $addr", 1347 "$Rn = $base_wb,@earlyclobber $base_wb", 1348 [(set GPRnopc:$base_wb, 1349 (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1350 1351def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb), 1352 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1353 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1354 "strh", "\t$Rt, [$Rn, $addr]!", 1355 "$Rn = $base_wb,@earlyclobber $base_wb", 1356 [(set GPRnopc:$base_wb, 1357 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1358 1359def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb), 1360 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1361 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1362 "strh", "\t$Rt, [$Rn], $addr", 1363 "$Rn = $base_wb,@earlyclobber $base_wb", 1364 [(set GPRnopc:$base_wb, 1365 (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1366 1367def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb), 1368 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1369 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1370 "strb", "\t$Rt, [$Rn, $addr]!", 1371 "$Rn = $base_wb,@earlyclobber $base_wb", 1372 [(set GPRnopc:$base_wb, 1373 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1374 1375def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb), 1376 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), 1377 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1378 "strb", "\t$Rt, [$Rn], $addr", 1379 "$Rn = $base_wb,@earlyclobber $base_wb", 1380 [(set GPRnopc:$base_wb, 1381 (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; 1382 1383// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1384// only. 1385// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1386class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1387 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1388 "\t$Rt, $addr", []> { 1389 let Inst{31-27} = 0b11111; 1390 let Inst{26-25} = 0b00; 1391 let Inst{24} = 0; // not signed 1392 let Inst{23} = 0; 1393 let Inst{22-21} = type; 1394 let Inst{20} = 0; // store 1395 let Inst{11} = 1; 1396 let Inst{10-8} = 0b110; // PUW 1397 1398 bits<4> Rt; 1399 bits<13> addr; 1400 let Inst{15-12} = Rt; 1401 let Inst{19-16} = addr{12-9}; 1402 let Inst{7-0} = addr{7-0}; 1403} 1404 1405def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1406def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1407def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1408 1409// ldrd / strd pre / post variants 1410// For disassembly only. 1411 1412def t2LDRD_PRE : T2Ii8s4Tied<1, 1, 1, 1413 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1414 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru, 1415 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>; 1416 1417def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1, 1418 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1419 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru, 1420 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>; 1421 1422def t2STRD_PRE : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb), 1423 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm), 1424 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>; 1425 1426def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb), 1427 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm), 1428 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>; 1429 1430// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1431// data/instruction access. These are for disassembly only. 1432// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1433// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1434multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1435 1436 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1437 "\t$addr", 1438 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> { 1439 let Inst{31-25} = 0b1111100; 1440 let Inst{24} = instr; 1441 let Inst{22} = 0; 1442 let Inst{21} = write; 1443 let Inst{20} = 1; 1444 let Inst{15-12} = 0b1111; 1445 1446 bits<17> addr; 1447 let addr{12} = 1; // add = TRUE 1448 let Inst{19-16} = addr{16-13}; // Rn 1449 let Inst{23} = addr{12}; // U 1450 let Inst{11-0} = addr{11-0}; // imm12 1451 } 1452 1453 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1454 "\t$addr", 1455 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> { 1456 let Inst{31-25} = 0b1111100; 1457 let Inst{24} = instr; 1458 let Inst{23} = 0; // U = 0 1459 let Inst{22} = 0; 1460 let Inst{21} = write; 1461 let Inst{20} = 1; 1462 let Inst{15-12} = 0b1111; 1463 let Inst{11-8} = 0b1100; 1464 1465 bits<13> addr; 1466 let Inst{19-16} = addr{12-9}; // Rn 1467 let Inst{7-0} = addr{7-0}; // imm8 1468 } 1469 1470 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1471 "\t$addr", 1472 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> { 1473 let Inst{31-25} = 0b1111100; 1474 let Inst{24} = instr; 1475 let Inst{23} = 0; // add = TRUE for T1 1476 let Inst{22} = 0; 1477 let Inst{21} = write; 1478 let Inst{20} = 1; 1479 let Inst{15-12} = 0b1111; 1480 let Inst{11-6} = 0000000; 1481 1482 bits<10> addr; 1483 let Inst{19-16} = addr{9-6}; // Rn 1484 let Inst{3-0} = addr{5-2}; // Rm 1485 let Inst{5-4} = addr{1-0}; // imm2 1486 1487 let DecoderMethod = "DecodeT2LoadShift"; 1488 } 1489} 1490 1491defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1492defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1493defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1494 1495//===----------------------------------------------------------------------===// 1496// Load / store multiple Instructions. 1497// 1498 1499multiclass thumb2_ldst_mult<string asm, InstrItinClass itin, 1500 InstrItinClass itin_upd, bit L_bit> { 1501 def IA : 1502 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1503 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1504 bits<4> Rn; 1505 bits<16> regs; 1506 1507 let Inst{31-27} = 0b11101; 1508 let Inst{26-25} = 0b00; 1509 let Inst{24-23} = 0b01; // Increment After 1510 let Inst{22} = 0; 1511 let Inst{21} = 0; // No writeback 1512 let Inst{20} = L_bit; 1513 let Inst{19-16} = Rn; 1514 let Inst{15-0} = regs; 1515 } 1516 def IA_UPD : 1517 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1518 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1519 bits<4> Rn; 1520 bits<16> regs; 1521 1522 let Inst{31-27} = 0b11101; 1523 let Inst{26-25} = 0b00; 1524 let Inst{24-23} = 0b01; // Increment After 1525 let Inst{22} = 0; 1526 let Inst{21} = 1; // Writeback 1527 let Inst{20} = L_bit; 1528 let Inst{19-16} = Rn; 1529 let Inst{15-0} = regs; 1530 } 1531 def DB : 1532 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1533 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1534 bits<4> Rn; 1535 bits<16> regs; 1536 1537 let Inst{31-27} = 0b11101; 1538 let Inst{26-25} = 0b00; 1539 let Inst{24-23} = 0b10; // Decrement Before 1540 let Inst{22} = 0; 1541 let Inst{21} = 0; // No writeback 1542 let Inst{20} = L_bit; 1543 let Inst{19-16} = Rn; 1544 let Inst{15-0} = regs; 1545 } 1546 def DB_UPD : 1547 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1548 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1549 bits<4> Rn; 1550 bits<16> regs; 1551 1552 let Inst{31-27} = 0b11101; 1553 let Inst{26-25} = 0b00; 1554 let Inst{24-23} = 0b10; // Decrement Before 1555 let Inst{22} = 0; 1556 let Inst{21} = 1; // Writeback 1557 let Inst{20} = L_bit; 1558 let Inst{19-16} = Rn; 1559 let Inst{15-0} = regs; 1560 } 1561} 1562 1563let neverHasSideEffects = 1 in { 1564 1565let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 1566defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 1567 1568let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1569defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 1570 1571} // neverHasSideEffects 1572 1573 1574//===----------------------------------------------------------------------===// 1575// Move Instructions. 1576// 1577 1578let neverHasSideEffects = 1 in 1579def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1580 "mov", ".w\t$Rd, $Rm", []> { 1581 let Inst{31-27} = 0b11101; 1582 let Inst{26-25} = 0b01; 1583 let Inst{24-21} = 0b0010; 1584 let Inst{19-16} = 0b1111; // Rn 1585 let Inst{14-12} = 0b000; 1586 let Inst{7-4} = 0b0000; 1587} 1588 1589// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1590let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 1591 AddedComplexity = 1 in 1592def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 1593 "mov", ".w\t$Rd, $imm", 1594 [(set rGPR:$Rd, t2_so_imm:$imm)]> { 1595 let Inst{31-27} = 0b11110; 1596 let Inst{25} = 0; 1597 let Inst{24-21} = 0b0010; 1598 let Inst{19-16} = 0b1111; // Rn 1599 let Inst{15} = 0; 1600} 1601 1602def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1603 pred:$p, cc_out:$s)>; 1604 1605let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 1606def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 1607 "movw", "\t$Rd, $imm", 1608 [(set rGPR:$Rd, imm0_65535:$imm)]> { 1609 let Inst{31-27} = 0b11110; 1610 let Inst{25} = 1; 1611 let Inst{24-21} = 0b0010; 1612 let Inst{20} = 0; // The S bit. 1613 let Inst{15} = 0; 1614 1615 bits<4> Rd; 1616 bits<16> imm; 1617 1618 let Inst{11-8} = Rd; 1619 let Inst{19-16} = imm{15-12}; 1620 let Inst{26} = imm{11}; 1621 let Inst{14-12} = imm{10-8}; 1622 let Inst{7-0} = imm{7-0}; 1623} 1624 1625def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1626 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1627 1628let Constraints = "$src = $Rd" in { 1629def t2MOVTi16 : T2I<(outs rGPR:$Rd), 1630 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 1631 "movt", "\t$Rd, $imm", 1632 [(set rGPR:$Rd, 1633 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { 1634 let Inst{31-27} = 0b11110; 1635 let Inst{25} = 1; 1636 let Inst{24-21} = 0b0110; 1637 let Inst{20} = 0; // The S bit. 1638 let Inst{15} = 0; 1639 1640 bits<4> Rd; 1641 bits<16> imm; 1642 1643 let Inst{11-8} = Rd; 1644 let Inst{19-16} = imm{15-12}; 1645 let Inst{26} = imm{11}; 1646 let Inst{14-12} = imm{10-8}; 1647 let Inst{7-0} = imm{7-0}; 1648} 1649 1650def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1651 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1652} // Constraints 1653 1654def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1655 1656//===----------------------------------------------------------------------===// 1657// Extend Instructions. 1658// 1659 1660// Sign extenders 1661 1662def t2SXTB : T2I_ext_rrot<0b100, "sxtb", 1663 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1664def t2SXTH : T2I_ext_rrot<0b000, "sxth", 1665 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1666def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1667 1668def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", 1669 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1670def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", 1671 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1672def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 1673 1674// TODO: SXT(A){B|H}16 1675 1676// Zero extenders 1677 1678let AddedComplexity = 16 in { 1679def t2UXTB : T2I_ext_rrot<0b101, "uxtb", 1680 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1681def t2UXTH : T2I_ext_rrot<0b001, "uxth", 1682 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1683def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", 1684 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1685 1686// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1687// The transformation should probably be done as a combiner action 1688// instead so we can include a check for masking back in the upper 1689// eight bits of the source into the lower eight bits of the result. 1690//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 1691// (t2UXTB16 rGPR:$Src, 3)>, 1692// Requires<[HasT2ExtractPack, IsThumb2]>; 1693def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 1694 (t2UXTB16 rGPR:$Src, 1)>, 1695 Requires<[HasT2ExtractPack, IsThumb2]>; 1696 1697def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", 1698 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1699def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", 1700 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1701def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; 1702} 1703 1704//===----------------------------------------------------------------------===// 1705// Arithmetic Instructions. 1706// 1707 1708defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1709 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1710defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1711 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1712 1713// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1714// FIXME: Eliminate them if we can write def : Pat patterns which defines 1715// CPSR and the implicit def of CPSR is not needed. 1716defm t2ADDS : T2I_bin_s_irs <0b1000, "add", 1717 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1718 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 1719defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", 1720 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1721 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1722 1723let hasPostISelHook = 1 in { 1724defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1725 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 1726defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1727 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 1728} 1729 1730// RSB 1731defm t2RSB : T2I_rbin_irs <0b1110, "rsb", 1732 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1733 1734// FIXME: Eliminate them if we can write def : Pat patterns which defines 1735// CPSR and the implicit def of CPSR is not needed. 1736defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", 1737 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1738 1739// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1740// The assume-no-carry-in form uses the negation of the input since add/sub 1741// assume opposite meanings of the carry flag (i.e., carry == !borrow). 1742// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 1743// details. 1744// The AddedComplexity preferences the first variant over the others since 1745// it can be shrunk to a 16-bit wide encoding, while the others cannot. 1746let AddedComplexity = 1 in 1747def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1748 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1749def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1750 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1751def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1752 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1753let AddedComplexity = 1 in 1754def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm), 1755 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; 1756def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 1757 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 1758// The with-carry-in form matches bitwise not instead of the negation. 1759// Effectively, the inverse interpretation of the carry flag already accounts 1760// for part of the negation. 1761let AddedComplexity = 1 in 1762def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 1763 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 1764def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 1765 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 1766 1767// Select Bytes -- for disassembly only 1768 1769def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1770 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>, 1771 Requires<[IsThumb2, HasThumb2DSP]> { 1772 let Inst{31-27} = 0b11111; 1773 let Inst{26-24} = 0b010; 1774 let Inst{23} = 0b1; 1775 let Inst{22-20} = 0b010; 1776 let Inst{15-12} = 0b1111; 1777 let Inst{7} = 0b1; 1778 let Inst{6-4} = 0b000; 1779} 1780 1781// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1782// And Miscellaneous operations -- for disassembly only 1783class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 1784 list<dag> pat = [/* For disassembly only; pattern left blank */], 1785 dag iops = (ins rGPR:$Rn, rGPR:$Rm), 1786 string asm = "\t$Rd, $Rn, $Rm"> 1787 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 1788 Requires<[IsThumb2, HasThumb2DSP]> { 1789 let Inst{31-27} = 0b11111; 1790 let Inst{26-23} = 0b0101; 1791 let Inst{22-20} = op22_20; 1792 let Inst{15-12} = 0b1111; 1793 let Inst{7-4} = op7_4; 1794 1795 bits<4> Rd; 1796 bits<4> Rn; 1797 bits<4> Rm; 1798 1799 let Inst{11-8} = Rd; 1800 let Inst{19-16} = Rn; 1801 let Inst{3-0} = Rm; 1802} 1803 1804// Saturating add/subtract -- for disassembly only 1805 1806def t2QADD : T2I_pam<0b000, 0b1000, "qadd", 1807 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))], 1808 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1809def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1810def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1811def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1812def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [], 1813 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1814def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [], 1815 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1816def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1817def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", 1818 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))], 1819 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1820def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1821def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1822def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1823def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1824def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1825def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1826def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1827def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1828 1829// Signed/Unsigned add/subtract -- for disassembly only 1830 1831def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1832def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1833def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1834def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1835def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1836def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1837def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1838def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 1839def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 1840def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 1841def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 1842def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 1843 1844// Signed/Unsigned halving add/subtract -- for disassembly only 1845 1846def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1847def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 1848def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 1849def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 1850def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 1851def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 1852def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 1853def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 1854def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 1855def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 1856def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 1857def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 1858 1859// Helper class for disassembly only 1860// A6.3.16 & A6.3.17 1861// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1862class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 1863 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1864 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 1865 let Inst{31-27} = 0b11111; 1866 let Inst{26-24} = 0b011; 1867 let Inst{23} = long; 1868 let Inst{22-20} = op22_20; 1869 let Inst{7-4} = op7_4; 1870} 1871 1872class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 1873 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1874 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 1875 let Inst{31-27} = 0b11111; 1876 let Inst{26-24} = 0b011; 1877 let Inst{23} = long; 1878 let Inst{22-20} = op22_20; 1879 let Inst{7-4} = op7_4; 1880} 1881 1882// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 1883 1884def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 1885 (ins rGPR:$Rn, rGPR:$Rm), 1886 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>, 1887 Requires<[IsThumb2, HasThumb2DSP]> { 1888 let Inst{15-12} = 0b1111; 1889} 1890def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 1891 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 1892 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>, 1893 Requires<[IsThumb2, HasThumb2DSP]>; 1894 1895// Signed/Unsigned saturate -- for disassembly only 1896 1897class T2SatI<dag oops, dag iops, InstrItinClass itin, 1898 string opc, string asm, list<dag> pattern> 1899 : T2I<oops, iops, itin, opc, asm, pattern> { 1900 bits<4> Rd; 1901 bits<4> Rn; 1902 bits<5> sat_imm; 1903 bits<7> sh; 1904 1905 let Inst{11-8} = Rd; 1906 let Inst{19-16} = Rn; 1907 let Inst{4-0} = sat_imm; 1908 let Inst{21} = sh{5}; 1909 let Inst{14-12} = sh{4-2}; 1910 let Inst{7-6} = sh{1-0}; 1911} 1912 1913def t2SSAT: T2SatI< 1914 (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh), 1915 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", 1916 [/* For disassembly only; pattern left blank */]> { 1917 let Inst{31-27} = 0b11110; 1918 let Inst{25-22} = 0b1100; 1919 let Inst{20} = 0; 1920 let Inst{15} = 0; 1921} 1922 1923def t2SSAT16: T2SatI< 1924 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary, 1925 "ssat16", "\t$Rd, $sat_imm, $Rn", 1926 [/* For disassembly only; pattern left blank */]>, 1927 Requires<[IsThumb2, HasThumb2DSP]> { 1928 let Inst{31-27} = 0b11110; 1929 let Inst{25-22} = 0b1100; 1930 let Inst{20} = 0; 1931 let Inst{15} = 0; 1932 let Inst{21} = 1; // sh = '1' 1933 let Inst{14-12} = 0b000; // imm3 = '000' 1934 let Inst{7-6} = 0b00; // imm2 = '00' 1935} 1936 1937def t2USAT: T2SatI< 1938 (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh), 1939 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", 1940 [/* For disassembly only; pattern left blank */]> { 1941 let Inst{31-27} = 0b11110; 1942 let Inst{25-22} = 0b1110; 1943 let Inst{20} = 0; 1944 let Inst{15} = 0; 1945} 1946 1947def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), 1948 NoItinerary, 1949 "usat16", "\t$Rd, $sat_imm, $Rn", 1950 [/* For disassembly only; pattern left blank */]>, 1951 Requires<[IsThumb2, HasThumb2DSP]> { 1952 let Inst{31-27} = 0b11110; 1953 let Inst{25-22} = 0b1110; 1954 let Inst{20} = 0; 1955 let Inst{15} = 0; 1956 let Inst{21} = 1; // sh = '1' 1957 let Inst{14-12} = 0b000; // imm3 = '000' 1958 let Inst{7-6} = 0b00; // imm2 = '00' 1959} 1960 1961def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>; 1962def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>; 1963 1964//===----------------------------------------------------------------------===// 1965// Shift and rotate Instructions. 1966// 1967 1968defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, 1969 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">; 1970defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, 1971 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">; 1972defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, 1973 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">; 1974defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, 1975 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">; 1976 1977// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 1978def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 1979 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 1980 1981let Uses = [CPSR] in { 1982def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 1983 "rrx", "\t$Rd, $Rm", 1984 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> { 1985 let Inst{31-27} = 0b11101; 1986 let Inst{26-25} = 0b01; 1987 let Inst{24-21} = 0b0010; 1988 let Inst{19-16} = 0b1111; // Rn 1989 let Inst{14-12} = 0b000; 1990 let Inst{7-4} = 0b0011; 1991} 1992} 1993 1994let isCodeGenOnly = 1, Defs = [CPSR] in { 1995def t2MOVsrl_flag : T2TwoRegShiftImm< 1996 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 1997 "lsrs", ".w\t$Rd, $Rm, #1", 1998 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> { 1999 let Inst{31-27} = 0b11101; 2000 let Inst{26-25} = 0b01; 2001 let Inst{24-21} = 0b0010; 2002 let Inst{20} = 1; // The S bit. 2003 let Inst{19-16} = 0b1111; // Rn 2004 let Inst{5-4} = 0b01; // Shift type. 2005 // Shift amount = Inst{14-12:7-6} = 1. 2006 let Inst{14-12} = 0b000; 2007 let Inst{7-6} = 0b01; 2008} 2009def t2MOVsra_flag : T2TwoRegShiftImm< 2010 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2011 "asrs", ".w\t$Rd, $Rm, #1", 2012 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> { 2013 let Inst{31-27} = 0b11101; 2014 let Inst{26-25} = 0b01; 2015 let Inst{24-21} = 0b0010; 2016 let Inst{20} = 1; // The S bit. 2017 let Inst{19-16} = 0b1111; // Rn 2018 let Inst{5-4} = 0b10; // Shift type. 2019 // Shift amount = Inst{14-12:7-6} = 1. 2020 let Inst{14-12} = 0b000; 2021 let Inst{7-6} = 0b01; 2022} 2023} 2024 2025//===----------------------------------------------------------------------===// 2026// Bitwise Instructions. 2027// 2028 2029defm t2AND : T2I_bin_w_irs<0b0000, "and", 2030 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2031 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>; 2032defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2033 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2034 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>; 2035defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2036 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2037 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>; 2038 2039defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2040 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2041 BinOpFrag<(and node:$LHS, (not node:$RHS))>, 2042 "t2BIC">; 2043 2044class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2045 string opc, string asm, list<dag> pattern> 2046 : T2I<oops, iops, itin, opc, asm, pattern> { 2047 bits<4> Rd; 2048 bits<5> msb; 2049 bits<5> lsb; 2050 2051 let Inst{11-8} = Rd; 2052 let Inst{4-0} = msb{4-0}; 2053 let Inst{14-12} = lsb{4-2}; 2054 let Inst{7-6} = lsb{1-0}; 2055} 2056 2057class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2058 string opc, string asm, list<dag> pattern> 2059 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2060 bits<4> Rn; 2061 2062 let Inst{19-16} = Rn; 2063} 2064 2065let Constraints = "$src = $Rd" in 2066def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2067 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2068 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 2069 let Inst{31-27} = 0b11110; 2070 let Inst{26} = 0; // should be 0. 2071 let Inst{25} = 1; 2072 let Inst{24-20} = 0b10110; 2073 let Inst{19-16} = 0b1111; // Rn 2074 let Inst{15} = 0; 2075 let Inst{5} = 0; // should be 0. 2076 2077 bits<10> imm; 2078 let msb{4-0} = imm{9-5}; 2079 let lsb{4-0} = imm{4-0}; 2080} 2081 2082def t2SBFX: T2TwoRegBitFI< 2083 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2084 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2085 let Inst{31-27} = 0b11110; 2086 let Inst{25} = 1; 2087 let Inst{24-20} = 0b10100; 2088 let Inst{15} = 0; 2089} 2090 2091def t2UBFX: T2TwoRegBitFI< 2092 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2093 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2094 let Inst{31-27} = 0b11110; 2095 let Inst{25} = 1; 2096 let Inst{24-20} = 0b11100; 2097 let Inst{15} = 0; 2098} 2099 2100// A8.6.18 BFI - Bitfield insert (Encoding T1) 2101let Constraints = "$src = $Rd" in { 2102 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2103 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2104 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2105 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2106 bf_inv_mask_imm:$imm))]> { 2107 let Inst{31-27} = 0b11110; 2108 let Inst{26} = 0; // should be 0. 2109 let Inst{25} = 1; 2110 let Inst{24-20} = 0b10110; 2111 let Inst{15} = 0; 2112 let Inst{5} = 0; // should be 0. 2113 2114 bits<10> imm; 2115 let msb{4-0} = imm{9-5}; 2116 let lsb{4-0} = imm{4-0}; 2117 } 2118 2119 // GNU as only supports this form of bfi (w/ 4 arguments) 2120 let isAsmParserOnly = 1 in 2121 def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd), 2122 (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit, 2123 width_imm:$width), 2124 IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width", 2125 []> { 2126 let Inst{31-27} = 0b11110; 2127 let Inst{26} = 0; // should be 0. 2128 let Inst{25} = 1; 2129 let Inst{24-20} = 0b10110; 2130 let Inst{15} = 0; 2131 let Inst{5} = 0; // should be 0. 2132 2133 bits<5> lsbit; 2134 bits<5> width; 2135 let msb{4-0} = width; // Custom encoder => lsb+width-1 2136 let lsb{4-0} = lsbit; 2137 } 2138} 2139 2140defm t2ORN : T2I_bin_irs<0b0011, "orn", 2141 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2142 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 2143 "t2ORN", 0, "">; 2144 2145// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2146let AddedComplexity = 1 in 2147defm t2MVN : T2I_un_irs <0b0011, "mvn", 2148 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2149 UnOpFrag<(not node:$Src)>, 1, 1>; 2150 2151 2152let AddedComplexity = 1 in 2153def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2154 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2155 2156// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2157def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2158 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2159 Requires<[IsThumb2]>; 2160 2161def : T2Pat<(t2_so_imm_not:$src), 2162 (t2MVNi t2_so_imm_not:$src)>; 2163 2164//===----------------------------------------------------------------------===// 2165// Multiply Instructions. 2166// 2167let isCommutable = 1 in 2168def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2169 "mul", "\t$Rd, $Rn, $Rm", 2170 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { 2171 let Inst{31-27} = 0b11111; 2172 let Inst{26-23} = 0b0110; 2173 let Inst{22-20} = 0b000; 2174 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2175 let Inst{7-4} = 0b0000; // Multiply 2176} 2177 2178def t2MLA: T2FourReg< 2179 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2180 "mla", "\t$Rd, $Rn, $Rm, $Ra", 2181 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> { 2182 let Inst{31-27} = 0b11111; 2183 let Inst{26-23} = 0b0110; 2184 let Inst{22-20} = 0b000; 2185 let Inst{7-4} = 0b0000; // Multiply 2186} 2187 2188def t2MLS: T2FourReg< 2189 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2190 "mls", "\t$Rd, $Rn, $Rm, $Ra", 2191 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> { 2192 let Inst{31-27} = 0b11111; 2193 let Inst{26-23} = 0b0110; 2194 let Inst{22-20} = 0b000; 2195 let Inst{7-4} = 0b0001; // Multiply and Subtract 2196} 2197 2198// Extra precision multiplies with low / high results 2199let neverHasSideEffects = 1 in { 2200let isCommutable = 1 in { 2201def t2SMULL : T2MulLong<0b000, 0b0000, 2202 (outs rGPR:$RdLo, rGPR:$RdHi), 2203 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2204 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2205 2206def t2UMULL : T2MulLong<0b010, 0b0000, 2207 (outs rGPR:$RdLo, rGPR:$RdHi), 2208 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2209 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2210} // isCommutable 2211 2212// Multiply + accumulate 2213def t2SMLAL : T2MulLong<0b100, 0b0000, 2214 (outs rGPR:$RdLo, rGPR:$RdHi), 2215 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2216 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2217 2218def t2UMLAL : T2MulLong<0b110, 0b0000, 2219 (outs rGPR:$RdLo, rGPR:$RdHi), 2220 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2221 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2222 2223def t2UMAAL : T2MulLong<0b110, 0b0110, 2224 (outs rGPR:$RdLo, rGPR:$RdHi), 2225 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2226 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2227 Requires<[IsThumb2, HasThumb2DSP]>; 2228} // neverHasSideEffects 2229 2230// Rounding variants of the below included for disassembly only 2231 2232// Most significant word multiply 2233def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2234 "smmul", "\t$Rd, $Rn, $Rm", 2235 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, 2236 Requires<[IsThumb2, HasThumb2DSP]> { 2237 let Inst{31-27} = 0b11111; 2238 let Inst{26-23} = 0b0110; 2239 let Inst{22-20} = 0b101; 2240 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2241 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2242} 2243 2244def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2245 "smmulr", "\t$Rd, $Rn, $Rm", []>, 2246 Requires<[IsThumb2, HasThumb2DSP]> { 2247 let Inst{31-27} = 0b11111; 2248 let Inst{26-23} = 0b0110; 2249 let Inst{22-20} = 0b101; 2250 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2251 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2252} 2253 2254def t2SMMLA : T2FourReg< 2255 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2256 "smmla", "\t$Rd, $Rn, $Rm, $Ra", 2257 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>, 2258 Requires<[IsThumb2, HasThumb2DSP]> { 2259 let Inst{31-27} = 0b11111; 2260 let Inst{26-23} = 0b0110; 2261 let Inst{22-20} = 0b101; 2262 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2263} 2264 2265def t2SMMLAR: T2FourReg< 2266 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2267 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 2268 Requires<[IsThumb2, HasThumb2DSP]> { 2269 let Inst{31-27} = 0b11111; 2270 let Inst{26-23} = 0b0110; 2271 let Inst{22-20} = 0b101; 2272 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2273} 2274 2275def t2SMMLS: T2FourReg< 2276 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2277 "smmls", "\t$Rd, $Rn, $Rm, $Ra", 2278 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>, 2279 Requires<[IsThumb2, HasThumb2DSP]> { 2280 let Inst{31-27} = 0b11111; 2281 let Inst{26-23} = 0b0110; 2282 let Inst{22-20} = 0b110; 2283 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2284} 2285 2286def t2SMMLSR:T2FourReg< 2287 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2288 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 2289 Requires<[IsThumb2, HasThumb2DSP]> { 2290 let Inst{31-27} = 0b11111; 2291 let Inst{26-23} = 0b0110; 2292 let Inst{22-20} = 0b110; 2293 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2294} 2295 2296multiclass T2I_smul<string opc, PatFrag opnode> { 2297 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2298 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 2299 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2300 (sext_inreg rGPR:$Rm, i16)))]>, 2301 Requires<[IsThumb2, HasThumb2DSP]> { 2302 let Inst{31-27} = 0b11111; 2303 let Inst{26-23} = 0b0110; 2304 let Inst{22-20} = 0b001; 2305 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2306 let Inst{7-6} = 0b00; 2307 let Inst{5-4} = 0b00; 2308 } 2309 2310 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2311 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 2312 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2313 (sra rGPR:$Rm, (i32 16))))]>, 2314 Requires<[IsThumb2, HasThumb2DSP]> { 2315 let Inst{31-27} = 0b11111; 2316 let Inst{26-23} = 0b0110; 2317 let Inst{22-20} = 0b001; 2318 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2319 let Inst{7-6} = 0b00; 2320 let Inst{5-4} = 0b01; 2321 } 2322 2323 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2324 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 2325 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2326 (sext_inreg rGPR:$Rm, i16)))]>, 2327 Requires<[IsThumb2, HasThumb2DSP]> { 2328 let Inst{31-27} = 0b11111; 2329 let Inst{26-23} = 0b0110; 2330 let Inst{22-20} = 0b001; 2331 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2332 let Inst{7-6} = 0b00; 2333 let Inst{5-4} = 0b10; 2334 } 2335 2336 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2337 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 2338 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2339 (sra rGPR:$Rm, (i32 16))))]>, 2340 Requires<[IsThumb2, HasThumb2DSP]> { 2341 let Inst{31-27} = 0b11111; 2342 let Inst{26-23} = 0b0110; 2343 let Inst{22-20} = 0b001; 2344 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2345 let Inst{7-6} = 0b00; 2346 let Inst{5-4} = 0b11; 2347 } 2348 2349 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2350 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 2351 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2352 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>, 2353 Requires<[IsThumb2, HasThumb2DSP]> { 2354 let Inst{31-27} = 0b11111; 2355 let Inst{26-23} = 0b0110; 2356 let Inst{22-20} = 0b011; 2357 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2358 let Inst{7-6} = 0b00; 2359 let Inst{5-4} = 0b00; 2360 } 2361 2362 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2363 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 2364 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2365 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>, 2366 Requires<[IsThumb2, HasThumb2DSP]> { 2367 let Inst{31-27} = 0b11111; 2368 let Inst{26-23} = 0b0110; 2369 let Inst{22-20} = 0b011; 2370 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2371 let Inst{7-6} = 0b00; 2372 let Inst{5-4} = 0b01; 2373 } 2374} 2375 2376 2377multiclass T2I_smla<string opc, PatFrag opnode> { 2378 def BB : T2FourReg< 2379 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2380 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 2381 [(set rGPR:$Rd, (add rGPR:$Ra, 2382 (opnode (sext_inreg rGPR:$Rn, i16), 2383 (sext_inreg rGPR:$Rm, i16))))]>, 2384 Requires<[IsThumb2, HasThumb2DSP]> { 2385 let Inst{31-27} = 0b11111; 2386 let Inst{26-23} = 0b0110; 2387 let Inst{22-20} = 0b001; 2388 let Inst{7-6} = 0b00; 2389 let Inst{5-4} = 0b00; 2390 } 2391 2392 def BT : T2FourReg< 2393 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2394 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 2395 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16), 2396 (sra rGPR:$Rm, (i32 16)))))]>, 2397 Requires<[IsThumb2, HasThumb2DSP]> { 2398 let Inst{31-27} = 0b11111; 2399 let Inst{26-23} = 0b0110; 2400 let Inst{22-20} = 0b001; 2401 let Inst{7-6} = 0b00; 2402 let Inst{5-4} = 0b01; 2403 } 2404 2405 def TB : T2FourReg< 2406 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2407 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 2408 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2409 (sext_inreg rGPR:$Rm, i16))))]>, 2410 Requires<[IsThumb2, HasThumb2DSP]> { 2411 let Inst{31-27} = 0b11111; 2412 let Inst{26-23} = 0b0110; 2413 let Inst{22-20} = 0b001; 2414 let Inst{7-6} = 0b00; 2415 let Inst{5-4} = 0b10; 2416 } 2417 2418 def TT : T2FourReg< 2419 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2420 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 2421 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2422 (sra rGPR:$Rm, (i32 16)))))]>, 2423 Requires<[IsThumb2, HasThumb2DSP]> { 2424 let Inst{31-27} = 0b11111; 2425 let Inst{26-23} = 0b0110; 2426 let Inst{22-20} = 0b001; 2427 let Inst{7-6} = 0b00; 2428 let Inst{5-4} = 0b11; 2429 } 2430 2431 def WB : T2FourReg< 2432 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2433 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 2434 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2435 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>, 2436 Requires<[IsThumb2, HasThumb2DSP]> { 2437 let Inst{31-27} = 0b11111; 2438 let Inst{26-23} = 0b0110; 2439 let Inst{22-20} = 0b011; 2440 let Inst{7-6} = 0b00; 2441 let Inst{5-4} = 0b00; 2442 } 2443 2444 def WT : T2FourReg< 2445 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2446 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 2447 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2448 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>, 2449 Requires<[IsThumb2, HasThumb2DSP]> { 2450 let Inst{31-27} = 0b11111; 2451 let Inst{26-23} = 0b0110; 2452 let Inst{22-20} = 0b011; 2453 let Inst{7-6} = 0b00; 2454 let Inst{5-4} = 0b01; 2455 } 2456} 2457 2458defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2459defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2460 2461// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only 2462def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), 2463 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", 2464 [/* For disassembly only; pattern left blank */]>, 2465 Requires<[IsThumb2, HasThumb2DSP]>; 2466def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd), 2467 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm", 2468 [/* For disassembly only; pattern left blank */]>, 2469 Requires<[IsThumb2, HasThumb2DSP]>; 2470def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd), 2471 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm", 2472 [/* For disassembly only; pattern left blank */]>, 2473 Requires<[IsThumb2, HasThumb2DSP]>; 2474def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd), 2475 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm", 2476 [/* For disassembly only; pattern left blank */]>, 2477 Requires<[IsThumb2, HasThumb2DSP]>; 2478 2479// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2480// These are for disassembly only. 2481 2482def t2SMUAD: T2ThreeReg_mac< 2483 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2484 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>, 2485 Requires<[IsThumb2, HasThumb2DSP]> { 2486 let Inst{15-12} = 0b1111; 2487} 2488def t2SMUADX:T2ThreeReg_mac< 2489 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2490 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>, 2491 Requires<[IsThumb2, HasThumb2DSP]> { 2492 let Inst{15-12} = 0b1111; 2493} 2494def t2SMUSD: T2ThreeReg_mac< 2495 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2496 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>, 2497 Requires<[IsThumb2, HasThumb2DSP]> { 2498 let Inst{15-12} = 0b1111; 2499} 2500def t2SMUSDX:T2ThreeReg_mac< 2501 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2502 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>, 2503 Requires<[IsThumb2, HasThumb2DSP]> { 2504 let Inst{15-12} = 0b1111; 2505} 2506def t2SMLAD : T2FourReg_mac< 2507 0, 0b010, 0b0000, (outs rGPR:$Rd), 2508 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", 2509 "\t$Rd, $Rn, $Rm, $Ra", []>, 2510 Requires<[IsThumb2, HasThumb2DSP]>; 2511def t2SMLADX : T2FourReg_mac< 2512 0, 0b010, 0b0001, (outs rGPR:$Rd), 2513 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx", 2514 "\t$Rd, $Rn, $Rm, $Ra", []>, 2515 Requires<[IsThumb2, HasThumb2DSP]>; 2516def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), 2517 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", 2518 "\t$Rd, $Rn, $Rm, $Ra", []>, 2519 Requires<[IsThumb2, HasThumb2DSP]>; 2520def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd), 2521 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx", 2522 "\t$Rd, $Rn, $Rm, $Ra", []>, 2523 Requires<[IsThumb2, HasThumb2DSP]>; 2524def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2525 (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald", 2526 "\t$Ra, $Rd, $Rm, $Rn", []>, 2527 Requires<[IsThumb2, HasThumb2DSP]>; 2528def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2529 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx", 2530 "\t$Ra, $Rd, $Rm, $Rn", []>, 2531 Requires<[IsThumb2, HasThumb2DSP]>; 2532def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2533 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld", 2534 "\t$Ra, $Rd, $Rm, $Rn", []>, 2535 Requires<[IsThumb2, HasThumb2DSP]>; 2536def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2537 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx", 2538 "\t$Ra, $Rd, $Rm, $Rn", []>, 2539 Requires<[IsThumb2, HasThumb2DSP]>; 2540 2541//===----------------------------------------------------------------------===// 2542// Division Instructions. 2543// Signed and unsigned division on v7-M 2544// 2545def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2546 "sdiv", "\t$Rd, $Rn, $Rm", 2547 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 2548 Requires<[HasDivide, IsThumb2]> { 2549 let Inst{31-27} = 0b11111; 2550 let Inst{26-21} = 0b011100; 2551 let Inst{20} = 0b1; 2552 let Inst{15-12} = 0b1111; 2553 let Inst{7-4} = 0b1111; 2554} 2555 2556def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2557 "udiv", "\t$Rd, $Rn, $Rm", 2558 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 2559 Requires<[HasDivide, IsThumb2]> { 2560 let Inst{31-27} = 0b11111; 2561 let Inst{26-21} = 0b011101; 2562 let Inst{20} = 0b1; 2563 let Inst{15-12} = 0b1111; 2564 let Inst{7-4} = 0b1111; 2565} 2566 2567//===----------------------------------------------------------------------===// 2568// Misc. Arithmetic Instructions. 2569// 2570 2571class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2572 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2573 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2574 let Inst{31-27} = 0b11111; 2575 let Inst{26-22} = 0b01010; 2576 let Inst{21-20} = op1; 2577 let Inst{15-12} = 0b1111; 2578 let Inst{7-6} = 0b10; 2579 let Inst{5-4} = op2; 2580 let Rn{3-0} = Rm; 2581} 2582 2583def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2584 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>; 2585 2586def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2587 "rbit", "\t$Rd, $Rm", 2588 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>; 2589 2590def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2591 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>; 2592 2593def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2594 "rev16", ".w\t$Rd, $Rm", 2595 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>; 2596 2597def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2598 "revsh", ".w\t$Rd, $Rm", 2599 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>; 2600 2601def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 2602 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 2603 (t2REVSH rGPR:$Rm)>; 2604 2605def t2PKHBT : T2ThreeReg< 2606 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), 2607 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh", 2608 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 2609 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 2610 0xFFFF0000)))]>, 2611 Requires<[HasT2ExtractPack, IsThumb2]> { 2612 let Inst{31-27} = 0b11101; 2613 let Inst{26-25} = 0b01; 2614 let Inst{24-20} = 0b01100; 2615 let Inst{5} = 0; // BT form 2616 let Inst{4} = 0; 2617 2618 bits<5> sh; 2619 let Inst{14-12} = sh{4-2}; 2620 let Inst{7-6} = sh{1-0}; 2621} 2622 2623// Alternate cases for PKHBT where identities eliminate some nodes. 2624def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 2625 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 2626 Requires<[HasT2ExtractPack, IsThumb2]>; 2627def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 2628 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2629 Requires<[HasT2ExtractPack, IsThumb2]>; 2630 2631// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2632// will match the pattern below. 2633def t2PKHTB : T2ThreeReg< 2634 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh), 2635 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh", 2636 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 2637 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 2638 0xFFFF)))]>, 2639 Requires<[HasT2ExtractPack, IsThumb2]> { 2640 let Inst{31-27} = 0b11101; 2641 let Inst{26-25} = 0b01; 2642 let Inst{24-20} = 0b01100; 2643 let Inst{5} = 1; // TB form 2644 let Inst{4} = 0; 2645 2646 bits<5> sh; 2647 let Inst{14-12} = sh{4-2}; 2648 let Inst{7-6} = sh{1-0}; 2649} 2650 2651// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2652// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2653def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), 2654 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2655 Requires<[HasT2ExtractPack, IsThumb2]>; 2656def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 2657 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 2658 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 2659 Requires<[HasT2ExtractPack, IsThumb2]>; 2660 2661//===----------------------------------------------------------------------===// 2662// Comparison Instructions... 2663// 2664defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2665 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2666 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">; 2667 2668def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 2669 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 2670def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 2671 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 2672def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 2673 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 2674 2675//FIXME: Disable CMN, as CCodes are backwards from compare expectations 2676// Compare-to-zero still works out, just not the relationals 2677//defm t2CMN : T2I_cmp_irs<0b1000, "cmn", 2678// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2679defm t2CMNz : T2I_cmp_irs<0b1000, "cmn", 2680 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2681 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>, 2682 "t2CMNz">; 2683 2684//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2685// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2686 2687def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 2688 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>; 2689 2690defm t2TST : T2I_cmp_irs<0b0000, "tst", 2691 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2692 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 2693 "t2TST">; 2694defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2695 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2696 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 2697 "t2TEQ">; 2698 2699// Conditional moves 2700// FIXME: should be able to write a pattern for ARMcmov, but can't use 2701// a two-value operand where a dag node expects two operands. :( 2702let neverHasSideEffects = 1 in { 2703def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 2704 (ins rGPR:$false, rGPR:$Rm, pred:$p), 2705 4, IIC_iCMOVr, 2706 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 2707 RegConstraint<"$false = $Rd">; 2708 2709let isMoveImm = 1 in 2710def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd), 2711 (ins rGPR:$false, t2_so_imm:$imm, pred:$p), 2712 4, IIC_iCMOVi, 2713[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, 2714 RegConstraint<"$false = $Rd">; 2715 2716// FIXME: Pseudo-ize these. For now, just mark codegen only. 2717let isCodeGenOnly = 1 in { 2718let isMoveImm = 1 in 2719def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm), 2720 IIC_iCMOVi, 2721 "movw", "\t$Rd, $imm", []>, 2722 RegConstraint<"$false = $Rd"> { 2723 let Inst{31-27} = 0b11110; 2724 let Inst{25} = 1; 2725 let Inst{24-21} = 0b0010; 2726 let Inst{20} = 0; // The S bit. 2727 let Inst{15} = 0; 2728 2729 bits<4> Rd; 2730 bits<16> imm; 2731 2732 let Inst{11-8} = Rd; 2733 let Inst{19-16} = imm{15-12}; 2734 let Inst{26} = imm{11}; 2735 let Inst{14-12} = imm{10-8}; 2736 let Inst{7-0} = imm{7-0}; 2737} 2738 2739let isMoveImm = 1 in 2740def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst), 2741 (ins rGPR:$false, i32imm:$src, pred:$p), 2742 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">; 2743 2744let isMoveImm = 1 in 2745def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm), 2746 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm", 2747[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm, 2748 imm:$cc, CCR:$ccr))*/]>, 2749 RegConstraint<"$false = $Rd"> { 2750 let Inst{31-27} = 0b11110; 2751 let Inst{25} = 0; 2752 let Inst{24-21} = 0b0011; 2753 let Inst{20} = 0; // The S bit. 2754 let Inst{19-16} = 0b1111; // Rn 2755 let Inst{15} = 0; 2756} 2757 2758class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2759 string opc, string asm, list<dag> pattern> 2760 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> { 2761 let Inst{31-27} = 0b11101; 2762 let Inst{26-25} = 0b01; 2763 let Inst{24-21} = 0b0010; 2764 let Inst{20} = 0; // The S bit. 2765 let Inst{19-16} = 0b1111; // Rn 2766 let Inst{5-4} = opcod; // Shift type. 2767} 2768def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd), 2769 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2770 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>, 2771 RegConstraint<"$false = $Rd">; 2772def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd), 2773 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2774 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>, 2775 RegConstraint<"$false = $Rd">; 2776def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd), 2777 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2778 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>, 2779 RegConstraint<"$false = $Rd">; 2780def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd), 2781 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2782 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>, 2783 RegConstraint<"$false = $Rd">; 2784} // isCodeGenOnly = 1 2785} // neverHasSideEffects 2786 2787//===----------------------------------------------------------------------===// 2788// Atomic operations intrinsics 2789// 2790 2791// memory barriers protect the atomic sequences 2792let hasSideEffects = 1 in { 2793def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2794 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>, 2795 Requires<[IsThumb, HasDB]> { 2796 bits<4> opt; 2797 let Inst{31-4} = 0xf3bf8f5; 2798 let Inst{3-0} = opt; 2799} 2800} 2801 2802def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2803 "dsb", "\t$opt", []>, 2804 Requires<[IsThumb, HasDB]> { 2805 bits<4> opt; 2806 let Inst{31-4} = 0xf3bf8f4; 2807 let Inst{3-0} = opt; 2808} 2809 2810def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2811 "isb", "\t$opt", 2812 []>, Requires<[IsThumb2, HasDB]> { 2813 bits<4> opt; 2814 let Inst{31-4} = 0xf3bf8f6; 2815 let Inst{3-0} = opt; 2816} 2817 2818class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 2819 InstrItinClass itin, string opc, string asm, string cstr, 2820 list<dag> pattern, bits<4> rt2 = 0b1111> 2821 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2822 let Inst{31-27} = 0b11101; 2823 let Inst{26-20} = 0b0001101; 2824 let Inst{11-8} = rt2; 2825 let Inst{7-6} = 0b01; 2826 let Inst{5-4} = opcod; 2827 let Inst{3-0} = 0b1111; 2828 2829 bits<4> addr; 2830 bits<4> Rt; 2831 let Inst{19-16} = addr; 2832 let Inst{15-12} = Rt; 2833} 2834class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 2835 InstrItinClass itin, string opc, string asm, string cstr, 2836 list<dag> pattern, bits<4> rt2 = 0b1111> 2837 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2838 let Inst{31-27} = 0b11101; 2839 let Inst{26-20} = 0b0001100; 2840 let Inst{11-8} = rt2; 2841 let Inst{7-6} = 0b01; 2842 let Inst{5-4} = opcod; 2843 2844 bits<4> Rd; 2845 bits<4> addr; 2846 bits<4> Rt; 2847 let Inst{3-0} = Rd; 2848 let Inst{19-16} = addr; 2849 let Inst{15-12} = Rt; 2850} 2851 2852let mayLoad = 1 in { 2853def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), 2854 AddrModeNone, 4, NoItinerary, 2855 "ldrexb", "\t$Rt, $addr", "", []>; 2856def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr), 2857 AddrModeNone, 4, NoItinerary, 2858 "ldrexh", "\t$Rt, $addr", "", []>; 2859def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr), 2860 AddrModeNone, 4, NoItinerary, 2861 "ldrex", "\t$Rt, $addr", "", []> { 2862 let Inst{31-27} = 0b11101; 2863 let Inst{26-20} = 0b0000101; 2864 let Inst{11-8} = 0b1111; 2865 let Inst{7-0} = 0b00000000; // imm8 = 0 2866 2867 bits<4> Rt; 2868 bits<4> addr; 2869 let Inst{19-16} = addr; 2870 let Inst{15-12} = Rt; 2871} 2872let hasExtraDefRegAllocReq = 1 in 2873def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), 2874 (ins t2addrmode_reg:$addr), 2875 AddrModeNone, 4, NoItinerary, 2876 "ldrexd", "\t$Rt, $Rt2, $addr", "", 2877 [], {?, ?, ?, ?}> { 2878 bits<4> Rt2; 2879 let Inst{11-8} = Rt2; 2880} 2881} 2882 2883let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 2884def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), 2885 (ins rGPR:$Rt, t2addrmode_reg:$addr), 2886 AddrModeNone, 4, NoItinerary, 2887 "strexb", "\t$Rd, $Rt, $addr", "", []>; 2888def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), 2889 (ins rGPR:$Rt, t2addrmode_reg:$addr), 2890 AddrModeNone, 4, NoItinerary, 2891 "strexh", "\t$Rd, $Rt, $addr", "", []>; 2892def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr), 2893 AddrModeNone, 4, NoItinerary, 2894 "strex", "\t$Rd, $Rt, $addr", "", 2895 []> { 2896 let Inst{31-27} = 0b11101; 2897 let Inst{26-20} = 0b0000100; 2898 let Inst{7-0} = 0b00000000; // imm8 = 0 2899 2900 bits<4> Rd; 2901 bits<4> addr; 2902 bits<4> Rt; 2903 let Inst{11-8} = Rd; 2904 let Inst{19-16} = addr; 2905 let Inst{15-12} = Rt; 2906} 2907} 2908 2909let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in 2910def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), 2911 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr), 2912 AddrModeNone, 4, NoItinerary, 2913 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 2914 {?, ?, ?, ?}> { 2915 bits<4> Rt2; 2916 let Inst{11-8} = Rt2; 2917} 2918 2919def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>, 2920 Requires<[IsThumb2, HasV7]> { 2921 let Inst{31-16} = 0xf3bf; 2922 let Inst{15-14} = 0b10; 2923 let Inst{13} = 0; 2924 let Inst{12} = 0; 2925 let Inst{11-8} = 0b1111; 2926 let Inst{7-4} = 0b0010; 2927 let Inst{3-0} = 0b1111; 2928} 2929 2930//===----------------------------------------------------------------------===// 2931// SJLJ Exception handling intrinsics 2932// eh_sjlj_setjmp() is an instruction sequence to store the return 2933// address and save #0 in R0 for the non-longjmp case. 2934// Since by its nature we may be coming from some other function to get 2935// here, and we're using the stack frame for the containing function to 2936// save/restore registers, we can't keep anything live in regs across 2937// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 2938// when we get here from a longjmp(). We force everything out of registers 2939// except for our own input by listing the relevant registers in Defs. By 2940// doing so, we also cause the prologue/epilogue code to actively preserve 2941// all of the callee-saved resgisters, which is exactly what we want. 2942// $val is a scratch register for our use. 2943let Defs = 2944 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 2945 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], 2946 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { 2947 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 2948 AddrModeNone, 0, NoItinerary, "", "", 2949 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 2950 Requires<[IsThumb2, HasVFP2]>; 2951} 2952 2953let Defs = 2954 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 2955 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { 2956 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 2957 AddrModeNone, 0, NoItinerary, "", "", 2958 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 2959 Requires<[IsThumb2, NoVFP]>; 2960} 2961 2962 2963//===----------------------------------------------------------------------===// 2964// Control-Flow Instructions 2965// 2966 2967// FIXME: remove when we have a way to marking a MI with these properties. 2968// FIXME: Should pc be an implicit operand like PICADD, etc? 2969let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2970 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 2971def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 2972 reglist:$regs, variable_ops), 2973 4, IIC_iLoad_mBr, [], 2974 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 2975 RegConstraint<"$Rn = $wb">; 2976 2977let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 2978let isPredicable = 1 in 2979def t2B : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br, 2980 "b.w\t$target", 2981 [(br bb:$target)]> { 2982 let Inst{31-27} = 0b11110; 2983 let Inst{15-14} = 0b10; 2984 let Inst{12} = 1; 2985 2986 bits<20> target; 2987 let Inst{26} = target{19}; 2988 let Inst{11} = target{18}; 2989 let Inst{13} = target{17}; 2990 let Inst{21-16} = target{16-11}; 2991 let Inst{10-0} = target{10-0}; 2992} 2993 2994let isNotDuplicable = 1, isIndirectBranch = 1 in { 2995def t2BR_JT : t2PseudoInst<(outs), 2996 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id), 2997 0, IIC_Br, 2998 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 2999 3000// FIXME: Add a non-pc based case that can be predicated. 3001def t2TBB_JT : t2PseudoInst<(outs), 3002 (ins GPR:$index, i32imm:$jt, i32imm:$id), 3003 0, IIC_Br, []>; 3004 3005def t2TBH_JT : t2PseudoInst<(outs), 3006 (ins GPR:$index, i32imm:$jt, i32imm:$id), 3007 0, IIC_Br, []>; 3008 3009def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br, 3010 "tbb", "\t[$Rn, $Rm]", []> { 3011 bits<4> Rn; 3012 bits<4> Rm; 3013 let Inst{31-20} = 0b111010001101; 3014 let Inst{19-16} = Rn; 3015 let Inst{15-5} = 0b11110000000; 3016 let Inst{4} = 0; // B form 3017 let Inst{3-0} = Rm; 3018} 3019 3020def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br, 3021 "tbh", "\t[$Rn, $Rm, lsl #1]", []> { 3022 bits<4> Rn; 3023 bits<4> Rm; 3024 let Inst{31-20} = 0b111010001101; 3025 let Inst{19-16} = Rn; 3026 let Inst{15-5} = 0b11110000000; 3027 let Inst{4} = 1; // H form 3028 let Inst{3-0} = Rm; 3029} 3030} // isNotDuplicable, isIndirectBranch 3031 3032} // isBranch, isTerminator, isBarrier 3033 3034// FIXME: should be able to write a pattern for ARMBrcond, but can't use 3035// a two-value operand where a dag node expects two operands. :( 3036let isBranch = 1, isTerminator = 1 in 3037def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3038 "b", ".w\t$target", 3039 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 3040 let Inst{31-27} = 0b11110; 3041 let Inst{15-14} = 0b10; 3042 let Inst{12} = 0; 3043 3044 bits<4> p; 3045 let Inst{25-22} = p; 3046 3047 bits<21> target; 3048 let Inst{26} = target{20}; 3049 let Inst{11} = target{19}; 3050 let Inst{13} = target{18}; 3051 let Inst{21-16} = target{17-12}; 3052 let Inst{10-0} = target{11-1}; 3053 3054 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3055} 3056 3057// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so 3058// it goes here. 3059let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3060 // Darwin version. 3061 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], 3062 Uses = [SP] in 3063 def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops), 3064 4, IIC_Br, [], 3065 (t2B uncondbrtarget:$dst)>, 3066 Requires<[IsThumb2, IsDarwin]>; 3067} 3068 3069// IT block 3070let Defs = [ITSTATE] in 3071def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3072 AddrModeNone, 2, IIC_iALUx, 3073 "it$mask\t$cc", "", []> { 3074 // 16-bit instruction. 3075 let Inst{31-16} = 0x0000; 3076 let Inst{15-8} = 0b10111111; 3077 3078 bits<4> cc; 3079 bits<4> mask; 3080 let Inst{7-4} = cc; 3081 let Inst{3-0} = mask; 3082 3083 let DecoderMethod = "DecodeIT"; 3084} 3085 3086// Branch and Exchange Jazelle -- for disassembly only 3087// Rm = Inst{19-16} 3088def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> { 3089 bits<4> func; 3090 let Inst{31-27} = 0b11110; 3091 let Inst{26} = 0; 3092 let Inst{25-20} = 0b111100; 3093 let Inst{19-16} = func; 3094 let Inst{15-0} = 0b1000111100000000; 3095} 3096 3097// Compare and branch on zero / non-zero 3098let isBranch = 1, isTerminator = 1 in { 3099 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3100 "cbz\t$Rn, $target", []>, 3101 T1Misc<{0,0,?,1,?,?,?}>, 3102 Requires<[IsThumb2]> { 3103 // A8.6.27 3104 bits<6> target; 3105 bits<3> Rn; 3106 let Inst{9} = target{5}; 3107 let Inst{7-3} = target{4-0}; 3108 let Inst{2-0} = Rn; 3109 } 3110 3111 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3112 "cbnz\t$Rn, $target", []>, 3113 T1Misc<{1,0,?,1,?,?,?}>, 3114 Requires<[IsThumb2]> { 3115 // A8.6.27 3116 bits<6> target; 3117 bits<3> Rn; 3118 let Inst{9} = target{5}; 3119 let Inst{7-3} = target{4-0}; 3120 let Inst{2-0} = Rn; 3121 } 3122} 3123 3124 3125// Change Processor State is a system instruction -- for disassembly and 3126// parsing only. 3127// FIXME: Since the asm parser has currently no clean way to handle optional 3128// operands, create 3 versions of the same instruction. Once there's a clean 3129// framework to represent optional operands, change this behavior. 3130class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3131 !strconcat("cps", asm_op), 3132 [/* For disassembly only; pattern left blank */]> { 3133 bits<2> imod; 3134 bits<3> iflags; 3135 bits<5> mode; 3136 bit M; 3137 3138 let Inst{31-27} = 0b11110; 3139 let Inst{26} = 0; 3140 let Inst{25-20} = 0b111010; 3141 let Inst{19-16} = 0b1111; 3142 let Inst{15-14} = 0b10; 3143 let Inst{12} = 0; 3144 let Inst{10-9} = imod; 3145 let Inst{8} = M; 3146 let Inst{7-5} = iflags; 3147 let Inst{4-0} = mode; 3148 let DecoderMethod = "DecodeT2CPSInstruction"; 3149} 3150 3151let M = 1 in 3152 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3153 "$imod.w\t$iflags, $mode">; 3154let mode = 0, M = 0 in 3155 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3156 "$imod.w\t$iflags">; 3157let imod = 0, iflags = 0, M = 1 in 3158 def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">; 3159 3160// A6.3.4 Branches and miscellaneous control 3161// Table A6-14 Change Processor State, and hint instructions 3162// Helper class for disassembly only. 3163class T2I_hint<bits<8> op7_0, string opc, string asm> 3164 : T2I<(outs), (ins), NoItinerary, opc, asm, 3165 [/* For disassembly only; pattern left blank */]> { 3166 let Inst{31-20} = 0xf3a; 3167 let Inst{19-16} = 0b1111; 3168 let Inst{15-14} = 0b10; 3169 let Inst{12} = 0; 3170 let Inst{10-8} = 0b000; 3171 let Inst{7-0} = op7_0; 3172} 3173 3174def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 3175def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 3176def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 3177def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 3178def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 3179 3180def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { 3181 bits<4> opt; 3182 let Inst{31-20} = 0b111100111010; 3183 let Inst{19-16} = 0b1111; 3184 let Inst{15-8} = 0b10000000; 3185 let Inst{7-4} = 0b1111; 3186 let Inst{3-0} = opt; 3187} 3188 3189// Secure Monitor Call is a system instruction -- for disassembly only 3190// Option = Inst{19-16} 3191def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 3192 [/* For disassembly only; pattern left blank */]> { 3193 let Inst{31-27} = 0b11110; 3194 let Inst{26-20} = 0b1111111; 3195 let Inst{15-12} = 0b1000; 3196 3197 bits<4> opt; 3198 let Inst{19-16} = opt; 3199} 3200 3201class T2SRS<bits<12> op31_20, 3202 dag oops, dag iops, InstrItinClass itin, 3203 string opc, string asm, list<dag> pattern> 3204 : T2I<oops, iops, itin, opc, asm, pattern> { 3205 let Inst{31-20} = op31_20{11-0}; 3206 3207 bits<5> mode; 3208 let Inst{4-0} = mode{4-0}; 3209} 3210 3211// Store Return State is a system instruction -- for disassembly only 3212def t2SRSDBW : T2SRS<0b111010000010, 3213 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode", 3214 [/* For disassembly only; pattern left blank */]>; 3215def t2SRSDB : T2SRS<0b111010000000, 3216 (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode", 3217 [/* For disassembly only; pattern left blank */]>; 3218def t2SRSIAW : T2SRS<0b111010011010, 3219 (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode", 3220 [/* For disassembly only; pattern left blank */]>; 3221def t2SRSIA : T2SRS<0b111010011000, 3222 (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode", 3223 [/* For disassembly only; pattern left blank */]>; 3224 3225// Return From Exception is a system instruction -- for disassembly only 3226 3227class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 3228 string opc, string asm, list<dag> pattern> 3229 : T2I<oops, iops, itin, opc, asm, pattern> { 3230 let Inst{31-20} = op31_20{11-0}; 3231 3232 bits<4> Rn; 3233 let Inst{19-16} = Rn; 3234 let Inst{15-0} = 0xc000; 3235} 3236 3237def t2RFEDBW : T2RFE<0b111010000011, 3238 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 3239 [/* For disassembly only; pattern left blank */]>; 3240def t2RFEDB : T2RFE<0b111010000001, 3241 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 3242 [/* For disassembly only; pattern left blank */]>; 3243def t2RFEIAW : T2RFE<0b111010011011, 3244 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 3245 [/* For disassembly only; pattern left blank */]>; 3246def t2RFEIA : T2RFE<0b111010011001, 3247 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 3248 [/* For disassembly only; pattern left blank */]>; 3249 3250//===----------------------------------------------------------------------===// 3251// Non-Instruction Patterns 3252// 3253 3254// 32-bit immediate using movw + movt. 3255// This is a single pseudo instruction to make it re-materializable. 3256// FIXME: Remove this when we can do generalized remat. 3257let isReMaterializable = 1, isMoveImm = 1 in 3258def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 3259 [(set rGPR:$dst, (i32 imm:$src))]>, 3260 Requires<[IsThumb, HasV6T2]>; 3261 3262// Pseudo instruction that combines movw + movt + add pc (if pic). 3263// It also makes it possible to rematerialize the instructions. 3264// FIXME: Remove this when we can do generalized remat and when machine licm 3265// can properly the instructions. 3266let isReMaterializable = 1 in { 3267def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3268 IIC_iMOVix2addpc, 3269 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 3270 Requires<[IsThumb2, UseMovt]>; 3271 3272def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3273 IIC_iMOVix2, 3274 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 3275 Requires<[IsThumb2, UseMovt]>; 3276} 3277 3278// ConstantPool, GlobalAddress, and JumpTable 3279def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 3280 Requires<[IsThumb2, DontUseMovt]>; 3281def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 3282def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 3283 Requires<[IsThumb2, UseMovt]>; 3284 3285def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 3286 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 3287 3288// Pseudo instruction that combines ldr from constpool and add pc. This should 3289// be expanded into two instructions late to allow if-conversion and 3290// scheduling. 3291let canFoldAsLoad = 1, isReMaterializable = 1 in 3292def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 3293 IIC_iLoadiALU, 3294 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 3295 imm:$cp))]>, 3296 Requires<[IsThumb2]>; 3297//===----------------------------------------------------------------------===// 3298// Coprocessor load/store -- for disassembly only 3299// 3300class T2CI<dag oops, dag iops, string opc, string asm> 3301 : T2I<oops, iops, NoItinerary, opc, asm, []> { 3302 let Inst{27-25} = 0b110; 3303} 3304 3305multiclass T2LdStCop<bits<4> op31_28, bit load, string opc> { 3306 def _OFFSET : T2CI<(outs), 3307 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3308 opc, "\tp$cop, cr$CRd, $addr"> { 3309 let Inst{31-28} = op31_28; 3310 let Inst{24} = 1; // P = 1 3311 let Inst{21} = 0; // W = 0 3312 let Inst{22} = 0; // D = 0 3313 let Inst{20} = load; 3314 let DecoderMethod = "DecodeCopMemInstruction"; 3315 } 3316 3317 def _PRE : T2CI<(outs), 3318 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3319 opc, "\tp$cop, cr$CRd, $addr!"> { 3320 let Inst{31-28} = op31_28; 3321 let Inst{24} = 1; // P = 1 3322 let Inst{21} = 1; // W = 1 3323 let Inst{22} = 0; // D = 0 3324 let Inst{20} = load; 3325 let DecoderMethod = "DecodeCopMemInstruction"; 3326 } 3327 3328 def _POST : T2CI<(outs), 3329 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3330 opc, "\tp$cop, cr$CRd, $addr"> { 3331 let Inst{31-28} = op31_28; 3332 let Inst{24} = 0; // P = 0 3333 let Inst{21} = 1; // W = 1 3334 let Inst{22} = 0; // D = 0 3335 let Inst{20} = load; 3336 let DecoderMethod = "DecodeCopMemInstruction"; 3337 } 3338 3339 def _OPTION : T2CI<(outs), 3340 (ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option), 3341 opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { 3342 let Inst{31-28} = op31_28; 3343 let Inst{24} = 0; // P = 0 3344 let Inst{23} = 1; // U = 1 3345 let Inst{21} = 0; // W = 0 3346 let Inst{22} = 0; // D = 0 3347 let Inst{20} = load; 3348 let DecoderMethod = "DecodeCopMemInstruction"; 3349 } 3350 3351 def L_OFFSET : T2CI<(outs), 3352 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3353 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> { 3354 let Inst{31-28} = op31_28; 3355 let Inst{24} = 1; // P = 1 3356 let Inst{21} = 0; // W = 0 3357 let Inst{22} = 1; // D = 1 3358 let Inst{20} = load; 3359 let DecoderMethod = "DecodeCopMemInstruction"; 3360 } 3361 3362 def L_PRE : T2CI<(outs), 3363 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), 3364 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> { 3365 let Inst{31-28} = op31_28; 3366 let Inst{24} = 1; // P = 1 3367 let Inst{21} = 1; // W = 1 3368 let Inst{22} = 1; // D = 1 3369 let Inst{20} = load; 3370 let DecoderMethod = "DecodeCopMemInstruction"; 3371 } 3372 3373 def L_POST : T2CI<(outs), 3374 (ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr, 3375 postidx_imm8s4:$offset), 3376 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr, $offset"> { 3377 let Inst{31-28} = op31_28; 3378 let Inst{24} = 0; // P = 0 3379 let Inst{21} = 1; // W = 1 3380 let Inst{22} = 1; // D = 1 3381 let Inst{20} = load; 3382 let DecoderMethod = "DecodeCopMemInstruction"; 3383 } 3384 3385 def L_OPTION : T2CI<(outs), 3386 (ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option), 3387 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> { 3388 let Inst{31-28} = op31_28; 3389 let Inst{24} = 0; // P = 0 3390 let Inst{23} = 1; // U = 1 3391 let Inst{21} = 0; // W = 0 3392 let Inst{22} = 1; // D = 1 3393 let Inst{20} = load; 3394 let DecoderMethod = "DecodeCopMemInstruction"; 3395 } 3396} 3397 3398defm t2LDC : T2LdStCop<0b1111, 1, "ldc">; 3399defm t2STC : T2LdStCop<0b1111, 0, "stc">; 3400 3401 3402//===----------------------------------------------------------------------===// 3403// Move between special register and ARM core register -- for disassembly only 3404// 3405 3406class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12, 3407 dag oops, dag iops, InstrItinClass itin, 3408 string opc, string asm, list<dag> pattern> 3409 : T2I<oops, iops, itin, opc, asm, pattern> { 3410 let Inst{31-20} = op31_20{11-0}; 3411 let Inst{15-14} = op15_14{1-0}; 3412 let Inst{13} = 0b0; 3413 let Inst{12} = op12{0}; 3414 let Inst{7-0} = 0; 3415} 3416 3417class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12, 3418 dag oops, dag iops, InstrItinClass itin, 3419 string opc, string asm, list<dag> pattern> 3420 : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> { 3421 bits<4> Rd; 3422 let Inst{11-8} = Rd; 3423 let Inst{19-16} = 0b1111; 3424} 3425 3426def t2MRS : T2MRS<0b111100111110, 0b10, 0, 3427 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr", 3428 [/* For disassembly only; pattern left blank */]>; 3429def t2MRSsys : T2MRS<0b111100111111, 0b10, 0, 3430 (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", 3431 [/* For disassembly only; pattern left blank */]>; 3432 3433// Move from ARM core register to Special Register 3434// 3435// No need to have both system and application versions, the encodings are the 3436// same and the assembly parser has no way to distinguish between them. The mask 3437// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 3438// the mask with the fields to be accessed in the special register. 3439def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */, 3440 0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn), 3441 NoItinerary, "msr", "\t$mask, $Rn", 3442 [/* For disassembly only; pattern left blank */]> { 3443 bits<5> mask; 3444 bits<4> Rn; 3445 let Inst{19-16} = Rn; 3446 let Inst{20} = mask{4}; // R Bit 3447 let Inst{11-8} = mask{3-0}; 3448} 3449 3450//===----------------------------------------------------------------------===// 3451// Move between coprocessor and ARM core register 3452// 3453 3454class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 3455 list<dag> pattern> 3456 : T2Cop<Op, oops, iops, 3457 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), 3458 pattern> { 3459 let Inst{27-24} = 0b1110; 3460 let Inst{20} = direction; 3461 let Inst{4} = 1; 3462 3463 bits<4> Rt; 3464 bits<4> cop; 3465 bits<3> opc1; 3466 bits<3> opc2; 3467 bits<4> CRm; 3468 bits<4> CRn; 3469 3470 let Inst{15-12} = Rt; 3471 let Inst{11-8} = cop; 3472 let Inst{23-21} = opc1; 3473 let Inst{7-5} = opc2; 3474 let Inst{3-0} = CRm; 3475 let Inst{19-16} = CRn; 3476} 3477 3478class t2MovRRCopro<bits<4> Op, string opc, bit direction, 3479 list<dag> pattern = []> 3480 : T2Cop<Op, (outs), 3481 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 3482 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { 3483 let Inst{27-24} = 0b1100; 3484 let Inst{23-21} = 0b010; 3485 let Inst{20} = direction; 3486 3487 bits<4> Rt; 3488 bits<4> Rt2; 3489 bits<4> cop; 3490 bits<4> opc1; 3491 bits<4> CRm; 3492 3493 let Inst{15-12} = Rt; 3494 let Inst{19-16} = Rt2; 3495 let Inst{11-8} = cop; 3496 let Inst{7-4} = opc1; 3497 let Inst{3-0} = CRm; 3498} 3499 3500/* from ARM core register to coprocessor */ 3501def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 3502 (outs), 3503 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3504 c_imm:$CRm, imm0_7:$opc2), 3505 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3506 imm:$CRm, imm:$opc2)]>; 3507def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 3508 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3509 c_imm:$CRm, imm0_7:$opc2), 3510 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3511 imm:$CRm, imm:$opc2)]>; 3512 3513/* from coprocessor to ARM core register */ 3514def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 3515 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3516 c_imm:$CRm, imm0_7:$opc2), []>; 3517 3518def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 3519 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3520 c_imm:$CRm, imm0_7:$opc2), []>; 3521 3522def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3523 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3524 3525def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3526 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3527 3528 3529/* from ARM core register to coprocessor */ 3530def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, 3531 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 3532 imm:$CRm)]>; 3533def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, 3534 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, 3535 GPR:$Rt2, imm:$CRm)]>; 3536/* from coprocessor to ARM core register */ 3537def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>; 3538 3539def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>; 3540 3541//===----------------------------------------------------------------------===// 3542// Other Coprocessor Instructions. 3543// 3544 3545def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3546 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3547 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3548 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3549 imm:$CRm, imm:$opc2)]> { 3550 let Inst{27-24} = 0b1110; 3551 3552 bits<4> opc1; 3553 bits<4> CRn; 3554 bits<4> CRd; 3555 bits<4> cop; 3556 bits<3> opc2; 3557 bits<4> CRm; 3558 3559 let Inst{3-0} = CRm; 3560 let Inst{4} = 0; 3561 let Inst{7-5} = opc2; 3562 let Inst{11-8} = cop; 3563 let Inst{15-12} = CRd; 3564 let Inst{19-16} = CRn; 3565 let Inst{23-20} = opc1; 3566} 3567 3568def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3569 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3570 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3571 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3572 imm:$CRm, imm:$opc2)]> { 3573 let Inst{27-24} = 0b1110; 3574 3575 bits<4> opc1; 3576 bits<4> CRn; 3577 bits<4> CRd; 3578 bits<4> cop; 3579 bits<3> opc2; 3580 bits<4> CRm; 3581 3582 let Inst{3-0} = CRm; 3583 let Inst{4} = 0; 3584 let Inst{7-5} = opc2; 3585 let Inst{11-8} = cop; 3586 let Inst{15-12} = CRd; 3587 let Inst{19-16} = CRn; 3588 let Inst{23-20} = opc1; 3589} 3590 3591 3592 3593//===----------------------------------------------------------------------===// 3594// Non-Instruction Patterns 3595// 3596 3597// SXT/UXT with no rotate 3598let AddedComplexity = 16 in { 3599def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 3600 Requires<[IsThumb2]>; 3601def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 3602 Requires<[IsThumb2]>; 3603def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 3604 Requires<[HasT2ExtractPack, IsThumb2]>; 3605def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 3606 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3607 Requires<[HasT2ExtractPack, IsThumb2]>; 3608def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 3609 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3610 Requires<[HasT2ExtractPack, IsThumb2]>; 3611} 3612 3613def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 3614 Requires<[IsThumb2]>; 3615def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 3616 Requires<[IsThumb2]>; 3617def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 3618 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3619 Requires<[HasT2ExtractPack, IsThumb2]>; 3620def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 3621 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3622 Requires<[HasT2ExtractPack, IsThumb2]>; 3623 3624// Atomic load/store patterns 3625def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 3626 (t2LDRBi12 t2addrmode_imm12:$addr)>; 3627def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 3628 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 3629def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 3630 (t2LDRBs t2addrmode_so_reg:$addr)>; 3631def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 3632 (t2LDRHi12 t2addrmode_imm12:$addr)>; 3633def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 3634 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 3635def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 3636 (t2LDRHs t2addrmode_so_reg:$addr)>; 3637def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 3638 (t2LDRi12 t2addrmode_imm12:$addr)>; 3639def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 3640 (t2LDRi8 t2addrmode_negimm8:$addr)>; 3641def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 3642 (t2LDRs t2addrmode_so_reg:$addr)>; 3643def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 3644 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 3645def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 3646 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3647def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 3648 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 3649def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 3650 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 3651def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 3652 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3653def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 3654 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 3655def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 3656 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 3657def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 3658 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3659def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 3660 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 3661 3662 3663//===----------------------------------------------------------------------===// 3664// Assembler aliases 3665// 3666 3667// Aliases for ADC without the ".w" optional width specifier. 3668def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 3669 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3670def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 3671 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3672 pred:$p, cc_out:$s)>; 3673 3674// Aliases for SBC without the ".w" optional width specifier. 3675def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 3676 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3677def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 3678 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3679 pred:$p, cc_out:$s)>; 3680 3681// Aliases for ADD without the ".w" optional width specifier. 3682def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 3683 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3684def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 3685 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 3686def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 3687 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3688def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 3689 (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 3690 pred:$p, cc_out:$s)>; 3691 3692// Alias for compares without the ".w" optional width specifier. 3693def : t2InstAlias<"cmn${p} $Rn, $Rm", 3694 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3695def : t2InstAlias<"teq${p} $Rn, $Rm", 3696 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3697def : t2InstAlias<"tst${p} $Rn, $Rm", 3698 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3699 3700// Memory barriers 3701def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>; 3702def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>; 3703def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>; 3704 3705// Alias for LDR, LDRB, LDRH without the ".w" optional width specifier. 3706def : t2InstAlias<"ldr${p} $Rt, $addr", 3707 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3708def : t2InstAlias<"ldrb${p} $Rt, $addr", 3709 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3710def : t2InstAlias<"ldrh${p} $Rt, $addr", 3711 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3712