ARMInstrThumb2.td revision 65b7f3af76d0ba5bce49b56ab3e18f970b95f9d1
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 53// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72// Break t2_so_imm's up into two pieces. This handles immediates with up to 16 73// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12] 74// to get the first/second pieces. 75def t2_so_imm2part : Operand<i32>, 76 PatLeaf<(imm), [{ 77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue()); 78 }]> { 79} 80 81def t2_so_imm2part_1 : SDNodeXForm<imm, [{ 82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue()); 83 return CurDAG->getTargetConstant(V, MVT::i32); 84}]>; 85 86def t2_so_imm2part_2 : SDNodeXForm<imm, [{ 87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue()); 88 return CurDAG->getTargetConstant(V, MVT::i32); 89}]>; 90 91/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 92def imm1_31 : PatLeaf<(i32 imm), [{ 93 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 94}]>; 95 96/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 97def imm0_4095 : Operand<i32>, 98 PatLeaf<(i32 imm), [{ 99 return (uint32_t)N->getZExtValue() < 4096; 100}]>; 101 102def imm0_4095_neg : PatLeaf<(i32 imm), [{ 103 return (uint32_t)(-N->getZExtValue()) < 4096; 104}], imm_neg_XFORM>; 105 106def imm0_255_neg : PatLeaf<(i32 imm), [{ 107 return (uint32_t)(-N->getZExtValue()) < 255; 108}], imm_neg_XFORM>; 109 110// Define Thumb2 specific addressing modes. 111 112// t2addrmode_imm12 := reg + imm12 113def t2addrmode_imm12 : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 115 let PrintMethod = "printT2AddrModeImm12Operand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119// t2addrmode_imm8 := reg - imm8 120def t2addrmode_imm8 : Operand<i32>, 121 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 122 let PrintMethod = "printT2AddrModeImm8Operand"; 123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 124} 125 126def t2am_imm8_offset : Operand<i32>, 127 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 128 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 129} 130 131// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 132def t2addrmode_imm8s4 : Operand<i32>, 133 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 134 let PrintMethod = "printT2AddrModeImm8s4Operand"; 135 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 136} 137 138// t2addrmode_so_reg := reg + (reg << imm2) 139def t2addrmode_so_reg : Operand<i32>, 140 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 141 let PrintMethod = "printT2AddrModeSoRegOperand"; 142 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 143} 144 145 146//===----------------------------------------------------------------------===// 147// Multiclass helpers... 148// 149 150/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 151/// unary operation that produces a value. These are predicable and can be 152/// changed to modify CPSR. 153multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 154 // shifted imm 155 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 156 opc, " $dst, $src", 157 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 158 let isAsCheapAsAMove = Cheap; 159 let isReMaterializable = ReMat; 160 } 161 // register 162 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 163 opc, ".w $dst, $src", 164 [(set GPR:$dst, (opnode GPR:$src))]>; 165 // shifted register 166 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, 167 opc, ".w $dst, $src", 168 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 169} 170 171/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 172// binary operation that produces a value. These are predicable and can be 173/// changed to modify CPSR. 174multiclass T2I_bin_irs<string opc, PatFrag opnode, 175 bit Commutable = 0, string wide =""> { 176 // shifted imm 177 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 178 opc, " $dst, $lhs, $rhs", 179 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 180 // register 181 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 182 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 183 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 184 let isCommutable = Commutable; 185 } 186 // shifted register 187 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 188 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 189 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 190} 191 192/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 193// the ".w" prefix to indicate that they are wide. 194multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> : 195 T2I_bin_irs<opc, opnode, Commutable, ".w">; 196 197/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 198/// reversed. It doesn't define the 'rr' form since it's handled by its 199/// T2I_bin_irs counterpart. 200multiclass T2I_rbin_is<string opc, PatFrag opnode> { 201 // shifted imm 202 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 203 opc, ".w $dst, $rhs, $lhs", 204 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 205 // shifted register 206 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 207 opc, " $dst, $rhs, $lhs", 208 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 209} 210 211/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 212/// instruction modifies the CPSR register. 213let Defs = [CPSR] in { 214multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 215 // shifted imm 216 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 217 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 218 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 219 // register 220 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 221 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 222 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 223 let isCommutable = Commutable; 224 } 225 // shifted register 226 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 227 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 228 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 229} 230} 231 232/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 233/// patterns for a binary operation that produces a value. 234multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 235 // shifted imm 236 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 237 opc, ".w $dst, $lhs, $rhs", 238 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 239 // 12-bit imm 240 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, 241 !strconcat(opc, "w"), " $dst, $lhs, $rhs", 242 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 243 // register 244 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 245 opc, ".w $dst, $lhs, $rhs", 246 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 247 let isCommutable = Commutable; 248 } 249 // shifted register 250 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 251 opc, ".w $dst, $lhs, $rhs", 252 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 253} 254 255/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 256/// binary operation that produces a value and use and define the carry bit. 257/// It's not predicable. 258let Uses = [CPSR] in { 259multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 260 // shifted imm 261 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 262 opc, " $dst, $lhs, $rhs", 263 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 264 Requires<[IsThumb2, CarryDefIsUnused]>; 265 // register 266 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 267 opc, ".w $dst, $lhs, $rhs", 268 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 269 Requires<[IsThumb2, CarryDefIsUnused]> { 270 let isCommutable = Commutable; 271 } 272 // shifted register 273 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 274 opc, ".w $dst, $lhs, $rhs", 275 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 276 Requires<[IsThumb2, CarryDefIsUnused]>; 277 // Carry setting variants 278 // shifted imm 279 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 280 !strconcat(opc, "s $dst, $lhs, $rhs"), 281 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 282 Requires<[IsThumb2, CarryDefIsUsed]> { 283 let Defs = [CPSR]; 284 } 285 // register 286 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 287 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 288 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 289 Requires<[IsThumb2, CarryDefIsUsed]> { 290 let Defs = [CPSR]; 291 let isCommutable = Commutable; 292 } 293 // shifted register 294 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 295 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 296 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 297 Requires<[IsThumb2, CarryDefIsUsed]> { 298 let Defs = [CPSR]; 299 } 300} 301} 302 303/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 304let Defs = [CPSR] in { 305multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 306 // shifted imm 307 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 308 IIC_iALUi, 309 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"), 310 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 311 // shifted register 312 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 313 IIC_iALUsi, 314 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 316} 317} 318 319/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 320// rotate operation that produces a value. 321multiclass T2I_sh_ir<string opc, PatFrag opnode> { 322 // 5-bit imm 323 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 324 opc, ".w $dst, $lhs, $rhs", 325 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 326 // register 327 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr, 328 opc, ".w $dst, $lhs, $rhs", 329 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 330} 331 332/// T2I_cmp_is - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 333/// patterns. Similar to T2I_bin_irs except the instruction does not produce 334/// a explicit result, only implicitly set CPSR. 335let Defs = [CPSR] in { 336multiclass T2I_cmp_is<string opc, PatFrag opnode> { 337 // shifted imm 338 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi, 339 opc, ".w $lhs, $rhs", 340 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 341 // register 342 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 343 opc, ".w $lhs, $rhs", 344 [(opnode GPR:$lhs, GPR:$rhs)]>; 345 // shifted register 346 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi, 347 opc, ".w $lhs, $rhs", 348 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 349} 350} 351 352/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 353multiclass T2I_ld<string opc, PatFrag opnode> { 354 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi, 355 opc, ".w $dst, $addr", 356 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 357 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, 358 opc, " $dst, $addr", 359 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 360 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr, 361 opc, ".w $dst, $addr", 362 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 363 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 364 opc, ".w $dst, $addr", 365 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; 366} 367 368/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 369multiclass T2I_st<string opc, PatFrag opnode> { 370 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei, 371 opc, ".w $src, $addr", 372 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 373 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei, 374 opc, " $src, $addr", 375 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 376 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer, 377 opc, ".w $src, $addr", 378 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 379} 380 381/// T2I_picld - Defines the PIC load pattern. 382class T2I_picld<string opc, PatFrag opnode> : 383 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoadi, 384 !strconcat("\n${addr:label}:\n\t", opc), " $dst, $addr", 385 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 386 387/// T2I_picst - Defines the PIC store pattern. 388class T2I_picst<string opc, PatFrag opnode> : 389 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStorer, 390 !strconcat("\n${addr:label}:\n\t", opc), " $src, $addr", 391 [(opnode GPR:$src, addrmodepc:$addr)]>; 392 393 394/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 395/// register and one whose operand is a register rotated by 8/16/24. 396multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 397 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 398 opc, ".w $dst, $src", 399 [(set GPR:$dst, (opnode GPR:$src))]>; 400 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 401 opc, ".w $dst, $src, ror $rot", 402 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>; 403} 404 405/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 406/// register and one whose operand is a register rotated by 8/16/24. 407multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 408 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 409 opc, " $dst, $LHS, $RHS", 410 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 411 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 412 IIC_iALUsr, opc, " $dst, $LHS, $RHS, ror $rot", 413 [(set GPR:$dst, (opnode GPR:$LHS, 414 (rotr GPR:$RHS, rot_imm:$rot)))]>; 415} 416 417//===----------------------------------------------------------------------===// 418// Instructions 419//===----------------------------------------------------------------------===// 420 421//===----------------------------------------------------------------------===// 422// Miscellaneous Instructions. 423// 424 425// LEApcrel - Load a pc-relative address into a register without offending the 426// assembler. 427def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 428 "adr$p.w $dst, #$label", []>; 429 430def t2LEApcrelJT : T2XI<(outs GPR:$dst), 431 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, 432 "adr$p.w $dst, #${label}_${id}", []>; 433 434// ADD r, sp, {so_imm|i12} 435def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 436 IIC_iALUi, "add", ".w $dst, $sp, $imm", []>; 437def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 438 IIC_iALUi, "addw", " $dst, $sp, $imm", []>; 439 440// ADD r, sp, so_reg 441def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 442 IIC_iALUsi, "add", ".w $dst, $sp, $rhs", []>; 443 444// SUB r, sp, {so_imm|i12} 445def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 446 IIC_iALUi, "sub", ".w $dst, $sp, $imm", []>; 447def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 448 IIC_iALUi, "subw", " $dst, $sp, $imm", []>; 449 450// SUB r, sp, so_reg 451def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 452 IIC_iALUsi, 453 "sub", " $dst, $sp, $rhs", []>; 454 455 456// Pseudo instruction that will expand into a t2SUBrSPi + a copy. 457let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. 458def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 459 NoItinerary, "@ sub.w $dst, $sp, $imm", []>; 460def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 461 NoItinerary, "@ subw $dst, $sp, $imm", []>; 462def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 463 NoItinerary, "@ sub $dst, $sp, $rhs", []>; 464} // usesCustomDAGSchedInserter 465 466 467//===----------------------------------------------------------------------===// 468// Load / store Instructions. 469// 470 471// Load 472let canFoldAsLoad = 1 in 473defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 474 475// Loads with zero extension 476defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 477defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 478 479// Loads with sign extension 480defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 481defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 482 483let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 484// Load doubleword 485def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2), 486 (ins t2addrmode_imm8s4:$addr), 487 IIC_iLoadi, "ldrd", " $dst1, $addr", []>; 488def t2LDRDpci : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2), 489 (ins i32imm:$addr), IIC_iLoadi, 490 "ldrd", " $dst1, $addr", []>; 491} 492 493// zextload i1 -> zextload i8 494def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 495 (t2LDRBi12 t2addrmode_imm12:$addr)>; 496def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 497 (t2LDRBi8 t2addrmode_imm8:$addr)>; 498def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 499 (t2LDRBs t2addrmode_so_reg:$addr)>; 500def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 501 (t2LDRBpci tconstpool:$addr)>; 502 503// extload -> zextload 504// FIXME: Reduce the number of patterns by legalizing extload to zextload 505// earlier? 506def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 507 (t2LDRBi12 t2addrmode_imm12:$addr)>; 508def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 509 (t2LDRBi8 t2addrmode_imm8:$addr)>; 510def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 511 (t2LDRBs t2addrmode_so_reg:$addr)>; 512def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 513 (t2LDRBpci tconstpool:$addr)>; 514 515def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 516 (t2LDRBi12 t2addrmode_imm12:$addr)>; 517def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 518 (t2LDRBi8 t2addrmode_imm8:$addr)>; 519def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 520 (t2LDRBs t2addrmode_so_reg:$addr)>; 521def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 522 (t2LDRBpci tconstpool:$addr)>; 523 524def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 525 (t2LDRHi12 t2addrmode_imm12:$addr)>; 526def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 527 (t2LDRHi8 t2addrmode_imm8:$addr)>; 528def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 529 (t2LDRHs t2addrmode_so_reg:$addr)>; 530def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 531 (t2LDRHpci tconstpool:$addr)>; 532 533// Indexed loads 534let mayLoad = 1 in { 535def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 536 (ins t2addrmode_imm8:$addr), 537 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 538 "ldr", " $dst, $addr!", "$addr.base = $base_wb", 539 []>; 540 541def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 542 (ins GPR:$base, t2am_imm8_offset:$offset), 543 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 544 "ldr", " $dst, [$base], $offset", "$base = $base_wb", 545 []>; 546 547def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 548 (ins t2addrmode_imm8:$addr), 549 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 550 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", 551 []>; 552def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 553 (ins GPR:$base, t2am_imm8_offset:$offset), 554 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 555 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", 556 []>; 557 558def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 559 (ins t2addrmode_imm8:$addr), 560 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 561 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", 562 []>; 563def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 564 (ins GPR:$base, t2am_imm8_offset:$offset), 565 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 566 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", 567 []>; 568 569def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 570 (ins t2addrmode_imm8:$addr), 571 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 572 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", 573 []>; 574def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 575 (ins GPR:$base, t2am_imm8_offset:$offset), 576 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 577 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", 578 []>; 579 580def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 581 (ins t2addrmode_imm8:$addr), 582 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 583 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", 584 []>; 585def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 586 (ins GPR:$base, t2am_imm8_offset:$offset), 587 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 588 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", 589 []>; 590} 591 592// Store 593defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 594defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 595defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 596 597// Store doubleword 598let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in 599def t2STRDi8 : T2Ii8s4<(outs), 600 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), 601 IIC_iStorer, "strd", " $src1, $addr", []>; 602 603// Indexed stores 604def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 605 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 606 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 607 "str", " $src, [$base, $offset]!", "$base = $base_wb", 608 [(set GPR:$base_wb, 609 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 610 611def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 612 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 613 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 614 "str", " $src, [$base], $offset", "$base = $base_wb", 615 [(set GPR:$base_wb, 616 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 617 618def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 619 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 620 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 621 "strh", " $src, [$base, $offset]!", "$base = $base_wb", 622 [(set GPR:$base_wb, 623 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 624 625def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 626 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 627 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 628 "strh", " $src, [$base], $offset", "$base = $base_wb", 629 [(set GPR:$base_wb, 630 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 631 632def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 633 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 634 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 635 "strb", " $src, [$base, $offset]!", "$base = $base_wb", 636 [(set GPR:$base_wb, 637 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 638 639def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 640 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 641 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 642 "strb", " $src, [$base], $offset", "$base = $base_wb", 643 [(set GPR:$base_wb, 644 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 645 646 647// FIXME: ldrd / strd pre / post variants 648 649//===----------------------------------------------------------------------===// 650// Load / store multiple Instructions. 651// 652 653let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 654def t2LDM : T2XI<(outs), 655 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 656 IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", []>; 657 658let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 659def t2STM : T2XI<(outs), 660 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 661 IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $wb", []>; 662 663//===----------------------------------------------------------------------===// 664// Move Instructions. 665// 666 667let neverHasSideEffects = 1 in 668def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 669 "mov", ".w $dst, $src", []>; 670 671// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 672let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in 673def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 674 "mov", ".w $dst, $src", 675 [(set GPR:$dst, t2_so_imm:$src)]>; 676 677let isReMaterializable = 1, isAsCheapAsAMove = 1 in 678def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 679 "movw", " $dst, $src", 680 [(set GPR:$dst, imm0_65535:$src)]>; 681 682let Constraints = "$src = $dst" in 683def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi, 684 "movt", " $dst, $imm", 685 [(set GPR:$dst, 686 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>; 687 688def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>; 689 690//===----------------------------------------------------------------------===// 691// Extend Instructions. 692// 693 694// Sign extenders 695 696defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 697defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 698 699defm t2SXTAB : T2I_bin_rrot<"sxtab", 700 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 701defm t2SXTAH : T2I_bin_rrot<"sxtah", 702 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 703 704// TODO: SXT(A){B|H}16 705 706// Zero extenders 707 708let AddedComplexity = 16 in { 709defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 710defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 711defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 712 713def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 714 (t2UXTB16r_rot GPR:$Src, 24)>; 715def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 716 (t2UXTB16r_rot GPR:$Src, 8)>; 717 718defm t2UXTAB : T2I_bin_rrot<"uxtab", 719 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 720defm t2UXTAH : T2I_bin_rrot<"uxtah", 721 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 722} 723 724//===----------------------------------------------------------------------===// 725// Arithmetic Instructions. 726// 727 728defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 729defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 730 731// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 732defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 733defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 734 735defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 736defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 737 738// RSB 739defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 740defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 741 742// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 743let AddedComplexity = 1 in 744def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 745 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 746def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 747 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 748def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 749 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 750 751 752//===----------------------------------------------------------------------===// 753// Shift and rotate Instructions. 754// 755 756defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 757defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 758defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 759defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 760 761let Uses = [CPSR] in { 762def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 763 "rrx", " $dst, $src", 764 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 765} 766 767let Defs = [CPSR] in { 768def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 769 "lsrs.w $dst, $src, #1", 770 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 771def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 772 "asrs.w $dst, $src, #1", 773 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 774} 775 776//===----------------------------------------------------------------------===// 777// Bitwise Instructions. 778// 779 780defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 781defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 782defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 783 784defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 785 786let Constraints = "$src = $dst" in 787def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 788 IIC_iALUi, "bfc", " $dst, $imm", 789 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 790 791def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 792 IIC_iALUi, "sbfx", " $dst, $src, $lsb, $width", []>; 793 794def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 795 IIC_iALUi, "ubfx", " $dst, $src, $lsb, $width", []>; 796 797// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 798 799defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 800 801// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 802let AddedComplexity = 1 in 803defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 804 805 806def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 807 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 808 809// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 810def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 811 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>, 812 Requires<[IsThumb2]>; 813 814def : T2Pat<(t2_so_imm_not:$src), 815 (t2MVNi t2_so_imm_not:$src)>; 816 817//===----------------------------------------------------------------------===// 818// Multiply Instructions. 819// 820let isCommutable = 1 in 821def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 822 "mul", " $dst, $a, $b", 823 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 824 825def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 826 "mla", " $dst, $a, $b, $c", 827 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 828 829def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 830 "mls", " $dst, $a, $b, $c", 831 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 832 833// Extra precision multiplies with low / high results 834let neverHasSideEffects = 1 in { 835let isCommutable = 1 in { 836def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 837 "smull", " $ldst, $hdst, $a, $b", []>; 838 839def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 840 "umull", " $ldst, $hdst, $a, $b", []>; 841} 842 843// Multiply + accumulate 844def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 845 "smlal", " $ldst, $hdst, $a, $b", []>; 846 847def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 848 "umlal", " $ldst, $hdst, $a, $b", []>; 849 850def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 851 "umaal", " $ldst, $hdst, $a, $b", []>; 852} // neverHasSideEffects 853 854// Most significant word multiply 855def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 856 "smmul", " $dst, $a, $b", 857 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 858 859def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 860 "smmla", " $dst, $a, $b, $c", 861 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 862 863 864def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 865 "smmls", " $dst, $a, $b, $c", 866 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 867 868multiclass T2I_smul<string opc, PatFrag opnode> { 869 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 870 !strconcat(opc, "bb"), " $dst, $a, $b", 871 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 872 (sext_inreg GPR:$b, i16)))]>; 873 874 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 875 !strconcat(opc, "bt"), " $dst, $a, $b", 876 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 877 (sra GPR:$b, (i32 16))))]>; 878 879 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 880 !strconcat(opc, "tb"), " $dst, $a, $b", 881 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 882 (sext_inreg GPR:$b, i16)))]>; 883 884 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 885 !strconcat(opc, "tt"), " $dst, $a, $b", 886 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 887 (sra GPR:$b, (i32 16))))]>; 888 889 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 890 !strconcat(opc, "wb"), " $dst, $a, $b", 891 [(set GPR:$dst, (sra (opnode GPR:$a, 892 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 893 894 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 895 !strconcat(opc, "wt"), " $dst, $a, $b", 896 [(set GPR:$dst, (sra (opnode GPR:$a, 897 (sra GPR:$b, (i32 16))), (i32 16)))]>; 898} 899 900 901multiclass T2I_smla<string opc, PatFrag opnode> { 902 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 903 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 904 [(set GPR:$dst, (add GPR:$acc, 905 (opnode (sext_inreg GPR:$a, i16), 906 (sext_inreg GPR:$b, i16))))]>; 907 908 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 909 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 910 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 911 (sra GPR:$b, (i32 16)))))]>; 912 913 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 914 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 915 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 916 (sext_inreg GPR:$b, i16))))]>; 917 918 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 919 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 920 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 921 (sra GPR:$b, (i32 16)))))]>; 922 923 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 924 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 925 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 926 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 927 928 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 929 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 930 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 931 (sra GPR:$b, (i32 16))), (i32 16))))]>; 932} 933 934defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 935defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 936 937// TODO: Halfword multiple accumulate long: SMLAL<x><y> 938// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 939 940 941//===----------------------------------------------------------------------===// 942// Misc. Arithmetic Instructions. 943// 944 945def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 946 "clz", " $dst, $src", 947 [(set GPR:$dst, (ctlz GPR:$src))]>; 948 949def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 950 "rev", ".w $dst, $src", 951 [(set GPR:$dst, (bswap GPR:$src))]>; 952 953def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 954 "rev16", ".w $dst, $src", 955 [(set GPR:$dst, 956 (or (and (srl GPR:$src, (i32 8)), 0xFF), 957 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 958 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 959 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 960 961def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 962 "revsh", ".w $dst, $src", 963 [(set GPR:$dst, 964 (sext_inreg 965 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 966 (shl GPR:$src, (i32 8))), i16))]>; 967 968def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 969 IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt", 970 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 971 (and (shl GPR:$src2, (i32 imm:$shamt)), 972 0xFFFF0000)))]>; 973 974// Alternate cases for PKHBT where identities eliminate some nodes. 975def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 976 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 977def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 978 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 979 980def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 981 IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt", 982 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 983 (and (sra GPR:$src2, imm16_31:$shamt), 984 0xFFFF)))]>; 985 986// Alternate cases for PKHTB where identities eliminate some nodes. Note that 987// a shift amount of 0 is *not legal* here, it is PKHBT instead. 988def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 989 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 990def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 991 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 992 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 993 994//===----------------------------------------------------------------------===// 995// Comparison Instructions... 996// 997 998defm t2CMP : T2I_cmp_is<"cmp", 999 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 1000defm t2CMPz : T2I_cmp_is<"cmp", 1001 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 1002 1003defm t2CMN : T2I_cmp_is<"cmn", 1004 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1005defm t2CMNz : T2I_cmp_is<"cmn", 1006 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 1007 1008def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 1009 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1010 1011def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 1012 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1013 1014defm t2TST : T2I_cmp_is<"tst", 1015 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 1016defm t2TEQ : T2I_cmp_is<"teq", 1017 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 1018 1019// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 1020// Short range conditional branch. Looks awesome for loops. Need to figure 1021// out how to use this one. 1022 1023 1024// Conditional moves 1025// FIXME: should be able to write a pattern for ARMcmov, but can't use 1026// a two-value operand where a dag node expects two operands. :( 1027def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr, 1028 "mov", ".w $dst, $true", 1029 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1030 RegConstraint<"$false = $dst">; 1031 1032def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 1033 IIC_iCMOVi, "mov", ".w $dst, $true", 1034[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1035 RegConstraint<"$false = $dst">; 1036 1037def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1038 IIC_iCMOVsi, "lsl", ".w $dst, $true, $rhs", []>, 1039 RegConstraint<"$false = $dst">; 1040def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1041 IIC_iCMOVsi, "lsr", ".w $dst, $true, $rhs", []>, 1042 RegConstraint<"$false = $dst">; 1043def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1044 IIC_iCMOVsi, "asr", ".w $dst, $true, $rhs", []>, 1045 RegConstraint<"$false = $dst">; 1046def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs), 1047 IIC_iCMOVsi, "ror", ".w $dst, $true, $rhs", []>, 1048 RegConstraint<"$false = $dst">; 1049 1050//===----------------------------------------------------------------------===// 1051// TLS Instructions 1052// 1053 1054// __aeabi_read_tp preserves the registers r1-r3. 1055let isCall = 1, 1056 Defs = [R0, R12, LR, CPSR] in { 1057 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 1058 "bl __aeabi_read_tp", 1059 [(set R0, ARMthread_pointer)]>; 1060} 1061 1062//===----------------------------------------------------------------------===// 1063// SJLJ Exception handling intrinsics 1064// eh_sjlj_setjmp() is an instruction sequence to store the return 1065// address and save #0 in R0 for the non-longjmp case. 1066// Since by its nature we may be coming from some other function to get 1067// here, and we're using the stack frame for the containing function to 1068// save/restore registers, we can't keep anything live in regs across 1069// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 1070// when we get here from a longjmp(). We force everthing out of registers 1071// except for our own input by listing the relevant registers in Defs. By 1072// doing so, we also cause the prologue/epilogue code to actively preserve 1073// all of the callee-saved resgisters, which is exactly what we want. 1074let Defs = 1075 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 1076 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 1077 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 1078 D31 ] in { 1079 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src), 1080 AddrModeNone, SizeSpecial, NoItinerary, 1081 "str.w sp, [$src, #+8] @ eh_setjmp begin\n" 1082 "\tadr r12, 0f\n" 1083 "\torr r12, #1\n" 1084 "\tstr.w r12, [$src, #+4]\n" 1085 "\tmovs r0, #0\n" 1086 "\tb 1f\n" 1087 "0:\tmovs r0, #1 @ eh_setjmp end\n" 1088 "1:", "", 1089 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 1090} 1091 1092 1093 1094//===----------------------------------------------------------------------===// 1095// Control-Flow Instructions 1096// 1097 1098// FIXME: remove when we have a way to marking a MI with these properties. 1099// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1100// operand list. 1101// FIXME: Should pc be an implicit operand like PICADD, etc? 1102let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1103 hasExtraDefRegAllocReq = 1 in 1104 def t2LDM_RET : T2XI<(outs), 1105 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 1106 IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", 1107 []>; 1108 1109let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1110let isPredicable = 1 in 1111def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 1112 "b.w $target", 1113 [(br bb:$target)]>; 1114 1115let isNotDuplicable = 1, isIndirectBranch = 1 in { 1116def t2BR_JT : 1117 T2JTI<(outs), 1118 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 1119 IIC_Br, "mov pc, $target\n$jt", 1120 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 1121 1122// FIXME: Add a non-pc based case that can be predicated. 1123def t2TBB : 1124 T2JTI<(outs), 1125 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1126 IIC_Br, "tbb $index\n$jt", []>; 1127 1128def t2TBH : 1129 T2JTI<(outs), 1130 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1131 IIC_Br, "tbh $index\n$jt", []>; 1132} // isNotDuplicable, isIndirectBranch 1133 1134} // isBranch, isTerminator, isBarrier 1135 1136// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1137// a two-value operand where a dag node expects two operands. :( 1138let isBranch = 1, isTerminator = 1 in 1139def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 1140 "b", ".w $target", 1141 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1142 1143 1144// IT block 1145def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1146 AddrModeNone, Size2Bytes, IIC_iALUx, 1147 "it$mask $cc", "", []>; 1148 1149//===----------------------------------------------------------------------===// 1150// Non-Instruction Patterns 1151// 1152 1153// Two piece so_imms. 1154def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS), 1155 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1156 (t2_so_imm2part_2 imm:$RHS))>; 1157def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS), 1158 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1159 (t2_so_imm2part_2 imm:$RHS))>; 1160def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS), 1161 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1162 (t2_so_imm2part_2 imm:$RHS))>; 1163def : T2Pat<(sub GPR:$LHS, t2_so_imm2part:$RHS), 1164 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 1165 (t2_so_imm2part_2 imm:$RHS))>; 1166 1167// ConstantPool, GlobalAddress, and JumpTable 1168def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1169def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1170def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1171 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1172 1173// 32-bit immediate using movw + movt. 1174// This is a single pseudo instruction to make it re-materializable. Remove 1175// when we can do generalized remat. 1176let isReMaterializable = 1 in 1177def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 1178 "movw", " $dst, ${src:lo16}\n\tmovt${p} $dst, ${src:hi16}", 1179 [(set GPR:$dst, (i32 imm:$src))]>; 1180