ARMInstrThumb2.td revision ffa5a763444e456cee17442af603fb4ef0843bb4 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred_asmoperand : AsmOperandClass {
16  let Name = "ITCondCode";
17  let ParserMethod = "parseITCondCode";
18}
19def it_pred : Operand<i32> {
20  let PrintMethod = "printMandatoryPredicateOperand";
21  let ParserMatchClass = it_pred_asmoperand;
22}
23
24// IT block condition mask
25def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; }
26def it_mask : Operand<i32> {
27  let PrintMethod = "printThumbITMask";
28  let ParserMatchClass = it_mask_asmoperand;
29}
30
31// Shifted operands. No register controlled shifts for Thumb2.
32// Note: We do not support rrx shifted operands yet.
33def t2_so_reg : Operand<i32>,    // reg imm
34                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
35                               [shl,srl,sra,rotr]> {
36  let EncoderMethod = "getT2SORegOpValue";
37  let PrintMethod = "printT2SOOperand";
38  let DecoderMethod = "DecodeSORegImmOperand";
39  let ParserMatchClass = ShiftedImmAsmOperand;
40  let MIOperandInfo = (ops rGPR, i32imm);
41}
42
43// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
44def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
45  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
46}]>;
47
48// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
49def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
50  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
51}]>;
52
53// t2_so_imm - Match a 32-bit immediate operand, which is an
54// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
55// immediate splatted into multiple bytes of the word.
56def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
57def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
58    return ARM_AM::getT2SOImmVal(Imm) != -1;
59  }]> {
60  let ParserMatchClass = t2_so_imm_asmoperand;
61  let EncoderMethod = "getT2SOImmOpValue";
62  let DecoderMethod = "DecodeT2SOImm";
63}
64
65// t2_so_imm_not - Match an immediate that is a complement
66// of a t2_so_imm.
67def t2_so_imm_not : Operand<i32>,
68                    PatLeaf<(imm), [{
69  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
70}], t2_so_imm_not_XFORM>;
71
72// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
73def t2_so_imm_neg : Operand<i32>,
74                    PatLeaf<(imm), [{
75  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
76}], t2_so_imm_neg_XFORM>;
77
78/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
79def imm0_4095 : Operand<i32>,
80                ImmLeaf<i32, [{
81  return Imm >= 0 && Imm < 4096;
82}]>;
83
84def imm0_4095_neg : PatLeaf<(i32 imm), [{
85 return (uint32_t)(-N->getZExtValue()) < 4096;
86}], imm_neg_XFORM>;
87
88def imm0_255_neg : PatLeaf<(i32 imm), [{
89  return (uint32_t)(-N->getZExtValue()) < 255;
90}], imm_neg_XFORM>;
91
92def imm0_255_not : PatLeaf<(i32 imm), [{
93  return (uint32_t)(~N->getZExtValue()) < 255;
94}], imm_comp_XFORM>;
95
96def lo5AllOne : PatLeaf<(i32 imm), [{
97  // Returns true if all low 5-bits are 1.
98  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
99}]>;
100
101// Define Thumb2 specific addressing modes.
102
103// t2addrmode_imm12  := reg + imm12
104def t2addrmode_imm12 : Operand<i32>,
105                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
106  let PrintMethod = "printAddrModeImm12Operand";
107  let EncoderMethod = "getAddrModeImm12OpValue";
108  let DecoderMethod = "DecodeT2AddrModeImm12";
109  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
110}
111
112// t2ldrlabel  := imm12
113def t2ldrlabel : Operand<i32> {
114  let EncoderMethod = "getAddrModeImm12OpValue";
115}
116
117
118// ADR instruction labels.
119def t2adrlabel : Operand<i32> {
120  let EncoderMethod = "getT2AdrLabelOpValue";
121}
122
123
124// t2addrmode_imm8  := reg +/- imm8
125def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
126def t2addrmode_imm8 : Operand<i32>,
127                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
128  let PrintMethod = "printT2AddrModeImm8Operand";
129  let EncoderMethod = "getT2AddrModeImm8OpValue";
130  let DecoderMethod = "DecodeT2AddrModeImm8";
131  let ParserMatchClass = MemImm8OffsetAsmOperand;
132  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133}
134
135def t2am_imm8_offset : Operand<i32>,
136                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
137                                      [], [SDNPWantRoot]> {
138  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
139  let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
140  let DecoderMethod = "DecodeT2Imm8";
141}
142
143// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
144def t2addrmode_imm8s4 : Operand<i32> {
145  let PrintMethod = "printT2AddrModeImm8s4Operand";
146  let EncoderMethod = "getT2AddrModeImm8s4OpValue";
147  let DecoderMethod = "DecodeT2AddrModeImm8s4";
148  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
149}
150
151def t2am_imm8s4_offset : Operand<i32> {
152  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
153  let DecoderMethod = "DecodeT2Imm8S4";
154}
155
156// t2addrmode_so_reg  := reg + (reg << imm2)
157def t2addrmode_so_reg : Operand<i32>,
158                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
159  let PrintMethod = "printT2AddrModeSoRegOperand";
160  let EncoderMethod = "getT2AddrModeSORegOpValue";
161  let DecoderMethod = "DecodeT2AddrModeSOReg";
162  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
163}
164
165// t2addrmode_reg := reg
166// Used by load/store exclusive instructions. Useful to enable right assembly
167// parsing and printing. Not used for any codegen matching.
168//
169def t2addrmode_reg : Operand<i32> {
170  let PrintMethod = "printAddrMode7Operand";
171  let DecoderMethod = "DecodeGPRRegisterClass";
172  let MIOperandInfo = (ops GPR);
173}
174
175//===----------------------------------------------------------------------===//
176// Multiclass helpers...
177//
178
179
180class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
181           string opc, string asm, list<dag> pattern>
182  : T2I<oops, iops, itin, opc, asm, pattern> {
183  bits<4> Rd;
184  bits<12> imm;
185
186  let Inst{11-8}  = Rd;
187  let Inst{26}    = imm{11};
188  let Inst{14-12} = imm{10-8};
189  let Inst{7-0}   = imm{7-0};
190}
191
192
193class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
194           string opc, string asm, list<dag> pattern>
195  : T2sI<oops, iops, itin, opc, asm, pattern> {
196  bits<4> Rd;
197  bits<4> Rn;
198  bits<12> imm;
199
200  let Inst{11-8}  = Rd;
201  let Inst{26}    = imm{11};
202  let Inst{14-12} = imm{10-8};
203  let Inst{7-0}   = imm{7-0};
204}
205
206class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
207           string opc, string asm, list<dag> pattern>
208  : T2I<oops, iops, itin, opc, asm, pattern> {
209  bits<4> Rn;
210  bits<12> imm;
211
212  let Inst{19-16}  = Rn;
213  let Inst{26}    = imm{11};
214  let Inst{14-12} = imm{10-8};
215  let Inst{7-0}   = imm{7-0};
216}
217
218
219class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
220           string opc, string asm, list<dag> pattern>
221  : T2I<oops, iops, itin, opc, asm, pattern> {
222  bits<4> Rd;
223  bits<12> ShiftedRm;
224
225  let Inst{11-8}  = Rd;
226  let Inst{3-0}   = ShiftedRm{3-0};
227  let Inst{5-4}   = ShiftedRm{6-5};
228  let Inst{14-12} = ShiftedRm{11-9};
229  let Inst{7-6}   = ShiftedRm{8-7};
230}
231
232class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
233           string opc, string asm, list<dag> pattern>
234  : T2sI<oops, iops, itin, opc, asm, pattern> {
235  bits<4> Rd;
236  bits<12> ShiftedRm;
237
238  let Inst{11-8}  = Rd;
239  let Inst{3-0}   = ShiftedRm{3-0};
240  let Inst{5-4}   = ShiftedRm{6-5};
241  let Inst{14-12} = ShiftedRm{11-9};
242  let Inst{7-6}   = ShiftedRm{8-7};
243}
244
245class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
246           string opc, string asm, list<dag> pattern>
247  : T2I<oops, iops, itin, opc, asm, pattern> {
248  bits<4> Rn;
249  bits<12> ShiftedRm;
250
251  let Inst{19-16} = Rn;
252  let Inst{3-0}   = ShiftedRm{3-0};
253  let Inst{5-4}   = ShiftedRm{6-5};
254  let Inst{14-12} = ShiftedRm{11-9};
255  let Inst{7-6}   = ShiftedRm{8-7};
256}
257
258class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
259           string opc, string asm, list<dag> pattern>
260  : T2I<oops, iops, itin, opc, asm, pattern> {
261  bits<4> Rd;
262  bits<4> Rm;
263
264  let Inst{11-8}  = Rd;
265  let Inst{3-0}   = Rm;
266}
267
268class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
269           string opc, string asm, list<dag> pattern>
270  : T2sI<oops, iops, itin, opc, asm, pattern> {
271  bits<4> Rd;
272  bits<4> Rm;
273
274  let Inst{11-8}  = Rd;
275  let Inst{3-0}   = Rm;
276}
277
278class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
279           string opc, string asm, list<dag> pattern>
280  : T2I<oops, iops, itin, opc, asm, pattern> {
281  bits<4> Rn;
282  bits<4> Rm;
283
284  let Inst{19-16} = Rn;
285  let Inst{3-0}   = Rm;
286}
287
288
289class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
290           string opc, string asm, list<dag> pattern>
291  : T2I<oops, iops, itin, opc, asm, pattern> {
292  bits<4> Rd;
293  bits<4> Rn;
294  bits<12> imm;
295
296  let Inst{11-8}  = Rd;
297  let Inst{19-16} = Rn;
298  let Inst{26}    = imm{11};
299  let Inst{14-12} = imm{10-8};
300  let Inst{7-0}   = imm{7-0};
301}
302
303class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
304           string opc, string asm, list<dag> pattern>
305  : T2sI<oops, iops, itin, opc, asm, pattern> {
306  bits<4> Rd;
307  bits<4> Rn;
308  bits<12> imm;
309
310  let Inst{11-8}  = Rd;
311  let Inst{19-16} = Rn;
312  let Inst{26}    = imm{11};
313  let Inst{14-12} = imm{10-8};
314  let Inst{7-0}   = imm{7-0};
315}
316
317class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
318           string opc, string asm, list<dag> pattern>
319  : T2I<oops, iops, itin, opc, asm, pattern> {
320  bits<4> Rd;
321  bits<4> Rm;
322  bits<5> imm;
323
324  let Inst{11-8}  = Rd;
325  let Inst{3-0}   = Rm;
326  let Inst{14-12} = imm{4-2};
327  let Inst{7-6}   = imm{1-0};
328}
329
330class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
331           string opc, string asm, list<dag> pattern>
332  : T2sI<oops, iops, itin, opc, asm, pattern> {
333  bits<4> Rd;
334  bits<4> Rm;
335  bits<5> imm;
336
337  let Inst{11-8}  = Rd;
338  let Inst{3-0}   = Rm;
339  let Inst{14-12} = imm{4-2};
340  let Inst{7-6}   = imm{1-0};
341}
342
343class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
344           string opc, string asm, list<dag> pattern>
345  : T2I<oops, iops, itin, opc, asm, pattern> {
346  bits<4> Rd;
347  bits<4> Rn;
348  bits<4> Rm;
349
350  let Inst{11-8}  = Rd;
351  let Inst{19-16} = Rn;
352  let Inst{3-0}   = Rm;
353}
354
355class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
356           string opc, string asm, list<dag> pattern>
357  : T2sI<oops, iops, itin, opc, asm, pattern> {
358  bits<4> Rd;
359  bits<4> Rn;
360  bits<4> Rm;
361
362  let Inst{11-8}  = Rd;
363  let Inst{19-16} = Rn;
364  let Inst{3-0}   = Rm;
365}
366
367class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
368           string opc, string asm, list<dag> pattern>
369  : T2I<oops, iops, itin, opc, asm, pattern> {
370  bits<4> Rd;
371  bits<4> Rn;
372  bits<12> ShiftedRm;
373
374  let Inst{11-8}  = Rd;
375  let Inst{19-16} = Rn;
376  let Inst{3-0}   = ShiftedRm{3-0};
377  let Inst{5-4}   = ShiftedRm{6-5};
378  let Inst{14-12} = ShiftedRm{11-9};
379  let Inst{7-6}   = ShiftedRm{8-7};
380}
381
382class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
383           string opc, string asm, list<dag> pattern>
384  : T2sI<oops, iops, itin, opc, asm, pattern> {
385  bits<4> Rd;
386  bits<4> Rn;
387  bits<12> ShiftedRm;
388
389  let Inst{11-8}  = Rd;
390  let Inst{19-16} = Rn;
391  let Inst{3-0}   = ShiftedRm{3-0};
392  let Inst{5-4}   = ShiftedRm{6-5};
393  let Inst{14-12} = ShiftedRm{11-9};
394  let Inst{7-6}   = ShiftedRm{8-7};
395}
396
397class T2FourReg<dag oops, dag iops, InstrItinClass itin,
398           string opc, string asm, list<dag> pattern>
399  : T2I<oops, iops, itin, opc, asm, pattern> {
400  bits<4> Rd;
401  bits<4> Rn;
402  bits<4> Rm;
403  bits<4> Ra;
404
405  let Inst{19-16} = Rn;
406  let Inst{15-12} = Ra;
407  let Inst{11-8}  = Rd;
408  let Inst{3-0}   = Rm;
409}
410
411class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
412                dag oops, dag iops, InstrItinClass itin,
413                string opc, string asm, list<dag> pattern>
414  : T2I<oops, iops, itin, opc, asm, pattern> {
415  bits<4> RdLo;
416  bits<4> RdHi;
417  bits<4> Rn;
418  bits<4> Rm;
419
420  let Inst{31-23} = 0b111110111;
421  let Inst{22-20} = opc22_20;
422  let Inst{19-16} = Rn;
423  let Inst{15-12} = RdLo;
424  let Inst{11-8}  = RdHi;
425  let Inst{7-4}   = opc7_4;
426  let Inst{3-0}   = Rm;
427}
428
429
430/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
431/// unary operation that produces a value. These are predicable and can be
432/// changed to modify CPSR.
433multiclass T2I_un_irs<bits<4> opcod, string opc,
434                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
435                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
436   // shifted imm
437   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
438                opc, "\t$Rd, $imm",
439                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
440     let isAsCheapAsAMove = Cheap;
441     let isReMaterializable = ReMat;
442     let Inst{31-27} = 0b11110;
443     let Inst{25} = 0;
444     let Inst{24-21} = opcod;
445     let Inst{19-16} = 0b1111; // Rn
446     let Inst{15} = 0;
447   }
448   // register
449   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
450                opc, ".w\t$Rd, $Rm",
451                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
452     let Inst{31-27} = 0b11101;
453     let Inst{26-25} = 0b01;
454     let Inst{24-21} = opcod;
455     let Inst{19-16} = 0b1111; // Rn
456     let Inst{14-12} = 0b000; // imm3
457     let Inst{7-6} = 0b00; // imm2
458     let Inst{5-4} = 0b00; // type
459   }
460   // shifted register
461   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
462                opc, ".w\t$Rd, $ShiftedRm",
463                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
464     let Inst{31-27} = 0b11101;
465     let Inst{26-25} = 0b01;
466     let Inst{24-21} = opcod;
467     let Inst{19-16} = 0b1111; // Rn
468   }
469}
470
471/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
472/// binary operation that produces a value. These are predicable and can be
473/// changed to modify CPSR.
474multiclass T2I_bin_irs<bits<4> opcod, string opc,
475                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
476                       PatFrag opnode, string baseOpc, bit Commutable = 0,
477                       string wide = ""> {
478   // shifted imm
479   def ri : T2sTwoRegImm<
480                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
481                 opc, "\t$Rd, $Rn, $imm",
482                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
483     let Inst{31-27} = 0b11110;
484     let Inst{25} = 0;
485     let Inst{24-21} = opcod;
486     let Inst{15} = 0;
487   }
488   // register
489   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
490                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
491                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
492     let isCommutable = Commutable;
493     let Inst{31-27} = 0b11101;
494     let Inst{26-25} = 0b01;
495     let Inst{24-21} = opcod;
496     let Inst{14-12} = 0b000; // imm3
497     let Inst{7-6} = 0b00; // imm2
498     let Inst{5-4} = 0b00; // type
499   }
500   // shifted register
501   def rs : T2sTwoRegShiftedReg<
502                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
503                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
504                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
505     let Inst{31-27} = 0b11101;
506     let Inst{26-25} = 0b01;
507     let Inst{24-21} = opcod;
508   }
509  // Assembly aliases for optional destination operand when it's the same
510  // as the source operand.
511  def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
512     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
513                                                    t2_so_imm:$imm, pred:$p,
514                                                    cc_out:$s)>;
515  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
516     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
517                                                    rGPR:$Rm, pred:$p,
518                                                    cc_out:$s)>;
519  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
520     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
521                                                    t2_so_reg:$shift, pred:$p,
522                                                    cc_out:$s)>;
523}
524
525/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
526//  the ".w" suffix to indicate that they are wide.
527multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
528                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
529                         PatFrag opnode, string baseOpc, bit Commutable = 0> :
530    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> {
531  // Assembler aliases w/o the ".w" suffix.
532  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
533     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
534                                                    rGPR:$Rm, pred:$p,
535                                                    cc_out:$s)>;
536  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
537     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn,
538                                                    t2_so_reg:$shift, pred:$p,
539                                                    cc_out:$s)>;
540
541  // and with the optional destination operand, too.
542  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
543     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
544                                                    rGPR:$Rm, pred:$p,
545                                                    cc_out:$s)>;
546  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"),
547     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
548                                                    t2_so_reg:$shift, pred:$p,
549                                                    cc_out:$s)>;
550}
551
552/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
553/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
554/// it is equivalent to the T2I_bin_irs counterpart.
555multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
556   // shifted imm
557   def ri : T2sTwoRegImm<
558                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
559                 opc, ".w\t$Rd, $Rn, $imm",
560                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
561     let Inst{31-27} = 0b11110;
562     let Inst{25} = 0;
563     let Inst{24-21} = opcod;
564     let Inst{15} = 0;
565   }
566   // register
567   def rr : T2sThreeReg<
568                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
569                 opc, "\t$Rd, $Rn, $Rm",
570                 [/* For disassembly only; pattern left blank */]> {
571     let Inst{31-27} = 0b11101;
572     let Inst{26-25} = 0b01;
573     let Inst{24-21} = opcod;
574     let Inst{14-12} = 0b000; // imm3
575     let Inst{7-6} = 0b00; // imm2
576     let Inst{5-4} = 0b00; // type
577   }
578   // shifted register
579   def rs : T2sTwoRegShiftedReg<
580                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
581                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
582                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
583     let Inst{31-27} = 0b11101;
584     let Inst{26-25} = 0b01;
585     let Inst{24-21} = opcod;
586   }
587}
588
589/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
590/// instruction modifies the CPSR register.
591let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
592multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
593                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
594                         PatFrag opnode, bit Commutable = 0> {
595   // shifted imm
596   def ri : T2sTwoRegImm<
597                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
598                opc, ".w\t$Rd, $Rn, $imm",
599                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
600     let Inst{31-27} = 0b11110;
601     let Inst{25} = 0;
602     let Inst{24-21} = opcod;
603     let Inst{15} = 0;
604   }
605   // register
606   def rr : T2sThreeReg<
607                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
608                opc, ".w\t$Rd, $Rn, $Rm",
609                [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]> {
610     let isCommutable = Commutable;
611     let Inst{31-27} = 0b11101;
612     let Inst{26-25} = 0b01;
613     let Inst{24-21} = opcod;
614     let Inst{14-12} = 0b000; // imm3
615     let Inst{7-6} = 0b00; // imm2
616     let Inst{5-4} = 0b00; // type
617   }
618   // shifted register
619   def rs : T2sTwoRegShiftedReg<
620                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
621                opc, ".w\t$Rd, $Rn, $ShiftedRm",
622               [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
623     let Inst{31-27} = 0b11101;
624     let Inst{26-25} = 0b01;
625     let Inst{24-21} = opcod;
626   }
627}
628}
629
630/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
631/// patterns for a binary operation that produces a value.
632multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
633                          bit Commutable = 0> {
634   // shifted imm
635   // The register-immediate version is re-materializable. This is useful
636   // in particular for taking the address of a local.
637   let isReMaterializable = 1 in {
638   def ri : T2sTwoRegImm<
639                 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
640                 opc, ".w\t$Rd, $Rn, $imm",
641                 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> {
642     let Inst{31-27} = 0b11110;
643     let Inst{25} = 0;
644     let Inst{24} = 1;
645     let Inst{23-21} = op23_21;
646     let Inst{15} = 0;
647   }
648   }
649   // 12-bit imm
650   def ri12 : T2I<
651                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
652                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
653                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
654     bits<4> Rd;
655     bits<4> Rn;
656     bits<12> imm;
657     let Inst{31-27} = 0b11110;
658     let Inst{26} = imm{11};
659     let Inst{25-24} = 0b10;
660     let Inst{23-21} = op23_21;
661     let Inst{20} = 0; // The S bit.
662     let Inst{19-16} = Rn;
663     let Inst{15} = 0;
664     let Inst{14-12} = imm{10-8};
665     let Inst{11-8} = Rd;
666     let Inst{7-0} = imm{7-0};
667   }
668   // register
669   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iALUr,
670                 opc, ".w\t$Rd, $Rn, $Rm",
671                 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> {
672     let isCommutable = Commutable;
673     let Inst{31-27} = 0b11101;
674     let Inst{26-25} = 0b01;
675     let Inst{24} = 1;
676     let Inst{23-21} = op23_21;
677     let Inst{14-12} = 0b000; // imm3
678     let Inst{7-6} = 0b00; // imm2
679     let Inst{5-4} = 0b00; // type
680   }
681   // shifted register
682   def rs : T2sTwoRegShiftedReg<
683                 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
684                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
685                 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> {
686     let Inst{31-27} = 0b11101;
687     let Inst{26-25} = 0b01;
688     let Inst{24} = 1;
689     let Inst{23-21} = op23_21;
690   }
691}
692
693/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
694/// for a binary operation that produces a value and use the carry
695/// bit. It's not predicable.
696let Defs = [CPSR], Uses = [CPSR] in {
697multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
698                             bit Commutable = 0> {
699   // shifted imm
700   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
701                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
702               [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
703                 Requires<[IsThumb2]> {
704     let Inst{31-27} = 0b11110;
705     let Inst{25} = 0;
706     let Inst{24-21} = opcod;
707     let Inst{15} = 0;
708   }
709   // register
710   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
711                 opc, ".w\t$Rd, $Rn, $Rm",
712                 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
713                 Requires<[IsThumb2]> {
714     let isCommutable = Commutable;
715     let Inst{31-27} = 0b11101;
716     let Inst{26-25} = 0b01;
717     let Inst{24-21} = opcod;
718     let Inst{14-12} = 0b000; // imm3
719     let Inst{7-6} = 0b00; // imm2
720     let Inst{5-4} = 0b00; // type
721   }
722   // shifted register
723   def rs : T2sTwoRegShiftedReg<
724                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
725                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
726         [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
727                 Requires<[IsThumb2]> {
728     let Inst{31-27} = 0b11101;
729     let Inst{26-25} = 0b01;
730     let Inst{24-21} = opcod;
731   }
732}
733}
734
735/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
736/// version is not needed since this is only for codegen.
737let hasPostISelHook = 1, isCodeGenOnly = 1, Defs = [CPSR] in {
738multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
739   // shifted imm
740   def ri : T2sTwoRegImm<
741                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
742                opc, ".w\t$Rd, $Rn, $imm",
743                [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
744     let Inst{31-27} = 0b11110;
745     let Inst{25} = 0;
746     let Inst{24-21} = opcod;
747     let Inst{15} = 0;
748   }
749   // shifted register
750   def rs : T2sTwoRegShiftedReg<
751                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
752                IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
753              [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
754     let Inst{31-27} = 0b11101;
755     let Inst{26-25} = 0b01;
756     let Inst{24-21} = opcod;
757   }
758}
759}
760
761/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
762//  rotate operation that produces a value.
763multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
764                     string baseOpc> {
765   // 5-bit imm
766   def ri : T2sTwoRegShiftImm<
767                 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
768                 opc, ".w\t$Rd, $Rm, $imm",
769                 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
770     let Inst{31-27} = 0b11101;
771     let Inst{26-21} = 0b010010;
772     let Inst{19-16} = 0b1111; // Rn
773     let Inst{5-4} = opcod;
774   }
775   // register
776   def rr : T2sThreeReg<
777                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
778                 opc, ".w\t$Rd, $Rn, $Rm",
779                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
780     let Inst{31-27} = 0b11111;
781     let Inst{26-23} = 0b0100;
782     let Inst{22-21} = opcod;
783     let Inst{15-12} = 0b1111;
784     let Inst{7-4} = 0b0000;
785   }
786
787  // Optional destination register
788  def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"),
789     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
790                                                    ty:$imm, pred:$p,
791                                                    cc_out:$s)>;
792  def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"),
793     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
794                                                    rGPR:$Rm, pred:$p,
795                                                    cc_out:$s)>;
796
797  // Assembler aliases w/o the ".w" suffix.
798  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
799     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn,
800                                                    ty:$imm, pred:$p,
801                                                   cc_out:$s)>;
802  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
803     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn,
804                                                    rGPR:$Rm, pred:$p,
805                                                    cc_out:$s)>;
806
807  // and with the optional destination operand, too.
808  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"),
809     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
810                                                    ty:$imm, pred:$p,
811                                                    cc_out:$s)>;
812  def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"),
813     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
814                                                    rGPR:$Rm, pred:$p,
815                                                    cc_out:$s)>;
816}
817
818/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
819/// patterns. Similar to T2I_bin_irs except the instruction does not produce
820/// a explicit result, only implicitly set CPSR.
821multiclass T2I_cmp_irs<bits<4> opcod, string opc,
822                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
823                       PatFrag opnode, string baseOpc> {
824let isCompare = 1, Defs = [CPSR] in {
825   // shifted imm
826   def ri : T2OneRegCmpImm<
827                (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
828                opc, ".w\t$Rn, $imm",
829                [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> {
830     let Inst{31-27} = 0b11110;
831     let Inst{25} = 0;
832     let Inst{24-21} = opcod;
833     let Inst{20} = 1; // The S bit.
834     let Inst{15} = 0;
835     let Inst{11-8} = 0b1111; // Rd
836   }
837   // register
838   def rr : T2TwoRegCmp<
839                (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
840                opc, ".w\t$Rn, $Rm",
841                [(opnode GPRnopc:$Rn, rGPR:$Rm)]> {
842     let Inst{31-27} = 0b11101;
843     let Inst{26-25} = 0b01;
844     let Inst{24-21} = opcod;
845     let Inst{20} = 1; // The S bit.
846     let Inst{14-12} = 0b000; // imm3
847     let Inst{11-8} = 0b1111; // Rd
848     let Inst{7-6} = 0b00; // imm2
849     let Inst{5-4} = 0b00; // type
850   }
851   // shifted register
852   def rs : T2OneRegCmpShiftedReg<
853                (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
854                opc, ".w\t$Rn, $ShiftedRm",
855                [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> {
856     let Inst{31-27} = 0b11101;
857     let Inst{26-25} = 0b01;
858     let Inst{24-21} = opcod;
859     let Inst{20} = 1; // The S bit.
860     let Inst{11-8} = 0b1111; // Rd
861   }
862}
863
864  // Assembler aliases w/o the ".w" suffix.
865  // No alias here for 'rr' version as not all instantiations of this
866  // multiclass want one (CMP in particular, does not).
867  def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"),
868     (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn,
869                                                    t2_so_imm:$imm, pred:$p)>;
870  def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"),
871     (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn,
872                                                    t2_so_reg:$shift,
873                                                    pred:$p)>;
874}
875
876/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
877multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
878                  InstrItinClass iii, InstrItinClass iis, RegisterClass target,
879                  PatFrag opnode> {
880  def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
881                   opc, ".w\t$Rt, $addr",
882                   [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
883    let Inst{31-27} = 0b11111;
884    let Inst{26-25} = 0b00;
885    let Inst{24} = signed;
886    let Inst{23} = 1;
887    let Inst{22-21} = opcod;
888    let Inst{20} = 1; // load
889
890    bits<4> Rt;
891    let Inst{15-12} = Rt;
892
893    bits<17> addr;
894    let addr{12}    = 1;           // add = TRUE
895    let Inst{19-16} = addr{16-13}; // Rn
896    let Inst{23}    = addr{12};    // U
897    let Inst{11-0}  = addr{11-0};  // imm
898  }
899  def i8  : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
900                   opc, "\t$Rt, $addr",
901                   [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
902    let Inst{31-27} = 0b11111;
903    let Inst{26-25} = 0b00;
904    let Inst{24} = signed;
905    let Inst{23} = 0;
906    let Inst{22-21} = opcod;
907    let Inst{20} = 1; // load
908    let Inst{11} = 1;
909    // Offset: index==TRUE, wback==FALSE
910    let Inst{10} = 1; // The P bit.
911    let Inst{8} = 0; // The W bit.
912
913    bits<4> Rt;
914    let Inst{15-12} = Rt;
915
916    bits<13> addr;
917    let Inst{19-16} = addr{12-9}; // Rn
918    let Inst{9}     = addr{8};    // U
919    let Inst{7-0}   = addr{7-0};  // imm
920  }
921  def s   : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
922                   opc, ".w\t$Rt, $addr",
923                   [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
924    let Inst{31-27} = 0b11111;
925    let Inst{26-25} = 0b00;
926    let Inst{24} = signed;
927    let Inst{23} = 0;
928    let Inst{22-21} = opcod;
929    let Inst{20} = 1; // load
930    let Inst{11-6} = 0b000000;
931
932    bits<4> Rt;
933    let Inst{15-12} = Rt;
934
935    bits<10> addr;
936    let Inst{19-16} = addr{9-6}; // Rn
937    let Inst{3-0}   = addr{5-2}; // Rm
938    let Inst{5-4}   = addr{1-0}; // imm
939
940    let DecoderMethod = "DecodeT2LoadShift";
941  }
942
943  // FIXME: Is the pci variant actually needed?
944  def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
945                   opc, ".w\t$Rt, $addr",
946                   [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
947    let isReMaterializable = 1;
948    let Inst{31-27} = 0b11111;
949    let Inst{26-25} = 0b00;
950    let Inst{24} = signed;
951    let Inst{23} = ?; // add = (U == '1')
952    let Inst{22-21} = opcod;
953    let Inst{20} = 1; // load
954    let Inst{19-16} = 0b1111; // Rn
955    bits<4> Rt;
956    bits<12> addr;
957    let Inst{15-12} = Rt{3-0};
958    let Inst{11-0}  = addr{11-0};
959  }
960}
961
962/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
963multiclass T2I_st<bits<2> opcod, string opc,
964                  InstrItinClass iii, InstrItinClass iis, RegisterClass target,
965                  PatFrag opnode> {
966  def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
967                   opc, ".w\t$Rt, $addr",
968                   [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
969    let Inst{31-27} = 0b11111;
970    let Inst{26-23} = 0b0001;
971    let Inst{22-21} = opcod;
972    let Inst{20} = 0; // !load
973
974    bits<4> Rt;
975    let Inst{15-12} = Rt;
976
977    bits<17> addr;
978    let addr{12}    = 1;           // add = TRUE
979    let Inst{19-16} = addr{16-13}; // Rn
980    let Inst{23}    = addr{12};    // U
981    let Inst{11-0}  = addr{11-0};  // imm
982  }
983  def i8  : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
984                   opc, "\t$Rt, $addr",
985                   [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
986    let Inst{31-27} = 0b11111;
987    let Inst{26-23} = 0b0000;
988    let Inst{22-21} = opcod;
989    let Inst{20} = 0; // !load
990    let Inst{11} = 1;
991    // Offset: index==TRUE, wback==FALSE
992    let Inst{10} = 1; // The P bit.
993    let Inst{8} = 0; // The W bit.
994
995    bits<4> Rt;
996    let Inst{15-12} = Rt;
997
998    bits<13> addr;
999    let Inst{19-16} = addr{12-9}; // Rn
1000    let Inst{9}     = addr{8};    // U
1001    let Inst{7-0}   = addr{7-0};  // imm
1002  }
1003  def s   : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
1004                   opc, ".w\t$Rt, $addr",
1005                   [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
1006    let Inst{31-27} = 0b11111;
1007    let Inst{26-23} = 0b0000;
1008    let Inst{22-21} = opcod;
1009    let Inst{20} = 0; // !load
1010    let Inst{11-6} = 0b000000;
1011
1012    bits<4> Rt;
1013    let Inst{15-12} = Rt;
1014
1015    bits<10> addr;
1016    let Inst{19-16}   = addr{9-6}; // Rn
1017    let Inst{3-0} = addr{5-2}; // Rm
1018    let Inst{5-4}   = addr{1-0}; // imm
1019  }
1020}
1021
1022/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
1023/// register and one whose operand is a register rotated by 8/16/24.
1024class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
1025  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1026             opc, ".w\t$Rd, $Rm$rot",
1027             [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1028             Requires<[IsThumb2]> {
1029   let Inst{31-27} = 0b11111;
1030   let Inst{26-23} = 0b0100;
1031   let Inst{22-20} = opcod;
1032   let Inst{19-16} = 0b1111; // Rn
1033   let Inst{15-12} = 0b1111;
1034   let Inst{7} = 1;
1035
1036   bits<2> rot;
1037   let Inst{5-4} = rot{1-0}; // rotate
1038}
1039
1040// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1041class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1042  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
1043             IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1044            [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1045          Requires<[HasT2ExtractPack, IsThumb2]> {
1046  bits<2> rot;
1047  let Inst{31-27} = 0b11111;
1048  let Inst{26-23} = 0b0100;
1049  let Inst{22-20} = opcod;
1050  let Inst{19-16} = 0b1111; // Rn
1051  let Inst{15-12} = 0b1111;
1052  let Inst{7} = 1;
1053  let Inst{5-4} = rot;
1054}
1055
1056// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1057// supported yet.
1058class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1059  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1060             opc, "\t$Rd, $Rm$rot", []>,
1061          Requires<[IsThumb2, HasT2ExtractPack]> {
1062  bits<2> rot;
1063  let Inst{31-27} = 0b11111;
1064  let Inst{26-23} = 0b0100;
1065  let Inst{22-20} = opcod;
1066  let Inst{19-16} = 0b1111; // Rn
1067  let Inst{15-12} = 0b1111;
1068  let Inst{7} = 1;
1069  let Inst{5-4} = rot;
1070}
1071
1072/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1073/// register and one whose operand is a register rotated by 8/16/24.
1074class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1075  : T2ThreeReg<(outs rGPR:$Rd),
1076               (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1077               IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1078             [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1079           Requires<[HasT2ExtractPack, IsThumb2]> {
1080  bits<2> rot;
1081  let Inst{31-27} = 0b11111;
1082  let Inst{26-23} = 0b0100;
1083  let Inst{22-20} = opcod;
1084  let Inst{15-12} = 0b1111;
1085  let Inst{7} = 1;
1086  let Inst{5-4} = rot;
1087}
1088
1089class T2I_exta_rrot_np<bits<3> opcod, string opc>
1090  : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1091               IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1092  bits<2> rot;
1093  let Inst{31-27} = 0b11111;
1094  let Inst{26-23} = 0b0100;
1095  let Inst{22-20} = opcod;
1096  let Inst{15-12} = 0b1111;
1097  let Inst{7} = 1;
1098  let Inst{5-4} = rot;
1099}
1100
1101//===----------------------------------------------------------------------===//
1102// Instructions
1103//===----------------------------------------------------------------------===//
1104
1105//===----------------------------------------------------------------------===//
1106//  Miscellaneous Instructions.
1107//
1108
1109class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1110           string asm, list<dag> pattern>
1111  : T2XI<oops, iops, itin, asm, pattern> {
1112  bits<4> Rd;
1113  bits<12> label;
1114
1115  let Inst{11-8}  = Rd;
1116  let Inst{26}    = label{11};
1117  let Inst{14-12} = label{10-8};
1118  let Inst{7-0}   = label{7-0};
1119}
1120
1121// LEApcrel - Load a pc-relative address into a register without offending the
1122// assembler.
1123def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1124              (ins t2adrlabel:$addr, pred:$p),
1125              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1126  let Inst{31-27} = 0b11110;
1127  let Inst{25-24} = 0b10;
1128  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1129  let Inst{22} = 0;
1130  let Inst{20} = 0;
1131  let Inst{19-16} = 0b1111; // Rn
1132  let Inst{15} = 0;
1133
1134  bits<4> Rd;
1135  bits<13> addr;
1136  let Inst{11-8} = Rd;
1137  let Inst{23}    = addr{12};
1138  let Inst{21}    = addr{12};
1139  let Inst{26}    = addr{11};
1140  let Inst{14-12} = addr{10-8};
1141  let Inst{7-0}   = addr{7-0};
1142}
1143
1144let neverHasSideEffects = 1, isReMaterializable = 1 in
1145def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1146                                4, IIC_iALUi, []>;
1147def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1148                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
1149                                4, IIC_iALUi,
1150                                []>;
1151
1152
1153//===----------------------------------------------------------------------===//
1154//  Load / store Instructions.
1155//
1156
1157// Load
1158let canFoldAsLoad = 1, isReMaterializable = 1  in
1159defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1160                      UnOpFrag<(load node:$Src)>>;
1161
1162// Loads with zero extension
1163defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1164                      rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1165defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1166                      rGPR, UnOpFrag<(zextloadi8  node:$Src)>>;
1167
1168// Loads with sign extension
1169defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1170                      rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1171defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1172                      rGPR, UnOpFrag<(sextloadi8  node:$Src)>>;
1173
1174let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1175// Load doubleword
1176def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1177                        (ins t2addrmode_imm8s4:$addr),
1178                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1179} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1180
1181// zextload i1 -> zextload i8
1182def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1183            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1184def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1185            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1186def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1187            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1188def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1189            (t2LDRBpci  tconstpool:$addr)>;
1190
1191// extload -> zextload
1192// FIXME: Reduce the number of patterns by legalizing extload to zextload
1193// earlier?
1194def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1195            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1196def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1197            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1198def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1199            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1200def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1201            (t2LDRBpci  tconstpool:$addr)>;
1202
1203def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1204            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1205def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1206            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1207def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1208            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1209def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1210            (t2LDRBpci  tconstpool:$addr)>;
1211
1212def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1213            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1214def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1215            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1216def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1217            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1218def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1219            (t2LDRHpci  tconstpool:$addr)>;
1220
1221// FIXME: The destination register of the loads and stores can't be PC, but
1222//        can be SP. We need another regclass (similar to rGPR) to represent
1223//        that. Not a pressing issue since these are selected manually,
1224//        not via pattern.
1225
1226// Indexed loads
1227
1228let mayLoad = 1, neverHasSideEffects = 1 in {
1229def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1230                            (ins t2addrmode_imm8:$addr),
1231                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1232                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1233                            []>;
1234
1235def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1236                            (ins GPR:$base, t2am_imm8_offset:$addr),
1237                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1238                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1239                            []>;
1240
1241def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1242                            (ins t2addrmode_imm8:$addr),
1243                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1244                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1245                            []>;
1246def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1247                            (ins GPR:$base, t2am_imm8_offset:$addr),
1248                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1249                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1250                            []>;
1251
1252def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1253                            (ins t2addrmode_imm8:$addr),
1254                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1255                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1256                            []>;
1257def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1258                            (ins GPR:$base, t2am_imm8_offset:$addr),
1259                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1260                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1261                            []>;
1262
1263def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1264                            (ins t2addrmode_imm8:$addr),
1265                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1266                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1267                            []>;
1268def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1269                            (ins GPR:$base, t2am_imm8_offset:$addr),
1270                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1271                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1272                            []>;
1273
1274def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1275                            (ins t2addrmode_imm8:$addr),
1276                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1277                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1278                            []>;
1279def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1280                            (ins GPR:$base, t2am_imm8_offset:$addr),
1281                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1282                        "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1283                            []>;
1284} // mayLoad = 1, neverHasSideEffects = 1
1285
1286// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1287// for disassembly only.
1288// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1289class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1290  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1291          "\t$Rt, $addr", []> {
1292  let Inst{31-27} = 0b11111;
1293  let Inst{26-25} = 0b00;
1294  let Inst{24} = signed;
1295  let Inst{23} = 0;
1296  let Inst{22-21} = type;
1297  let Inst{20} = 1; // load
1298  let Inst{11} = 1;
1299  let Inst{10-8} = 0b110; // PUW.
1300
1301  bits<4> Rt;
1302  bits<13> addr;
1303  let Inst{15-12} = Rt;
1304  let Inst{19-16} = addr{12-9};
1305  let Inst{7-0}   = addr{7-0};
1306}
1307
1308def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1309def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1310def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1311def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1312def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1313
1314// Store
1315defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1316                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1317defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1318                   rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1319defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1320                   rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1321
1322// Store doubleword
1323let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1324def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1325                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1326               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1327
1328// Indexed stores
1329def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1330                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1331                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1332                         "str", "\t$Rt, [$Rn, $addr]!",
1333                         "$Rn = $base_wb,@earlyclobber $base_wb",
1334             [(set GPRnopc:$base_wb,
1335                   (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1336
1337def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1338                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1339                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1340                          "str", "\t$Rt, [$Rn], $addr",
1341                          "$Rn = $base_wb,@earlyclobber $base_wb",
1342             [(set GPRnopc:$base_wb,
1343                  (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1344
1345def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1346                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1347                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1348                        "strh", "\t$Rt, [$Rn, $addr]!",
1349                        "$Rn = $base_wb,@earlyclobber $base_wb",
1350        [(set GPRnopc:$base_wb,
1351              (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1352
1353def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1354                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1355                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1356                         "strh", "\t$Rt, [$Rn], $addr",
1357                         "$Rn = $base_wb,@earlyclobber $base_wb",
1358       [(set GPRnopc:$base_wb,
1359             (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1360
1361def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1362                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1363                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1364                        "strb", "\t$Rt, [$Rn, $addr]!",
1365                        "$Rn = $base_wb,@earlyclobber $base_wb",
1366         [(set GPRnopc:$base_wb,
1367               (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1368
1369def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1370                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1371                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1372                         "strb", "\t$Rt, [$Rn], $addr",
1373                         "$Rn = $base_wb,@earlyclobber $base_wb",
1374        [(set GPRnopc:$base_wb,
1375              (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1376
1377// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1378// only.
1379// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1380class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1381  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1382          "\t$Rt, $addr", []> {
1383  let Inst{31-27} = 0b11111;
1384  let Inst{26-25} = 0b00;
1385  let Inst{24} = 0; // not signed
1386  let Inst{23} = 0;
1387  let Inst{22-21} = type;
1388  let Inst{20} = 0; // store
1389  let Inst{11} = 1;
1390  let Inst{10-8} = 0b110; // PUW
1391
1392  bits<4> Rt;
1393  bits<13> addr;
1394  let Inst{15-12} = Rt;
1395  let Inst{19-16} = addr{12-9};
1396  let Inst{7-0}   = addr{7-0};
1397}
1398
1399def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1400def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1401def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1402
1403// ldrd / strd pre / post variants
1404// For disassembly only.
1405
1406def t2LDRD_PRE  : T2Ii8s4Tied<1, 1, 1,
1407                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1408                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1409                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1410
1411def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1412                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1413                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1414                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1415
1416def t2STRD_PRE  : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1417                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1418                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1419
1420def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1421                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1422                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1423
1424// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1425// data/instruction access.  These are for disassembly only.
1426// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1427// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1428multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1429
1430  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1431                "\t$addr",
1432              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1433    let Inst{31-25} = 0b1111100;
1434    let Inst{24} = instr;
1435    let Inst{22} = 0;
1436    let Inst{21} = write;
1437    let Inst{20} = 1;
1438    let Inst{15-12} = 0b1111;
1439
1440    bits<17> addr;
1441    let addr{12}    = 1;           // add = TRUE
1442    let Inst{19-16} = addr{16-13}; // Rn
1443    let Inst{23}    = addr{12};    // U
1444    let Inst{11-0}  = addr{11-0};  // imm12
1445  }
1446
1447  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1448                "\t$addr",
1449               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1450    let Inst{31-25} = 0b1111100;
1451    let Inst{24} = instr;
1452    let Inst{23} = 0; // U = 0
1453    let Inst{22} = 0;
1454    let Inst{21} = write;
1455    let Inst{20} = 1;
1456    let Inst{15-12} = 0b1111;
1457    let Inst{11-8} = 0b1100;
1458
1459    bits<13> addr;
1460    let Inst{19-16} = addr{12-9}; // Rn
1461    let Inst{7-0}   = addr{7-0};  // imm8
1462  }
1463
1464  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1465               "\t$addr",
1466             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1467    let Inst{31-25} = 0b1111100;
1468    let Inst{24} = instr;
1469    let Inst{23} = 0; // add = TRUE for T1
1470    let Inst{22} = 0;
1471    let Inst{21} = write;
1472    let Inst{20} = 1;
1473    let Inst{15-12} = 0b1111;
1474    let Inst{11-6} = 0000000;
1475
1476    bits<10> addr;
1477    let Inst{19-16} = addr{9-6}; // Rn
1478    let Inst{3-0}   = addr{5-2}; // Rm
1479    let Inst{5-4}   = addr{1-0}; // imm2
1480
1481    let DecoderMethod = "DecodeT2LoadShift";
1482  }
1483}
1484
1485defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1486defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1487defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1488
1489//===----------------------------------------------------------------------===//
1490//  Load / store multiple Instructions.
1491//
1492
1493multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1494                            InstrItinClass itin_upd, bit L_bit> {
1495  def IA :
1496    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1497         itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
1498    bits<4>  Rn;
1499    bits<16> regs;
1500
1501    let Inst{31-27} = 0b11101;
1502    let Inst{26-25} = 0b00;
1503    let Inst{24-23} = 0b01;     // Increment After
1504    let Inst{22}    = 0;
1505    let Inst{21}    = 0;        // No writeback
1506    let Inst{20}    = L_bit;
1507    let Inst{19-16} = Rn;
1508    let Inst{15-0}  = regs;
1509  }
1510  def IA_UPD :
1511    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1512          itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1513    bits<4>  Rn;
1514    bits<16> regs;
1515
1516    let Inst{31-27} = 0b11101;
1517    let Inst{26-25} = 0b00;
1518    let Inst{24-23} = 0b01;     // Increment After
1519    let Inst{22}    = 0;
1520    let Inst{21}    = 1;        // Writeback
1521    let Inst{20}    = L_bit;
1522    let Inst{19-16} = Rn;
1523    let Inst{15-0}  = regs;
1524  }
1525  def DB :
1526    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1527         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1528    bits<4>  Rn;
1529    bits<16> regs;
1530
1531    let Inst{31-27} = 0b11101;
1532    let Inst{26-25} = 0b00;
1533    let Inst{24-23} = 0b10;     // Decrement Before
1534    let Inst{22}    = 0;
1535    let Inst{21}    = 0;        // No writeback
1536    let Inst{20}    = L_bit;
1537    let Inst{19-16} = Rn;
1538    let Inst{15-0}  = regs;
1539  }
1540  def DB_UPD :
1541    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1542          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1543    bits<4>  Rn;
1544    bits<16> regs;
1545
1546    let Inst{31-27} = 0b11101;
1547    let Inst{26-25} = 0b00;
1548    let Inst{24-23} = 0b10;     // Decrement Before
1549    let Inst{22}    = 0;
1550    let Inst{21}    = 1;        // Writeback
1551    let Inst{20}    = L_bit;
1552    let Inst{19-16} = Rn;
1553    let Inst{15-0}  = regs;
1554  }
1555}
1556
1557let neverHasSideEffects = 1 in {
1558
1559let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1560defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1561
1562let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1563defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1564
1565} // neverHasSideEffects
1566
1567
1568//===----------------------------------------------------------------------===//
1569//  Move Instructions.
1570//
1571
1572let neverHasSideEffects = 1 in
1573def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1574                   "mov", ".w\t$Rd, $Rm", []> {
1575  let Inst{31-27} = 0b11101;
1576  let Inst{26-25} = 0b01;
1577  let Inst{24-21} = 0b0010;
1578  let Inst{19-16} = 0b1111; // Rn
1579  let Inst{14-12} = 0b000;
1580  let Inst{7-4} = 0b0000;
1581}
1582
1583// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1584let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1585    AddedComplexity = 1 in
1586def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1587                   "mov", ".w\t$Rd, $imm",
1588                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1589  let Inst{31-27} = 0b11110;
1590  let Inst{25} = 0;
1591  let Inst{24-21} = 0b0010;
1592  let Inst{19-16} = 0b1111; // Rn
1593  let Inst{15} = 0;
1594}
1595
1596def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1597                                                   pred:$p, cc_out:$s)>;
1598
1599let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1600def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1601                   "movw", "\t$Rd, $imm",
1602                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1603  let Inst{31-27} = 0b11110;
1604  let Inst{25} = 1;
1605  let Inst{24-21} = 0b0010;
1606  let Inst{20} = 0; // The S bit.
1607  let Inst{15} = 0;
1608
1609  bits<4> Rd;
1610  bits<16> imm;
1611
1612  let Inst{11-8}  = Rd;
1613  let Inst{19-16} = imm{15-12};
1614  let Inst{26}    = imm{11};
1615  let Inst{14-12} = imm{10-8};
1616  let Inst{7-0}   = imm{7-0};
1617}
1618
1619def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1620                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1621
1622let Constraints = "$src = $Rd" in {
1623def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1624                    (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1625                    "movt", "\t$Rd, $imm",
1626                    [(set rGPR:$Rd,
1627                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1628  let Inst{31-27} = 0b11110;
1629  let Inst{25} = 1;
1630  let Inst{24-21} = 0b0110;
1631  let Inst{20} = 0; // The S bit.
1632  let Inst{15} = 0;
1633
1634  bits<4> Rd;
1635  bits<16> imm;
1636
1637  let Inst{11-8}  = Rd;
1638  let Inst{19-16} = imm{15-12};
1639  let Inst{26}    = imm{11};
1640  let Inst{14-12} = imm{10-8};
1641  let Inst{7-0}   = imm{7-0};
1642}
1643
1644def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1645                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1646} // Constraints
1647
1648def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1649
1650//===----------------------------------------------------------------------===//
1651//  Extend Instructions.
1652//
1653
1654// Sign extenders
1655
1656def t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1657                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1658def t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1659                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1660def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1661
1662def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1663                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1664def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1665                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1666def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1667
1668// TODO: SXT(A){B|H}16
1669
1670// Zero extenders
1671
1672let AddedComplexity = 16 in {
1673def t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1674                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1675def t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1676                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1677def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1678                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1679
1680// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1681//        The transformation should probably be done as a combiner action
1682//        instead so we can include a check for masking back in the upper
1683//        eight bits of the source into the lower eight bits of the result.
1684//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1685//            (t2UXTB16 rGPR:$Src, 3)>,
1686//          Requires<[HasT2ExtractPack, IsThumb2]>;
1687def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1688            (t2UXTB16 rGPR:$Src, 1)>,
1689        Requires<[HasT2ExtractPack, IsThumb2]>;
1690
1691def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1692                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1693def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1694                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1695def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1696}
1697
1698//===----------------------------------------------------------------------===//
1699//  Arithmetic Instructions.
1700//
1701
1702defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1703                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1704defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1705                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1706
1707// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1708// FIXME: Eliminate them if we can write def : Pat patterns which defines
1709// CPSR and the implicit def of CPSR is not needed.
1710defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1711                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1712                             BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
1713defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1714                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1715                             BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1716
1717let hasPostISelHook = 1 in {
1718defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1719              BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
1720defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1721              BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
1722}
1723
1724// RSB
1725defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1726                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1727
1728// FIXME: Eliminate them if we can write def : Pat patterns which defines
1729// CPSR and the implicit def of CPSR is not needed.
1730defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1731                             BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
1732
1733// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1734// The assume-no-carry-in form uses the negation of the input since add/sub
1735// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1736// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1737// details.
1738// The AddedComplexity preferences the first variant over the others since
1739// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1740let AddedComplexity = 1 in
1741def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1742            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1743def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1744            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1745def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1746            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1747let AddedComplexity = 1 in
1748def : T2Pat<(ARMaddc    rGPR:$src, imm0_255_neg:$imm),
1749            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1750def : T2Pat<(ARMaddc    rGPR:$src, t2_so_imm_neg:$imm),
1751            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1752// The with-carry-in form matches bitwise not instead of the negation.
1753// Effectively, the inverse interpretation of the carry flag already accounts
1754// for part of the negation.
1755let AddedComplexity = 1 in
1756def : T2Pat<(ARMadde    rGPR:$src, imm0_255_not:$imm, CPSR),
1757            (t2SBCri    rGPR:$src, imm0_255_not:$imm)>;
1758def : T2Pat<(ARMadde    rGPR:$src, t2_so_imm_not:$imm, CPSR),
1759            (t2SBCri    rGPR:$src, t2_so_imm_not:$imm)>;
1760
1761// Select Bytes -- for disassembly only
1762
1763def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1764                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1765          Requires<[IsThumb2, HasThumb2DSP]> {
1766  let Inst{31-27} = 0b11111;
1767  let Inst{26-24} = 0b010;
1768  let Inst{23} = 0b1;
1769  let Inst{22-20} = 0b010;
1770  let Inst{15-12} = 0b1111;
1771  let Inst{7} = 0b1;
1772  let Inst{6-4} = 0b000;
1773}
1774
1775// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1776// And Miscellaneous operations -- for disassembly only
1777class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1778              list<dag> pat = [/* For disassembly only; pattern left blank */],
1779              dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1780              string asm = "\t$Rd, $Rn, $Rm">
1781  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1782    Requires<[IsThumb2, HasThumb2DSP]> {
1783  let Inst{31-27} = 0b11111;
1784  let Inst{26-23} = 0b0101;
1785  let Inst{22-20} = op22_20;
1786  let Inst{15-12} = 0b1111;
1787  let Inst{7-4} = op7_4;
1788
1789  bits<4> Rd;
1790  bits<4> Rn;
1791  bits<4> Rm;
1792
1793  let Inst{11-8}  = Rd;
1794  let Inst{19-16} = Rn;
1795  let Inst{3-0}   = Rm;
1796}
1797
1798// Saturating add/subtract -- for disassembly only
1799
1800def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1801                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1802                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1803def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1804def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1805def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1806def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd", [],
1807                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1808def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub", [],
1809                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1810def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1811def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1812                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1813                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1814def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1815def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1816def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1817def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1818def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1819def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1820def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1821def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1822
1823// Signed/Unsigned add/subtract -- for disassembly only
1824
1825def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1826def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1827def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1828def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1829def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1830def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1831def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1832def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1833def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1834def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1835def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1836def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1837
1838// Signed/Unsigned halving add/subtract -- for disassembly only
1839
1840def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1841def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1842def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1843def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1844def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1845def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1846def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1847def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1848def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1849def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1850def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1851def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1852
1853// Helper class for disassembly only
1854// A6.3.16 & A6.3.17
1855// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1856class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1857  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1858  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1859  let Inst{31-27} = 0b11111;
1860  let Inst{26-24} = 0b011;
1861  let Inst{23}    = long;
1862  let Inst{22-20} = op22_20;
1863  let Inst{7-4}   = op7_4;
1864}
1865
1866class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1867  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1868  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1869  let Inst{31-27} = 0b11111;
1870  let Inst{26-24} = 0b011;
1871  let Inst{23}    = long;
1872  let Inst{22-20} = op22_20;
1873  let Inst{7-4}   = op7_4;
1874}
1875
1876// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1877
1878def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1879                                           (ins rGPR:$Rn, rGPR:$Rm),
1880                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1881          Requires<[IsThumb2, HasThumb2DSP]> {
1882  let Inst{15-12} = 0b1111;
1883}
1884def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1885                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1886                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1887          Requires<[IsThumb2, HasThumb2DSP]>;
1888
1889// Signed/Unsigned saturate -- for disassembly only
1890
1891class T2SatI<dag oops, dag iops, InstrItinClass itin,
1892           string opc, string asm, list<dag> pattern>
1893  : T2I<oops, iops, itin, opc, asm, pattern> {
1894  bits<4> Rd;
1895  bits<4> Rn;
1896  bits<5> sat_imm;
1897  bits<7> sh;
1898
1899  let Inst{11-8}  = Rd;
1900  let Inst{19-16} = Rn;
1901  let Inst{4-0}   = sat_imm;
1902  let Inst{21}    = sh{5};
1903  let Inst{14-12} = sh{4-2};
1904  let Inst{7-6}   = sh{1-0};
1905}
1906
1907def t2SSAT: T2SatI<
1908              (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1909              NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1910              [/* For disassembly only; pattern left blank */]> {
1911  let Inst{31-27} = 0b11110;
1912  let Inst{25-22} = 0b1100;
1913  let Inst{20} = 0;
1914  let Inst{15} = 0;
1915}
1916
1917def t2SSAT16: T2SatI<
1918                (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1919                "ssat16", "\t$Rd, $sat_imm, $Rn",
1920                [/* For disassembly only; pattern left blank */]>,
1921          Requires<[IsThumb2, HasThumb2DSP]> {
1922  let Inst{31-27} = 0b11110;
1923  let Inst{25-22} = 0b1100;
1924  let Inst{20} = 0;
1925  let Inst{15} = 0;
1926  let Inst{21} = 1;        // sh = '1'
1927  let Inst{14-12} = 0b000; // imm3 = '000'
1928  let Inst{7-6} = 0b00;    // imm2 = '00'
1929}
1930
1931def t2USAT: T2SatI<
1932                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1933                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1934                [/* For disassembly only; pattern left blank */]> {
1935  let Inst{31-27} = 0b11110;
1936  let Inst{25-22} = 0b1110;
1937  let Inst{20} = 0;
1938  let Inst{15} = 0;
1939}
1940
1941def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1942                     NoItinerary,
1943                     "usat16", "\t$Rd, $sat_imm, $Rn",
1944                     [/* For disassembly only; pattern left blank */]>,
1945          Requires<[IsThumb2, HasThumb2DSP]> {
1946  let Inst{31-27} = 0b11110;
1947  let Inst{25-22} = 0b1110;
1948  let Inst{20} = 0;
1949  let Inst{15} = 0;
1950  let Inst{21} = 1;        // sh = '1'
1951  let Inst{14-12} = 0b000; // imm3 = '000'
1952  let Inst{7-6} = 0b00;    // imm2 = '00'
1953}
1954
1955def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1956def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1957
1958//===----------------------------------------------------------------------===//
1959//  Shift and rotate Instructions.
1960//
1961
1962defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm0_31,
1963                        BinOpFrag<(shl  node:$LHS, node:$RHS)>, "t2LSL">;
1964defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr,
1965                        BinOpFrag<(srl  node:$LHS, node:$RHS)>, "t2LSR">;
1966defm t2ASR  : T2I_sh_ir<0b10, "asr", imm_sr,
1967                        BinOpFrag<(sra  node:$LHS, node:$RHS)>, "t2ASR">;
1968defm t2ROR  : T2I_sh_ir<0b11, "ror", imm0_31,
1969                        BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">;
1970
1971// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1972def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1973          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1974
1975let Uses = [CPSR] in {
1976def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1977                   "rrx", "\t$Rd, $Rm",
1978                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1979  let Inst{31-27} = 0b11101;
1980  let Inst{26-25} = 0b01;
1981  let Inst{24-21} = 0b0010;
1982  let Inst{19-16} = 0b1111; // Rn
1983  let Inst{14-12} = 0b000;
1984  let Inst{7-4} = 0b0011;
1985}
1986}
1987
1988let isCodeGenOnly = 1, Defs = [CPSR] in {
1989def t2MOVsrl_flag : T2TwoRegShiftImm<
1990                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1991                        "lsrs", ".w\t$Rd, $Rm, #1",
1992                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1993  let Inst{31-27} = 0b11101;
1994  let Inst{26-25} = 0b01;
1995  let Inst{24-21} = 0b0010;
1996  let Inst{20} = 1; // The S bit.
1997  let Inst{19-16} = 0b1111; // Rn
1998  let Inst{5-4} = 0b01; // Shift type.
1999  // Shift amount = Inst{14-12:7-6} = 1.
2000  let Inst{14-12} = 0b000;
2001  let Inst{7-6} = 0b01;
2002}
2003def t2MOVsra_flag : T2TwoRegShiftImm<
2004                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2005                        "asrs", ".w\t$Rd, $Rm, #1",
2006                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2007  let Inst{31-27} = 0b11101;
2008  let Inst{26-25} = 0b01;
2009  let Inst{24-21} = 0b0010;
2010  let Inst{20} = 1; // The S bit.
2011  let Inst{19-16} = 0b1111; // Rn
2012  let Inst{5-4} = 0b10; // Shift type.
2013  // Shift amount = Inst{14-12:7-6} = 1.
2014  let Inst{14-12} = 0b000;
2015  let Inst{7-6} = 0b01;
2016}
2017}
2018
2019//===----------------------------------------------------------------------===//
2020//  Bitwise Instructions.
2021//
2022
2023defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2024                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2025                            BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2026defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
2027                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2028                            BinOpFrag<(or  node:$LHS, node:$RHS)>, "t2ORR", 1>;
2029defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
2030                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2031                            BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2032
2033defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
2034                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2035                            BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2036                            "t2BIC">;
2037
2038class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2039              string opc, string asm, list<dag> pattern>
2040    : T2I<oops, iops, itin, opc, asm, pattern> {
2041  bits<4> Rd;
2042  bits<5> msb;
2043  bits<5> lsb;
2044
2045  let Inst{11-8}  = Rd;
2046  let Inst{4-0}   = msb{4-0};
2047  let Inst{14-12} = lsb{4-2};
2048  let Inst{7-6}   = lsb{1-0};
2049}
2050
2051class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2052              string opc, string asm, list<dag> pattern>
2053    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2054  bits<4> Rn;
2055
2056  let Inst{19-16} = Rn;
2057}
2058
2059let Constraints = "$src = $Rd" in
2060def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2061                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2062                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2063  let Inst{31-27} = 0b11110;
2064  let Inst{26} = 0; // should be 0.
2065  let Inst{25} = 1;
2066  let Inst{24-20} = 0b10110;
2067  let Inst{19-16} = 0b1111; // Rn
2068  let Inst{15} = 0;
2069  let Inst{5} = 0; // should be 0.
2070
2071  bits<10> imm;
2072  let msb{4-0} = imm{9-5};
2073  let lsb{4-0} = imm{4-0};
2074}
2075
2076def t2SBFX: T2TwoRegBitFI<
2077                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2078                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2079  let Inst{31-27} = 0b11110;
2080  let Inst{25} = 1;
2081  let Inst{24-20} = 0b10100;
2082  let Inst{15} = 0;
2083}
2084
2085def t2UBFX: T2TwoRegBitFI<
2086                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2087                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2088  let Inst{31-27} = 0b11110;
2089  let Inst{25} = 1;
2090  let Inst{24-20} = 0b11100;
2091  let Inst{15} = 0;
2092}
2093
2094// A8.6.18  BFI - Bitfield insert (Encoding T1)
2095let Constraints = "$src = $Rd" in {
2096  def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2097                  (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2098                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2099                  [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2100                                   bf_inv_mask_imm:$imm))]> {
2101    let Inst{31-27} = 0b11110;
2102    let Inst{26} = 0; // should be 0.
2103    let Inst{25} = 1;
2104    let Inst{24-20} = 0b10110;
2105    let Inst{15} = 0;
2106    let Inst{5} = 0; // should be 0.
2107
2108    bits<10> imm;
2109    let msb{4-0} = imm{9-5};
2110    let lsb{4-0} = imm{4-0};
2111  }
2112
2113  // GNU as only supports this form of bfi (w/ 4 arguments)
2114  let isAsmParserOnly = 1 in
2115  def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2116                  (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2117                       width_imm:$width),
2118                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2119                  []> {
2120    let Inst{31-27} = 0b11110;
2121    let Inst{26} = 0; // should be 0.
2122    let Inst{25} = 1;
2123    let Inst{24-20} = 0b10110;
2124    let Inst{15} = 0;
2125    let Inst{5} = 0; // should be 0.
2126
2127    bits<5> lsbit;
2128    bits<5> width;
2129    let msb{4-0} = width; // Custom encoder => lsb+width-1
2130    let lsb{4-0} = lsbit;
2131  }
2132}
2133
2134defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2135                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2136                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>,
2137                          "t2ORN", 0, "">;
2138
2139// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2140let AddedComplexity = 1 in
2141defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2142                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2143                          UnOpFrag<(not node:$Src)>, 1, 1>;
2144
2145
2146let AddedComplexity = 1 in
2147def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2148            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2149
2150// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2151def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2152            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2153            Requires<[IsThumb2]>;
2154
2155def : T2Pat<(t2_so_imm_not:$src),
2156            (t2MVNi t2_so_imm_not:$src)>;
2157
2158//===----------------------------------------------------------------------===//
2159//  Multiply Instructions.
2160//
2161let isCommutable = 1 in
2162def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2163                "mul", "\t$Rd, $Rn, $Rm",
2164                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2165  let Inst{31-27} = 0b11111;
2166  let Inst{26-23} = 0b0110;
2167  let Inst{22-20} = 0b000;
2168  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2169  let Inst{7-4} = 0b0000; // Multiply
2170}
2171
2172def t2MLA: T2FourReg<
2173                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2174                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2175                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2176  let Inst{31-27} = 0b11111;
2177  let Inst{26-23} = 0b0110;
2178  let Inst{22-20} = 0b000;
2179  let Inst{7-4} = 0b0000; // Multiply
2180}
2181
2182def t2MLS: T2FourReg<
2183                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2184                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2185                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2186  let Inst{31-27} = 0b11111;
2187  let Inst{26-23} = 0b0110;
2188  let Inst{22-20} = 0b000;
2189  let Inst{7-4} = 0b0001; // Multiply and Subtract
2190}
2191
2192// Extra precision multiplies with low / high results
2193let neverHasSideEffects = 1 in {
2194let isCommutable = 1 in {
2195def t2SMULL : T2MulLong<0b000, 0b0000,
2196                  (outs rGPR:$RdLo, rGPR:$RdHi),
2197                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2198                   "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2199
2200def t2UMULL : T2MulLong<0b010, 0b0000,
2201                  (outs rGPR:$RdLo, rGPR:$RdHi),
2202                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2203                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2204} // isCommutable
2205
2206// Multiply + accumulate
2207def t2SMLAL : T2MulLong<0b100, 0b0000,
2208                  (outs rGPR:$RdLo, rGPR:$RdHi),
2209                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2210                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2211
2212def t2UMLAL : T2MulLong<0b110, 0b0000,
2213                  (outs rGPR:$RdLo, rGPR:$RdHi),
2214                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2215                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2216
2217def t2UMAAL : T2MulLong<0b110, 0b0110,
2218                  (outs rGPR:$RdLo, rGPR:$RdHi),
2219                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2220                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2221          Requires<[IsThumb2, HasThumb2DSP]>;
2222} // neverHasSideEffects
2223
2224// Rounding variants of the below included for disassembly only
2225
2226// Most significant word multiply
2227def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2228                  "smmul", "\t$Rd, $Rn, $Rm",
2229                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2230          Requires<[IsThumb2, HasThumb2DSP]> {
2231  let Inst{31-27} = 0b11111;
2232  let Inst{26-23} = 0b0110;
2233  let Inst{22-20} = 0b101;
2234  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2235  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2236}
2237
2238def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2239                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
2240          Requires<[IsThumb2, HasThumb2DSP]> {
2241  let Inst{31-27} = 0b11111;
2242  let Inst{26-23} = 0b0110;
2243  let Inst{22-20} = 0b101;
2244  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2245  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2246}
2247
2248def t2SMMLA : T2FourReg<
2249        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2250                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2251                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2252          Requires<[IsThumb2, HasThumb2DSP]> {
2253  let Inst{31-27} = 0b11111;
2254  let Inst{26-23} = 0b0110;
2255  let Inst{22-20} = 0b101;
2256  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2257}
2258
2259def t2SMMLAR: T2FourReg<
2260        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2261                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2262          Requires<[IsThumb2, HasThumb2DSP]> {
2263  let Inst{31-27} = 0b11111;
2264  let Inst{26-23} = 0b0110;
2265  let Inst{22-20} = 0b101;
2266  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2267}
2268
2269def t2SMMLS: T2FourReg<
2270        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2271                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2272                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2273          Requires<[IsThumb2, HasThumb2DSP]> {
2274  let Inst{31-27} = 0b11111;
2275  let Inst{26-23} = 0b0110;
2276  let Inst{22-20} = 0b110;
2277  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2278}
2279
2280def t2SMMLSR:T2FourReg<
2281        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2282                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2283          Requires<[IsThumb2, HasThumb2DSP]> {
2284  let Inst{31-27} = 0b11111;
2285  let Inst{26-23} = 0b0110;
2286  let Inst{22-20} = 0b110;
2287  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2288}
2289
2290multiclass T2I_smul<string opc, PatFrag opnode> {
2291  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2292              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2293              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2294                                      (sext_inreg rGPR:$Rm, i16)))]>,
2295          Requires<[IsThumb2, HasThumb2DSP]> {
2296    let Inst{31-27} = 0b11111;
2297    let Inst{26-23} = 0b0110;
2298    let Inst{22-20} = 0b001;
2299    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2300    let Inst{7-6} = 0b00;
2301    let Inst{5-4} = 0b00;
2302  }
2303
2304  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2305              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2306              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2307                                      (sra rGPR:$Rm, (i32 16))))]>,
2308          Requires<[IsThumb2, HasThumb2DSP]> {
2309    let Inst{31-27} = 0b11111;
2310    let Inst{26-23} = 0b0110;
2311    let Inst{22-20} = 0b001;
2312    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2313    let Inst{7-6} = 0b00;
2314    let Inst{5-4} = 0b01;
2315  }
2316
2317  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2318              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2319              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2320                                      (sext_inreg rGPR:$Rm, i16)))]>,
2321          Requires<[IsThumb2, HasThumb2DSP]> {
2322    let Inst{31-27} = 0b11111;
2323    let Inst{26-23} = 0b0110;
2324    let Inst{22-20} = 0b001;
2325    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2326    let Inst{7-6} = 0b00;
2327    let Inst{5-4} = 0b10;
2328  }
2329
2330  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2331              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2332              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2333                                      (sra rGPR:$Rm, (i32 16))))]>,
2334          Requires<[IsThumb2, HasThumb2DSP]> {
2335    let Inst{31-27} = 0b11111;
2336    let Inst{26-23} = 0b0110;
2337    let Inst{22-20} = 0b001;
2338    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2339    let Inst{7-6} = 0b00;
2340    let Inst{5-4} = 0b11;
2341  }
2342
2343  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2344              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2345              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2346                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2347          Requires<[IsThumb2, HasThumb2DSP]> {
2348    let Inst{31-27} = 0b11111;
2349    let Inst{26-23} = 0b0110;
2350    let Inst{22-20} = 0b011;
2351    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2352    let Inst{7-6} = 0b00;
2353    let Inst{5-4} = 0b00;
2354  }
2355
2356  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2357              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2358              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2359                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2360          Requires<[IsThumb2, HasThumb2DSP]> {
2361    let Inst{31-27} = 0b11111;
2362    let Inst{26-23} = 0b0110;
2363    let Inst{22-20} = 0b011;
2364    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2365    let Inst{7-6} = 0b00;
2366    let Inst{5-4} = 0b01;
2367  }
2368}
2369
2370
2371multiclass T2I_smla<string opc, PatFrag opnode> {
2372  def BB : T2FourReg<
2373        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2374              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2375              [(set rGPR:$Rd, (add rGPR:$Ra,
2376                               (opnode (sext_inreg rGPR:$Rn, i16),
2377                                       (sext_inreg rGPR:$Rm, i16))))]>,
2378          Requires<[IsThumb2, HasThumb2DSP]> {
2379    let Inst{31-27} = 0b11111;
2380    let Inst{26-23} = 0b0110;
2381    let Inst{22-20} = 0b001;
2382    let Inst{7-6} = 0b00;
2383    let Inst{5-4} = 0b00;
2384  }
2385
2386  def BT : T2FourReg<
2387       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2388             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2389             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2390                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2391          Requires<[IsThumb2, HasThumb2DSP]> {
2392    let Inst{31-27} = 0b11111;
2393    let Inst{26-23} = 0b0110;
2394    let Inst{22-20} = 0b001;
2395    let Inst{7-6} = 0b00;
2396    let Inst{5-4} = 0b01;
2397  }
2398
2399  def TB : T2FourReg<
2400        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2401              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2402              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2403                                               (sext_inreg rGPR:$Rm, i16))))]>,
2404          Requires<[IsThumb2, HasThumb2DSP]> {
2405    let Inst{31-27} = 0b11111;
2406    let Inst{26-23} = 0b0110;
2407    let Inst{22-20} = 0b001;
2408    let Inst{7-6} = 0b00;
2409    let Inst{5-4} = 0b10;
2410  }
2411
2412  def TT : T2FourReg<
2413        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2414              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2415             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2416                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2417          Requires<[IsThumb2, HasThumb2DSP]> {
2418    let Inst{31-27} = 0b11111;
2419    let Inst{26-23} = 0b0110;
2420    let Inst{22-20} = 0b001;
2421    let Inst{7-6} = 0b00;
2422    let Inst{5-4} = 0b11;
2423  }
2424
2425  def WB : T2FourReg<
2426        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2427              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2428              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2429                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2430          Requires<[IsThumb2, HasThumb2DSP]> {
2431    let Inst{31-27} = 0b11111;
2432    let Inst{26-23} = 0b0110;
2433    let Inst{22-20} = 0b011;
2434    let Inst{7-6} = 0b00;
2435    let Inst{5-4} = 0b00;
2436  }
2437
2438  def WT : T2FourReg<
2439        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2440              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2441              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2442                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2443          Requires<[IsThumb2, HasThumb2DSP]> {
2444    let Inst{31-27} = 0b11111;
2445    let Inst{26-23} = 0b0110;
2446    let Inst{22-20} = 0b011;
2447    let Inst{7-6} = 0b00;
2448    let Inst{5-4} = 0b01;
2449  }
2450}
2451
2452defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2453defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2454
2455// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2456def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2457         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2458           [/* For disassembly only; pattern left blank */]>,
2459          Requires<[IsThumb2, HasThumb2DSP]>;
2460def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2461         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2462           [/* For disassembly only; pattern left blank */]>,
2463          Requires<[IsThumb2, HasThumb2DSP]>;
2464def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2465         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2466           [/* For disassembly only; pattern left blank */]>,
2467          Requires<[IsThumb2, HasThumb2DSP]>;
2468def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2469         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2470           [/* For disassembly only; pattern left blank */]>,
2471          Requires<[IsThumb2, HasThumb2DSP]>;
2472
2473// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2474// These are for disassembly only.
2475
2476def t2SMUAD: T2ThreeReg_mac<
2477            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2478            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2479          Requires<[IsThumb2, HasThumb2DSP]> {
2480  let Inst{15-12} = 0b1111;
2481}
2482def t2SMUADX:T2ThreeReg_mac<
2483            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2484            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2485          Requires<[IsThumb2, HasThumb2DSP]> {
2486  let Inst{15-12} = 0b1111;
2487}
2488def t2SMUSD: T2ThreeReg_mac<
2489            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2490            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2491          Requires<[IsThumb2, HasThumb2DSP]> {
2492  let Inst{15-12} = 0b1111;
2493}
2494def t2SMUSDX:T2ThreeReg_mac<
2495            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2496            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2497          Requires<[IsThumb2, HasThumb2DSP]> {
2498  let Inst{15-12} = 0b1111;
2499}
2500def t2SMLAD   : T2FourReg_mac<
2501            0, 0b010, 0b0000, (outs rGPR:$Rd),
2502            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2503            "\t$Rd, $Rn, $Rm, $Ra", []>,
2504          Requires<[IsThumb2, HasThumb2DSP]>;
2505def t2SMLADX  : T2FourReg_mac<
2506            0, 0b010, 0b0001, (outs rGPR:$Rd),
2507            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2508            "\t$Rd, $Rn, $Rm, $Ra", []>,
2509          Requires<[IsThumb2, HasThumb2DSP]>;
2510def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2511            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2512            "\t$Rd, $Rn, $Rm, $Ra", []>,
2513          Requires<[IsThumb2, HasThumb2DSP]>;
2514def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2515            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2516            "\t$Rd, $Rn, $Rm, $Ra", []>,
2517          Requires<[IsThumb2, HasThumb2DSP]>;
2518def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2519                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2520                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2521          Requires<[IsThumb2, HasThumb2DSP]>;
2522def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2523                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2524                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2525          Requires<[IsThumb2, HasThumb2DSP]>;
2526def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2527                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2528                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2529          Requires<[IsThumb2, HasThumb2DSP]>;
2530def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2531                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2532                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2533          Requires<[IsThumb2, HasThumb2DSP]>;
2534
2535//===----------------------------------------------------------------------===//
2536//  Division Instructions.
2537//  Signed and unsigned division on v7-M
2538//
2539def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2540                 "sdiv", "\t$Rd, $Rn, $Rm",
2541                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2542                 Requires<[HasDivide, IsThumb2]> {
2543  let Inst{31-27} = 0b11111;
2544  let Inst{26-21} = 0b011100;
2545  let Inst{20} = 0b1;
2546  let Inst{15-12} = 0b1111;
2547  let Inst{7-4} = 0b1111;
2548}
2549
2550def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2551                 "udiv", "\t$Rd, $Rn, $Rm",
2552                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2553                 Requires<[HasDivide, IsThumb2]> {
2554  let Inst{31-27} = 0b11111;
2555  let Inst{26-21} = 0b011101;
2556  let Inst{20} = 0b1;
2557  let Inst{15-12} = 0b1111;
2558  let Inst{7-4} = 0b1111;
2559}
2560
2561//===----------------------------------------------------------------------===//
2562//  Misc. Arithmetic Instructions.
2563//
2564
2565class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2566      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2567  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2568  let Inst{31-27} = 0b11111;
2569  let Inst{26-22} = 0b01010;
2570  let Inst{21-20} = op1;
2571  let Inst{15-12} = 0b1111;
2572  let Inst{7-6} = 0b10;
2573  let Inst{5-4} = op2;
2574  let Rn{3-0} = Rm;
2575}
2576
2577def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2578                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2579
2580def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2581                      "rbit", "\t$Rd, $Rm",
2582                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2583
2584def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2585                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2586
2587def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2588                       "rev16", ".w\t$Rd, $Rm",
2589                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2590
2591def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2592                       "revsh", ".w\t$Rd, $Rm",
2593                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2594
2595def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2596                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2597            (t2REVSH rGPR:$Rm)>;
2598
2599def t2PKHBT : T2ThreeReg<
2600            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2601                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2602                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2603                                      (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2604                                           0xFFFF0000)))]>,
2605                  Requires<[HasT2ExtractPack, IsThumb2]> {
2606  let Inst{31-27} = 0b11101;
2607  let Inst{26-25} = 0b01;
2608  let Inst{24-20} = 0b01100;
2609  let Inst{5} = 0; // BT form
2610  let Inst{4} = 0;
2611
2612  bits<5> sh;
2613  let Inst{14-12} = sh{4-2};
2614  let Inst{7-6}   = sh{1-0};
2615}
2616
2617// Alternate cases for PKHBT where identities eliminate some nodes.
2618def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2619            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2620            Requires<[HasT2ExtractPack, IsThumb2]>;
2621def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2622            (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2623            Requires<[HasT2ExtractPack, IsThumb2]>;
2624
2625// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2626// will match the pattern below.
2627def t2PKHTB : T2ThreeReg<
2628                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2629                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2630                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2631                                       (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2632                                            0xFFFF)))]>,
2633                  Requires<[HasT2ExtractPack, IsThumb2]> {
2634  let Inst{31-27} = 0b11101;
2635  let Inst{26-25} = 0b01;
2636  let Inst{24-20} = 0b01100;
2637  let Inst{5} = 1; // TB form
2638  let Inst{4} = 0;
2639
2640  bits<5> sh;
2641  let Inst{14-12} = sh{4-2};
2642  let Inst{7-6}   = sh{1-0};
2643}
2644
2645// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2646// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2647def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2648            (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2649            Requires<[HasT2ExtractPack, IsThumb2]>;
2650def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2651                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2652            (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2653            Requires<[HasT2ExtractPack, IsThumb2]>;
2654
2655//===----------------------------------------------------------------------===//
2656//  Comparison Instructions...
2657//
2658defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2659                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2660                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">;
2661
2662def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, t2_so_imm:$imm),
2663            (t2CMPri  GPRnopc:$lhs, t2_so_imm:$imm)>;
2664def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, rGPR:$rhs),
2665            (t2CMPrr  GPRnopc:$lhs, rGPR:$rhs)>;
2666def : T2Pat<(ARMcmpZ  GPRnopc:$lhs, t2_so_reg:$rhs),
2667            (t2CMPrs  GPRnopc:$lhs, t2_so_reg:$rhs)>;
2668
2669//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2670//       Compare-to-zero still works out, just not the relationals
2671//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2672//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2673defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2674                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2675                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>,
2676                          "t2CMNz">;
2677
2678//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2679//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2680
2681def : T2Pat<(ARMcmpZ  GPRnopc:$src, t2_so_imm_neg:$imm),
2682            (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>;
2683
2684defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2685                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2686                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>,
2687                          "t2TST">;
2688defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2689                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2690                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>,
2691                          "t2TEQ">;
2692
2693// Conditional moves
2694// FIXME: should be able to write a pattern for ARMcmov, but can't use
2695// a two-value operand where a dag node expects two operands. :(
2696let neverHasSideEffects = 1 in {
2697def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2698                            (ins rGPR:$false, rGPR:$Rm, pred:$p),
2699                            4, IIC_iCMOVr,
2700   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2701                RegConstraint<"$false = $Rd">;
2702
2703let isMoveImm = 1 in
2704def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2705                            (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2706                   4, IIC_iCMOVi,
2707[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2708                   RegConstraint<"$false = $Rd">;
2709
2710// FIXME: Pseudo-ize these. For now, just mark codegen only.
2711let isCodeGenOnly = 1 in {
2712let isMoveImm = 1 in
2713def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2714                      IIC_iCMOVi,
2715                      "movw", "\t$Rd, $imm", []>,
2716                      RegConstraint<"$false = $Rd"> {
2717  let Inst{31-27} = 0b11110;
2718  let Inst{25} = 1;
2719  let Inst{24-21} = 0b0010;
2720  let Inst{20} = 0; // The S bit.
2721  let Inst{15} = 0;
2722
2723  bits<4> Rd;
2724  bits<16> imm;
2725
2726  let Inst{11-8}  = Rd;
2727  let Inst{19-16} = imm{15-12};
2728  let Inst{26}    = imm{11};
2729  let Inst{14-12} = imm{10-8};
2730  let Inst{7-0}   = imm{7-0};
2731}
2732
2733let isMoveImm = 1 in
2734def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2735                               (ins rGPR:$false, i32imm:$src, pred:$p),
2736                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2737
2738let isMoveImm = 1 in
2739def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2740                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2741[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2742                   imm:$cc, CCR:$ccr))*/]>,
2743                   RegConstraint<"$false = $Rd"> {
2744  let Inst{31-27} = 0b11110;
2745  let Inst{25} = 0;
2746  let Inst{24-21} = 0b0011;
2747  let Inst{20} = 0; // The S bit.
2748  let Inst{19-16} = 0b1111; // Rn
2749  let Inst{15} = 0;
2750}
2751
2752class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2753                   string opc, string asm, list<dag> pattern>
2754  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2755  let Inst{31-27} = 0b11101;
2756  let Inst{26-25} = 0b01;
2757  let Inst{24-21} = 0b0010;
2758  let Inst{20} = 0; // The S bit.
2759  let Inst{19-16} = 0b1111; // Rn
2760  let Inst{5-4} = opcod; // Shift type.
2761}
2762def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2763                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2764                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2765                 RegConstraint<"$false = $Rd">;
2766def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2767                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2768                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2769                 RegConstraint<"$false = $Rd">;
2770def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2771                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2772                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2773                 RegConstraint<"$false = $Rd">;
2774def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2775                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2776                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2777                 RegConstraint<"$false = $Rd">;
2778} // isCodeGenOnly = 1
2779} // neverHasSideEffects
2780
2781//===----------------------------------------------------------------------===//
2782// Atomic operations intrinsics
2783//
2784
2785// memory barriers protect the atomic sequences
2786let hasSideEffects = 1 in {
2787def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2788                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2789                  Requires<[IsThumb, HasDB]> {
2790  bits<4> opt;
2791  let Inst{31-4} = 0xf3bf8f5;
2792  let Inst{3-0} = opt;
2793}
2794}
2795
2796def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2797                  "dsb", "\t$opt", []>,
2798                  Requires<[IsThumb, HasDB]> {
2799  bits<4> opt;
2800  let Inst{31-4} = 0xf3bf8f4;
2801  let Inst{3-0} = opt;
2802}
2803
2804def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2805                  "isb", "\t$opt",
2806                  []>, Requires<[IsThumb2, HasDB]> {
2807  bits<4> opt;
2808  let Inst{31-4} = 0xf3bf8f6;
2809  let Inst{3-0} = opt;
2810}
2811
2812class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2813                InstrItinClass itin, string opc, string asm, string cstr,
2814                list<dag> pattern, bits<4> rt2 = 0b1111>
2815  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2816  let Inst{31-27} = 0b11101;
2817  let Inst{26-20} = 0b0001101;
2818  let Inst{11-8} = rt2;
2819  let Inst{7-6} = 0b01;
2820  let Inst{5-4} = opcod;
2821  let Inst{3-0} = 0b1111;
2822
2823  bits<4> addr;
2824  bits<4> Rt;
2825  let Inst{19-16} = addr;
2826  let Inst{15-12} = Rt;
2827}
2828class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2829                InstrItinClass itin, string opc, string asm, string cstr,
2830                list<dag> pattern, bits<4> rt2 = 0b1111>
2831  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2832  let Inst{31-27} = 0b11101;
2833  let Inst{26-20} = 0b0001100;
2834  let Inst{11-8} = rt2;
2835  let Inst{7-6} = 0b01;
2836  let Inst{5-4} = opcod;
2837
2838  bits<4> Rd;
2839  bits<4> addr;
2840  bits<4> Rt;
2841  let Inst{3-0}  = Rd;
2842  let Inst{19-16} = addr;
2843  let Inst{15-12} = Rt;
2844}
2845
2846let mayLoad = 1 in {
2847def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2848                         AddrModeNone, 4, NoItinerary,
2849                         "ldrexb", "\t$Rt, $addr", "", []>;
2850def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2851                         AddrModeNone, 4, NoItinerary,
2852                         "ldrexh", "\t$Rt, $addr", "", []>;
2853def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2854                       AddrModeNone, 4, NoItinerary,
2855                       "ldrex", "\t$Rt, $addr", "", []> {
2856  let Inst{31-27} = 0b11101;
2857  let Inst{26-20} = 0b0000101;
2858  let Inst{11-8} = 0b1111;
2859  let Inst{7-0} = 0b00000000; // imm8 = 0
2860
2861  bits<4> Rt;
2862  bits<4> addr;
2863  let Inst{19-16} = addr;
2864  let Inst{15-12} = Rt;
2865}
2866let hasExtraDefRegAllocReq = 1 in
2867def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2868                         (ins t2addrmode_reg:$addr),
2869                         AddrModeNone, 4, NoItinerary,
2870                         "ldrexd", "\t$Rt, $Rt2, $addr", "",
2871                         [], {?, ?, ?, ?}> {
2872  bits<4> Rt2;
2873  let Inst{11-8} = Rt2;
2874}
2875}
2876
2877let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2878def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2879                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2880                         AddrModeNone, 4, NoItinerary,
2881                         "strexb", "\t$Rd, $Rt, $addr", "", []>;
2882def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2883                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2884                         AddrModeNone, 4, NoItinerary,
2885                         "strexh", "\t$Rd, $Rt, $addr", "", []>;
2886def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2887                  AddrModeNone, 4, NoItinerary,
2888                  "strex", "\t$Rd, $Rt, $addr", "",
2889                  []> {
2890  let Inst{31-27} = 0b11101;
2891  let Inst{26-20} = 0b0000100;
2892  let Inst{7-0} = 0b00000000; // imm8 = 0
2893
2894  bits<4> Rd;
2895  bits<4> addr;
2896  bits<4> Rt;
2897  let Inst{11-8}  = Rd;
2898  let Inst{19-16} = addr;
2899  let Inst{15-12} = Rt;
2900}
2901}
2902
2903let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2904def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2905                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2906                         AddrModeNone, 4, NoItinerary,
2907                         "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2908                         {?, ?, ?, ?}> {
2909  bits<4> Rt2;
2910  let Inst{11-8} = Rt2;
2911}
2912
2913def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
2914            Requires<[IsThumb2, HasV7]>  {
2915  let Inst{31-16} = 0xf3bf;
2916  let Inst{15-14} = 0b10;
2917  let Inst{13} = 0;
2918  let Inst{12} = 0;
2919  let Inst{11-8} = 0b1111;
2920  let Inst{7-4} = 0b0010;
2921  let Inst{3-0} = 0b1111;
2922}
2923
2924//===----------------------------------------------------------------------===//
2925// SJLJ Exception handling intrinsics
2926//   eh_sjlj_setjmp() is an instruction sequence to store the return
2927//   address and save #0 in R0 for the non-longjmp case.
2928//   Since by its nature we may be coming from some other function to get
2929//   here, and we're using the stack frame for the containing function to
2930//   save/restore registers, we can't keep anything live in regs across
2931//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2932//   when we get here from a longjmp(). We force everything out of registers
2933//   except for our own input by listing the relevant registers in Defs. By
2934//   doing so, we also cause the prologue/epilogue code to actively preserve
2935//   all of the callee-saved resgisters, which is exactly what we want.
2936//   $val is a scratch register for our use.
2937let Defs =
2938  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
2939    QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2940  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2941  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2942                               AddrModeNone, 0, NoItinerary, "", "",
2943                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2944                             Requires<[IsThumb2, HasVFP2]>;
2945}
2946
2947let Defs =
2948  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
2949  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2950  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2951                               AddrModeNone, 0, NoItinerary, "", "",
2952                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2953                                  Requires<[IsThumb2, NoVFP]>;
2954}
2955
2956
2957//===----------------------------------------------------------------------===//
2958// Control-Flow Instructions
2959//
2960
2961// FIXME: remove when we have a way to marking a MI with these properties.
2962// FIXME: Should pc be an implicit operand like PICADD, etc?
2963let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2964    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2965def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2966                                                   reglist:$regs, variable_ops),
2967                              4, IIC_iLoad_mBr, [],
2968            (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2969                         RegConstraint<"$Rn = $wb">;
2970
2971let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2972let isPredicable = 1 in
2973def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2974                 "b.w\t$target",
2975                 [(br bb:$target)]> {
2976  let Inst{31-27} = 0b11110;
2977  let Inst{15-14} = 0b10;
2978  let Inst{12} = 1;
2979
2980  bits<20> target;
2981  let Inst{26} = target{19};
2982  let Inst{11} = target{18};
2983  let Inst{13} = target{17};
2984  let Inst{21-16} = target{16-11};
2985  let Inst{10-0} = target{10-0};
2986}
2987
2988let isNotDuplicable = 1, isIndirectBranch = 1 in {
2989def t2BR_JT : t2PseudoInst<(outs),
2990          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2991           0, IIC_Br,
2992          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2993
2994// FIXME: Add a non-pc based case that can be predicated.
2995def t2TBB_JT : t2PseudoInst<(outs),
2996        (ins GPR:$index, i32imm:$jt, i32imm:$id),
2997         0, IIC_Br, []>;
2998
2999def t2TBH_JT : t2PseudoInst<(outs),
3000        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3001         0, IIC_Br, []>;
3002
3003def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3004                    "tbb", "\t[$Rn, $Rm]", []> {
3005  bits<4> Rn;
3006  bits<4> Rm;
3007  let Inst{31-20} = 0b111010001101;
3008  let Inst{19-16} = Rn;
3009  let Inst{15-5} = 0b11110000000;
3010  let Inst{4} = 0; // B form
3011  let Inst{3-0} = Rm;
3012}
3013
3014def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3015                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3016  bits<4> Rn;
3017  bits<4> Rm;
3018  let Inst{31-20} = 0b111010001101;
3019  let Inst{19-16} = Rn;
3020  let Inst{15-5} = 0b11110000000;
3021  let Inst{4} = 1; // H form
3022  let Inst{3-0} = Rm;
3023}
3024} // isNotDuplicable, isIndirectBranch
3025
3026} // isBranch, isTerminator, isBarrier
3027
3028// FIXME: should be able to write a pattern for ARMBrcond, but can't use
3029// a two-value operand where a dag node expects two operands. :(
3030let isBranch = 1, isTerminator = 1 in
3031def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3032                "b", ".w\t$target",
3033                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3034  let Inst{31-27} = 0b11110;
3035  let Inst{15-14} = 0b10;
3036  let Inst{12} = 0;
3037
3038  bits<4> p;
3039  let Inst{25-22} = p;
3040
3041  bits<21> target;
3042  let Inst{26} = target{20};
3043  let Inst{11} = target{19};
3044  let Inst{13} = target{18};
3045  let Inst{21-16} = target{17-12};
3046  let Inst{10-0} = target{11-1};
3047
3048  let DecoderMethod = "DecodeThumb2BCCInstruction";
3049}
3050
3051// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3052// it goes here.
3053let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3054  // Darwin version.
3055  let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3056      Uses = [SP] in
3057  def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3058                   4, IIC_Br, [],
3059                   (t2B uncondbrtarget:$dst)>,
3060                 Requires<[IsThumb2, IsDarwin]>;
3061}
3062
3063// IT block
3064let Defs = [ITSTATE] in
3065def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3066                    AddrModeNone, 2,  IIC_iALUx,
3067                    "it$mask\t$cc", "", []> {
3068  // 16-bit instruction.
3069  let Inst{31-16} = 0x0000;
3070  let Inst{15-8} = 0b10111111;
3071
3072  bits<4> cc;
3073  bits<4> mask;
3074  let Inst{7-4} = cc;
3075  let Inst{3-0} = mask;
3076
3077  let DecoderMethod = "DecodeIT";
3078}
3079
3080// Branch and Exchange Jazelle -- for disassembly only
3081// Rm = Inst{19-16}
3082def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> {
3083  bits<4> func;
3084  let Inst{31-27} = 0b11110;
3085  let Inst{26} = 0;
3086  let Inst{25-20} = 0b111100;
3087  let Inst{19-16} = func;
3088  let Inst{15-0} = 0b1000111100000000;
3089}
3090
3091// Compare and branch on zero / non-zero
3092let isBranch = 1, isTerminator = 1 in {
3093  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3094                  "cbz\t$Rn, $target", []>,
3095              T1Misc<{0,0,?,1,?,?,?}>,
3096              Requires<[IsThumb2]> {
3097    // A8.6.27
3098    bits<6> target;
3099    bits<3> Rn;
3100    let Inst{9}   = target{5};
3101    let Inst{7-3} = target{4-0};
3102    let Inst{2-0} = Rn;
3103  }
3104
3105  def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3106                  "cbnz\t$Rn, $target", []>,
3107              T1Misc<{1,0,?,1,?,?,?}>,
3108              Requires<[IsThumb2]> {
3109    // A8.6.27
3110    bits<6> target;
3111    bits<3> Rn;
3112    let Inst{9}   = target{5};
3113    let Inst{7-3} = target{4-0};
3114    let Inst{2-0} = Rn;
3115  }
3116}
3117
3118
3119// Change Processor State is a system instruction -- for disassembly and
3120// parsing only.
3121// FIXME: Since the asm parser has currently no clean way to handle optional
3122// operands, create 3 versions of the same instruction. Once there's a clean
3123// framework to represent optional operands, change this behavior.
3124class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3125            !strconcat("cps", asm_op),
3126            [/* For disassembly only; pattern left blank */]> {
3127  bits<2> imod;
3128  bits<3> iflags;
3129  bits<5> mode;
3130  bit M;
3131
3132  let Inst{31-27} = 0b11110;
3133  let Inst{26}    = 0;
3134  let Inst{25-20} = 0b111010;
3135  let Inst{19-16} = 0b1111;
3136  let Inst{15-14} = 0b10;
3137  let Inst{12}    = 0;
3138  let Inst{10-9}  = imod;
3139  let Inst{8}     = M;
3140  let Inst{7-5}   = iflags;
3141  let Inst{4-0}   = mode;
3142  let DecoderMethod = "DecodeT2CPSInstruction";
3143}
3144
3145let M = 1 in
3146  def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3147                      "$imod.w\t$iflags, $mode">;
3148let mode = 0, M = 0 in
3149  def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3150                      "$imod.w\t$iflags">;
3151let imod = 0, iflags = 0, M = 1 in
3152  def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3153
3154// A6.3.4 Branches and miscellaneous control
3155// Table A6-14 Change Processor State, and hint instructions
3156// Helper class for disassembly only.
3157class T2I_hint<bits<8> op7_0, string opc, string asm>
3158  : T2I<(outs), (ins), NoItinerary, opc, asm,
3159        [/* For disassembly only; pattern left blank */]> {
3160  let Inst{31-20} = 0xf3a;
3161  let Inst{19-16} = 0b1111;
3162  let Inst{15-14} = 0b10;
3163  let Inst{12} = 0;
3164  let Inst{10-8} = 0b000;
3165  let Inst{7-0} = op7_0;
3166}
3167
3168def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3169def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3170def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3171def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3172def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3173
3174def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3175  bits<4> opt;
3176  let Inst{31-20} = 0b111100111010;
3177  let Inst{19-16} = 0b1111;
3178  let Inst{15-8} = 0b10000000;
3179  let Inst{7-4} = 0b1111;
3180  let Inst{3-0} = opt;
3181}
3182
3183// Secure Monitor Call is a system instruction -- for disassembly only
3184// Option = Inst{19-16}
3185def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3186                [/* For disassembly only; pattern left blank */]> {
3187  let Inst{31-27} = 0b11110;
3188  let Inst{26-20} = 0b1111111;
3189  let Inst{15-12} = 0b1000;
3190
3191  bits<4> opt;
3192  let Inst{19-16} = opt;
3193}
3194
3195class T2SRS<bits<12> op31_20,
3196           dag oops, dag iops, InstrItinClass itin,
3197          string opc, string asm, list<dag> pattern>
3198  : T2I<oops, iops, itin, opc, asm, pattern> {
3199  let Inst{31-20} = op31_20{11-0};
3200
3201  bits<5> mode;
3202  let Inst{4-0} = mode{4-0};
3203}
3204
3205// Store Return State is a system instruction -- for disassembly only
3206def t2SRSDBW : T2SRS<0b111010000010,
3207                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3208                   [/* For disassembly only; pattern left blank */]>;
3209def t2SRSDB  : T2SRS<0b111010000000,
3210                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3211                   [/* For disassembly only; pattern left blank */]>;
3212def t2SRSIAW : T2SRS<0b111010011010,
3213                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3214                   [/* For disassembly only; pattern left blank */]>;
3215def t2SRSIA  : T2SRS<0b111010011000,
3216                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3217                   [/* For disassembly only; pattern left blank */]>;
3218
3219// Return From Exception is a system instruction -- for disassembly only
3220
3221class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3222          string opc, string asm, list<dag> pattern>
3223  : T2I<oops, iops, itin, opc, asm, pattern> {
3224  let Inst{31-20} = op31_20{11-0};
3225
3226  bits<4> Rn;
3227  let Inst{19-16} = Rn;
3228  let Inst{15-0} = 0xc000;
3229}
3230
3231def t2RFEDBW : T2RFE<0b111010000011,
3232                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3233                   [/* For disassembly only; pattern left blank */]>;
3234def t2RFEDB  : T2RFE<0b111010000001,
3235                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3236                   [/* For disassembly only; pattern left blank */]>;
3237def t2RFEIAW : T2RFE<0b111010011011,
3238                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3239                   [/* For disassembly only; pattern left blank */]>;
3240def t2RFEIA  : T2RFE<0b111010011001,
3241                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3242                   [/* For disassembly only; pattern left blank */]>;
3243
3244//===----------------------------------------------------------------------===//
3245// Non-Instruction Patterns
3246//
3247
3248// 32-bit immediate using movw + movt.
3249// This is a single pseudo instruction to make it re-materializable.
3250// FIXME: Remove this when we can do generalized remat.
3251let isReMaterializable = 1, isMoveImm = 1 in
3252def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3253                            [(set rGPR:$dst, (i32 imm:$src))]>,
3254                            Requires<[IsThumb, HasV6T2]>;
3255
3256// Pseudo instruction that combines movw + movt + add pc (if pic).
3257// It also makes it possible to rematerialize the instructions.
3258// FIXME: Remove this when we can do generalized remat and when machine licm
3259// can properly the instructions.
3260let isReMaterializable = 1 in {
3261def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3262                                IIC_iMOVix2addpc,
3263                          [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3264                          Requires<[IsThumb2, UseMovt]>;
3265
3266def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3267                              IIC_iMOVix2,
3268                          [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3269                          Requires<[IsThumb2, UseMovt]>;
3270}
3271
3272// ConstantPool, GlobalAddress, and JumpTable
3273def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3274           Requires<[IsThumb2, DontUseMovt]>;
3275def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3276def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3277           Requires<[IsThumb2, UseMovt]>;
3278
3279def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3280            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3281
3282// Pseudo instruction that combines ldr from constpool and add pc. This should
3283// be expanded into two instructions late to allow if-conversion and
3284// scheduling.
3285let canFoldAsLoad = 1, isReMaterializable = 1 in
3286def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3287                   IIC_iLoadiALU,
3288              [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3289                                           imm:$cp))]>,
3290               Requires<[IsThumb2]>;
3291
3292//===----------------------------------------------------------------------===//
3293// Move between special register and ARM core register -- for disassembly only
3294//
3295
3296class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3297          dag oops, dag iops, InstrItinClass itin,
3298          string opc, string asm, list<dag> pattern>
3299  : T2I<oops, iops, itin, opc, asm, pattern> {
3300  let Inst{31-20} = op31_20{11-0};
3301  let Inst{15-14} = op15_14{1-0};
3302  let Inst{13}    = 0b0;
3303  let Inst{12} = op12{0};
3304  let Inst{7-0}   = 0;
3305}
3306
3307class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3308          dag oops, dag iops, InstrItinClass itin,
3309          string opc, string asm, list<dag> pattern>
3310  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3311  bits<4> Rd;
3312  let Inst{11-8} = Rd;
3313  let Inst{19-16} = 0b1111;
3314}
3315
3316def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3317                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3318                [/* For disassembly only; pattern left blank */]>;
3319def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3320                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3321                   [/* For disassembly only; pattern left blank */]>;
3322
3323// Move from ARM core register to Special Register
3324//
3325// No need to have both system and application versions, the encodings are the
3326// same and the assembly parser has no way to distinguish between them. The mask
3327// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3328// the mask with the fields to be accessed in the special register.
3329def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3330                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3331                         NoItinerary, "msr", "\t$mask, $Rn",
3332                         [/* For disassembly only; pattern left blank */]> {
3333  bits<5> mask;
3334  bits<4> Rn;
3335  let Inst{19-16} = Rn;
3336  let Inst{20}    = mask{4}; // R Bit
3337  let Inst{11-8}  = mask{3-0};
3338}
3339
3340//===----------------------------------------------------------------------===//
3341// Move between coprocessor and ARM core register
3342//
3343
3344class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3345                  list<dag> pattern>
3346  : T2Cop<Op, oops, iops,
3347          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3348          pattern> {
3349  let Inst{27-24} = 0b1110;
3350  let Inst{20} = direction;
3351  let Inst{4} = 1;
3352
3353  bits<4> Rt;
3354  bits<4> cop;
3355  bits<3> opc1;
3356  bits<3> opc2;
3357  bits<4> CRm;
3358  bits<4> CRn;
3359
3360  let Inst{15-12} = Rt;
3361  let Inst{11-8}  = cop;
3362  let Inst{23-21} = opc1;
3363  let Inst{7-5}   = opc2;
3364  let Inst{3-0}   = CRm;
3365  let Inst{19-16} = CRn;
3366}
3367
3368class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3369                   list<dag> pattern = []>
3370  : T2Cop<Op, (outs),
3371          (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3372          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3373  let Inst{27-24} = 0b1100;
3374  let Inst{23-21} = 0b010;
3375  let Inst{20} = direction;
3376
3377  bits<4> Rt;
3378  bits<4> Rt2;
3379  bits<4> cop;
3380  bits<4> opc1;
3381  bits<4> CRm;
3382
3383  let Inst{15-12} = Rt;
3384  let Inst{19-16} = Rt2;
3385  let Inst{11-8}  = cop;
3386  let Inst{7-4}   = opc1;
3387  let Inst{3-0}   = CRm;
3388}
3389
3390/* from ARM core register to coprocessor */
3391def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3392           (outs),
3393           (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3394                c_imm:$CRm, imm0_7:$opc2),
3395           [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3396                         imm:$CRm, imm:$opc2)]>;
3397def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3398             (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3399                          c_imm:$CRm, imm0_7:$opc2),
3400             [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3401                            imm:$CRm, imm:$opc2)]>;
3402
3403/* from coprocessor to ARM core register */
3404def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3405             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3406                                  c_imm:$CRm, imm0_7:$opc2), []>;
3407
3408def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3409             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3410                                  c_imm:$CRm, imm0_7:$opc2), []>;
3411
3412def : T2v6Pat<(int_arm_mrc  imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3413              (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3414
3415def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3416              (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3417
3418
3419/* from ARM core register to coprocessor */
3420def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3421                        [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3422                                       imm:$CRm)]>;
3423def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3424                           [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3425                                           GPR:$Rt2, imm:$CRm)]>;
3426/* from coprocessor to ARM core register */
3427def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3428
3429def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3430
3431//===----------------------------------------------------------------------===//
3432// Other Coprocessor Instructions.
3433//
3434
3435def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3436                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3437                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3438                 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3439                               imm:$CRm, imm:$opc2)]> {
3440  let Inst{27-24} = 0b1110;
3441
3442  bits<4> opc1;
3443  bits<4> CRn;
3444  bits<4> CRd;
3445  bits<4> cop;
3446  bits<3> opc2;
3447  bits<4> CRm;
3448
3449  let Inst{3-0}   = CRm;
3450  let Inst{4}     = 0;
3451  let Inst{7-5}   = opc2;
3452  let Inst{11-8}  = cop;
3453  let Inst{15-12} = CRd;
3454  let Inst{19-16} = CRn;
3455  let Inst{23-20} = opc1;
3456}
3457
3458def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3459                   c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3460                   "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3461                   [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3462                                  imm:$CRm, imm:$opc2)]> {
3463  let Inst{27-24} = 0b1110;
3464
3465  bits<4> opc1;
3466  bits<4> CRn;
3467  bits<4> CRd;
3468  bits<4> cop;
3469  bits<3> opc2;
3470  bits<4> CRm;
3471
3472  let Inst{3-0}   = CRm;
3473  let Inst{4}     = 0;
3474  let Inst{7-5}   = opc2;
3475  let Inst{11-8}  = cop;
3476  let Inst{15-12} = CRd;
3477  let Inst{19-16} = CRn;
3478  let Inst{23-20} = opc1;
3479}
3480
3481
3482
3483//===----------------------------------------------------------------------===//
3484// Non-Instruction Patterns
3485//
3486
3487// SXT/UXT with no rotate
3488let AddedComplexity = 16 in {
3489def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3490           Requires<[IsThumb2]>;
3491def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3492           Requires<[IsThumb2]>;
3493def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3494           Requires<[HasT2ExtractPack, IsThumb2]>;
3495def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3496            (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3497           Requires<[HasT2ExtractPack, IsThumb2]>;
3498def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3499            (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3500           Requires<[HasT2ExtractPack, IsThumb2]>;
3501}
3502
3503def : T2Pat<(sext_inreg rGPR:$Src, i8),  (t2SXTB rGPR:$Src, 0)>,
3504           Requires<[IsThumb2]>;
3505def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3506           Requires<[IsThumb2]>;
3507def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3508            (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3509           Requires<[HasT2ExtractPack, IsThumb2]>;
3510def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3511            (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3512           Requires<[HasT2ExtractPack, IsThumb2]>;
3513
3514// Atomic load/store patterns
3515def : T2Pat<(atomic_load_8   t2addrmode_imm12:$addr),
3516            (t2LDRBi12  t2addrmode_imm12:$addr)>;
3517def : T2Pat<(atomic_load_8   t2addrmode_imm8:$addr),
3518            (t2LDRBi8   t2addrmode_imm8:$addr)>;
3519def : T2Pat<(atomic_load_8   t2addrmode_so_reg:$addr),
3520            (t2LDRBs    t2addrmode_so_reg:$addr)>;
3521def : T2Pat<(atomic_load_16  t2addrmode_imm12:$addr),
3522            (t2LDRHi12  t2addrmode_imm12:$addr)>;
3523def : T2Pat<(atomic_load_16  t2addrmode_imm8:$addr),
3524            (t2LDRHi8   t2addrmode_imm8:$addr)>;
3525def : T2Pat<(atomic_load_16  t2addrmode_so_reg:$addr),
3526            (t2LDRHs    t2addrmode_so_reg:$addr)>;
3527def : T2Pat<(atomic_load_32  t2addrmode_imm12:$addr),
3528            (t2LDRi12   t2addrmode_imm12:$addr)>;
3529def : T2Pat<(atomic_load_32  t2addrmode_imm8:$addr),
3530            (t2LDRi8    t2addrmode_imm8:$addr)>;
3531def : T2Pat<(atomic_load_32  t2addrmode_so_reg:$addr),
3532            (t2LDRs     t2addrmode_so_reg:$addr)>;
3533def : T2Pat<(atomic_store_8  t2addrmode_imm12:$addr, GPR:$val),
3534            (t2STRBi12  GPR:$val, t2addrmode_imm12:$addr)>;
3535def : T2Pat<(atomic_store_8  t2addrmode_imm8:$addr, GPR:$val),
3536            (t2STRBi8   GPR:$val, t2addrmode_imm8:$addr)>;
3537def : T2Pat<(atomic_store_8  t2addrmode_so_reg:$addr, GPR:$val),
3538            (t2STRBs    GPR:$val, t2addrmode_so_reg:$addr)>;
3539def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val),
3540            (t2STRHi12  GPR:$val, t2addrmode_imm12:$addr)>;
3541def : T2Pat<(atomic_store_16 t2addrmode_imm8:$addr, GPR:$val),
3542            (t2STRHi8   GPR:$val, t2addrmode_imm8:$addr)>;
3543def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val),
3544            (t2STRHs    GPR:$val, t2addrmode_so_reg:$addr)>;
3545def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val),
3546            (t2STRi12   GPR:$val, t2addrmode_imm12:$addr)>;
3547def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
3548            (t2STRi8    GPR:$val, t2addrmode_imm8:$addr)>;
3549def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
3550            (t2STRs     GPR:$val, t2addrmode_so_reg:$addr)>;
3551
3552
3553//===----------------------------------------------------------------------===//
3554// Assembler aliases
3555//
3556
3557// Aliases for ADC without the ".w" optional width specifier.
3558def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
3559                  (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3560def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
3561                  (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3562                           pred:$p, cc_out:$s)>;
3563
3564// Aliases for SBC without the ".w" optional width specifier.
3565def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
3566                  (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3567def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
3568                  (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
3569                           pred:$p, cc_out:$s)>;
3570
3571// Aliases for ADD without the ".w" optional width specifier.
3572def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
3573           (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
3574def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
3575           (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
3576def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
3577                 (t2ADDrr rGPR:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
3578def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
3579                  (t2ADDrs rGPR:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
3580                           pred:$p, cc_out:$s)>;
3581
3582// Alias for compares without the ".w" optional width specifier.
3583def : t2InstAlias<"cmn${p} $Rn, $Rm",
3584                  (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3585def : t2InstAlias<"teq${p} $Rn, $Rm",
3586                  (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3587def : t2InstAlias<"tst${p} $Rn, $Rm",
3588                  (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>;
3589
3590// Memory barriers
3591def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>;
3592def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>;
3593def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>;
3594