ARMInstrThumb2.td revision fed76ffa569444596b4e15e2681298c8d7b6be83
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printMandatoryPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant 53// bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72// Break t2_so_imm's up into two pieces. This handles immediates with up to 16 73// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12] 74// to get the first/second pieces. 75def t2_so_imm2part : Operand<i32>, 76 PatLeaf<(imm), [{ 77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue()); 78 }]> { 79} 80 81def t2_so_imm2part_1 : SDNodeXForm<imm, [{ 82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue()); 83 return CurDAG->getTargetConstant(V, MVT::i32); 84}]>; 85 86def t2_so_imm2part_2 : SDNodeXForm<imm, [{ 87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue()); 88 return CurDAG->getTargetConstant(V, MVT::i32); 89}]>; 90 91def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ 92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue()); 93 }]> { 94} 95 96def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{ 97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue()); 98 return CurDAG->getTargetConstant(V, MVT::i32); 99}]>; 100 101def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{ 102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue()); 103 return CurDAG->getTargetConstant(V, MVT::i32); 104}]>; 105 106/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 107def imm1_31 : PatLeaf<(i32 imm), [{ 108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 109}]>; 110 111/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 112def imm0_4095 : Operand<i32>, 113 PatLeaf<(i32 imm), [{ 114 return (uint32_t)N->getZExtValue() < 4096; 115}]>; 116 117def imm0_4095_neg : PatLeaf<(i32 imm), [{ 118 return (uint32_t)(-N->getZExtValue()) < 4096; 119}], imm_neg_XFORM>; 120 121def imm0_255_neg : PatLeaf<(i32 imm), [{ 122 return (uint32_t)(-N->getZExtValue()) < 255; 123}], imm_neg_XFORM>; 124 125// Define Thumb2 specific addressing modes. 126 127// t2addrmode_imm12 := reg + imm12 128def t2addrmode_imm12 : Operand<i32>, 129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 130 let PrintMethod = "printT2AddrModeImm12Operand"; 131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 132} 133 134// t2addrmode_imm8 := reg +/- imm8 135def t2addrmode_imm8 : Operand<i32>, 136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 137 let PrintMethod = "printT2AddrModeImm8Operand"; 138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 139} 140 141def t2am_imm8_offset : Operand<i32>, 142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 143 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 144} 145 146// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 147def t2addrmode_imm8s4 : Operand<i32>, 148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 149 let PrintMethod = "printT2AddrModeImm8s4Operand"; 150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 151} 152 153def t2am_imm8s4_offset : Operand<i32> { 154 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 155} 156 157// t2addrmode_so_reg := reg + (reg << imm2) 158def t2addrmode_so_reg : Operand<i32>, 159 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 160 let PrintMethod = "printT2AddrModeSoRegOperand"; 161 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 162} 163 164 165//===----------------------------------------------------------------------===// 166// Multiclass helpers... 167// 168 169/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 170/// unary operation that produces a value. These are predicable and can be 171/// changed to modify CPSR. 172multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode, 173 bit Cheap = 0, bit ReMat = 0> { 174 // shifted imm 175 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 176 opc, "\t$dst, $src", 177 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 178 let isAsCheapAsAMove = Cheap; 179 let isReMaterializable = ReMat; 180 let Inst{31-27} = 0b11110; 181 let Inst{25} = 0; 182 let Inst{24-21} = opcod; 183 let Inst{20} = ?; // The S bit. 184 let Inst{19-16} = 0b1111; // Rn 185 let Inst{15} = 0; 186 } 187 // register 188 def r : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 189 opc, ".w\t$dst, $src", 190 [(set GPR:$dst, (opnode GPR:$src))]> { 191 let Inst{31-27} = 0b11101; 192 let Inst{26-25} = 0b01; 193 let Inst{24-21} = opcod; 194 let Inst{20} = ?; // The S bit. 195 let Inst{19-16} = 0b1111; // Rn 196 let Inst{14-12} = 0b000; // imm3 197 let Inst{7-6} = 0b00; // imm2 198 let Inst{5-4} = 0b00; // type 199 } 200 // shifted register 201 def s : T2sI<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, 202 opc, ".w\t$dst, $src", 203 [(set GPR:$dst, (opnode t2_so_reg:$src))]> { 204 let Inst{31-27} = 0b11101; 205 let Inst{26-25} = 0b01; 206 let Inst{24-21} = opcod; 207 let Inst{20} = ?; // The S bit. 208 let Inst{19-16} = 0b1111; // Rn 209 } 210} 211 212/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 213/// binary operation that produces a value. These are predicable and can be 214/// changed to modify CPSR. 215multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode, 216 bit Commutable = 0, string wide =""> { 217 // shifted imm 218 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 219 opc, "\t$dst, $lhs, $rhs", 220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 221 let Inst{31-27} = 0b11110; 222 let Inst{25} = 0; 223 let Inst{24-21} = opcod; 224 let Inst{20} = ?; // The S bit. 225 let Inst{15} = 0; 226 } 227 // register 228 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 229 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 230 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 231 let isCommutable = Commutable; 232 let Inst{31-27} = 0b11101; 233 let Inst{26-25} = 0b01; 234 let Inst{24-21} = opcod; 235 let Inst{20} = ?; // The S bit. 236 let Inst{14-12} = 0b000; // imm3 237 let Inst{7-6} = 0b00; // imm2 238 let Inst{5-4} = 0b00; // type 239 } 240 // shifted register 241 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 242 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 243 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 244 let Inst{31-27} = 0b11101; 245 let Inst{26-25} = 0b01; 246 let Inst{24-21} = opcod; 247 let Inst{20} = ?; // The S bit. 248 } 249} 250 251/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 252// the ".w" prefix to indicate that they are wide. 253multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode, 254 bit Commutable = 0> : 255 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">; 256 257/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 258/// reversed. It doesn't define the 'rr' form since it's handled by its 259/// T2I_bin_irs counterpart. 260multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> { 261 // shifted imm 262 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 263 opc, ".w\t$dst, $rhs, $lhs", 264 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> { 265 let Inst{31-27} = 0b11110; 266 let Inst{25} = 0; 267 let Inst{24-21} = opcod; 268 let Inst{20} = ?; // The S bit. 269 let Inst{15} = 0; 270 } 271 // shifted register 272 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 273 opc, "\t$dst, $rhs, $lhs", 274 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> { 275 let Inst{31-27} = 0b11101; 276 let Inst{26-25} = 0b01; 277 let Inst{24-21} = opcod; 278 let Inst{20} = ?; // The S bit. 279 } 280} 281 282/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 283/// instruction modifies the CPSR register. 284let Defs = [CPSR] in { 285multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode, 286 bit Commutable = 0> { 287 // shifted imm 288 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 289 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 291 let Inst{31-27} = 0b11110; 292 let Inst{25} = 0; 293 let Inst{24-21} = opcod; 294 let Inst{20} = 1; // The S bit. 295 let Inst{15} = 0; 296 } 297 // register 298 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 299 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 300 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 301 let isCommutable = Commutable; 302 let Inst{31-27} = 0b11101; 303 let Inst{26-25} = 0b01; 304 let Inst{24-21} = opcod; 305 let Inst{20} = 1; // The S bit. 306 let Inst{14-12} = 0b000; // imm3 307 let Inst{7-6} = 0b00; // imm2 308 let Inst{5-4} = 0b00; // type 309 } 310 // shifted register 311 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 312 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 313 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 314 let Inst{31-27} = 0b11101; 315 let Inst{26-25} = 0b01; 316 let Inst{24-21} = opcod; 317 let Inst{20} = 1; // The S bit. 318 } 319} 320} 321 322/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 323/// patterns for a binary operation that produces a value. 324multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 325 bit Commutable = 0> { 326 // shifted imm 327 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 328 opc, ".w\t$dst, $lhs, $rhs", 329 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 330 let Inst{31-27} = 0b11110; 331 let Inst{25} = 0; 332 let Inst{24} = 1; 333 let Inst{23-21} = op23_21; 334 let Inst{20} = 0; // The S bit. 335 let Inst{15} = 0; 336 } 337 // 12-bit imm 338 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, 339 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", 340 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { 341 let Inst{31-27} = 0b11110; 342 let Inst{25} = 1; 343 let Inst{24} = 0; 344 let Inst{23-21} = op23_21; 345 let Inst{20} = 0; // The S bit. 346 let Inst{15} = 0; 347 } 348 // register 349 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 350 opc, ".w\t$dst, $lhs, $rhs", 351 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 352 let isCommutable = Commutable; 353 let Inst{31-27} = 0b11101; 354 let Inst{26-25} = 0b01; 355 let Inst{24} = 1; 356 let Inst{23-21} = op23_21; 357 let Inst{20} = 0; // The S bit. 358 let Inst{14-12} = 0b000; // imm3 359 let Inst{7-6} = 0b00; // imm2 360 let Inst{5-4} = 0b00; // type 361 } 362 // shifted register 363 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 364 opc, ".w\t$dst, $lhs, $rhs", 365 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 366 let Inst{31-27} = 0b11101; 367 let Inst{26-25} = 0b01; 368 let Inst{24} = 1; 369 let Inst{23-21} = op23_21; 370 let Inst{20} = 0; // The S bit. 371 } 372} 373 374/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 375/// for a binary operation that produces a value and use the carry 376/// bit. It's not predicable. 377let Uses = [CPSR] in { 378multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 379 bit Commutable = 0> { 380 // shifted imm 381 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 382 opc, "\t$dst, $lhs, $rhs", 383 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 384 Requires<[IsThumb2]> { 385 let Inst{31-27} = 0b11110; 386 let Inst{25} = 0; 387 let Inst{24-21} = opcod; 388 let Inst{20} = 0; // The S bit. 389 let Inst{15} = 0; 390 } 391 // register 392 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 393 opc, ".w\t$dst, $lhs, $rhs", 394 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 395 Requires<[IsThumb2]> { 396 let isCommutable = Commutable; 397 let Inst{31-27} = 0b11101; 398 let Inst{26-25} = 0b01; 399 let Inst{24-21} = opcod; 400 let Inst{20} = 0; // The S bit. 401 let Inst{14-12} = 0b000; // imm3 402 let Inst{7-6} = 0b00; // imm2 403 let Inst{5-4} = 0b00; // type 404 } 405 // shifted register 406 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 407 opc, ".w\t$dst, $lhs, $rhs", 408 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 409 Requires<[IsThumb2]> { 410 let Inst{31-27} = 0b11101; 411 let Inst{26-25} = 0b01; 412 let Inst{24-21} = opcod; 413 let Inst{20} = 0; // The S bit. 414 } 415} 416 417// Carry setting variants 418let Defs = [CPSR] in { 419multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, 420 bit Commutable = 0> { 421 // shifted imm 422 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 423 opc, "\t$dst, $lhs, $rhs", 424 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 425 Requires<[IsThumb2]> { 426 let Inst{31-27} = 0b11110; 427 let Inst{25} = 0; 428 let Inst{24-21} = opcod; 429 let Inst{20} = 1; // The S bit. 430 let Inst{15} = 0; 431 } 432 // register 433 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 434 opc, ".w\t$dst, $lhs, $rhs", 435 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 436 Requires<[IsThumb2]> { 437 let isCommutable = Commutable; 438 let Inst{31-27} = 0b11101; 439 let Inst{26-25} = 0b01; 440 let Inst{24-21} = opcod; 441 let Inst{20} = 1; // The S bit. 442 let Inst{14-12} = 0b000; // imm3 443 let Inst{7-6} = 0b00; // imm2 444 let Inst{5-4} = 0b00; // type 445 } 446 // shifted register 447 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 448 opc, ".w\t$dst, $lhs, $rhs", 449 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 450 Requires<[IsThumb2]> { 451 let Inst{31-27} = 0b11101; 452 let Inst{26-25} = 0b01; 453 let Inst{24-21} = opcod; 454 let Inst{20} = 1; // The S bit. 455 } 456} 457} 458} 459 460/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 461let Defs = [CPSR] in { 462multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { 463 // shifted imm 464 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 465 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs", 466 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> { 467 let Inst{31-27} = 0b11110; 468 let Inst{25} = 0; 469 let Inst{24-21} = opcod; 470 let Inst{20} = 1; // The S bit. 471 let Inst{15} = 0; 472 } 473 // shifted register 474 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 475 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs", 476 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> { 477 let Inst{31-27} = 0b11101; 478 let Inst{26-25} = 0b01; 479 let Inst{24-21} = opcod; 480 let Inst{20} = 1; // The S bit. 481 } 482} 483} 484 485/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 486// rotate operation that produces a value. 487multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> { 488 // 5-bit imm 489 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 490 opc, ".w\t$dst, $lhs, $rhs", 491 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> { 492 let Inst{31-27} = 0b11101; 493 let Inst{26-21} = 0b010010; 494 let Inst{19-16} = 0b1111; // Rn 495 let Inst{5-4} = opcod; 496 } 497 // register 498 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr, 499 opc, ".w\t$dst, $lhs, $rhs", 500 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 501 let Inst{31-27} = 0b11111; 502 let Inst{26-23} = 0b0100; 503 let Inst{22-21} = opcod; 504 let Inst{15-12} = 0b1111; 505 let Inst{7-4} = 0b0000; 506 } 507} 508 509/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 510/// patterns. Similar to T2I_bin_irs except the instruction does not produce 511/// a explicit result, only implicitly set CPSR. 512let Defs = [CPSR] in { 513multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> { 514 // shifted imm 515 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi, 516 opc, ".w\t$lhs, $rhs", 517 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> { 518 let Inst{31-27} = 0b11110; 519 let Inst{25} = 0; 520 let Inst{24-21} = opcod; 521 let Inst{20} = 1; // The S bit. 522 let Inst{15} = 0; 523 let Inst{11-8} = 0b1111; // Rd 524 } 525 // register 526 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 527 opc, ".w\t$lhs, $rhs", 528 [(opnode GPR:$lhs, GPR:$rhs)]> { 529 let Inst{31-27} = 0b11101; 530 let Inst{26-25} = 0b01; 531 let Inst{24-21} = opcod; 532 let Inst{20} = 1; // The S bit. 533 let Inst{14-12} = 0b000; // imm3 534 let Inst{11-8} = 0b1111; // Rd 535 let Inst{7-6} = 0b00; // imm2 536 let Inst{5-4} = 0b00; // type 537 } 538 // shifted register 539 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi, 540 opc, ".w\t$lhs, $rhs", 541 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> { 542 let Inst{31-27} = 0b11101; 543 let Inst{26-25} = 0b01; 544 let Inst{24-21} = opcod; 545 let Inst{20} = 1; // The S bit. 546 let Inst{11-8} = 0b1111; // Rd 547 } 548} 549} 550 551/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 552multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> { 553 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi, 554 opc, ".w\t$dst, $addr", 555 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> { 556 let Inst{31-27} = 0b11111; 557 let Inst{26-25} = 0b00; 558 let Inst{24} = signed; 559 let Inst{23} = 1; 560 let Inst{22-21} = opcod; 561 let Inst{20} = 1; // load 562 } 563 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, 564 opc, "\t$dst, $addr", 565 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> { 566 let Inst{31-27} = 0b11111; 567 let Inst{26-25} = 0b00; 568 let Inst{24} = signed; 569 let Inst{23} = 0; 570 let Inst{22-21} = opcod; 571 let Inst{20} = 1; // load 572 let Inst{11} = 1; 573 // Offset: index==TRUE, wback==FALSE 574 let Inst{10} = 1; // The P bit. 575 let Inst{8} = 0; // The W bit. 576 } 577 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr, 578 opc, ".w\t$dst, $addr", 579 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> { 580 let Inst{31-27} = 0b11111; 581 let Inst{26-25} = 0b00; 582 let Inst{24} = signed; 583 let Inst{23} = 0; 584 let Inst{22-21} = opcod; 585 let Inst{20} = 1; // load 586 let Inst{11-6} = 0b000000; 587 } 588 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 589 opc, ".w\t$dst, $addr", 590 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> { 591 let isReMaterializable = 1; 592 let Inst{31-27} = 0b11111; 593 let Inst{26-25} = 0b00; 594 let Inst{24} = signed; 595 let Inst{23} = ?; // add = (U == '1') 596 let Inst{22-21} = opcod; 597 let Inst{20} = 1; // load 598 let Inst{19-16} = 0b1111; // Rn 599 } 600} 601 602/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 603multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> { 604 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei, 605 opc, ".w\t$src, $addr", 606 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> { 607 let Inst{31-27} = 0b11111; 608 let Inst{26-23} = 0b0001; 609 let Inst{22-21} = opcod; 610 let Inst{20} = 0; // !load 611 } 612 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei, 613 opc, "\t$src, $addr", 614 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> { 615 let Inst{31-27} = 0b11111; 616 let Inst{26-23} = 0b0000; 617 let Inst{22-21} = opcod; 618 let Inst{20} = 0; // !load 619 let Inst{11} = 1; 620 // Offset: index==TRUE, wback==FALSE 621 let Inst{10} = 1; // The P bit. 622 let Inst{8} = 0; // The W bit. 623 } 624 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer, 625 opc, ".w\t$src, $addr", 626 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> { 627 let Inst{31-27} = 0b11111; 628 let Inst{26-23} = 0b0000; 629 let Inst{22-21} = opcod; 630 let Inst{20} = 0; // !load 631 let Inst{11-6} = 0b000000; 632 } 633} 634 635/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 636/// register and one whose operand is a register rotated by 8/16/24. 637multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> { 638 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 639 opc, ".w\t$dst, $src", 640 [(set GPR:$dst, (opnode GPR:$src))]> { 641 let Inst{31-27} = 0b11111; 642 let Inst{26-23} = 0b0100; 643 let Inst{22-20} = opcod; 644 let Inst{19-16} = 0b1111; // Rn 645 let Inst{15-12} = 0b1111; 646 let Inst{7} = 1; 647 let Inst{5-4} = 0b00; // rotate 648 } 649 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 650 opc, ".w\t$dst, $src, ror $rot", 651 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]> { 652 let Inst{31-27} = 0b11111; 653 let Inst{26-23} = 0b0100; 654 let Inst{22-20} = opcod; 655 let Inst{19-16} = 0b1111; // Rn 656 let Inst{15-12} = 0b1111; 657 let Inst{7} = 1; 658 let Inst{5-4} = {?,?}; // rotate 659 } 660} 661 662// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 663multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> { 664 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 665 opc, "\t$dst, $src", 666 [(set GPR:$dst, (opnode GPR:$src))]>, 667 Requires<[HasT2ExtractPack]> { 668 let Inst{31-27} = 0b11111; 669 let Inst{26-23} = 0b0100; 670 let Inst{22-20} = opcod; 671 let Inst{19-16} = 0b1111; // Rn 672 let Inst{15-12} = 0b1111; 673 let Inst{7} = 1; 674 let Inst{5-4} = 0b00; // rotate 675 } 676 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 677 opc, "\t$dst, $src, ror $rot", 678 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, 679 Requires<[HasT2ExtractPack]> { 680 let Inst{31-27} = 0b11111; 681 let Inst{26-23} = 0b0100; 682 let Inst{22-20} = opcod; 683 let Inst{19-16} = 0b1111; // Rn 684 let Inst{15-12} = 0b1111; 685 let Inst{7} = 1; 686 let Inst{5-4} = {?,?}; // rotate 687 } 688} 689 690// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 691// supported yet. 692multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> { 693 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 694 opc, "\t$dst, $src", []> { 695 let Inst{31-27} = 0b11111; 696 let Inst{26-23} = 0b0100; 697 let Inst{22-20} = opcod; 698 let Inst{19-16} = 0b1111; // Rn 699 let Inst{15-12} = 0b1111; 700 let Inst{7} = 1; 701 let Inst{5-4} = 0b00; // rotate 702 } 703 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 704 opc, "\t$dst, $src, ror $rot", []> { 705 let Inst{31-27} = 0b11111; 706 let Inst{26-23} = 0b0100; 707 let Inst{22-20} = opcod; 708 let Inst{19-16} = 0b1111; // Rn 709 let Inst{15-12} = 0b1111; 710 let Inst{7} = 1; 711 let Inst{5-4} = {?,?}; // rotate 712 } 713} 714 715/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 716/// register and one whose operand is a register rotated by 8/16/24. 717multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> { 718 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 719 opc, "\t$dst, $LHS, $RHS", 720 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 721 Requires<[HasT2ExtractPack]> { 722 let Inst{31-27} = 0b11111; 723 let Inst{26-23} = 0b0100; 724 let Inst{22-20} = opcod; 725 let Inst{15-12} = 0b1111; 726 let Inst{7} = 1; 727 let Inst{5-4} = 0b00; // rotate 728 } 729 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 730 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", 731 [(set GPR:$dst, (opnode GPR:$LHS, 732 (rotr GPR:$RHS, rot_imm:$rot)))]>, 733 Requires<[HasT2ExtractPack]> { 734 let Inst{31-27} = 0b11111; 735 let Inst{26-23} = 0b0100; 736 let Inst{22-20} = opcod; 737 let Inst{15-12} = 0b1111; 738 let Inst{7} = 1; 739 let Inst{5-4} = {?,?}; // rotate 740 } 741} 742 743// DO variant - disassembly only, no pattern 744 745multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> { 746 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 747 opc, "\t$dst, $LHS, $RHS", []> { 748 let Inst{31-27} = 0b11111; 749 let Inst{26-23} = 0b0100; 750 let Inst{22-20} = opcod; 751 let Inst{15-12} = 0b1111; 752 let Inst{7} = 1; 753 let Inst{5-4} = 0b00; // rotate 754 } 755 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 756 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> { 757 let Inst{31-27} = 0b11111; 758 let Inst{26-23} = 0b0100; 759 let Inst{22-20} = opcod; 760 let Inst{15-12} = 0b1111; 761 let Inst{7} = 1; 762 let Inst{5-4} = {?,?}; // rotate 763 } 764} 765 766//===----------------------------------------------------------------------===// 767// Instructions 768//===----------------------------------------------------------------------===// 769 770//===----------------------------------------------------------------------===// 771// Miscellaneous Instructions. 772// 773 774// LEApcrel - Load a pc-relative address into a register without offending the 775// assembler. 776let neverHasSideEffects = 1 in { 777let isReMaterializable = 1 in 778def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 779 "adr$p.w\t$dst, #$label", []> { 780 let Inst{31-27} = 0b11110; 781 let Inst{25-24} = 0b10; 782 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 783 let Inst{22} = 0; 784 let Inst{20} = 0; 785 let Inst{19-16} = 0b1111; // Rn 786 let Inst{15} = 0; 787} 788} // neverHasSideEffects 789def t2LEApcrelJT : T2XI<(outs GPR:$dst), 790 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, 791 "adr$p.w\t$dst, #${label}_${id}", []> { 792 let Inst{31-27} = 0b11110; 793 let Inst{25-24} = 0b10; 794 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 795 let Inst{22} = 0; 796 let Inst{20} = 0; 797 let Inst{19-16} = 0b1111; // Rn 798 let Inst{15} = 0; 799} 800 801// ADD r, sp, {so_imm|i12} 802def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 803 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> { 804 let Inst{31-27} = 0b11110; 805 let Inst{25} = 0; 806 let Inst{24-21} = 0b1000; 807 let Inst{20} = ?; // The S bit. 808 let Inst{19-16} = 0b1101; // Rn = sp 809 let Inst{15} = 0; 810} 811def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 812 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> { 813 let Inst{31-27} = 0b11110; 814 let Inst{25} = 1; 815 let Inst{24-21} = 0b0000; 816 let Inst{20} = 0; // The S bit. 817 let Inst{19-16} = 0b1101; // Rn = sp 818 let Inst{15} = 0; 819} 820 821// ADD r, sp, so_reg 822def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 823 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> { 824 let Inst{31-27} = 0b11101; 825 let Inst{26-25} = 0b01; 826 let Inst{24-21} = 0b1000; 827 let Inst{20} = ?; // The S bit. 828 let Inst{19-16} = 0b1101; // Rn = sp 829 let Inst{15} = 0; 830} 831 832// SUB r, sp, {so_imm|i12} 833def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 834 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> { 835 let Inst{31-27} = 0b11110; 836 let Inst{25} = 0; 837 let Inst{24-21} = 0b1101; 838 let Inst{20} = ?; // The S bit. 839 let Inst{19-16} = 0b1101; // Rn = sp 840 let Inst{15} = 0; 841} 842def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 843 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> { 844 let Inst{31-27} = 0b11110; 845 let Inst{25} = 1; 846 let Inst{24-21} = 0b0101; 847 let Inst{20} = 0; // The S bit. 848 let Inst{19-16} = 0b1101; // Rn = sp 849 let Inst{15} = 0; 850} 851 852// SUB r, sp, so_reg 853def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 854 IIC_iALUsi, 855 "sub", "\t$dst, $sp, $rhs", []> { 856 let Inst{31-27} = 0b11101; 857 let Inst{26-25} = 0b01; 858 let Inst{24-21} = 0b1101; 859 let Inst{20} = ?; // The S bit. 860 let Inst{19-16} = 0b1101; // Rn = sp 861 let Inst{15} = 0; 862} 863 864// Signed and unsigned division on v7-M 865def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, 866 "sdiv", "\t$dst, $a, $b", 867 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>, 868 Requires<[HasDivide]> { 869 let Inst{31-27} = 0b11111; 870 let Inst{26-21} = 0b011100; 871 let Inst{20} = 0b1; 872 let Inst{15-12} = 0b1111; 873 let Inst{7-4} = 0b1111; 874} 875 876def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, 877 "udiv", "\t$dst, $a, $b", 878 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>, 879 Requires<[HasDivide]> { 880 let Inst{31-27} = 0b11111; 881 let Inst{26-21} = 0b011101; 882 let Inst{20} = 0b1; 883 let Inst{15-12} = 0b1111; 884 let Inst{7-4} = 0b1111; 885} 886 887// Pseudo instruction that will expand into a t2SUBrSPi + a copy. 888let usesCustomInserter = 1 in { // Expanded after instruction selection. 889def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 890 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>; 891def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 892 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>; 893def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 894 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>; 895} // usesCustomInserter 896 897 898//===----------------------------------------------------------------------===// 899// Load / store Instructions. 900// 901 902// Load 903let canFoldAsLoad = 1, isReMaterializable = 1 in 904defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>; 905 906// Loads with zero extension 907defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 908defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 909 910// Loads with sign extension 911defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 912defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 913 914let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 915// Load doubleword 916def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2), 917 (ins t2addrmode_imm8s4:$addr), 918 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>; 919def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2), 920 (ins i32imm:$addr), IIC_iLoadi, 921 "ldrd", "\t$dst1, $addr", []> { 922 let Inst{19-16} = 0b1111; // Rn 923} 924} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 925 926// zextload i1 -> zextload i8 927def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 928 (t2LDRBi12 t2addrmode_imm12:$addr)>; 929def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 930 (t2LDRBi8 t2addrmode_imm8:$addr)>; 931def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 932 (t2LDRBs t2addrmode_so_reg:$addr)>; 933def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 934 (t2LDRBpci tconstpool:$addr)>; 935 936// extload -> zextload 937// FIXME: Reduce the number of patterns by legalizing extload to zextload 938// earlier? 939def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 940 (t2LDRBi12 t2addrmode_imm12:$addr)>; 941def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 942 (t2LDRBi8 t2addrmode_imm8:$addr)>; 943def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 944 (t2LDRBs t2addrmode_so_reg:$addr)>; 945def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 946 (t2LDRBpci tconstpool:$addr)>; 947 948def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 949 (t2LDRBi12 t2addrmode_imm12:$addr)>; 950def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 951 (t2LDRBi8 t2addrmode_imm8:$addr)>; 952def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 953 (t2LDRBs t2addrmode_so_reg:$addr)>; 954def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 955 (t2LDRBpci tconstpool:$addr)>; 956 957def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 958 (t2LDRHi12 t2addrmode_imm12:$addr)>; 959def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 960 (t2LDRHi8 t2addrmode_imm8:$addr)>; 961def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 962 (t2LDRHs t2addrmode_so_reg:$addr)>; 963def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 964 (t2LDRHpci tconstpool:$addr)>; 965 966// Indexed loads 967let mayLoad = 1, neverHasSideEffects = 1 in { 968def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb), 969 (ins t2addrmode_imm8:$addr), 970 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 971 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", 972 []>; 973 974def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb), 975 (ins GPR:$base, t2am_imm8_offset:$offset), 976 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 977 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", 978 []>; 979 980def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 981 (ins t2addrmode_imm8:$addr), 982 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 983 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", 984 []>; 985def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 986 (ins GPR:$base, t2am_imm8_offset:$offset), 987 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 988 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", 989 []>; 990 991def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 992 (ins t2addrmode_imm8:$addr), 993 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 994 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", 995 []>; 996def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 997 (ins GPR:$base, t2am_imm8_offset:$offset), 998 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 999 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", 1000 []>; 1001 1002def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1003 (ins t2addrmode_imm8:$addr), 1004 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1005 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", 1006 []>; 1007def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1008 (ins GPR:$base, t2am_imm8_offset:$offset), 1009 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1010 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", 1011 []>; 1012 1013def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1014 (ins t2addrmode_imm8:$addr), 1015 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1016 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", 1017 []>; 1018def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1019 (ins GPR:$base, t2am_imm8_offset:$offset), 1020 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1021 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", 1022 []>; 1023} // mayLoad = 1, neverHasSideEffects = 1 1024 1025// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are 1026// for disassembly only. 1027// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1028class T2IldT<bit signed, bits<2> type, string opc> 1029 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc, 1030 "\t$dst, $addr", []> { 1031 let Inst{31-27} = 0b11111; 1032 let Inst{26-25} = 0b00; 1033 let Inst{24} = signed; 1034 let Inst{23} = 0; 1035 let Inst{22-21} = type; 1036 let Inst{20} = 1; // load 1037 let Inst{11} = 1; 1038 let Inst{10-8} = 0b110; // PUW. 1039} 1040 1041def t2LDRT : T2IldT<0, 0b10, "ldrt">; 1042def t2LDRBT : T2IldT<0, 0b00, "ldrbt">; 1043def t2LDRHT : T2IldT<0, 0b01, "ldrht">; 1044def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">; 1045def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">; 1046 1047// Store 1048defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 1049defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1050defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1051 1052// Store doubleword 1053let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1054def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1055 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), 1056 IIC_iStorer, "strd", "\t$src1, $addr", []>; 1057 1058// Indexed stores 1059def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb), 1060 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1061 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1062 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 1063 [(set GPR:$base_wb, 1064 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1065 1066def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb), 1067 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1068 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1069 "str", "\t$src, [$base], $offset", "$base = $base_wb", 1070 [(set GPR:$base_wb, 1071 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1072 1073def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb), 1074 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1075 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1076 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 1077 [(set GPR:$base_wb, 1078 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1079 1080def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb), 1081 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1082 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1083 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 1084 [(set GPR:$base_wb, 1085 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1086 1087def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb), 1088 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1089 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1090 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 1091 [(set GPR:$base_wb, 1092 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1093 1094def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb), 1095 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1096 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1097 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 1098 [(set GPR:$base_wb, 1099 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1100 1101// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1102// only. 1103// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1104class T2IstT<bits<2> type, string opc> 1105 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc, 1106 "\t$src, $addr", []> { 1107 let Inst{31-27} = 0b11111; 1108 let Inst{26-25} = 0b00; 1109 let Inst{24} = 0; // not signed 1110 let Inst{23} = 0; 1111 let Inst{22-21} = type; 1112 let Inst{20} = 0; // store 1113 let Inst{11} = 1; 1114 let Inst{10-8} = 0b110; // PUW 1115} 1116 1117def t2STRT : T2IstT<0b10, "strt">; 1118def t2STRBT : T2IstT<0b00, "strbt">; 1119def t2STRHT : T2IstT<0b01, "strht">; 1120 1121// ldrd / strd pre / post variants 1122// For disassembly only. 1123 1124def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1125 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1126 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>; 1127 1128def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1129 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1130 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>; 1131 1132def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs), 1133 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1134 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>; 1135 1136def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs), 1137 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1138 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>; 1139 1140// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1141// data/instruction access. These are for disassembly only. 1142// 1143// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 1144// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 1145multiclass T2Ipl<bit instr, bit write, string opc> { 1146 1147 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc, 1148 "\t[$base, $imm]", []> { 1149 let Inst{31-25} = 0b1111100; 1150 let Inst{24} = instr; 1151 let Inst{23} = 1; // U = 1 1152 let Inst{22} = 0; 1153 let Inst{21} = write; 1154 let Inst{20} = 1; 1155 let Inst{15-12} = 0b1111; 1156 } 1157 1158 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1159 "\t[$base, $imm]", []> { 1160 let Inst{31-25} = 0b1111100; 1161 let Inst{24} = instr; 1162 let Inst{23} = 0; // U = 0 1163 let Inst{22} = 0; 1164 let Inst{21} = write; 1165 let Inst{20} = 1; 1166 let Inst{15-12} = 0b1111; 1167 let Inst{11-8} = 0b1100; 1168 } 1169 1170 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1171 "\t[pc, $imm]", []> { 1172 let Inst{31-25} = 0b1111100; 1173 let Inst{24} = instr; 1174 let Inst{23} = ?; // add = (U == 1) 1175 let Inst{22} = 0; 1176 let Inst{21} = write; 1177 let Inst{20} = 1; 1178 let Inst{19-16} = 0b1111; // Rn = 0b1111 1179 let Inst{15-12} = 0b1111; 1180 } 1181 1182 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc, 1183 "\t[$base, $a]", []> { 1184 let Inst{31-25} = 0b1111100; 1185 let Inst{24} = instr; 1186 let Inst{23} = 0; // add = TRUE for T1 1187 let Inst{22} = 0; 1188 let Inst{21} = write; 1189 let Inst{20} = 1; 1190 let Inst{15-12} = 0b1111; 1191 let Inst{11-6} = 0000000; 1192 let Inst{5-4} = 0b00; // no shift is applied 1193 } 1194 1195 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc, 1196 "\t[$base, $a, lsl $shamt]", []> { 1197 let Inst{31-25} = 0b1111100; 1198 let Inst{24} = instr; 1199 let Inst{23} = 0; // add = TRUE for T1 1200 let Inst{22} = 0; 1201 let Inst{21} = write; 1202 let Inst{20} = 1; 1203 let Inst{15-12} = 0b1111; 1204 let Inst{11-6} = 0000000; 1205 } 1206} 1207 1208defm t2PLD : T2Ipl<0, 0, "pld">; 1209defm t2PLDW : T2Ipl<0, 1, "pldw">; 1210defm t2PLI : T2Ipl<1, 0, "pli">; 1211 1212//===----------------------------------------------------------------------===// 1213// Load / store multiple Instructions. 1214// 1215 1216let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1217def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1218 reglist:$dsts, variable_ops), IIC_iLoadm, 1219 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { 1220 let Inst{31-27} = 0b11101; 1221 let Inst{26-25} = 0b00; 1222 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1223 let Inst{22} = 0; 1224 let Inst{21} = 0; // The W bit. 1225 let Inst{20} = 1; // Load 1226} 1227 1228def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1229 reglist:$dsts, variable_ops), IIC_iLoadm, 1230 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", 1231 "$addr.addr = $wb", []> { 1232 let Inst{31-27} = 0b11101; 1233 let Inst{26-25} = 0b00; 1234 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1235 let Inst{22} = 0; 1236 let Inst{21} = 1; // The W bit. 1237 let Inst{20} = 1; // Load 1238} 1239} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq 1240 1241let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 1242def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1243 reglist:$srcs, variable_ops), IIC_iStorem, 1244 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { 1245 let Inst{31-27} = 0b11101; 1246 let Inst{26-25} = 0b00; 1247 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1248 let Inst{22} = 0; 1249 let Inst{21} = 0; // The W bit. 1250 let Inst{20} = 0; // Store 1251} 1252 1253def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1254 reglist:$srcs, variable_ops), 1255 IIC_iStorem, 1256 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs", 1257 "$addr.addr = $wb", []> { 1258 let Inst{31-27} = 0b11101; 1259 let Inst{26-25} = 0b00; 1260 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1261 let Inst{22} = 0; 1262 let Inst{21} = 1; // The W bit. 1263 let Inst{20} = 0; // Store 1264} 1265} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq 1266 1267//===----------------------------------------------------------------------===// 1268// Move Instructions. 1269// 1270 1271let neverHasSideEffects = 1 in 1272def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 1273 "mov", ".w\t$dst, $src", []> { 1274 let Inst{31-27} = 0b11101; 1275 let Inst{26-25} = 0b01; 1276 let Inst{24-21} = 0b0010; 1277 let Inst{20} = ?; // The S bit. 1278 let Inst{19-16} = 0b1111; // Rn 1279 let Inst{14-12} = 0b000; 1280 let Inst{7-4} = 0b0000; 1281} 1282 1283// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1284let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in 1285def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 1286 "mov", ".w\t$dst, $src", 1287 [(set GPR:$dst, t2_so_imm:$src)]> { 1288 let Inst{31-27} = 0b11110; 1289 let Inst{25} = 0; 1290 let Inst{24-21} = 0b0010; 1291 let Inst{20} = ?; // The S bit. 1292 let Inst{19-16} = 0b1111; // Rn 1293 let Inst{15} = 0; 1294} 1295 1296let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1297def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 1298 "movw", "\t$dst, $src", 1299 [(set GPR:$dst, imm0_65535:$src)]> { 1300 let Inst{31-27} = 0b11110; 1301 let Inst{25} = 1; 1302 let Inst{24-21} = 0b0010; 1303 let Inst{20} = 0; // The S bit. 1304 let Inst{15} = 0; 1305} 1306 1307let Constraints = "$src = $dst" in 1308def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi, 1309 "movt", "\t$dst, $imm", 1310 [(set GPR:$dst, 1311 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> { 1312 let Inst{31-27} = 0b11110; 1313 let Inst{25} = 1; 1314 let Inst{24-21} = 0b0110; 1315 let Inst{20} = 0; // The S bit. 1316 let Inst{15} = 0; 1317} 1318 1319def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>; 1320 1321//===----------------------------------------------------------------------===// 1322// Extend Instructions. 1323// 1324 1325// Sign extenders 1326 1327defm t2SXTB : T2I_unary_rrot<0b100, "sxtb", 1328 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1329defm t2SXTH : T2I_unary_rrot<0b000, "sxth", 1330 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1331defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">; 1332 1333defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab", 1334 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1335defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah", 1336 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1337defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">; 1338 1339// TODO: SXT(A){B|H}16 - done for disassembly only 1340 1341// Zero extenders 1342 1343let AddedComplexity = 16 in { 1344defm t2UXTB : T2I_unary_rrot<0b101, "uxtb", 1345 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1346defm t2UXTH : T2I_unary_rrot<0b001, "uxth", 1347 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1348defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16", 1349 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1350 1351def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 1352 (t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>; 1353def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 1354 (t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>; 1355 1356defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab", 1357 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1358defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah", 1359 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1360defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">; 1361} 1362 1363//===----------------------------------------------------------------------===// 1364// Arithmetic Instructions. 1365// 1366 1367defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1368 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1369defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1370 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1371 1372// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1373defm t2ADDS : T2I_bin_s_irs <0b1000, "add", 1374 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 1375defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", 1376 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1377 1378defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1379 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; 1380defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1381 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; 1382defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc", 1383 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; 1384defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc", 1385 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>; 1386 1387// RSB 1388defm t2RSB : T2I_rbin_is <0b1110, "rsb", 1389 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1390defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", 1391 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1392 1393// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1394let AddedComplexity = 1 in 1395def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1396 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1397def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1398 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1399def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1400 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1401 1402// Select Bytes -- for disassembly only 1403 1404def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel", 1405 "\t$dst, $a, $b", []> { 1406 let Inst{31-27} = 0b11111; 1407 let Inst{26-24} = 0b010; 1408 let Inst{23} = 0b1; 1409 let Inst{22-20} = 0b010; 1410 let Inst{15-12} = 0b1111; 1411 let Inst{7} = 0b1; 1412 let Inst{6-4} = 0b000; 1413} 1414 1415// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1416// And Miscellaneous operations -- for disassembly only 1417class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc> 1418 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc, 1419 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> { 1420 let Inst{31-27} = 0b11111; 1421 let Inst{26-23} = 0b0101; 1422 let Inst{22-20} = op22_20; 1423 let Inst{15-12} = 0b1111; 1424 let Inst{7-4} = op7_4; 1425} 1426 1427// Saturating add/subtract -- for disassembly only 1428 1429def t2QADD : T2I_pam<0b000, 0b1000, "qadd">; 1430def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1431def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1432def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1433def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">; 1434def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">; 1435def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1436def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">; 1437def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1438def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1439def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1440def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1441def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1442def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1443def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1444def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1445 1446// Signed/Unsigned add/subtract -- for disassembly only 1447 1448def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1449def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1450def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1451def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1452def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1453def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1454def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1455def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 1456def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 1457def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 1458def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 1459def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 1460 1461// Signed/Unsigned halving add/subtract -- for disassembly only 1462 1463def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1464def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 1465def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 1466def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 1467def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 1468def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 1469def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 1470def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 1471def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 1472def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 1473def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 1474def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 1475 1476// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 1477 1478def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1479 NoItinerary, "usad8", "\t$dst, $a, $b", []> { 1480 let Inst{15-12} = 0b1111; 1481} 1482def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), 1483 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8", 1484 "\t$dst, $a, $b, $acc", []>; 1485 1486// Signed/Unsigned saturate -- for disassembly only 1487 1488def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1489 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt", 1490 [/* For disassembly only; pattern left blank */]> { 1491 let Inst{31-27} = 0b11110; 1492 let Inst{25-22} = 0b1100; 1493 let Inst{20} = 0; 1494 let Inst{15} = 0; 1495 let Inst{21} = 0; // sh = '0' 1496} 1497 1498def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1499 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt", 1500 [/* For disassembly only; pattern left blank */]> { 1501 let Inst{31-27} = 0b11110; 1502 let Inst{25-22} = 0b1100; 1503 let Inst{20} = 0; 1504 let Inst{15} = 0; 1505 let Inst{21} = 1; // sh = '1' 1506} 1507 1508def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary, 1509 "ssat16", "\t$dst, $bit_pos, $a", 1510 [/* For disassembly only; pattern left blank */]> { 1511 let Inst{31-27} = 0b11110; 1512 let Inst{25-22} = 0b1100; 1513 let Inst{20} = 0; 1514 let Inst{15} = 0; 1515 let Inst{21} = 1; // sh = '1' 1516 let Inst{14-12} = 0b000; // imm3 = '000' 1517 let Inst{7-6} = 0b00; // imm2 = '00' 1518} 1519 1520def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1521 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt", 1522 [/* For disassembly only; pattern left blank */]> { 1523 let Inst{31-27} = 0b11110; 1524 let Inst{25-22} = 0b1110; 1525 let Inst{20} = 0; 1526 let Inst{15} = 0; 1527 let Inst{21} = 0; // sh = '0' 1528} 1529 1530def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1531 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt", 1532 [/* For disassembly only; pattern left blank */]> { 1533 let Inst{31-27} = 0b11110; 1534 let Inst{25-22} = 0b1110; 1535 let Inst{20} = 0; 1536 let Inst{15} = 0; 1537 let Inst{21} = 1; // sh = '1' 1538} 1539 1540def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary, 1541 "usat16", "\t$dst, $bit_pos, $a", 1542 [/* For disassembly only; pattern left blank */]> { 1543 let Inst{31-27} = 0b11110; 1544 let Inst{25-22} = 0b1110; 1545 let Inst{20} = 0; 1546 let Inst{15} = 0; 1547 let Inst{21} = 1; // sh = '1' 1548 let Inst{14-12} = 0b000; // imm3 = '000' 1549 let Inst{7-6} = 0b00; // imm2 = '00' 1550} 1551 1552//===----------------------------------------------------------------------===// 1553// Shift and rotate Instructions. 1554// 1555 1556defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 1557defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 1558defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 1559defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 1560 1561let Uses = [CPSR] in { 1562def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1563 "rrx", "\t$dst, $src", 1564 [(set GPR:$dst, (ARMrrx GPR:$src))]> { 1565 let Inst{31-27} = 0b11101; 1566 let Inst{26-25} = 0b01; 1567 let Inst{24-21} = 0b0010; 1568 let Inst{20} = ?; // The S bit. 1569 let Inst{19-16} = 0b1111; // Rn 1570 let Inst{14-12} = 0b000; 1571 let Inst{7-4} = 0b0011; 1572} 1573} 1574 1575let Defs = [CPSR] in { 1576def t2MOVsrl_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1577 "lsrs", ".w\t$dst, $src, #1", 1578 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> { 1579 let Inst{31-27} = 0b11101; 1580 let Inst{26-25} = 0b01; 1581 let Inst{24-21} = 0b0010; 1582 let Inst{20} = 1; // The S bit. 1583 let Inst{19-16} = 0b1111; // Rn 1584 let Inst{5-4} = 0b01; // Shift type. 1585 // Shift amount = Inst{14-12:7-6} = 1. 1586 let Inst{14-12} = 0b000; 1587 let Inst{7-6} = 0b01; 1588} 1589def t2MOVsra_flag : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1590 "asrs", ".w\t$dst, $src, #1", 1591 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> { 1592 let Inst{31-27} = 0b11101; 1593 let Inst{26-25} = 0b01; 1594 let Inst{24-21} = 0b0010; 1595 let Inst{20} = 1; // The S bit. 1596 let Inst{19-16} = 0b1111; // Rn 1597 let Inst{5-4} = 0b10; // Shift type. 1598 // Shift amount = Inst{14-12:7-6} = 1. 1599 let Inst{14-12} = 0b000; 1600 let Inst{7-6} = 0b01; 1601} 1602} 1603 1604//===----------------------------------------------------------------------===// 1605// Bitwise Instructions. 1606// 1607 1608defm t2AND : T2I_bin_w_irs<0b0000, "and", 1609 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 1610defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 1611 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 1612defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 1613 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 1614 1615defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 1616 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1617 1618let Constraints = "$src = $dst" in 1619def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 1620 IIC_iUNAsi, "bfc", "\t$dst, $imm", 1621 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> { 1622 let Inst{31-27} = 0b11110; 1623 let Inst{25} = 1; 1624 let Inst{24-20} = 0b10110; 1625 let Inst{19-16} = 0b1111; // Rn 1626 let Inst{15} = 0; 1627} 1628 1629def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1630 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> { 1631 let Inst{31-27} = 0b11110; 1632 let Inst{25} = 1; 1633 let Inst{24-20} = 0b10100; 1634 let Inst{15} = 0; 1635} 1636 1637def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1638 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> { 1639 let Inst{31-27} = 0b11110; 1640 let Inst{25} = 1; 1641 let Inst{24-20} = 0b11100; 1642 let Inst{15} = 0; 1643} 1644 1645// A8.6.18 BFI - Bitfield insert (Encoding T1) 1646// Added for disassembler with the pattern field purposely left blank. 1647// FIXME: Utilize this instruction in codgen. 1648def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1649 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> { 1650 let Inst{31-27} = 0b11110; 1651 let Inst{25} = 1; 1652 let Inst{24-20} = 0b10110; 1653 let Inst{15} = 0; 1654} 1655 1656defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS, 1657 (not node:$RHS))>>; 1658 1659// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 1660let AddedComplexity = 1 in 1661defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 1662 1663 1664def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 1665 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 1666 1667// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 1668def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 1669 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>, 1670 Requires<[IsThumb2]>; 1671 1672def : T2Pat<(t2_so_imm_not:$src), 1673 (t2MVNi t2_so_imm_not:$src)>; 1674 1675//===----------------------------------------------------------------------===// 1676// Multiply Instructions. 1677// 1678let isCommutable = 1 in 1679def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1680 "mul", "\t$dst, $a, $b", 1681 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> { 1682 let Inst{31-27} = 0b11111; 1683 let Inst{26-23} = 0b0110; 1684 let Inst{22-20} = 0b000; 1685 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1686 let Inst{7-4} = 0b0000; // Multiply 1687} 1688 1689def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1690 "mla", "\t$dst, $a, $b, $c", 1691 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> { 1692 let Inst{31-27} = 0b11111; 1693 let Inst{26-23} = 0b0110; 1694 let Inst{22-20} = 0b000; 1695 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1696 let Inst{7-4} = 0b0000; // Multiply 1697} 1698 1699def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1700 "mls", "\t$dst, $a, $b, $c", 1701 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> { 1702 let Inst{31-27} = 0b11111; 1703 let Inst{26-23} = 0b0110; 1704 let Inst{22-20} = 0b000; 1705 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1706 let Inst{7-4} = 0b0001; // Multiply and Subtract 1707} 1708 1709// Extra precision multiplies with low / high results 1710let neverHasSideEffects = 1 in { 1711let isCommutable = 1 in { 1712def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 1713 "smull", "\t$ldst, $hdst, $a, $b", []> { 1714 let Inst{31-27} = 0b11111; 1715 let Inst{26-23} = 0b0111; 1716 let Inst{22-20} = 0b000; 1717 let Inst{7-4} = 0b0000; 1718} 1719 1720def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 1721 "umull", "\t$ldst, $hdst, $a, $b", []> { 1722 let Inst{31-27} = 0b11111; 1723 let Inst{26-23} = 0b0111; 1724 let Inst{22-20} = 0b010; 1725 let Inst{7-4} = 0b0000; 1726} 1727} // isCommutable 1728 1729// Multiply + accumulate 1730def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1731 "smlal", "\t$ldst, $hdst, $a, $b", []>{ 1732 let Inst{31-27} = 0b11111; 1733 let Inst{26-23} = 0b0111; 1734 let Inst{22-20} = 0b100; 1735 let Inst{7-4} = 0b0000; 1736} 1737 1738def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1739 "umlal", "\t$ldst, $hdst, $a, $b", []>{ 1740 let Inst{31-27} = 0b11111; 1741 let Inst{26-23} = 0b0111; 1742 let Inst{22-20} = 0b110; 1743 let Inst{7-4} = 0b0000; 1744} 1745 1746def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1747 "umaal", "\t$ldst, $hdst, $a, $b", []>{ 1748 let Inst{31-27} = 0b11111; 1749 let Inst{26-23} = 0b0111; 1750 let Inst{22-20} = 0b110; 1751 let Inst{7-4} = 0b0110; 1752} 1753} // neverHasSideEffects 1754 1755// Rounding variants of the below included for disassembly only 1756 1757// Most significant word multiply 1758def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1759 "smmul", "\t$dst, $a, $b", 1760 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> { 1761 let Inst{31-27} = 0b11111; 1762 let Inst{26-23} = 0b0110; 1763 let Inst{22-20} = 0b101; 1764 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1765 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1766} 1767 1768def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1769 "smmulr", "\t$dst, $a, $b", []> { 1770 let Inst{31-27} = 0b11111; 1771 let Inst{26-23} = 0b0110; 1772 let Inst{22-20} = 0b101; 1773 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1774 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1775} 1776 1777def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1778 "smmla", "\t$dst, $a, $b, $c", 1779 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> { 1780 let Inst{31-27} = 0b11111; 1781 let Inst{26-23} = 0b0110; 1782 let Inst{22-20} = 0b101; 1783 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1784 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1785} 1786 1787def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1788 "smmlar", "\t$dst, $a, $b, $c", []> { 1789 let Inst{31-27} = 0b11111; 1790 let Inst{26-23} = 0b0110; 1791 let Inst{22-20} = 0b101; 1792 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1793 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1794} 1795 1796def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1797 "smmls", "\t$dst, $a, $b, $c", 1798 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> { 1799 let Inst{31-27} = 0b11111; 1800 let Inst{26-23} = 0b0110; 1801 let Inst{22-20} = 0b110; 1802 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1803 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1804} 1805 1806def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1807 "smmlsr", "\t$dst, $a, $b, $c", []> { 1808 let Inst{31-27} = 0b11111; 1809 let Inst{26-23} = 0b0110; 1810 let Inst{22-20} = 0b110; 1811 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1812 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1813} 1814 1815multiclass T2I_smul<string opc, PatFrag opnode> { 1816 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1817 !strconcat(opc, "bb"), "\t$dst, $a, $b", 1818 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1819 (sext_inreg GPR:$b, i16)))]> { 1820 let Inst{31-27} = 0b11111; 1821 let Inst{26-23} = 0b0110; 1822 let Inst{22-20} = 0b001; 1823 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1824 let Inst{7-6} = 0b00; 1825 let Inst{5-4} = 0b00; 1826 } 1827 1828 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1829 !strconcat(opc, "bt"), "\t$dst, $a, $b", 1830 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1831 (sra GPR:$b, (i32 16))))]> { 1832 let Inst{31-27} = 0b11111; 1833 let Inst{26-23} = 0b0110; 1834 let Inst{22-20} = 0b001; 1835 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1836 let Inst{7-6} = 0b00; 1837 let Inst{5-4} = 0b01; 1838 } 1839 1840 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1841 !strconcat(opc, "tb"), "\t$dst, $a, $b", 1842 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1843 (sext_inreg GPR:$b, i16)))]> { 1844 let Inst{31-27} = 0b11111; 1845 let Inst{26-23} = 0b0110; 1846 let Inst{22-20} = 0b001; 1847 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1848 let Inst{7-6} = 0b00; 1849 let Inst{5-4} = 0b10; 1850 } 1851 1852 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1853 !strconcat(opc, "tt"), "\t$dst, $a, $b", 1854 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1855 (sra GPR:$b, (i32 16))))]> { 1856 let Inst{31-27} = 0b11111; 1857 let Inst{26-23} = 0b0110; 1858 let Inst{22-20} = 0b001; 1859 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1860 let Inst{7-6} = 0b00; 1861 let Inst{5-4} = 0b11; 1862 } 1863 1864 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 1865 !strconcat(opc, "wb"), "\t$dst, $a, $b", 1866 [(set GPR:$dst, (sra (opnode GPR:$a, 1867 (sext_inreg GPR:$b, i16)), (i32 16)))]> { 1868 let Inst{31-27} = 0b11111; 1869 let Inst{26-23} = 0b0110; 1870 let Inst{22-20} = 0b011; 1871 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1872 let Inst{7-6} = 0b00; 1873 let Inst{5-4} = 0b00; 1874 } 1875 1876 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 1877 !strconcat(opc, "wt"), "\t$dst, $a, $b", 1878 [(set GPR:$dst, (sra (opnode GPR:$a, 1879 (sra GPR:$b, (i32 16))), (i32 16)))]> { 1880 let Inst{31-27} = 0b11111; 1881 let Inst{26-23} = 0b0110; 1882 let Inst{22-20} = 0b011; 1883 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1884 let Inst{7-6} = 0b00; 1885 let Inst{5-4} = 0b01; 1886 } 1887} 1888 1889 1890multiclass T2I_smla<string opc, PatFrag opnode> { 1891 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1892 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", 1893 [(set GPR:$dst, (add GPR:$acc, 1894 (opnode (sext_inreg GPR:$a, i16), 1895 (sext_inreg GPR:$b, i16))))]> { 1896 let Inst{31-27} = 0b11111; 1897 let Inst{26-23} = 0b0110; 1898 let Inst{22-20} = 0b001; 1899 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1900 let Inst{7-6} = 0b00; 1901 let Inst{5-4} = 0b00; 1902 } 1903 1904 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1905 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", 1906 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1907 (sra GPR:$b, (i32 16)))))]> { 1908 let Inst{31-27} = 0b11111; 1909 let Inst{26-23} = 0b0110; 1910 let Inst{22-20} = 0b001; 1911 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1912 let Inst{7-6} = 0b00; 1913 let Inst{5-4} = 0b01; 1914 } 1915 1916 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1917 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", 1918 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1919 (sext_inreg GPR:$b, i16))))]> { 1920 let Inst{31-27} = 0b11111; 1921 let Inst{26-23} = 0b0110; 1922 let Inst{22-20} = 0b001; 1923 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1924 let Inst{7-6} = 0b00; 1925 let Inst{5-4} = 0b10; 1926 } 1927 1928 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1929 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", 1930 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1931 (sra GPR:$b, (i32 16)))))]> { 1932 let Inst{31-27} = 0b11111; 1933 let Inst{26-23} = 0b0110; 1934 let Inst{22-20} = 0b001; 1935 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1936 let Inst{7-6} = 0b00; 1937 let Inst{5-4} = 0b11; 1938 } 1939 1940 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1941 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", 1942 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1943 (sext_inreg GPR:$b, i16)), (i32 16))))]> { 1944 let Inst{31-27} = 0b11111; 1945 let Inst{26-23} = 0b0110; 1946 let Inst{22-20} = 0b011; 1947 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1948 let Inst{7-6} = 0b00; 1949 let Inst{5-4} = 0b00; 1950 } 1951 1952 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1953 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", 1954 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1955 (sra GPR:$b, (i32 16))), (i32 16))))]> { 1956 let Inst{31-27} = 0b11111; 1957 let Inst{26-23} = 0b0110; 1958 let Inst{22-20} = 0b011; 1959 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1960 let Inst{7-6} = 0b00; 1961 let Inst{5-4} = 0b01; 1962 } 1963} 1964 1965defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1966defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1967 1968// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only 1969def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst), 1970 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b", 1971 [/* For disassembly only; pattern left blank */]>; 1972def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst), 1973 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b", 1974 [/* For disassembly only; pattern left blank */]>; 1975def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst), 1976 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b", 1977 [/* For disassembly only; pattern left blank */]>; 1978def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst), 1979 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b", 1980 [/* For disassembly only; pattern left blank */]>; 1981 1982// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 1983// These are for disassembly only. 1984 1985def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1986 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> { 1987 let Inst{15-12} = 0b1111; 1988} 1989def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1990 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> { 1991 let Inst{15-12} = 0b1111; 1992} 1993def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1994 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> { 1995 let Inst{15-12} = 0b1111; 1996} 1997def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1998 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> { 1999 let Inst{15-12} = 0b1111; 2000} 2001def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), 2002 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad", 2003 "\t$dst, $a, $b, $acc", []>; 2004def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), 2005 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx", 2006 "\t$dst, $a, $b, $acc", []>; 2007def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), 2008 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd", 2009 "\t$dst, $a, $b, $acc", []>; 2010def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), 2011 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx", 2012 "\t$dst, $a, $b, $acc", []>; 2013def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst), 2014 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald", 2015 "\t$ldst, $hdst, $a, $b", []>; 2016def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst), 2017 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx", 2018 "\t$ldst, $hdst, $a, $b", []>; 2019def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst), 2020 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld", 2021 "\t$ldst, $hdst, $a, $b", []>; 2022def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst), 2023 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx", 2024 "\t$ldst, $hdst, $a, $b", []>; 2025 2026//===----------------------------------------------------------------------===// 2027// Misc. Arithmetic Instructions. 2028// 2029 2030class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2031 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2032 : T2I<oops, iops, itin, opc, asm, pattern> { 2033 let Inst{31-27} = 0b11111; 2034 let Inst{26-22} = 0b01010; 2035 let Inst{21-20} = op1; 2036 let Inst{15-12} = 0b1111; 2037 let Inst{7-6} = 0b10; 2038 let Inst{5-4} = op2; 2039} 2040 2041def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2042 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>; 2043 2044def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2045 "rbit", "\t$dst, $src", 2046 [(set GPR:$dst, (ARMrbit GPR:$src))]>; 2047 2048def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2049 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>; 2050 2051def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2052 "rev16", ".w\t$dst, $src", 2053 [(set GPR:$dst, 2054 (or (and (srl GPR:$src, (i32 8)), 0xFF), 2055 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 2056 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 2057 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 2058 2059def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2060 "revsh", ".w\t$dst, $src", 2061 [(set GPR:$dst, 2062 (sext_inreg 2063 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 2064 (shl GPR:$src, (i32 8))), i16))]>; 2065 2066def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2067 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt", 2068 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 2069 (and (shl GPR:$src2, (i32 imm:$shamt)), 2070 0xFFFF0000)))]>, 2071 Requires<[HasT2ExtractPack]> { 2072 let Inst{31-27} = 0b11101; 2073 let Inst{26-25} = 0b01; 2074 let Inst{24-20} = 0b01100; 2075 let Inst{5} = 0; // BT form 2076 let Inst{4} = 0; 2077} 2078 2079// Alternate cases for PKHBT where identities eliminate some nodes. 2080def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 2081 (t2PKHBT GPR:$src1, GPR:$src2, 0)>, 2082 Requires<[HasT2ExtractPack]>; 2083def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 2084 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>, 2085 Requires<[HasT2ExtractPack]>; 2086 2087def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2088 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt", 2089 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 2090 (and (sra GPR:$src2, imm16_31:$shamt), 2091 0xFFFF)))]>, 2092 Requires<[HasT2ExtractPack]> { 2093 let Inst{31-27} = 0b11101; 2094 let Inst{26-25} = 0b01; 2095 let Inst{24-20} = 0b01100; 2096 let Inst{5} = 1; // TB form 2097 let Inst{4} = 0; 2098} 2099 2100// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2101// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2102def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 2103 (t2PKHTB GPR:$src1, GPR:$src2, 16)>, 2104 Requires<[HasT2ExtractPack]>; 2105def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 2106 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 2107 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>, 2108 Requires<[HasT2ExtractPack]>; 2109 2110//===----------------------------------------------------------------------===// 2111// Comparison Instructions... 2112// 2113 2114defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2115 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 2116defm t2CMPz : T2I_cmp_irs<0b1101, "cmp", 2117 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 2118 2119//FIXME: Disable CMN, as CCodes are backwards from compare expectations 2120// Compare-to-zero still works out, just not the relationals 2121//defm t2CMN : T2I_cmp_irs<0b1000, "cmn", 2122// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2123defm t2CMNz : T2I_cmp_irs<0b1000, "cmn", 2124 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 2125 2126//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2127// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2128 2129def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 2130 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>; 2131 2132defm t2TST : T2I_cmp_irs<0b0000, "tst", 2133 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 2134defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2135 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 2136 2137// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 2138// Short range conditional branch. Looks awesome for loops. Need to figure 2139// out how to use this one. 2140 2141 2142// Conditional moves 2143// FIXME: should be able to write a pattern for ARMcmov, but can't use 2144// a two-value operand where a dag node expects two operands. :( 2145let neverHasSideEffects = 1 in { 2146def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr, 2147 "mov", ".w\t$dst, $true", 2148 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 2149 RegConstraint<"$false = $dst"> { 2150 let Inst{31-27} = 0b11101; 2151 let Inst{26-25} = 0b01; 2152 let Inst{24-21} = 0b0010; 2153 let Inst{20} = 0; // The S bit. 2154 let Inst{19-16} = 0b1111; // Rn 2155 let Inst{14-12} = 0b000; 2156 let Inst{7-4} = 0b0000; 2157} 2158 2159def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 2160 IIC_iCMOVi, "mov", ".w\t$dst, $true", 2161[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 2162 RegConstraint<"$false = $dst"> { 2163 let Inst{31-27} = 0b11110; 2164 let Inst{25} = 0; 2165 let Inst{24-21} = 0b0010; 2166 let Inst{20} = 0; // The S bit. 2167 let Inst{19-16} = 0b1111; // Rn 2168 let Inst{15} = 0; 2169} 2170 2171class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2172 string opc, string asm, list<dag> pattern> 2173 : T2I<oops, iops, itin, opc, asm, pattern> { 2174 let Inst{31-27} = 0b11101; 2175 let Inst{26-25} = 0b01; 2176 let Inst{24-21} = 0b0010; 2177 let Inst{20} = 0; // The S bit. 2178 let Inst{19-16} = 0b1111; // Rn 2179 let Inst{5-4} = opcod; // Shift type. 2180} 2181def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst), 2182 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2183 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>, 2184 RegConstraint<"$false = $dst">; 2185def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst), 2186 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2187 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>, 2188 RegConstraint<"$false = $dst">; 2189def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst), 2190 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2191 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>, 2192 RegConstraint<"$false = $dst">; 2193def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst), 2194 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2195 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>, 2196 RegConstraint<"$false = $dst">; 2197} // neverHasSideEffects 2198 2199//===----------------------------------------------------------------------===// 2200// Atomic operations intrinsics 2201// 2202 2203// memory barriers protect the atomic sequences 2204let hasSideEffects = 1 in { 2205def t2Int_MemBarrierV7 : AInoP<(outs), (ins), 2206 ThumbFrm, NoItinerary, 2207 "dmb", "", 2208 [(ARMMemBarrierV7)]>, 2209 Requires<[IsThumb2]> { 2210 let Inst{31-4} = 0xF3BF8F5; 2211 // FIXME: add support for options other than a full system DMB 2212 let Inst{3-0} = 0b1111; 2213} 2214 2215def t2Int_SyncBarrierV7 : AInoP<(outs), (ins), 2216 ThumbFrm, NoItinerary, 2217 "dsb", "", 2218 [(ARMSyncBarrierV7)]>, 2219 Requires<[IsThumb2]> { 2220 let Inst{31-4} = 0xF3BF8F4; 2221 // FIXME: add support for options other than a full system DSB 2222 let Inst{3-0} = 0b1111; 2223} 2224} 2225 2226// Helper class for multiclass T2MemB -- for disassembly only 2227class T2I_memb<string opc, string asm> 2228 : T2I<(outs), (ins), NoItinerary, opc, asm, 2229 [/* For disassembly only; pattern left blank */]>, 2230 Requires<[IsThumb2, HasV7]> { 2231 let Inst{31-20} = 0xf3b; 2232 let Inst{15-14} = 0b10; 2233 let Inst{12} = 0; 2234} 2235 2236multiclass T2MemB<bits<4> op7_4, string opc> { 2237 2238 def st : T2I_memb<opc, "\tst"> { 2239 let Inst{7-4} = op7_4; 2240 let Inst{3-0} = 0b1110; 2241 } 2242 2243 def ish : T2I_memb<opc, "\tish"> { 2244 let Inst{7-4} = op7_4; 2245 let Inst{3-0} = 0b1011; 2246 } 2247 2248 def ishst : T2I_memb<opc, "\tishst"> { 2249 let Inst{7-4} = op7_4; 2250 let Inst{3-0} = 0b1010; 2251 } 2252 2253 def nsh : T2I_memb<opc, "\tnsh"> { 2254 let Inst{7-4} = op7_4; 2255 let Inst{3-0} = 0b0111; 2256 } 2257 2258 def nshst : T2I_memb<opc, "\tnshst"> { 2259 let Inst{7-4} = op7_4; 2260 let Inst{3-0} = 0b0110; 2261 } 2262 2263 def osh : T2I_memb<opc, "\tosh"> { 2264 let Inst{7-4} = op7_4; 2265 let Inst{3-0} = 0b0011; 2266 } 2267 2268 def oshst : T2I_memb<opc, "\toshst"> { 2269 let Inst{7-4} = op7_4; 2270 let Inst{3-0} = 0b0010; 2271 } 2272} 2273 2274// These DMB variants are for disassembly only. 2275defm t2DMB : T2MemB<0b0101, "dmb">; 2276 2277// These DSB variants are for disassembly only. 2278defm t2DSB : T2MemB<0b0100, "dsb">; 2279 2280// ISB has only full system option -- for disassembly only 2281def t2ISBsy : T2I_memb<"isb", ""> { 2282 let Inst{7-4} = 0b0110; 2283 let Inst{3-0} = 0b1111; 2284} 2285 2286class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2287 InstrItinClass itin, string opc, string asm, string cstr, 2288 list<dag> pattern, bits<4> rt2 = 0b1111> 2289 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2290 let Inst{31-27} = 0b11101; 2291 let Inst{26-20} = 0b0001101; 2292 let Inst{11-8} = rt2; 2293 let Inst{7-6} = 0b01; 2294 let Inst{5-4} = opcod; 2295 let Inst{3-0} = 0b1111; 2296} 2297class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2298 InstrItinClass itin, string opc, string asm, string cstr, 2299 list<dag> pattern, bits<4> rt2 = 0b1111> 2300 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2301 let Inst{31-27} = 0b11101; 2302 let Inst{26-20} = 0b0001100; 2303 let Inst{11-8} = rt2; 2304 let Inst{7-6} = 0b01; 2305 let Inst{5-4} = opcod; 2306} 2307 2308let mayLoad = 1 in { 2309def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2310 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]", 2311 "", []>; 2312def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2313 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]", 2314 "", []>; 2315def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2316 Size4Bytes, NoItinerary, 2317 "ldrex", "\t$dest, [$ptr]", "", 2318 []> { 2319 let Inst{31-27} = 0b11101; 2320 let Inst{26-20} = 0b0000101; 2321 let Inst{11-8} = 0b1111; 2322 let Inst{7-0} = 0b00000000; // imm8 = 0 2323} 2324def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr), 2325 AddrModeNone, Size4Bytes, NoItinerary, 2326 "ldrexd", "\t$dest, $dest2, [$ptr]", "", 2327 [], {?, ?, ?, ?}>; 2328} 2329 2330let mayStore = 1, Constraints = "@earlyclobber $success" in { 2331def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2332 AddrModeNone, Size4Bytes, NoItinerary, 2333 "strexb", "\t$success, $src, [$ptr]", "", []>; 2334def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2335 AddrModeNone, Size4Bytes, NoItinerary, 2336 "strexh", "\t$success, $src, [$ptr]", "", []>; 2337def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2338 AddrModeNone, Size4Bytes, NoItinerary, 2339 "strex", "\t$success, $src, [$ptr]", "", 2340 []> { 2341 let Inst{31-27} = 0b11101; 2342 let Inst{26-20} = 0b0000100; 2343 let Inst{7-0} = 0b00000000; // imm8 = 0 2344} 2345def t2STREXD : T2I_strex<0b11, (outs GPR:$success), 2346 (ins GPR:$src, GPR:$src2, GPR:$ptr), 2347 AddrModeNone, Size4Bytes, NoItinerary, 2348 "strexd", "\t$success, $src, $src2, [$ptr]", "", [], 2349 {?, ?, ?, ?}>; 2350} 2351 2352// Clear-Exclusive is for disassembly only. 2353def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", 2354 [/* For disassembly only; pattern left blank */]>, 2355 Requires<[IsARM, HasV7]> { 2356 let Inst{31-20} = 0xf3b; 2357 let Inst{15-14} = 0b10; 2358 let Inst{12} = 0; 2359 let Inst{7-4} = 0b0010; 2360} 2361 2362//===----------------------------------------------------------------------===// 2363// TLS Instructions 2364// 2365 2366// __aeabi_read_tp preserves the registers r1-r3. 2367let isCall = 1, 2368 Defs = [R0, R12, LR, CPSR] in { 2369 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 2370 "bl\t__aeabi_read_tp", 2371 [(set R0, ARMthread_pointer)]> { 2372 let Inst{31-27} = 0b11110; 2373 let Inst{15-14} = 0b11; 2374 let Inst{12} = 1; 2375 } 2376} 2377 2378//===----------------------------------------------------------------------===// 2379// SJLJ Exception handling intrinsics 2380// eh_sjlj_setjmp() is an instruction sequence to store the return 2381// address and save #0 in R0 for the non-longjmp case. 2382// Since by its nature we may be coming from some other function to get 2383// here, and we're using the stack frame for the containing function to 2384// save/restore registers, we can't keep anything live in regs across 2385// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 2386// when we get here from a longjmp(). We force everthing out of registers 2387// except for our own input by listing the relevant registers in Defs. By 2388// doing so, we also cause the prologue/epilogue code to actively preserve 2389// all of the callee-saved resgisters, which is exactly what we want. 2390// $val is a scratch register for our use. 2391let Defs = 2392 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 2393 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 2394 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 2395 D31 ], hasSideEffects = 1, isBarrier = 1 in { 2396 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val), 2397 AddrModeNone, SizeSpecial, NoItinerary, 2398 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t" 2399 "adds\t$val, #7\n\t" 2400 "str\t$val, [$src, #4]\n\t" 2401 "movs\tr0, #0\n\t" 2402 "b\t1f\n\t" 2403 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t" 2404 "1:", "", 2405 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>, 2406 Requires<[IsThumb2, HasVFP2]>; 2407} 2408 2409let Defs = 2410 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], 2411 hasSideEffects = 1, isBarrier = 1 in { 2412 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val), 2413 AddrModeNone, SizeSpecial, NoItinerary, 2414 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t" 2415 "adds\t$val, #7\n\t" 2416 "str\t$val, [$src, #4]\n\t" 2417 "movs\tr0, #0\n\t" 2418 "b\t1f\n\t" 2419 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t" 2420 "1:", "", 2421 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>, 2422 Requires<[IsThumb2, NoVFP]>; 2423} 2424 2425 2426//===----------------------------------------------------------------------===// 2427// Control-Flow Instructions 2428// 2429 2430// FIXME: remove when we have a way to marking a MI with these properties. 2431// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 2432// operand list. 2433// FIXME: Should pc be an implicit operand like PICADD, etc? 2434let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2435 hasExtraDefRegAllocReq = 1 in 2436 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 2437 reglist:$dsts, variable_ops), IIC_Br, 2438 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", 2439 "$addr.addr = $wb", []> { 2440 let Inst{31-27} = 0b11101; 2441 let Inst{26-25} = 0b00; 2442 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 2443 let Inst{22} = 0; 2444 let Inst{21} = 1; // The W bit. 2445 let Inst{20} = 1; // Load 2446} 2447 2448let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 2449let isPredicable = 1 in 2450def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 2451 "b.w\t$target", 2452 [(br bb:$target)]> { 2453 let Inst{31-27} = 0b11110; 2454 let Inst{15-14} = 0b10; 2455 let Inst{12} = 1; 2456} 2457 2458let isNotDuplicable = 1, isIndirectBranch = 1 in { 2459def t2BR_JT : 2460 T2JTI<(outs), 2461 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 2462 IIC_Br, "mov\tpc, $target\n$jt", 2463 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> { 2464 let Inst{31-27} = 0b11101; 2465 let Inst{26-20} = 0b0100100; 2466 let Inst{19-16} = 0b1111; 2467 let Inst{14-12} = 0b000; 2468 let Inst{11-8} = 0b1111; // Rd = pc 2469 let Inst{7-4} = 0b0000; 2470} 2471 2472// FIXME: Add a non-pc based case that can be predicated. 2473def t2TBB : 2474 T2JTI<(outs), 2475 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2476 IIC_Br, "tbb\t$index\n$jt", []> { 2477 let Inst{31-27} = 0b11101; 2478 let Inst{26-20} = 0b0001101; 2479 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2480 let Inst{15-8} = 0b11110000; 2481 let Inst{7-4} = 0b0000; // B form 2482} 2483 2484def t2TBH : 2485 T2JTI<(outs), 2486 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2487 IIC_Br, "tbh\t$index\n$jt", []> { 2488 let Inst{31-27} = 0b11101; 2489 let Inst{26-20} = 0b0001101; 2490 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2491 let Inst{15-8} = 0b11110000; 2492 let Inst{7-4} = 0b0001; // H form 2493} 2494 2495// Generic versions of the above two instructions, for disassembly only 2496 2497def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2498 "tbb", "\t[$a, $b]", []>{ 2499 let Inst{31-27} = 0b11101; 2500 let Inst{26-20} = 0b0001101; 2501 let Inst{15-8} = 0b11110000; 2502 let Inst{7-4} = 0b0000; // B form 2503} 2504 2505def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2506 "tbh", "\t[$a, $b, lsl #1]", []> { 2507 let Inst{31-27} = 0b11101; 2508 let Inst{26-20} = 0b0001101; 2509 let Inst{15-8} = 0b11110000; 2510 let Inst{7-4} = 0b0001; // H form 2511} 2512} // isNotDuplicable, isIndirectBranch 2513 2514} // isBranch, isTerminator, isBarrier 2515 2516// FIXME: should be able to write a pattern for ARMBrcond, but can't use 2517// a two-value operand where a dag node expects two operands. :( 2518let isBranch = 1, isTerminator = 1 in 2519def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 2520 "b", ".w\t$target", 2521 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 2522 let Inst{31-27} = 0b11110; 2523 let Inst{15-14} = 0b10; 2524 let Inst{12} = 0; 2525} 2526 2527 2528// IT block 2529let Defs = [ITSTATE] in 2530def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 2531 AddrModeNone, Size2Bytes, IIC_iALUx, 2532 "it$mask\t$cc", "", []> { 2533 // 16-bit instruction. 2534 let Inst{31-16} = 0x0000; 2535 let Inst{15-8} = 0b10111111; 2536} 2537 2538// Branch and Exchange Jazelle -- for disassembly only 2539// Rm = Inst{19-16} 2540def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2541 [/* For disassembly only; pattern left blank */]> { 2542 let Inst{31-27} = 0b11110; 2543 let Inst{26} = 0; 2544 let Inst{25-20} = 0b111100; 2545 let Inst{15-14} = 0b10; 2546 let Inst{12} = 0; 2547} 2548 2549// Change Processor State is a system instruction -- for disassembly only. 2550// The singleton $opt operand contains the following information: 2551// opt{4-0} = mode from Inst{4-0} 2552// opt{5} = changemode from Inst{17} 2553// opt{8-6} = AIF from Inst{8-6} 2554// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable 2555def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt", 2556 [/* For disassembly only; pattern left blank */]> { 2557 let Inst{31-27} = 0b11110; 2558 let Inst{26} = 0; 2559 let Inst{25-20} = 0b111010; 2560 let Inst{15-14} = 0b10; 2561 let Inst{12} = 0; 2562} 2563 2564// A6.3.4 Branches and miscellaneous control 2565// Table A6-14 Change Processor State, and hint instructions 2566// Helper class for disassembly only. 2567class T2I_hint<bits<8> op7_0, string opc, string asm> 2568 : T2I<(outs), (ins), NoItinerary, opc, asm, 2569 [/* For disassembly only; pattern left blank */]> { 2570 let Inst{31-20} = 0xf3a; 2571 let Inst{15-14} = 0b10; 2572 let Inst{12} = 0; 2573 let Inst{10-8} = 0b000; 2574 let Inst{7-0} = op7_0; 2575} 2576 2577def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 2578def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 2579def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 2580def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 2581def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 2582 2583def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt", 2584 [/* For disassembly only; pattern left blank */]> { 2585 let Inst{31-20} = 0xf3a; 2586 let Inst{15-14} = 0b10; 2587 let Inst{12} = 0; 2588 let Inst{10-8} = 0b000; 2589 let Inst{7-4} = 0b1111; 2590} 2591 2592// Secure Monitor Call is a system instruction -- for disassembly only 2593// Option = Inst{19-16} 2594def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", 2595 [/* For disassembly only; pattern left blank */]> { 2596 let Inst{31-27} = 0b11110; 2597 let Inst{26-20} = 0b1111111; 2598 let Inst{15-12} = 0b1000; 2599} 2600 2601// Store Return State is a system instruction -- for disassembly only 2602def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode", 2603 [/* For disassembly only; pattern left blank */]> { 2604 let Inst{31-27} = 0b11101; 2605 let Inst{26-20} = 0b0000010; // W = 1 2606} 2607 2608def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode", 2609 [/* For disassembly only; pattern left blank */]> { 2610 let Inst{31-27} = 0b11101; 2611 let Inst{26-20} = 0b0000000; // W = 0 2612} 2613 2614def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode", 2615 [/* For disassembly only; pattern left blank */]> { 2616 let Inst{31-27} = 0b11101; 2617 let Inst{26-20} = 0b0011010; // W = 1 2618} 2619 2620def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode", 2621 [/* For disassembly only; pattern left blank */]> { 2622 let Inst{31-27} = 0b11101; 2623 let Inst{26-20} = 0b0011000; // W = 0 2624} 2625 2626// Return From Exception is a system instruction -- for disassembly only 2627def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!", 2628 [/* For disassembly only; pattern left blank */]> { 2629 let Inst{31-27} = 0b11101; 2630 let Inst{26-20} = 0b0000011; // W = 1 2631} 2632 2633def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base", 2634 [/* For disassembly only; pattern left blank */]> { 2635 let Inst{31-27} = 0b11101; 2636 let Inst{26-20} = 0b0000001; // W = 0 2637} 2638 2639def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!", 2640 [/* For disassembly only; pattern left blank */]> { 2641 let Inst{31-27} = 0b11101; 2642 let Inst{26-20} = 0b0011011; // W = 1 2643} 2644 2645def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base", 2646 [/* For disassembly only; pattern left blank */]> { 2647 let Inst{31-27} = 0b11101; 2648 let Inst{26-20} = 0b0011001; // W = 0 2649} 2650 2651//===----------------------------------------------------------------------===// 2652// Non-Instruction Patterns 2653// 2654 2655// Two piece so_imms. 2656def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS), 2657 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2658 (t2_so_imm2part_2 imm:$RHS))>; 2659def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS), 2660 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2661 (t2_so_imm2part_2 imm:$RHS))>; 2662def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS), 2663 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2664 (t2_so_imm2part_2 imm:$RHS))>; 2665def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS), 2666 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)), 2667 (t2_so_neg_imm2part_2 imm:$RHS))>; 2668 2669// 32-bit immediate using movw + movt. 2670// This is a single pseudo instruction to make it re-materializable. Remove 2671// when we can do generalized remat. 2672let isReMaterializable = 1 in 2673def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 2674 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}", 2675 [(set GPR:$dst, (i32 imm:$src))]>; 2676 2677// ConstantPool, GlobalAddress, and JumpTable 2678def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 2679 Requires<[IsThumb2, DontUseMovt]>; 2680def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 2681def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 2682 Requires<[IsThumb2, UseMovt]>; 2683 2684def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 2685 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 2686 2687// Pseudo instruction that combines ldr from constpool and add pc. This should 2688// be expanded into two instructions late to allow if-conversion and 2689// scheduling. 2690let canFoldAsLoad = 1, isReMaterializable = 1 in 2691def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 2692 NoItinerary, 2693 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 2694 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 2695 imm:$cp))]>, 2696 Requires<[IsThumb2]>; 2697 2698//===----------------------------------------------------------------------===// 2699// Move between special register and ARM core register -- for disassembly only 2700// 2701 2702// Rd = Instr{11-8} 2703def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr", 2704 [/* For disassembly only; pattern left blank */]> { 2705 let Inst{31-27} = 0b11110; 2706 let Inst{26} = 0; 2707 let Inst{25-21} = 0b11111; 2708 let Inst{20} = 0; // The R bit. 2709 let Inst{15-14} = 0b10; 2710 let Inst{12} = 0; 2711} 2712 2713// Rd = Instr{11-8} 2714def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr", 2715 [/* For disassembly only; pattern left blank */]> { 2716 let Inst{31-27} = 0b11110; 2717 let Inst{26} = 0; 2718 let Inst{25-21} = 0b11111; 2719 let Inst{20} = 1; // The R bit. 2720 let Inst{15-14} = 0b10; 2721 let Inst{12} = 0; 2722} 2723 2724// Rn = Inst{19-16} 2725def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr", 2726 "\tcpsr$mask, $src", 2727 [/* For disassembly only; pattern left blank */]> { 2728 let Inst{31-27} = 0b11110; 2729 let Inst{26} = 0; 2730 let Inst{25-21} = 0b11100; 2731 let Inst{20} = 0; // The R bit. 2732 let Inst{15-14} = 0b10; 2733 let Inst{12} = 0; 2734} 2735 2736// Rn = Inst{19-16} 2737def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr", 2738 "\tspsr$mask, $src", 2739 [/* For disassembly only; pattern left blank */]> { 2740 let Inst{31-27} = 0b11110; 2741 let Inst{26} = 0; 2742 let Inst{25-21} = 0b11100; 2743 let Inst{20} = 1; // The R bit. 2744 let Inst{15-14} = 0b10; 2745 let Inst{12} = 0; 2746} 2747