ARMInstrThumb2.td revision e35c5e06fe5b1fd6e754773168ad0281ecda7009 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred : Operand<i32> {
16  let PrintMethod = "printMandatoryPredicateOperand";
17}
18
19// IT block condition mask
20def it_mask : Operand<i32> {
21  let PrintMethod = "printThumbITMask";
22}
23
24// Shifted operands. No register controlled shifts for Thumb2.
25// Note: We do not support rrx shifted operands yet.
26def t2_so_reg : Operand<i32>,    // reg imm
27                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
28                               [shl,srl,sra,rotr]> {
29  let EncoderMethod = "getT2SORegOpValue";
30  let PrintMethod = "printT2SOOperand";
31  let MIOperandInfo = (ops rGPR, i32imm);
32}
33
34// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
37}]>;
38
39// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
42}]>;
43
44// t2_so_imm - Match a 32-bit immediate operand, which is an
45// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46// immediate splatted into multiple bytes of the word.
47def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
48def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
49    return ARM_AM::getT2SOImmVal(Imm) != -1;
50  }]> {
51  let ParserMatchClass = t2_so_imm_asmoperand;
52  let EncoderMethod = "getT2SOImmOpValue";
53}
54
55// t2_so_imm_not - Match an immediate that is a complement
56// of a t2_so_imm.
57def t2_so_imm_not : Operand<i32>,
58                    PatLeaf<(imm), [{
59  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60}], t2_so_imm_not_XFORM>;
61
62// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
63def t2_so_imm_neg : Operand<i32>,
64                    PatLeaf<(imm), [{
65  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
66}], t2_so_imm_neg_XFORM>;
67
68/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
69def imm1_31 : ImmLeaf<i32, [{
70  return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
71}]>;
72
73/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
74def imm0_4095 : Operand<i32>,
75                ImmLeaf<i32, [{
76  return Imm >= 0 && Imm < 4096;
77}]>;
78
79def imm0_4095_neg : PatLeaf<(i32 imm), [{
80 return (uint32_t)(-N->getZExtValue()) < 4096;
81}], imm_neg_XFORM>;
82
83def imm0_255_neg : PatLeaf<(i32 imm), [{
84  return (uint32_t)(-N->getZExtValue()) < 255;
85}], imm_neg_XFORM>;
86
87def imm0_255_not : PatLeaf<(i32 imm), [{
88  return (uint32_t)(~N->getZExtValue()) < 255;
89}], imm_comp_XFORM>;
90
91def lo5AllOne : PatLeaf<(i32 imm), [{
92  // Returns true if all low 5-bits are 1.
93  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
94}]>;
95
96// Define Thumb2 specific addressing modes.
97
98// t2addrmode_imm12  := reg + imm12
99def t2addrmode_imm12 : Operand<i32>,
100                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
101  let PrintMethod = "printAddrModeImm12Operand";
102  let EncoderMethod = "getAddrModeImm12OpValue";
103  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
104  let ParserMatchClass = MemMode5AsmOperand;
105}
106
107// t2ldrlabel  := imm12
108def t2ldrlabel : Operand<i32> {
109  let EncoderMethod = "getAddrModeImm12OpValue";
110}
111
112
113// ADR instruction labels.
114def t2adrlabel : Operand<i32> {
115  let EncoderMethod = "getT2AdrLabelOpValue";
116}
117
118
119// t2addrmode_imm8  := reg +/- imm8
120def t2addrmode_imm8 : Operand<i32>,
121                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
122  let PrintMethod = "printT2AddrModeImm8Operand";
123  let EncoderMethod = "getT2AddrModeImm8OpValue";
124  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
125  let ParserMatchClass = MemMode5AsmOperand;
126}
127
128def t2am_imm8_offset : Operand<i32>,
129                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
130                                      [], [SDNPWantRoot]> {
131  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
132  let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
133  let ParserMatchClass = MemMode5AsmOperand;
134}
135
136// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
137def t2addrmode_imm8s4 : Operand<i32> {
138  let PrintMethod = "printT2AddrModeImm8s4Operand";
139  let EncoderMethod = "getT2AddrModeImm8s4OpValue";
140  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141  let ParserMatchClass = MemMode5AsmOperand;
142}
143
144def t2am_imm8s4_offset : Operand<i32> {
145  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
146}
147
148// t2addrmode_so_reg  := reg + (reg << imm2)
149def t2addrmode_so_reg : Operand<i32>,
150                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
151  let PrintMethod = "printT2AddrModeSoRegOperand";
152  let EncoderMethod = "getT2AddrModeSORegOpValue";
153  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
154  let ParserMatchClass = MemMode5AsmOperand;
155}
156
157// t2addrmode_reg := reg
158// Used by load/store exclusive instructions. Useful to enable right assembly
159// parsing and printing. Not used for any codegen matching.
160//
161def t2addrmode_reg : Operand<i32> {
162  let PrintMethod = "printAddrMode7Operand";
163  let MIOperandInfo = (ops GPR);
164  let ParserMatchClass = MemMode7AsmOperand;
165}
166
167//===----------------------------------------------------------------------===//
168// Multiclass helpers...
169//
170
171
172class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
173           string opc, string asm, list<dag> pattern>
174  : T2I<oops, iops, itin, opc, asm, pattern> {
175  bits<4> Rd;
176  bits<12> imm;
177
178  let Inst{11-8}  = Rd;
179  let Inst{26}    = imm{11};
180  let Inst{14-12} = imm{10-8};
181  let Inst{7-0}   = imm{7-0};
182}
183
184
185class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
186           string opc, string asm, list<dag> pattern>
187  : T2sI<oops, iops, itin, opc, asm, pattern> {
188  bits<4> Rd;
189  bits<4> Rn;
190  bits<12> imm;
191
192  let Inst{11-8}  = Rd;
193  let Inst{26}    = imm{11};
194  let Inst{14-12} = imm{10-8};
195  let Inst{7-0}   = imm{7-0};
196}
197
198class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
199           string opc, string asm, list<dag> pattern>
200  : T2I<oops, iops, itin, opc, asm, pattern> {
201  bits<4> Rn;
202  bits<12> imm;
203
204  let Inst{19-16}  = Rn;
205  let Inst{26}    = imm{11};
206  let Inst{14-12} = imm{10-8};
207  let Inst{7-0}   = imm{7-0};
208}
209
210
211class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
212           string opc, string asm, list<dag> pattern>
213  : T2I<oops, iops, itin, opc, asm, pattern> {
214  bits<4> Rd;
215  bits<12> ShiftedRm;
216
217  let Inst{11-8}  = Rd;
218  let Inst{3-0}   = ShiftedRm{3-0};
219  let Inst{5-4}   = ShiftedRm{6-5};
220  let Inst{14-12} = ShiftedRm{11-9};
221  let Inst{7-6}   = ShiftedRm{8-7};
222}
223
224class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
225           string opc, string asm, list<dag> pattern>
226  : T2sI<oops, iops, itin, opc, asm, pattern> {
227  bits<4> Rd;
228  bits<12> ShiftedRm;
229
230  let Inst{11-8}  = Rd;
231  let Inst{3-0}   = ShiftedRm{3-0};
232  let Inst{5-4}   = ShiftedRm{6-5};
233  let Inst{14-12} = ShiftedRm{11-9};
234  let Inst{7-6}   = ShiftedRm{8-7};
235}
236
237class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
238           string opc, string asm, list<dag> pattern>
239  : T2I<oops, iops, itin, opc, asm, pattern> {
240  bits<4> Rn;
241  bits<12> ShiftedRm;
242
243  let Inst{19-16} = Rn;
244  let Inst{3-0}   = ShiftedRm{3-0};
245  let Inst{5-4}   = ShiftedRm{6-5};
246  let Inst{14-12} = ShiftedRm{11-9};
247  let Inst{7-6}   = ShiftedRm{8-7};
248}
249
250class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
251           string opc, string asm, list<dag> pattern>
252  : T2I<oops, iops, itin, opc, asm, pattern> {
253  bits<4> Rd;
254  bits<4> Rm;
255
256  let Inst{11-8}  = Rd;
257  let Inst{3-0}   = Rm;
258}
259
260class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
261           string opc, string asm, list<dag> pattern>
262  : T2sI<oops, iops, itin, opc, asm, pattern> {
263  bits<4> Rd;
264  bits<4> Rm;
265
266  let Inst{11-8}  = Rd;
267  let Inst{3-0}   = Rm;
268}
269
270class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
271           string opc, string asm, list<dag> pattern>
272  : T2I<oops, iops, itin, opc, asm, pattern> {
273  bits<4> Rn;
274  bits<4> Rm;
275
276  let Inst{19-16} = Rn;
277  let Inst{3-0}   = Rm;
278}
279
280
281class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
282           string opc, string asm, list<dag> pattern>
283  : T2I<oops, iops, itin, opc, asm, pattern> {
284  bits<4> Rd;
285  bits<4> Rn;
286  bits<12> imm;
287
288  let Inst{11-8}  = Rd;
289  let Inst{19-16} = Rn;
290  let Inst{26}    = imm{11};
291  let Inst{14-12} = imm{10-8};
292  let Inst{7-0}   = imm{7-0};
293}
294
295class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
296           string opc, string asm, list<dag> pattern>
297  : T2sI<oops, iops, itin, opc, asm, pattern> {
298  bits<4> Rd;
299  bits<4> Rn;
300  bits<12> imm;
301
302  let Inst{11-8}  = Rd;
303  let Inst{19-16} = Rn;
304  let Inst{26}    = imm{11};
305  let Inst{14-12} = imm{10-8};
306  let Inst{7-0}   = imm{7-0};
307}
308
309class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
310           string opc, string asm, list<dag> pattern>
311  : T2I<oops, iops, itin, opc, asm, pattern> {
312  bits<4> Rd;
313  bits<4> Rm;
314  bits<5> imm;
315
316  let Inst{11-8}  = Rd;
317  let Inst{3-0}   = Rm;
318  let Inst{14-12} = imm{4-2};
319  let Inst{7-6}   = imm{1-0};
320}
321
322class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
323           string opc, string asm, list<dag> pattern>
324  : T2sI<oops, iops, itin, opc, asm, pattern> {
325  bits<4> Rd;
326  bits<4> Rm;
327  bits<5> imm;
328
329  let Inst{11-8}  = Rd;
330  let Inst{3-0}   = Rm;
331  let Inst{14-12} = imm{4-2};
332  let Inst{7-6}   = imm{1-0};
333}
334
335class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
336           string opc, string asm, list<dag> pattern>
337  : T2I<oops, iops, itin, opc, asm, pattern> {
338  bits<4> Rd;
339  bits<4> Rn;
340  bits<4> Rm;
341
342  let Inst{11-8}  = Rd;
343  let Inst{19-16} = Rn;
344  let Inst{3-0}   = Rm;
345}
346
347class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
348           string opc, string asm, list<dag> pattern>
349  : T2sI<oops, iops, itin, opc, asm, pattern> {
350  bits<4> Rd;
351  bits<4> Rn;
352  bits<4> Rm;
353
354  let Inst{11-8}  = Rd;
355  let Inst{19-16} = Rn;
356  let Inst{3-0}   = Rm;
357}
358
359class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
360           string opc, string asm, list<dag> pattern>
361  : T2I<oops, iops, itin, opc, asm, pattern> {
362  bits<4> Rd;
363  bits<4> Rn;
364  bits<12> ShiftedRm;
365
366  let Inst{11-8}  = Rd;
367  let Inst{19-16} = Rn;
368  let Inst{3-0}   = ShiftedRm{3-0};
369  let Inst{5-4}   = ShiftedRm{6-5};
370  let Inst{14-12} = ShiftedRm{11-9};
371  let Inst{7-6}   = ShiftedRm{8-7};
372}
373
374class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
375           string opc, string asm, list<dag> pattern>
376  : T2sI<oops, iops, itin, opc, asm, pattern> {
377  bits<4> Rd;
378  bits<4> Rn;
379  bits<12> ShiftedRm;
380
381  let Inst{11-8}  = Rd;
382  let Inst{19-16} = Rn;
383  let Inst{3-0}   = ShiftedRm{3-0};
384  let Inst{5-4}   = ShiftedRm{6-5};
385  let Inst{14-12} = ShiftedRm{11-9};
386  let Inst{7-6}   = ShiftedRm{8-7};
387}
388
389class T2FourReg<dag oops, dag iops, InstrItinClass itin,
390           string opc, string asm, list<dag> pattern>
391  : T2I<oops, iops, itin, opc, asm, pattern> {
392  bits<4> Rd;
393  bits<4> Rn;
394  bits<4> Rm;
395  bits<4> Ra;
396
397  let Inst{19-16} = Rn;
398  let Inst{15-12} = Ra;
399  let Inst{11-8}  = Rd;
400  let Inst{3-0}   = Rm;
401}
402
403class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
404                dag oops, dag iops, InstrItinClass itin,
405                string opc, string asm, list<dag> pattern>
406  : T2I<oops, iops, itin, opc, asm, pattern> {
407  bits<4> RdLo;
408  bits<4> RdHi;
409  bits<4> Rn;
410  bits<4> Rm;
411
412  let Inst{31-23} = 0b111110111;
413  let Inst{22-20} = opc22_20;
414  let Inst{19-16} = Rn;
415  let Inst{15-12} = RdLo;
416  let Inst{11-8}  = RdHi;
417  let Inst{7-4}   = opc7_4;
418  let Inst{3-0}   = Rm;
419}
420
421
422/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
423/// unary operation that produces a value. These are predicable and can be
424/// changed to modify CPSR.
425multiclass T2I_un_irs<bits<4> opcod, string opc,
426                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
427                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
428   // shifted imm
429   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
430                opc, "\t$Rd, $imm",
431                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
432     let isAsCheapAsAMove = Cheap;
433     let isReMaterializable = ReMat;
434     let Inst{31-27} = 0b11110;
435     let Inst{25} = 0;
436     let Inst{24-21} = opcod;
437     let Inst{19-16} = 0b1111; // Rn
438     let Inst{15} = 0;
439   }
440   // register
441   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
442                opc, ".w\t$Rd, $Rm",
443                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
444     let Inst{31-27} = 0b11101;
445     let Inst{26-25} = 0b01;
446     let Inst{24-21} = opcod;
447     let Inst{19-16} = 0b1111; // Rn
448     let Inst{14-12} = 0b000; // imm3
449     let Inst{7-6} = 0b00; // imm2
450     let Inst{5-4} = 0b00; // type
451   }
452   // shifted register
453   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
454                opc, ".w\t$Rd, $ShiftedRm",
455                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
456     let Inst{31-27} = 0b11101;
457     let Inst{26-25} = 0b01;
458     let Inst{24-21} = opcod;
459     let Inst{19-16} = 0b1111; // Rn
460   }
461}
462
463/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
464/// binary operation that produces a value. These are predicable and can be
465/// changed to modify CPSR.
466multiclass T2I_bin_irs<bits<4> opcod, string opc,
467                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
468                       PatFrag opnode, string baseOpc, bit Commutable = 0,
469                       string wide = ""> {
470   // shifted imm
471   def ri : T2sTwoRegImm<
472                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
473                 opc, "\t$Rd, $Rn, $imm",
474                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
475     let Inst{31-27} = 0b11110;
476     let Inst{25} = 0;
477     let Inst{24-21} = opcod;
478     let Inst{15} = 0;
479   }
480   // register
481   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
482                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
483                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
484     let isCommutable = Commutable;
485     let Inst{31-27} = 0b11101;
486     let Inst{26-25} = 0b01;
487     let Inst{24-21} = opcod;
488     let Inst{14-12} = 0b000; // imm3
489     let Inst{7-6} = 0b00; // imm2
490     let Inst{5-4} = 0b00; // type
491   }
492   // shifted register
493   def rs : T2sTwoRegShiftedReg<
494                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
495                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
496                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
497     let Inst{31-27} = 0b11101;
498     let Inst{26-25} = 0b01;
499     let Inst{24-21} = opcod;
500   }
501  // Assembly aliases for optional destination operand when it's the same
502  // as the source operand.
503  def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
504     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
505                                                    t2_so_imm:$imm, pred:$p,
506                                                    cc_out:$s)>,
507     Requires<[IsThumb2]>;
508  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
509     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
510                                                    rGPR:$Rm, pred:$p,
511                                                    cc_out:$s)>,
512     Requires<[IsThumb2]>;
513  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
514     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
515                                                    t2_so_reg:$shift, pred:$p,
516                                                    cc_out:$s)>,
517     Requires<[IsThumb2]>;
518}
519
520/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
521//  the ".w" suffix to indicate that they are wide.
522multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
523                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
524                         PatFrag opnode, string baseOpc, bit Commutable = 0> :
525    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
526
527/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
528/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
529/// it is equivalent to the T2I_bin_irs counterpart.
530multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
531   // shifted imm
532   def ri : T2sTwoRegImm<
533                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
534                 opc, ".w\t$Rd, $Rn, $imm",
535                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
536     let Inst{31-27} = 0b11110;
537     let Inst{25} = 0;
538     let Inst{24-21} = opcod;
539     let Inst{15} = 0;
540   }
541   // register
542   def rr : T2sThreeReg<
543                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
544                 opc, "\t$Rd, $Rn, $Rm",
545                 [/* For disassembly only; pattern left blank */]> {
546     let Inst{31-27} = 0b11101;
547     let Inst{26-25} = 0b01;
548     let Inst{24-21} = opcod;
549     let Inst{14-12} = 0b000; // imm3
550     let Inst{7-6} = 0b00; // imm2
551     let Inst{5-4} = 0b00; // type
552   }
553   // shifted register
554   def rs : T2sTwoRegShiftedReg<
555                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
556                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
557                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
558     let Inst{31-27} = 0b11101;
559     let Inst{26-25} = 0b01;
560     let Inst{24-21} = opcod;
561   }
562}
563
564/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
565/// instruction modifies the CPSR register.
566let isCodeGenOnly = 1, Defs = [CPSR] in {
567multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
568                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
569                         PatFrag opnode, bit Commutable = 0> {
570   // shifted imm
571   def ri : T2TwoRegImm<
572                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
573                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
574                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
575     let Inst{31-27} = 0b11110;
576     let Inst{25} = 0;
577     let Inst{24-21} = opcod;
578     let Inst{20} = 1; // The S bit.
579     let Inst{15} = 0;
580   }
581   // register
582   def rr : T2ThreeReg<
583                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
584                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
585                [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
586     let isCommutable = Commutable;
587     let Inst{31-27} = 0b11101;
588     let Inst{26-25} = 0b01;
589     let Inst{24-21} = opcod;
590     let Inst{20} = 1; // The S bit.
591     let Inst{14-12} = 0b000; // imm3
592     let Inst{7-6} = 0b00; // imm2
593     let Inst{5-4} = 0b00; // type
594   }
595   // shifted register
596   def rs : T2TwoRegShiftedReg<
597                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
598                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
599                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
600     let Inst{31-27} = 0b11101;
601     let Inst{26-25} = 0b01;
602     let Inst{24-21} = opcod;
603     let Inst{20} = 1; // The S bit.
604   }
605}
606}
607
608/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
609/// patterns for a binary operation that produces a value.
610multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
611                          bit Commutable = 0> {
612   // shifted imm
613   // The register-immediate version is re-materializable. This is useful
614   // in particular for taking the address of a local.
615   let isReMaterializable = 1 in {
616   def ri : T2sTwoRegImm<
617                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
618                 opc, ".w\t$Rd, $Rn, $imm",
619                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
620     let Inst{31-27} = 0b11110;
621     let Inst{25} = 0;
622     let Inst{24} = 1;
623     let Inst{23-21} = op23_21;
624     let Inst{15} = 0;
625   }
626   }
627   // 12-bit imm
628   def ri12 : T2I<
629                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
630                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
631                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
632     bits<4> Rd;
633     bits<4> Rn;
634     bits<12> imm;
635     let Inst{31-27} = 0b11110;
636     let Inst{26} = imm{11};
637     let Inst{25-24} = 0b10;
638     let Inst{23-21} = op23_21;
639     let Inst{20} = 0; // The S bit.
640     let Inst{19-16} = Rn;
641     let Inst{15} = 0;
642     let Inst{14-12} = imm{10-8};
643     let Inst{11-8} = Rd;
644     let Inst{7-0} = imm{7-0};
645   }
646   // register
647   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
648                 opc, ".w\t$Rd, $Rn, $Rm",
649                 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
650     let isCommutable = Commutable;
651     let Inst{31-27} = 0b11101;
652     let Inst{26-25} = 0b01;
653     let Inst{24} = 1;
654     let Inst{23-21} = op23_21;
655     let Inst{14-12} = 0b000; // imm3
656     let Inst{7-6} = 0b00; // imm2
657     let Inst{5-4} = 0b00; // type
658   }
659   // shifted register
660   def rs : T2sTwoRegShiftedReg<
661                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
662                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
663                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
664     let Inst{31-27} = 0b11101;
665     let Inst{26-25} = 0b01;
666     let Inst{24} = 1;
667     let Inst{23-21} = op23_21;
668   }
669}
670
671/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
672/// for a binary operation that produces a value and use the carry
673/// bit. It's not predicable.
674let Uses = [CPSR] in {
675multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
676                             bit Commutable = 0> {
677   // shifted imm
678   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
679                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
680                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
681                 Requires<[IsThumb2]> {
682     let Inst{31-27} = 0b11110;
683     let Inst{25} = 0;
684     let Inst{24-21} = opcod;
685     let Inst{15} = 0;
686   }
687   // register
688   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
689                 opc, ".w\t$Rd, $Rn, $Rm",
690                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
691                 Requires<[IsThumb2]> {
692     let isCommutable = Commutable;
693     let Inst{31-27} = 0b11101;
694     let Inst{26-25} = 0b01;
695     let Inst{24-21} = opcod;
696     let Inst{14-12} = 0b000; // imm3
697     let Inst{7-6} = 0b00; // imm2
698     let Inst{5-4} = 0b00; // type
699   }
700   // shifted register
701   def rs : T2sTwoRegShiftedReg<
702                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
703                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
704                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
705                 Requires<[IsThumb2]> {
706     let Inst{31-27} = 0b11101;
707     let Inst{26-25} = 0b01;
708     let Inst{24-21} = opcod;
709   }
710}
711}
712
713// Carry setting variants
714// NOTE: CPSR def omitted because it will be handled by the custom inserter.
715let usesCustomInserter = 1 in {
716multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
717   // shifted imm
718   def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
719                Size4Bytes, IIC_iALUi,
720                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
721   // register
722   def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
723                Size4Bytes, IIC_iALUr,
724                [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
725     let isCommutable = Commutable;
726   }
727   // shifted register
728   def rs : t2PseudoInst<
729                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
730                Size4Bytes, IIC_iALUsi,
731                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
732}
733}
734
735/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
736/// version is not needed since this is only for codegen.
737let isCodeGenOnly = 1, Defs = [CPSR] in {
738multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
739   // shifted imm
740   def ri : T2TwoRegImm<
741                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
742                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
743                [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
744     let Inst{31-27} = 0b11110;
745     let Inst{25} = 0;
746     let Inst{24-21} = opcod;
747     let Inst{20} = 1; // The S bit.
748     let Inst{15} = 0;
749   }
750   // shifted register
751   def rs : T2TwoRegShiftedReg<
752                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
753                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
754                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
755     let Inst{31-27} = 0b11101;
756     let Inst{26-25} = 0b01;
757     let Inst{24-21} = opcod;
758     let Inst{20} = 1; // The S bit.
759   }
760}
761}
762
763/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
764//  rotate operation that produces a value.
765multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
766   // 5-bit imm
767   def ri : T2sTwoRegShiftImm<
768                 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
769                 opc, ".w\t$Rd, $Rm, $imm",
770                 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
771     let Inst{31-27} = 0b11101;
772     let Inst{26-21} = 0b010010;
773     let Inst{19-16} = 0b1111; // Rn
774     let Inst{5-4} = opcod;
775   }
776   // register
777   def rr : T2sThreeReg<
778                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
779                 opc, ".w\t$Rd, $Rn, $Rm",
780                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
781     let Inst{31-27} = 0b11111;
782     let Inst{26-23} = 0b0100;
783     let Inst{22-21} = opcod;
784     let Inst{15-12} = 0b1111;
785     let Inst{7-4} = 0b0000;
786   }
787}
788
789/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
790/// patterns. Similar to T2I_bin_irs except the instruction does not produce
791/// a explicit result, only implicitly set CPSR.
792let isCompare = 1, Defs = [CPSR] in {
793multiclass T2I_cmp_irs<bits<4> opcod, string opc,
794                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
795                       PatFrag opnode> {
796   // shifted imm
797   def ri : T2OneRegCmpImm<
798                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
799                opc, ".w\t$Rn, $imm",
800                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
801     let Inst{31-27} = 0b11110;
802     let Inst{25} = 0;
803     let Inst{24-21} = opcod;
804     let Inst{20} = 1; // The S bit.
805     let Inst{15} = 0;
806     let Inst{11-8} = 0b1111; // Rd
807   }
808   // register
809   def rr : T2TwoRegCmp<
810                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
811                opc, ".w\t$lhs, $rhs",
812                [(opnode GPR:$lhs, rGPR:$rhs)]> {
813     let Inst{31-27} = 0b11101;
814     let Inst{26-25} = 0b01;
815     let Inst{24-21} = opcod;
816     let Inst{20} = 1; // The S bit.
817     let Inst{14-12} = 0b000; // imm3
818     let Inst{11-8} = 0b1111; // Rd
819     let Inst{7-6} = 0b00; // imm2
820     let Inst{5-4} = 0b00; // type
821   }
822   // shifted register
823   def rs : T2OneRegCmpShiftedReg<
824                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
825                opc, ".w\t$Rn, $ShiftedRm",
826                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
827     let Inst{31-27} = 0b11101;
828     let Inst{26-25} = 0b01;
829     let Inst{24-21} = opcod;
830     let Inst{20} = 1; // The S bit.
831     let Inst{11-8} = 0b1111; // Rd
832   }
833}
834}
835
836/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
837multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
838                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
839  def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
840                   opc, ".w\t$Rt, $addr",
841                   [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
842    let Inst{31-27} = 0b11111;
843    let Inst{26-25} = 0b00;
844    let Inst{24} = signed;
845    let Inst{23} = 1;
846    let Inst{22-21} = opcod;
847    let Inst{20} = 1; // load
848
849    bits<4> Rt;
850    let Inst{15-12} = Rt;
851
852    bits<17> addr;
853    let addr{12}    = 1;           // add = TRUE
854    let Inst{19-16} = addr{16-13}; // Rn
855    let Inst{23}    = addr{12};    // U
856    let Inst{11-0}  = addr{11-0};  // imm
857  }
858  def i8  : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
859                   opc, "\t$Rt, $addr",
860                   [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
861    let Inst{31-27} = 0b11111;
862    let Inst{26-25} = 0b00;
863    let Inst{24} = signed;
864    let Inst{23} = 0;
865    let Inst{22-21} = opcod;
866    let Inst{20} = 1; // load
867    let Inst{11} = 1;
868    // Offset: index==TRUE, wback==FALSE
869    let Inst{10} = 1; // The P bit.
870    let Inst{8} = 0; // The W bit.
871
872    bits<4> Rt;
873    let Inst{15-12} = Rt;
874
875    bits<13> addr;
876    let Inst{19-16} = addr{12-9}; // Rn
877    let Inst{9}     = addr{8};    // U
878    let Inst{7-0}   = addr{7-0};  // imm
879  }
880  def s   : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
881                   opc, ".w\t$Rt, $addr",
882                   [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
883    let Inst{31-27} = 0b11111;
884    let Inst{26-25} = 0b00;
885    let Inst{24} = signed;
886    let Inst{23} = 0;
887    let Inst{22-21} = opcod;
888    let Inst{20} = 1; // load
889    let Inst{11-6} = 0b000000;
890
891    bits<4> Rt;
892    let Inst{15-12} = Rt;
893
894    bits<10> addr;
895    let Inst{19-16} = addr{9-6}; // Rn
896    let Inst{3-0}   = addr{5-2}; // Rm
897    let Inst{5-4}   = addr{1-0}; // imm
898  }
899
900  // FIXME: Is the pci variant actually needed?
901  def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
902                   opc, ".w\t$Rt, $addr",
903                   [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
904    let isReMaterializable = 1;
905    let Inst{31-27} = 0b11111;
906    let Inst{26-25} = 0b00;
907    let Inst{24} = signed;
908    let Inst{23} = ?; // add = (U == '1')
909    let Inst{22-21} = opcod;
910    let Inst{20} = 1; // load
911    let Inst{19-16} = 0b1111; // Rn
912    bits<4> Rt;
913    bits<12> addr;
914    let Inst{15-12} = Rt{3-0};
915    let Inst{11-0}  = addr{11-0};
916  }
917}
918
919/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
920multiclass T2I_st<bits<2> opcod, string opc,
921                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
922  def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
923                   opc, ".w\t$Rt, $addr",
924                   [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
925    let Inst{31-27} = 0b11111;
926    let Inst{26-23} = 0b0001;
927    let Inst{22-21} = opcod;
928    let Inst{20} = 0; // !load
929
930    bits<4> Rt;
931    let Inst{15-12} = Rt;
932
933    bits<17> addr;
934    let addr{12}    = 1;           // add = TRUE
935    let Inst{19-16} = addr{16-13}; // Rn
936    let Inst{23}    = addr{12};    // U
937    let Inst{11-0}  = addr{11-0};  // imm
938  }
939  def i8  : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
940                   opc, "\t$Rt, $addr",
941                   [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
942    let Inst{31-27} = 0b11111;
943    let Inst{26-23} = 0b0000;
944    let Inst{22-21} = opcod;
945    let Inst{20} = 0; // !load
946    let Inst{11} = 1;
947    // Offset: index==TRUE, wback==FALSE
948    let Inst{10} = 1; // The P bit.
949    let Inst{8} = 0; // The W bit.
950
951    bits<4> Rt;
952    let Inst{15-12} = Rt;
953
954    bits<13> addr;
955    let Inst{19-16} = addr{12-9}; // Rn
956    let Inst{9}     = addr{8};    // U
957    let Inst{7-0}   = addr{7-0};  // imm
958  }
959  def s   : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
960                   opc, ".w\t$Rt, $addr",
961                   [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
962    let Inst{31-27} = 0b11111;
963    let Inst{26-23} = 0b0000;
964    let Inst{22-21} = opcod;
965    let Inst{20} = 0; // !load
966    let Inst{11-6} = 0b000000;
967
968    bits<4> Rt;
969    let Inst{15-12} = Rt;
970
971    bits<10> addr;
972    let Inst{19-16}   = addr{9-6}; // Rn
973    let Inst{3-0} = addr{5-2}; // Rm
974    let Inst{5-4}   = addr{1-0}; // imm
975  }
976}
977
978/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
979/// register and one whose operand is a register rotated by 8/16/24.
980multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
981  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
982                  opc, ".w\t$Rd, $Rm",
983                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
984     let Inst{31-27} = 0b11111;
985     let Inst{26-23} = 0b0100;
986     let Inst{22-20} = opcod;
987     let Inst{19-16} = 0b1111; // Rn
988     let Inst{15-12} = 0b1111;
989     let Inst{7} = 1;
990     let Inst{5-4} = 0b00; // rotate
991   }
992  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
993                  opc, ".w\t$Rd, $Rm, ror $rot",
994                 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
995     let Inst{31-27} = 0b11111;
996     let Inst{26-23} = 0b0100;
997     let Inst{22-20} = opcod;
998     let Inst{19-16} = 0b1111; // Rn
999     let Inst{15-12} = 0b1111;
1000     let Inst{7} = 1;
1001
1002     bits<2> rot;
1003     let Inst{5-4} = rot{1-0}; // rotate
1004   }
1005}
1006
1007// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1008multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1009  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1010                  opc, "\t$Rd, $Rm",
1011                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1012                 Requires<[HasT2ExtractPack, IsThumb2]> {
1013     let Inst{31-27} = 0b11111;
1014     let Inst{26-23} = 0b0100;
1015     let Inst{22-20} = opcod;
1016     let Inst{19-16} = 0b1111; // Rn
1017     let Inst{15-12} = 0b1111;
1018     let Inst{7} = 1;
1019     let Inst{5-4} = 0b00; // rotate
1020   }
1021  def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1022                  IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1023                 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1024                 Requires<[HasT2ExtractPack, IsThumb2]> {
1025     let Inst{31-27} = 0b11111;
1026     let Inst{26-23} = 0b0100;
1027     let Inst{22-20} = opcod;
1028     let Inst{19-16} = 0b1111; // Rn
1029     let Inst{15-12} = 0b1111;
1030     let Inst{7} = 1;
1031
1032     bits<2> rot;
1033     let Inst{5-4} = rot{1-0}; // rotate
1034   }
1035}
1036
1037// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1038// supported yet.
1039multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1040  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1041                  opc, "\t$Rd, $Rm", []>,
1042          Requires<[IsThumb2, HasT2ExtractPack]> {
1043     let Inst{31-27} = 0b11111;
1044     let Inst{26-23} = 0b0100;
1045     let Inst{22-20} = opcod;
1046     let Inst{19-16} = 0b1111; // Rn
1047     let Inst{15-12} = 0b1111;
1048     let Inst{7} = 1;
1049     let Inst{5-4} = 0b00; // rotate
1050   }
1051  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1052                  opc, "\t$Rd, $Rm, ror $rot", []>,
1053          Requires<[IsThumb2, HasT2ExtractPack]> {
1054     let Inst{31-27} = 0b11111;
1055     let Inst{26-23} = 0b0100;
1056     let Inst{22-20} = opcod;
1057     let Inst{19-16} = 0b1111; // Rn
1058     let Inst{15-12} = 0b1111;
1059     let Inst{7} = 1;
1060
1061      bits<2> rot;
1062      let Inst{5-4} = rot{1-0}; // rotate
1063   }
1064}
1065
1066/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1067/// register and one whose operand is a register rotated by 8/16/24.
1068multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1069  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1070                  opc, "\t$Rd, $Rn, $Rm",
1071                  [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1072                  Requires<[HasT2ExtractPack, IsThumb2]> {
1073     let Inst{31-27} = 0b11111;
1074     let Inst{26-23} = 0b0100;
1075     let Inst{22-20} = opcod;
1076     let Inst{15-12} = 0b1111;
1077     let Inst{7} = 1;
1078     let Inst{5-4} = 0b00; // rotate
1079   }
1080  def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1081                  (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1082                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1083                  [(set rGPR:$Rd, (opnode rGPR:$Rn,
1084                                          (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1085                  Requires<[HasT2ExtractPack, IsThumb2]> {
1086     let Inst{31-27} = 0b11111;
1087     let Inst{26-23} = 0b0100;
1088     let Inst{22-20} = opcod;
1089     let Inst{15-12} = 0b1111;
1090     let Inst{7} = 1;
1091
1092     bits<2> rot;
1093     let Inst{5-4} = rot{1-0}; // rotate
1094   }
1095}
1096
1097// DO variant - disassembly only, no pattern
1098
1099multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1100  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1101                  opc, "\t$Rd, $Rn, $Rm", []> {
1102     let Inst{31-27} = 0b11111;
1103     let Inst{26-23} = 0b0100;
1104     let Inst{22-20} = opcod;
1105     let Inst{15-12} = 0b1111;
1106     let Inst{7} = 1;
1107     let Inst{5-4} = 0b00; // rotate
1108   }
1109  def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1110                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1111     let Inst{31-27} = 0b11111;
1112     let Inst{26-23} = 0b0100;
1113     let Inst{22-20} = opcod;
1114     let Inst{15-12} = 0b1111;
1115     let Inst{7} = 1;
1116
1117     bits<2> rot;
1118     let Inst{5-4} = rot{1-0}; // rotate
1119   }
1120}
1121
1122//===----------------------------------------------------------------------===//
1123// Instructions
1124//===----------------------------------------------------------------------===//
1125
1126//===----------------------------------------------------------------------===//
1127//  Miscellaneous Instructions.
1128//
1129
1130class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1131           string asm, list<dag> pattern>
1132  : T2XI<oops, iops, itin, asm, pattern> {
1133  bits<4> Rd;
1134  bits<12> label;
1135
1136  let Inst{11-8}  = Rd;
1137  let Inst{26}    = label{11};
1138  let Inst{14-12} = label{10-8};
1139  let Inst{7-0}   = label{7-0};
1140}
1141
1142// LEApcrel - Load a pc-relative address into a register without offending the
1143// assembler.
1144def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1145              (ins t2adrlabel:$addr, pred:$p),
1146              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1147  let Inst{31-27} = 0b11110;
1148  let Inst{25-24} = 0b10;
1149  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1150  let Inst{22} = 0;
1151  let Inst{20} = 0;
1152  let Inst{19-16} = 0b1111; // Rn
1153  let Inst{15} = 0;
1154
1155  bits<4> Rd;
1156  bits<13> addr;
1157  let Inst{11-8} = Rd;
1158  let Inst{23}    = addr{12};
1159  let Inst{21}    = addr{12};
1160  let Inst{26}    = addr{11};
1161  let Inst{14-12} = addr{10-8};
1162  let Inst{7-0}   = addr{7-0};
1163}
1164
1165let neverHasSideEffects = 1, isReMaterializable = 1 in
1166def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1167                                Size4Bytes, IIC_iALUi, []>;
1168def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1169                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
1170                                Size4Bytes, IIC_iALUi,
1171                                []>;
1172
1173
1174//===----------------------------------------------------------------------===//
1175//  Load / store Instructions.
1176//
1177
1178// Load
1179let canFoldAsLoad = 1, isReMaterializable = 1  in
1180defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1181                      UnOpFrag<(load node:$Src)>>;
1182
1183// Loads with zero extension
1184defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1185                      UnOpFrag<(zextloadi16 node:$Src)>>;
1186defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1187                      UnOpFrag<(zextloadi8  node:$Src)>>;
1188
1189// Loads with sign extension
1190defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1191                      UnOpFrag<(sextloadi16 node:$Src)>>;
1192defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1193                      UnOpFrag<(sextloadi8  node:$Src)>>;
1194
1195let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1196// Load doubleword
1197def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1198                        (ins t2addrmode_imm8s4:$addr),
1199                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1200} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1201
1202// zextload i1 -> zextload i8
1203def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1204            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1205def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1206            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1207def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1208            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1209def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1210            (t2LDRBpci  tconstpool:$addr)>;
1211
1212// extload -> zextload
1213// FIXME: Reduce the number of patterns by legalizing extload to zextload
1214// earlier?
1215def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1216            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1217def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1218            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1219def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1220            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1221def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1222            (t2LDRBpci  tconstpool:$addr)>;
1223
1224def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1225            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1226def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1227            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1228def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1229            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1230def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1231            (t2LDRBpci  tconstpool:$addr)>;
1232
1233def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1234            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1235def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1236            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1237def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1238            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1239def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1240            (t2LDRHpci  tconstpool:$addr)>;
1241
1242// FIXME: The destination register of the loads and stores can't be PC, but
1243//        can be SP. We need another regclass (similar to rGPR) to represent
1244//        that. Not a pressing issue since these are selected manually,
1245//        not via pattern.
1246
1247// Indexed loads
1248
1249let mayLoad = 1, neverHasSideEffects = 1 in {
1250def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1251                            (ins t2addrmode_imm8:$addr),
1252                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1253                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1254                            []>;
1255
1256def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1257                            (ins GPR:$base, t2am_imm8_offset:$addr),
1258                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1259                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1260                            []>;
1261
1262def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1263                            (ins t2addrmode_imm8:$addr),
1264                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1265                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1266                            []>;
1267def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1268                            (ins GPR:$base, t2am_imm8_offset:$addr),
1269                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1270                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1271                            []>;
1272
1273def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1274                            (ins t2addrmode_imm8:$addr),
1275                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1276                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1277                            []>;
1278def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1279                            (ins GPR:$base, t2am_imm8_offset:$addr),
1280                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1281                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1282                            []>;
1283
1284def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1285                            (ins t2addrmode_imm8:$addr),
1286                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1287                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1288                            []>;
1289def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1290                            (ins GPR:$base, t2am_imm8_offset:$addr),
1291                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1292                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1293                            []>;
1294
1295def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1296                            (ins t2addrmode_imm8:$addr),
1297                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1298                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1299                            []>;
1300def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1301                            (ins GPR:$base, t2am_imm8_offset:$addr),
1302                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1303                        "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1304                            []>;
1305} // mayLoad = 1, neverHasSideEffects = 1
1306
1307// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1308// for disassembly only.
1309// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1310class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1311  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1312          "\t$Rt, $addr", []> {
1313  let Inst{31-27} = 0b11111;
1314  let Inst{26-25} = 0b00;
1315  let Inst{24} = signed;
1316  let Inst{23} = 0;
1317  let Inst{22-21} = type;
1318  let Inst{20} = 1; // load
1319  let Inst{11} = 1;
1320  let Inst{10-8} = 0b110; // PUW.
1321
1322  bits<4> Rt;
1323  bits<13> addr;
1324  let Inst{15-12} = Rt;
1325  let Inst{19-16} = addr{12-9};
1326  let Inst{7-0}   = addr{7-0};
1327}
1328
1329def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1330def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1331def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1332def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1333def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1334
1335// Store
1336defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1337                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1338defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1339                   BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1340defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1341                   BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1342
1343// Store doubleword
1344let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1345def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1346                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1347               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1348
1349// Indexed stores
1350def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1351                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1352                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1353                         "str", "\t$Rt, [$Rn, $addr]!",
1354                         "$Rn = $base_wb,@earlyclobber $base_wb",
1355             [(set GPR:$base_wb,
1356                   (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1357
1358def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1359                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1360                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1361                          "str", "\t$Rt, [$Rn], $addr",
1362                          "$Rn = $base_wb,@earlyclobber $base_wb",
1363             [(set GPR:$base_wb,
1364                  (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1365
1366def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1367                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1368                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1369                        "strh", "\t$Rt, [$Rn, $addr]!",
1370                        "$Rn = $base_wb,@earlyclobber $base_wb",
1371        [(set GPR:$base_wb,
1372              (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1373
1374def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1375                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1376                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1377                         "strh", "\t$Rt, [$Rn], $addr",
1378                         "$Rn = $base_wb,@earlyclobber $base_wb",
1379       [(set GPR:$base_wb,
1380             (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1381
1382def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1383                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1384                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1385                        "strb", "\t$Rt, [$Rn, $addr]!",
1386                        "$Rn = $base_wb,@earlyclobber $base_wb",
1387         [(set GPR:$base_wb,
1388               (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1389
1390def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1391                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1392                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1393                         "strb", "\t$Rt, [$Rn], $addr",
1394                         "$Rn = $base_wb,@earlyclobber $base_wb",
1395        [(set GPR:$base_wb,
1396              (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1397
1398// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1399// only.
1400// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1401class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1402  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1403          "\t$Rt, $addr", []> {
1404  let Inst{31-27} = 0b11111;
1405  let Inst{26-25} = 0b00;
1406  let Inst{24} = 0; // not signed
1407  let Inst{23} = 0;
1408  let Inst{22-21} = type;
1409  let Inst{20} = 0; // store
1410  let Inst{11} = 1;
1411  let Inst{10-8} = 0b110; // PUW
1412
1413  bits<4> Rt;
1414  bits<13> addr;
1415  let Inst{15-12} = Rt;
1416  let Inst{19-16} = addr{12-9};
1417  let Inst{7-0}   = addr{7-0};
1418}
1419
1420def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1421def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1422def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1423
1424// ldrd / strd pre / post variants
1425// For disassembly only.
1426
1427def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1428                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1429                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1430
1431def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1432                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1433                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1434
1435def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs),
1436                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1437                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1438
1439def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1440                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1441                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1442
1443// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1444// data/instruction access.  These are for disassembly only.
1445// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1446// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1447multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1448
1449  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1450                "\t$addr",
1451              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1452    let Inst{31-25} = 0b1111100;
1453    let Inst{24} = instr;
1454    let Inst{22} = 0;
1455    let Inst{21} = write;
1456    let Inst{20} = 1;
1457    let Inst{15-12} = 0b1111;
1458
1459    bits<17> addr;
1460    let addr{12}    = 1;           // add = TRUE
1461    let Inst{19-16} = addr{16-13}; // Rn
1462    let Inst{23}    = addr{12};    // U
1463    let Inst{11-0}  = addr{11-0};  // imm12
1464  }
1465
1466  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1467                "\t$addr",
1468               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1469    let Inst{31-25} = 0b1111100;
1470    let Inst{24} = instr;
1471    let Inst{23} = 0; // U = 0
1472    let Inst{22} = 0;
1473    let Inst{21} = write;
1474    let Inst{20} = 1;
1475    let Inst{15-12} = 0b1111;
1476    let Inst{11-8} = 0b1100;
1477
1478    bits<13> addr;
1479    let Inst{19-16} = addr{12-9}; // Rn
1480    let Inst{7-0}   = addr{7-0};  // imm8
1481  }
1482
1483  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1484               "\t$addr",
1485             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1486    let Inst{31-25} = 0b1111100;
1487    let Inst{24} = instr;
1488    let Inst{23} = 0; // add = TRUE for T1
1489    let Inst{22} = 0;
1490    let Inst{21} = write;
1491    let Inst{20} = 1;
1492    let Inst{15-12} = 0b1111;
1493    let Inst{11-6} = 0000000;
1494
1495    bits<10> addr;
1496    let Inst{19-16} = addr{9-6}; // Rn
1497    let Inst{3-0}   = addr{5-2}; // Rm
1498    let Inst{5-4}   = addr{1-0}; // imm2
1499  }
1500}
1501
1502defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1503defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1504defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1505
1506//===----------------------------------------------------------------------===//
1507//  Load / store multiple Instructions.
1508//
1509
1510multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1511                            InstrItinClass itin_upd, bit L_bit> {
1512  def IA :
1513    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1514         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1515    bits<4>  Rn;
1516    bits<16> regs;
1517
1518    let Inst{31-27} = 0b11101;
1519    let Inst{26-25} = 0b00;
1520    let Inst{24-23} = 0b01;     // Increment After
1521    let Inst{22}    = 0;
1522    let Inst{21}    = 0;        // No writeback
1523    let Inst{20}    = L_bit;
1524    let Inst{19-16} = Rn;
1525    let Inst{15-0}  = regs;
1526  }
1527  def IA_UPD :
1528    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1529          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1530    bits<4>  Rn;
1531    bits<16> regs;
1532
1533    let Inst{31-27} = 0b11101;
1534    let Inst{26-25} = 0b00;
1535    let Inst{24-23} = 0b01;     // Increment After
1536    let Inst{22}    = 0;
1537    let Inst{21}    = 1;        // Writeback
1538    let Inst{20}    = L_bit;
1539    let Inst{19-16} = Rn;
1540    let Inst{15-0}  = regs;
1541  }
1542  def DB :
1543    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1544         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1545    bits<4>  Rn;
1546    bits<16> regs;
1547
1548    let Inst{31-27} = 0b11101;
1549    let Inst{26-25} = 0b00;
1550    let Inst{24-23} = 0b10;     // Decrement Before
1551    let Inst{22}    = 0;
1552    let Inst{21}    = 0;        // No writeback
1553    let Inst{20}    = L_bit;
1554    let Inst{19-16} = Rn;
1555    let Inst{15-0}  = regs;
1556  }
1557  def DB_UPD :
1558    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1559          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1560    bits<4>  Rn;
1561    bits<16> regs;
1562
1563    let Inst{31-27} = 0b11101;
1564    let Inst{26-25} = 0b00;
1565    let Inst{24-23} = 0b10;     // Decrement Before
1566    let Inst{22}    = 0;
1567    let Inst{21}    = 1;        // Writeback
1568    let Inst{20}    = L_bit;
1569    let Inst{19-16} = Rn;
1570    let Inst{15-0}  = regs;
1571  }
1572}
1573
1574let neverHasSideEffects = 1 in {
1575
1576let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1577defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1578
1579let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1580defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1581
1582} // neverHasSideEffects
1583
1584
1585//===----------------------------------------------------------------------===//
1586//  Move Instructions.
1587//
1588
1589let neverHasSideEffects = 1 in
1590def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1591                   "mov", ".w\t$Rd, $Rm", []> {
1592  let Inst{31-27} = 0b11101;
1593  let Inst{26-25} = 0b01;
1594  let Inst{24-21} = 0b0010;
1595  let Inst{19-16} = 0b1111; // Rn
1596  let Inst{14-12} = 0b000;
1597  let Inst{7-4} = 0b0000;
1598}
1599
1600// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1601let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1602    AddedComplexity = 1 in
1603def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1604                   "mov", ".w\t$Rd, $imm",
1605                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1606  let Inst{31-27} = 0b11110;
1607  let Inst{25} = 0;
1608  let Inst{24-21} = 0b0010;
1609  let Inst{19-16} = 0b1111; // Rn
1610  let Inst{15} = 0;
1611}
1612
1613def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1614                                                 pred:$p, cc_out:$s)>,
1615                Requires<[IsThumb2]>;
1616
1617let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1618def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
1619                   "movw", "\t$Rd, $imm",
1620                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1621  let Inst{31-27} = 0b11110;
1622  let Inst{25} = 1;
1623  let Inst{24-21} = 0b0010;
1624  let Inst{20} = 0; // The S bit.
1625  let Inst{15} = 0;
1626
1627  bits<4> Rd;
1628  bits<16> imm;
1629
1630  let Inst{11-8}  = Rd;
1631  let Inst{19-16} = imm{15-12};
1632  let Inst{26}    = imm{11};
1633  let Inst{14-12} = imm{10-8};
1634  let Inst{7-0}   = imm{7-0};
1635}
1636
1637def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1638                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1639
1640let Constraints = "$src = $Rd" in {
1641def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1642                    (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
1643                    "movt", "\t$Rd, $imm",
1644                    [(set rGPR:$Rd,
1645                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1646  let Inst{31-27} = 0b11110;
1647  let Inst{25} = 1;
1648  let Inst{24-21} = 0b0110;
1649  let Inst{20} = 0; // The S bit.
1650  let Inst{15} = 0;
1651
1652  bits<4> Rd;
1653  bits<16> imm;
1654
1655  let Inst{11-8}  = Rd;
1656  let Inst{19-16} = imm{15-12};
1657  let Inst{26}    = imm{11};
1658  let Inst{14-12} = imm{10-8};
1659  let Inst{7-0}   = imm{7-0};
1660}
1661
1662def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1663                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1664} // Constraints
1665
1666def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1667
1668//===----------------------------------------------------------------------===//
1669//  Extend Instructions.
1670//
1671
1672// Sign extenders
1673
1674defm t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1675                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1676defm t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1677                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1678defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1679
1680defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1681                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1682defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1683                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1684defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1685
1686// TODO: SXT(A){B|H}16 - done for disassembly only
1687
1688// Zero extenders
1689
1690let AddedComplexity = 16 in {
1691defm t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1692                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1693defm t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1694                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1695defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1696                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1697
1698// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1699//        The transformation should probably be done as a combiner action
1700//        instead so we can include a check for masking back in the upper
1701//        eight bits of the source into the lower eight bits of the result.
1702//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1703//            (t2UXTB16r_rot rGPR:$Src, 24)>,
1704//          Requires<[HasT2ExtractPack, IsThumb2]>;
1705def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1706            (t2UXTB16r_rot rGPR:$Src, 8)>,
1707        Requires<[HasT2ExtractPack, IsThumb2]>;
1708
1709defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1710                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1711defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1712                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1713defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1714}
1715
1716//===----------------------------------------------------------------------===//
1717//  Arithmetic Instructions.
1718//
1719
1720defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1721                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1722defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1723                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1724
1725// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1726defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1727                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1728                             BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1729defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1730                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1731                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1732
1733defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1734                          BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1735defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1736                          BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1737defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1738                                                             node:$RHS)>, 1>;
1739defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1740                                                             node:$RHS)>>;
1741
1742// RSB
1743defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1744                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1745defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1746                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1747
1748// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1749// The assume-no-carry-in form uses the negation of the input since add/sub
1750// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1751// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1752// details.
1753// The AddedComplexity preferences the first variant over the others since
1754// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1755let AddedComplexity = 1 in
1756def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1757            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1758def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1759            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1760def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1761            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1762let AddedComplexity = 1 in
1763def : T2Pat<(addc       rGPR:$src, imm0_255_neg:$imm),
1764            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1765def : T2Pat<(addc       rGPR:$src, t2_so_imm_neg:$imm),
1766            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1767// The with-carry-in form matches bitwise not instead of the negation.
1768// Effectively, the inverse interpretation of the carry flag already accounts
1769// for part of the negation.
1770let AddedComplexity = 1 in
1771def : T2Pat<(adde_dead_carry       rGPR:$src, imm0_255_not:$imm),
1772            (t2SBCri    rGPR:$src, imm0_255_not:$imm)>;
1773def : T2Pat<(adde_dead_carry       rGPR:$src, t2_so_imm_not:$imm),
1774            (t2SBCri    rGPR:$src, t2_so_imm_not:$imm)>;
1775let AddedComplexity = 1 in
1776def : T2Pat<(adde_live_carry       rGPR:$src, imm0_255_not:$imm),
1777            (t2SBCSri   rGPR:$src, imm0_255_not:$imm)>;
1778def : T2Pat<(adde_live_carry       rGPR:$src, t2_so_imm_not:$imm),
1779            (t2SBCSri   rGPR:$src, t2_so_imm_not:$imm)>;
1780
1781// Select Bytes -- for disassembly only
1782
1783def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1784                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1785          Requires<[IsThumb2, HasThumb2DSP]> {
1786  let Inst{31-27} = 0b11111;
1787  let Inst{26-24} = 0b010;
1788  let Inst{23} = 0b1;
1789  let Inst{22-20} = 0b010;
1790  let Inst{15-12} = 0b1111;
1791  let Inst{7} = 0b1;
1792  let Inst{6-4} = 0b000;
1793}
1794
1795// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1796// And Miscellaneous operations -- for disassembly only
1797class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1798              list<dag> pat = [/* For disassembly only; pattern left blank */],
1799              dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1800              string asm = "\t$Rd, $Rn, $Rm">
1801  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1802    Requires<[IsThumb2, HasThumb2DSP]> {
1803  let Inst{31-27} = 0b11111;
1804  let Inst{26-23} = 0b0101;
1805  let Inst{22-20} = op22_20;
1806  let Inst{15-12} = 0b1111;
1807  let Inst{7-4} = op7_4;
1808
1809  bits<4> Rd;
1810  bits<4> Rn;
1811  bits<4> Rm;
1812
1813  let Inst{11-8}  = Rd;
1814  let Inst{19-16} = Rn;
1815  let Inst{3-0}   = Rm;
1816}
1817
1818// Saturating add/subtract -- for disassembly only
1819
1820def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1821                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1822                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1823def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1824def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1825def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1826def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd", [],
1827                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1828def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub", [],
1829                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1830def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1831def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1832                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1833                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1834def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1835def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1836def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1837def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1838def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1839def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1840def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1841def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1842
1843// Signed/Unsigned add/subtract -- for disassembly only
1844
1845def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1846def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1847def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1848def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1849def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1850def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1851def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1852def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1853def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1854def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1855def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1856def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1857
1858// Signed/Unsigned halving add/subtract -- for disassembly only
1859
1860def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1861def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1862def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1863def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1864def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1865def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1866def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1867def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1868def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1869def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1870def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1871def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1872
1873// Helper class for disassembly only
1874// A6.3.16 & A6.3.17
1875// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1876class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1877  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1878  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1879  let Inst{31-27} = 0b11111;
1880  let Inst{26-24} = 0b011;
1881  let Inst{23}    = long;
1882  let Inst{22-20} = op22_20;
1883  let Inst{7-4}   = op7_4;
1884}
1885
1886class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1887  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1888  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1889  let Inst{31-27} = 0b11111;
1890  let Inst{26-24} = 0b011;
1891  let Inst{23}    = long;
1892  let Inst{22-20} = op22_20;
1893  let Inst{7-4}   = op7_4;
1894}
1895
1896// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1897
1898def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1899                                           (ins rGPR:$Rn, rGPR:$Rm),
1900                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1901          Requires<[IsThumb2, HasThumb2DSP]> {
1902  let Inst{15-12} = 0b1111;
1903}
1904def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1905                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1906                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1907          Requires<[IsThumb2, HasThumb2DSP]>;
1908
1909// Signed/Unsigned saturate -- for disassembly only
1910
1911class T2SatI<dag oops, dag iops, InstrItinClass itin,
1912           string opc, string asm, list<dag> pattern>
1913  : T2I<oops, iops, itin, opc, asm, pattern> {
1914  bits<4> Rd;
1915  bits<4> Rn;
1916  bits<5> sat_imm;
1917  bits<7> sh;
1918
1919  let Inst{11-8}  = Rd;
1920  let Inst{19-16} = Rn;
1921  let Inst{4-0}   = sat_imm{4-0};
1922  let Inst{21}    = sh{6};
1923  let Inst{14-12} = sh{4-2};
1924  let Inst{7-6}   = sh{1-0};
1925}
1926
1927def t2SSAT: T2SatI<
1928              (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1929              NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1930              [/* For disassembly only; pattern left blank */]> {
1931  let Inst{31-27} = 0b11110;
1932  let Inst{25-22} = 0b1100;
1933  let Inst{20} = 0;
1934  let Inst{15} = 0;
1935}
1936
1937def t2SSAT16: T2SatI<
1938                (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
1939                "ssat16", "\t$Rd, $sat_imm, $Rn",
1940                [/* For disassembly only; pattern left blank */]>,
1941          Requires<[IsThumb2, HasThumb2DSP]> {
1942  let Inst{31-27} = 0b11110;
1943  let Inst{25-22} = 0b1100;
1944  let Inst{20} = 0;
1945  let Inst{15} = 0;
1946  let Inst{21} = 1;        // sh = '1'
1947  let Inst{14-12} = 0b000; // imm3 = '000'
1948  let Inst{7-6} = 0b00;    // imm2 = '00'
1949}
1950
1951def t2USAT: T2SatI<
1952                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1953                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1954                [/* For disassembly only; pattern left blank */]> {
1955  let Inst{31-27} = 0b11110;
1956  let Inst{25-22} = 0b1110;
1957  let Inst{20} = 0;
1958  let Inst{15} = 0;
1959}
1960
1961def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
1962                     NoItinerary,
1963                     "usat16", "\t$dst, $sat_imm, $Rn",
1964                     [/* For disassembly only; pattern left blank */]>,
1965          Requires<[IsThumb2, HasThumb2DSP]> {
1966  let Inst{31-27} = 0b11110;
1967  let Inst{25-22} = 0b1110;
1968  let Inst{20} = 0;
1969  let Inst{15} = 0;
1970  let Inst{21} = 1;        // sh = '1'
1971  let Inst{14-12} = 0b000; // imm3 = '000'
1972  let Inst{7-6} = 0b00;    // imm2 = '00'
1973}
1974
1975def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1976def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1977
1978//===----------------------------------------------------------------------===//
1979//  Shift and rotate Instructions.
1980//
1981
1982defm t2LSL  : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
1983defm t2LSR  : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl  node:$LHS, node:$RHS)>>;
1984defm t2ASR  : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
1985defm t2ROR  : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1986
1987// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1988def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1989          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1990
1991let Uses = [CPSR] in {
1992def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1993                   "rrx", "\t$Rd, $Rm",
1994                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1995  let Inst{31-27} = 0b11101;
1996  let Inst{26-25} = 0b01;
1997  let Inst{24-21} = 0b0010;
1998  let Inst{19-16} = 0b1111; // Rn
1999  let Inst{14-12} = 0b000;
2000  let Inst{7-4} = 0b0011;
2001}
2002}
2003
2004let isCodeGenOnly = 1, Defs = [CPSR] in {
2005def t2MOVsrl_flag : T2TwoRegShiftImm<
2006                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2007                        "lsrs", ".w\t$Rd, $Rm, #1",
2008                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2009  let Inst{31-27} = 0b11101;
2010  let Inst{26-25} = 0b01;
2011  let Inst{24-21} = 0b0010;
2012  let Inst{20} = 1; // The S bit.
2013  let Inst{19-16} = 0b1111; // Rn
2014  let Inst{5-4} = 0b01; // Shift type.
2015  // Shift amount = Inst{14-12:7-6} = 1.
2016  let Inst{14-12} = 0b000;
2017  let Inst{7-6} = 0b01;
2018}
2019def t2MOVsra_flag : T2TwoRegShiftImm<
2020                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2021                        "asrs", ".w\t$Rd, $Rm, #1",
2022                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2023  let Inst{31-27} = 0b11101;
2024  let Inst{26-25} = 0b01;
2025  let Inst{24-21} = 0b0010;
2026  let Inst{20} = 1; // The S bit.
2027  let Inst{19-16} = 0b1111; // Rn
2028  let Inst{5-4} = 0b10; // Shift type.
2029  // Shift amount = Inst{14-12:7-6} = 1.
2030  let Inst{14-12} = 0b000;
2031  let Inst{7-6} = 0b01;
2032}
2033}
2034
2035//===----------------------------------------------------------------------===//
2036//  Bitwise Instructions.
2037//
2038
2039defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2040                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2041                            BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2042defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
2043                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2044                            BinOpFrag<(or  node:$LHS, node:$RHS)>, "t2ORR", 1>;
2045defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
2046                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2047                            BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2048
2049defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
2050                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2051                            BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2052                            "t2BIC">;
2053
2054class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2055              string opc, string asm, list<dag> pattern>
2056    : T2I<oops, iops, itin, opc, asm, pattern> {
2057  bits<4> Rd;
2058  bits<5> msb;
2059  bits<5> lsb;
2060
2061  let Inst{11-8}  = Rd;
2062  let Inst{4-0}   = msb{4-0};
2063  let Inst{14-12} = lsb{4-2};
2064  let Inst{7-6}   = lsb{1-0};
2065}
2066
2067class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2068              string opc, string asm, list<dag> pattern>
2069    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2070  bits<4> Rn;
2071
2072  let Inst{19-16} = Rn;
2073}
2074
2075let Constraints = "$src = $Rd" in
2076def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2077                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2078                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2079  let Inst{31-27} = 0b11110;
2080  let Inst{26} = 0; // should be 0.
2081  let Inst{25} = 1;
2082  let Inst{24-20} = 0b10110;
2083  let Inst{19-16} = 0b1111; // Rn
2084  let Inst{15} = 0;
2085  let Inst{5} = 0; // should be 0.
2086
2087  bits<10> imm;
2088  let msb{4-0} = imm{9-5};
2089  let lsb{4-0} = imm{4-0};
2090}
2091
2092def t2SBFX: T2TwoRegBitFI<
2093                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2094                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2095  let Inst{31-27} = 0b11110;
2096  let Inst{25} = 1;
2097  let Inst{24-20} = 0b10100;
2098  let Inst{15} = 0;
2099}
2100
2101def t2UBFX: T2TwoRegBitFI<
2102                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2103                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2104  let Inst{31-27} = 0b11110;
2105  let Inst{25} = 1;
2106  let Inst{24-20} = 0b11100;
2107  let Inst{15} = 0;
2108}
2109
2110// A8.6.18  BFI - Bitfield insert (Encoding T1)
2111let Constraints = "$src = $Rd" in {
2112  def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2113                  (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2114                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2115                  [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2116                                   bf_inv_mask_imm:$imm))]> {
2117    let Inst{31-27} = 0b11110;
2118    let Inst{26} = 0; // should be 0.
2119    let Inst{25} = 1;
2120    let Inst{24-20} = 0b10110;
2121    let Inst{15} = 0;
2122    let Inst{5} = 0; // should be 0.
2123
2124    bits<10> imm;
2125    let msb{4-0} = imm{9-5};
2126    let lsb{4-0} = imm{4-0};
2127  }
2128
2129  // GNU as only supports this form of bfi (w/ 4 arguments)
2130  let isAsmParserOnly = 1 in
2131  def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2132                  (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2133                       width_imm:$width),
2134                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2135                  []> {
2136    let Inst{31-27} = 0b11110;
2137    let Inst{26} = 0; // should be 0.
2138    let Inst{25} = 1;
2139    let Inst{24-20} = 0b10110;
2140    let Inst{15} = 0;
2141    let Inst{5} = 0; // should be 0.
2142
2143    bits<5> lsbit;
2144    bits<5> width;
2145    let msb{4-0} = width; // Custom encoder => lsb+width-1
2146    let lsb{4-0} = lsbit;
2147  }
2148}
2149
2150defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2151                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2152                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>,
2153                          "t2ORN", 0, "">;
2154
2155// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2156let AddedComplexity = 1 in
2157defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2158                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2159                          UnOpFrag<(not node:$Src)>, 1, 1>;
2160
2161
2162let AddedComplexity = 1 in
2163def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2164            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2165
2166// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2167def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2168            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2169            Requires<[IsThumb2]>;
2170
2171def : T2Pat<(t2_so_imm_not:$src),
2172            (t2MVNi t2_so_imm_not:$src)>;
2173
2174//===----------------------------------------------------------------------===//
2175//  Multiply Instructions.
2176//
2177let isCommutable = 1 in
2178def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2179                "mul", "\t$Rd, $Rn, $Rm",
2180                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2181  let Inst{31-27} = 0b11111;
2182  let Inst{26-23} = 0b0110;
2183  let Inst{22-20} = 0b000;
2184  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2185  let Inst{7-4} = 0b0000; // Multiply
2186}
2187
2188def t2MLA: T2FourReg<
2189                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2190                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2191                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2192  let Inst{31-27} = 0b11111;
2193  let Inst{26-23} = 0b0110;
2194  let Inst{22-20} = 0b000;
2195  let Inst{7-4} = 0b0000; // Multiply
2196}
2197
2198def t2MLS: T2FourReg<
2199                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2200                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2201                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2202  let Inst{31-27} = 0b11111;
2203  let Inst{26-23} = 0b0110;
2204  let Inst{22-20} = 0b000;
2205  let Inst{7-4} = 0b0001; // Multiply and Subtract
2206}
2207
2208// Extra precision multiplies with low / high results
2209let neverHasSideEffects = 1 in {
2210let isCommutable = 1 in {
2211def t2SMULL : T2MulLong<0b000, 0b0000,
2212                  (outs rGPR:$Rd, rGPR:$Ra),
2213                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2214                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2215
2216def t2UMULL : T2MulLong<0b010, 0b0000,
2217                  (outs rGPR:$RdLo, rGPR:$RdHi),
2218                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2219                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2220} // isCommutable
2221
2222// Multiply + accumulate
2223def t2SMLAL : T2MulLong<0b100, 0b0000,
2224                  (outs rGPR:$RdLo, rGPR:$RdHi),
2225                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2226                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2227
2228def t2UMLAL : T2MulLong<0b110, 0b0000,
2229                  (outs rGPR:$RdLo, rGPR:$RdHi),
2230                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2231                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2232
2233def t2UMAAL : T2MulLong<0b110, 0b0110,
2234                  (outs rGPR:$RdLo, rGPR:$RdHi),
2235                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2236                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2237          Requires<[IsThumb2, HasThumb2DSP]>;
2238} // neverHasSideEffects
2239
2240// Rounding variants of the below included for disassembly only
2241
2242// Most significant word multiply
2243def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2244                  "smmul", "\t$Rd, $Rn, $Rm",
2245                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2246          Requires<[IsThumb2, HasThumb2DSP]> {
2247  let Inst{31-27} = 0b11111;
2248  let Inst{26-23} = 0b0110;
2249  let Inst{22-20} = 0b101;
2250  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2251  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2252}
2253
2254def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2255                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
2256          Requires<[IsThumb2, HasThumb2DSP]> {
2257  let Inst{31-27} = 0b11111;
2258  let Inst{26-23} = 0b0110;
2259  let Inst{22-20} = 0b101;
2260  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2261  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2262}
2263
2264def t2SMMLA : T2FourReg<
2265        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2266                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2267                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2268          Requires<[IsThumb2, HasThumb2DSP]> {
2269  let Inst{31-27} = 0b11111;
2270  let Inst{26-23} = 0b0110;
2271  let Inst{22-20} = 0b101;
2272  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2273}
2274
2275def t2SMMLAR: T2FourReg<
2276        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2277                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2278          Requires<[IsThumb2, HasThumb2DSP]> {
2279  let Inst{31-27} = 0b11111;
2280  let Inst{26-23} = 0b0110;
2281  let Inst{22-20} = 0b101;
2282  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2283}
2284
2285def t2SMMLS: T2FourReg<
2286        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2287                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2288                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2289          Requires<[IsThumb2, HasThumb2DSP]> {
2290  let Inst{31-27} = 0b11111;
2291  let Inst{26-23} = 0b0110;
2292  let Inst{22-20} = 0b110;
2293  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2294}
2295
2296def t2SMMLSR:T2FourReg<
2297        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2298                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2299          Requires<[IsThumb2, HasThumb2DSP]> {
2300  let Inst{31-27} = 0b11111;
2301  let Inst{26-23} = 0b0110;
2302  let Inst{22-20} = 0b110;
2303  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2304}
2305
2306multiclass T2I_smul<string opc, PatFrag opnode> {
2307  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2308              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2309              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2310                                      (sext_inreg rGPR:$Rm, i16)))]>,
2311          Requires<[IsThumb2, HasThumb2DSP]> {
2312    let Inst{31-27} = 0b11111;
2313    let Inst{26-23} = 0b0110;
2314    let Inst{22-20} = 0b001;
2315    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2316    let Inst{7-6} = 0b00;
2317    let Inst{5-4} = 0b00;
2318  }
2319
2320  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2321              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2322              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2323                                      (sra rGPR:$Rm, (i32 16))))]>,
2324          Requires<[IsThumb2, HasThumb2DSP]> {
2325    let Inst{31-27} = 0b11111;
2326    let Inst{26-23} = 0b0110;
2327    let Inst{22-20} = 0b001;
2328    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2329    let Inst{7-6} = 0b00;
2330    let Inst{5-4} = 0b01;
2331  }
2332
2333  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2334              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2335              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2336                                      (sext_inreg rGPR:$Rm, i16)))]>,
2337          Requires<[IsThumb2, HasThumb2DSP]> {
2338    let Inst{31-27} = 0b11111;
2339    let Inst{26-23} = 0b0110;
2340    let Inst{22-20} = 0b001;
2341    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2342    let Inst{7-6} = 0b00;
2343    let Inst{5-4} = 0b10;
2344  }
2345
2346  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2347              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2348              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2349                                      (sra rGPR:$Rm, (i32 16))))]>,
2350          Requires<[IsThumb2, HasThumb2DSP]> {
2351    let Inst{31-27} = 0b11111;
2352    let Inst{26-23} = 0b0110;
2353    let Inst{22-20} = 0b001;
2354    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2355    let Inst{7-6} = 0b00;
2356    let Inst{5-4} = 0b11;
2357  }
2358
2359  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2360              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2361              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2362                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2363          Requires<[IsThumb2, HasThumb2DSP]> {
2364    let Inst{31-27} = 0b11111;
2365    let Inst{26-23} = 0b0110;
2366    let Inst{22-20} = 0b011;
2367    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2368    let Inst{7-6} = 0b00;
2369    let Inst{5-4} = 0b00;
2370  }
2371
2372  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2373              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2374              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2375                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2376          Requires<[IsThumb2, HasThumb2DSP]> {
2377    let Inst{31-27} = 0b11111;
2378    let Inst{26-23} = 0b0110;
2379    let Inst{22-20} = 0b011;
2380    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2381    let Inst{7-6} = 0b00;
2382    let Inst{5-4} = 0b01;
2383  }
2384}
2385
2386
2387multiclass T2I_smla<string opc, PatFrag opnode> {
2388  def BB : T2FourReg<
2389        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2390              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2391              [(set rGPR:$Rd, (add rGPR:$Ra,
2392                               (opnode (sext_inreg rGPR:$Rn, i16),
2393                                       (sext_inreg rGPR:$Rm, i16))))]>,
2394          Requires<[IsThumb2, HasThumb2DSP]> {
2395    let Inst{31-27} = 0b11111;
2396    let Inst{26-23} = 0b0110;
2397    let Inst{22-20} = 0b001;
2398    let Inst{7-6} = 0b00;
2399    let Inst{5-4} = 0b00;
2400  }
2401
2402  def BT : T2FourReg<
2403       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2404             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2405             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2406                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2407          Requires<[IsThumb2, HasThumb2DSP]> {
2408    let Inst{31-27} = 0b11111;
2409    let Inst{26-23} = 0b0110;
2410    let Inst{22-20} = 0b001;
2411    let Inst{7-6} = 0b00;
2412    let Inst{5-4} = 0b01;
2413  }
2414
2415  def TB : T2FourReg<
2416        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2417              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2418              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2419                                               (sext_inreg rGPR:$Rm, i16))))]>,
2420          Requires<[IsThumb2, HasThumb2DSP]> {
2421    let Inst{31-27} = 0b11111;
2422    let Inst{26-23} = 0b0110;
2423    let Inst{22-20} = 0b001;
2424    let Inst{7-6} = 0b00;
2425    let Inst{5-4} = 0b10;
2426  }
2427
2428  def TT : T2FourReg<
2429        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2430              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2431             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2432                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2433          Requires<[IsThumb2, HasThumb2DSP]> {
2434    let Inst{31-27} = 0b11111;
2435    let Inst{26-23} = 0b0110;
2436    let Inst{22-20} = 0b001;
2437    let Inst{7-6} = 0b00;
2438    let Inst{5-4} = 0b11;
2439  }
2440
2441  def WB : T2FourReg<
2442        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2443              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2444              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2445                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2446          Requires<[IsThumb2, HasThumb2DSP]> {
2447    let Inst{31-27} = 0b11111;
2448    let Inst{26-23} = 0b0110;
2449    let Inst{22-20} = 0b011;
2450    let Inst{7-6} = 0b00;
2451    let Inst{5-4} = 0b00;
2452  }
2453
2454  def WT : T2FourReg<
2455        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2456              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2457              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2458                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2459          Requires<[IsThumb2, HasThumb2DSP]> {
2460    let Inst{31-27} = 0b11111;
2461    let Inst{26-23} = 0b0110;
2462    let Inst{22-20} = 0b011;
2463    let Inst{7-6} = 0b00;
2464    let Inst{5-4} = 0b01;
2465  }
2466}
2467
2468defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2469defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2470
2471// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2472def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2473         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2474           [/* For disassembly only; pattern left blank */]>,
2475          Requires<[IsThumb2, HasThumb2DSP]>;
2476def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2477         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2478           [/* For disassembly only; pattern left blank */]>,
2479          Requires<[IsThumb2, HasThumb2DSP]>;
2480def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2481         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2482           [/* For disassembly only; pattern left blank */]>,
2483          Requires<[IsThumb2, HasThumb2DSP]>;
2484def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2485         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2486           [/* For disassembly only; pattern left blank */]>,
2487          Requires<[IsThumb2, HasThumb2DSP]>;
2488
2489// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2490// These are for disassembly only.
2491
2492def t2SMUAD: T2ThreeReg_mac<
2493            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2494            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2495          Requires<[IsThumb2, HasThumb2DSP]> {
2496  let Inst{15-12} = 0b1111;
2497}
2498def t2SMUADX:T2ThreeReg_mac<
2499            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2500            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2501          Requires<[IsThumb2, HasThumb2DSP]> {
2502  let Inst{15-12} = 0b1111;
2503}
2504def t2SMUSD: T2ThreeReg_mac<
2505            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2506            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2507          Requires<[IsThumb2, HasThumb2DSP]> {
2508  let Inst{15-12} = 0b1111;
2509}
2510def t2SMUSDX:T2ThreeReg_mac<
2511            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2512            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2513          Requires<[IsThumb2, HasThumb2DSP]> {
2514  let Inst{15-12} = 0b1111;
2515}
2516def t2SMLAD   : T2ThreeReg_mac<
2517            0, 0b010, 0b0000, (outs rGPR:$Rd),
2518            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2519            "\t$Rd, $Rn, $Rm, $Ra", []>,
2520          Requires<[IsThumb2, HasThumb2DSP]>;
2521def t2SMLADX  : T2FourReg_mac<
2522            0, 0b010, 0b0001, (outs rGPR:$Rd),
2523            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2524            "\t$Rd, $Rn, $Rm, $Ra", []>,
2525          Requires<[IsThumb2, HasThumb2DSP]>;
2526def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2527            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2528            "\t$Rd, $Rn, $Rm, $Ra", []>,
2529          Requires<[IsThumb2, HasThumb2DSP]>;
2530def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2531            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2532            "\t$Rd, $Rn, $Rm, $Ra", []>,
2533          Requires<[IsThumb2, HasThumb2DSP]>;
2534def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2535                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2536                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2537          Requires<[IsThumb2, HasThumb2DSP]>;
2538def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2539                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2540                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2541          Requires<[IsThumb2, HasThumb2DSP]>;
2542def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2543                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2544                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2545          Requires<[IsThumb2, HasThumb2DSP]>;
2546def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2547                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2548                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2549          Requires<[IsThumb2, HasThumb2DSP]>;
2550
2551//===----------------------------------------------------------------------===//
2552//  Division Instructions.
2553//  Signed and unsigned division on v7-M
2554//
2555def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2556                 "sdiv", "\t$Rd, $Rn, $Rm",
2557                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2558                 Requires<[HasDivide, IsThumb2]> {
2559  let Inst{31-27} = 0b11111;
2560  let Inst{26-21} = 0b011100;
2561  let Inst{20} = 0b1;
2562  let Inst{15-12} = 0b1111;
2563  let Inst{7-4} = 0b1111;
2564}
2565
2566def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2567                 "udiv", "\t$Rd, $Rn, $Rm",
2568                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2569                 Requires<[HasDivide, IsThumb2]> {
2570  let Inst{31-27} = 0b11111;
2571  let Inst{26-21} = 0b011101;
2572  let Inst{20} = 0b1;
2573  let Inst{15-12} = 0b1111;
2574  let Inst{7-4} = 0b1111;
2575}
2576
2577//===----------------------------------------------------------------------===//
2578//  Misc. Arithmetic Instructions.
2579//
2580
2581class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2582      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2583  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2584  let Inst{31-27} = 0b11111;
2585  let Inst{26-22} = 0b01010;
2586  let Inst{21-20} = op1;
2587  let Inst{15-12} = 0b1111;
2588  let Inst{7-6} = 0b10;
2589  let Inst{5-4} = op2;
2590  let Rn{3-0} = Rm;
2591}
2592
2593def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2594                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2595
2596def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2597                      "rbit", "\t$Rd, $Rm",
2598                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2599
2600def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2601                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2602
2603def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2604                       "rev16", ".w\t$Rd, $Rm",
2605                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2606
2607def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2608                       "revsh", ".w\t$Rd, $Rm",
2609                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2610
2611def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2612                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2613            (t2REVSH rGPR:$Rm)>;
2614
2615def t2PKHBT : T2ThreeReg<
2616            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2617                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2618                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2619                                      (and (shl rGPR:$Rm, lsl_amt:$sh),
2620                                           0xFFFF0000)))]>,
2621                  Requires<[HasT2ExtractPack, IsThumb2]> {
2622  let Inst{31-27} = 0b11101;
2623  let Inst{26-25} = 0b01;
2624  let Inst{24-20} = 0b01100;
2625  let Inst{5} = 0; // BT form
2626  let Inst{4} = 0;
2627
2628  bits<8> sh;
2629  let Inst{14-12} = sh{7-5};
2630  let Inst{7-6}   = sh{4-3};
2631}
2632
2633// Alternate cases for PKHBT where identities eliminate some nodes.
2634def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2635            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2636            Requires<[HasT2ExtractPack, IsThumb2]>;
2637def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2638            (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2639            Requires<[HasT2ExtractPack, IsThumb2]>;
2640
2641// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2642// will match the pattern below.
2643def t2PKHTB : T2ThreeReg<
2644                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2645                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2646                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2647                                       (and (sra rGPR:$Rm, asr_amt:$sh),
2648                                            0xFFFF)))]>,
2649                  Requires<[HasT2ExtractPack, IsThumb2]> {
2650  let Inst{31-27} = 0b11101;
2651  let Inst{26-25} = 0b01;
2652  let Inst{24-20} = 0b01100;
2653  let Inst{5} = 1; // TB form
2654  let Inst{4} = 0;
2655
2656  bits<8> sh;
2657  let Inst{14-12} = sh{7-5};
2658  let Inst{7-6}   = sh{4-3};
2659}
2660
2661// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2662// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2663def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2664            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2665            Requires<[HasT2ExtractPack, IsThumb2]>;
2666def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2667                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2668            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2669            Requires<[HasT2ExtractPack, IsThumb2]>;
2670
2671//===----------------------------------------------------------------------===//
2672//  Comparison Instructions...
2673//
2674defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2675                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2676                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2677
2678def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_imm:$imm),
2679            (t2CMPri  GPR:$lhs, t2_so_imm:$imm)>;
2680def : T2Pat<(ARMcmpZ  GPR:$lhs, rGPR:$rhs),
2681            (t2CMPrr  GPR:$lhs, rGPR:$rhs)>;
2682def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_reg:$rhs),
2683            (t2CMPrs  GPR:$lhs, t2_so_reg:$rhs)>;
2684
2685//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2686//       Compare-to-zero still works out, just not the relationals
2687//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2688//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2689defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2690                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2691                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2692
2693//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2694//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2695
2696def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
2697            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2698
2699defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2700                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2701                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2702defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2703                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2704                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2705
2706// Conditional moves
2707// FIXME: should be able to write a pattern for ARMcmov, but can't use
2708// a two-value operand where a dag node expects two operands. :(
2709let neverHasSideEffects = 1 in {
2710def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2711                            (ins rGPR:$false, rGPR:$Rm, pred:$p),
2712                            Size4Bytes, IIC_iCMOVr,
2713   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2714                RegConstraint<"$false = $Rd">;
2715
2716let isMoveImm = 1 in
2717def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2718                            (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2719                   Size4Bytes, IIC_iCMOVi,
2720[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2721                   RegConstraint<"$false = $Rd">;
2722
2723// FIXME: Pseudo-ize these. For now, just mark codegen only.
2724let isCodeGenOnly = 1 in {
2725let isMoveImm = 1 in
2726def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
2727                      IIC_iCMOVi,
2728                      "movw", "\t$Rd, $imm", []>,
2729                      RegConstraint<"$false = $Rd"> {
2730  let Inst{31-27} = 0b11110;
2731  let Inst{25} = 1;
2732  let Inst{24-21} = 0b0010;
2733  let Inst{20} = 0; // The S bit.
2734  let Inst{15} = 0;
2735
2736  bits<4> Rd;
2737  bits<16> imm;
2738
2739  let Inst{11-8}  = Rd;
2740  let Inst{19-16} = imm{15-12};
2741  let Inst{26}    = imm{11};
2742  let Inst{14-12} = imm{10-8};
2743  let Inst{7-0}   = imm{7-0};
2744}
2745
2746let isMoveImm = 1 in
2747def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2748                               (ins rGPR:$false, i32imm:$src, pred:$p),
2749                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2750
2751let isMoveImm = 1 in
2752def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2753                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2754[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2755                   imm:$cc, CCR:$ccr))*/]>,
2756                   RegConstraint<"$false = $Rd"> {
2757  let Inst{31-27} = 0b11110;
2758  let Inst{25} = 0;
2759  let Inst{24-21} = 0b0011;
2760  let Inst{20} = 0; // The S bit.
2761  let Inst{19-16} = 0b1111; // Rn
2762  let Inst{15} = 0;
2763}
2764
2765class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2766                   string opc, string asm, list<dag> pattern>
2767  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2768  let Inst{31-27} = 0b11101;
2769  let Inst{26-25} = 0b01;
2770  let Inst{24-21} = 0b0010;
2771  let Inst{20} = 0; // The S bit.
2772  let Inst{19-16} = 0b1111; // Rn
2773  let Inst{5-4} = opcod; // Shift type.
2774}
2775def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2776                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2777                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2778                 RegConstraint<"$false = $Rd">;
2779def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2780                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2781                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2782                 RegConstraint<"$false = $Rd">;
2783def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2784                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2785                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2786                 RegConstraint<"$false = $Rd">;
2787def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2788                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2789                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2790                 RegConstraint<"$false = $Rd">;
2791} // isCodeGenOnly = 1
2792} // neverHasSideEffects
2793
2794//===----------------------------------------------------------------------===//
2795// Atomic operations intrinsics
2796//
2797
2798// memory barriers protect the atomic sequences
2799let hasSideEffects = 1 in {
2800def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2801                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2802                  Requires<[IsThumb, HasDB]> {
2803  bits<4> opt;
2804  let Inst{31-4} = 0xf3bf8f5;
2805  let Inst{3-0} = opt;
2806}
2807}
2808
2809def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2810                  "dsb", "\t$opt",
2811                  [/* For disassembly only; pattern left blank */]>,
2812                  Requires<[IsThumb, HasDB]> {
2813  bits<4> opt;
2814  let Inst{31-4} = 0xf3bf8f4;
2815  let Inst{3-0} = opt;
2816}
2817
2818// ISB has only full system option -- for disassembly only
2819def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2820                  [/* For disassembly only; pattern left blank */]>,
2821                  Requires<[IsThumb2, HasV7]> {
2822  let Inst{31-4} = 0xf3bf8f6;
2823  let Inst{3-0} = 0b1111;
2824}
2825
2826class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2827                InstrItinClass itin, string opc, string asm, string cstr,
2828                list<dag> pattern, bits<4> rt2 = 0b1111>
2829  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2830  let Inst{31-27} = 0b11101;
2831  let Inst{26-20} = 0b0001101;
2832  let Inst{11-8} = rt2;
2833  let Inst{7-6} = 0b01;
2834  let Inst{5-4} = opcod;
2835  let Inst{3-0} = 0b1111;
2836
2837  bits<4> addr;
2838  bits<4> Rt;
2839  let Inst{19-16} = addr;
2840  let Inst{15-12} = Rt;
2841}
2842class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2843                InstrItinClass itin, string opc, string asm, string cstr,
2844                list<dag> pattern, bits<4> rt2 = 0b1111>
2845  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2846  let Inst{31-27} = 0b11101;
2847  let Inst{26-20} = 0b0001100;
2848  let Inst{11-8} = rt2;
2849  let Inst{7-6} = 0b01;
2850  let Inst{5-4} = opcod;
2851
2852  bits<4> Rd;
2853  bits<4> addr;
2854  bits<4> Rt;
2855  let Inst{3-0}  = Rd;
2856  let Inst{19-16} = addr;
2857  let Inst{15-12} = Rt;
2858}
2859
2860let mayLoad = 1 in {
2861def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2862                         AddrModeNone, Size4Bytes, NoItinerary,
2863                         "ldrexb", "\t$Rt, $addr", "", []>;
2864def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2865                         AddrModeNone, Size4Bytes, NoItinerary,
2866                         "ldrexh", "\t$Rt, $addr", "", []>;
2867def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2868                       AddrModeNone, Size4Bytes, NoItinerary,
2869                       "ldrex", "\t$Rt, $addr", "", []> {
2870  let Inst{31-27} = 0b11101;
2871  let Inst{26-20} = 0b0000101;
2872  let Inst{11-8} = 0b1111;
2873  let Inst{7-0} = 0b00000000; // imm8 = 0
2874
2875  bits<4> Rt;
2876  bits<4> addr;
2877  let Inst{19-16} = addr;
2878  let Inst{15-12} = Rt;
2879}
2880let hasExtraDefRegAllocReq = 1 in
2881def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2882                         (ins t2addrmode_reg:$addr),
2883                         AddrModeNone, Size4Bytes, NoItinerary,
2884                         "ldrexd", "\t$Rt, $Rt2, $addr", "",
2885                         [], {?, ?, ?, ?}> {
2886  bits<4> Rt2;
2887  let Inst{11-8} = Rt2;
2888}
2889}
2890
2891let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2892def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2893                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2894                         AddrModeNone, Size4Bytes, NoItinerary,
2895                         "strexb", "\t$Rd, $Rt, $addr", "", []>;
2896def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2897                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2898                         AddrModeNone, Size4Bytes, NoItinerary,
2899                         "strexh", "\t$Rd, $Rt, $addr", "", []>;
2900def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2901                  AddrModeNone, Size4Bytes, NoItinerary,
2902                  "strex", "\t$Rd, $Rt, $addr", "",
2903                  []> {
2904  let Inst{31-27} = 0b11101;
2905  let Inst{26-20} = 0b0000100;
2906  let Inst{7-0} = 0b00000000; // imm8 = 0
2907
2908  bits<4> Rd;
2909  bits<4> addr;
2910  bits<4> Rt;
2911  let Inst{11-8}  = Rd;
2912  let Inst{19-16} = addr;
2913  let Inst{15-12} = Rt;
2914}
2915}
2916
2917let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2918def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2919                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2920                         AddrModeNone, Size4Bytes, NoItinerary,
2921                         "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2922                         {?, ?, ?, ?}> {
2923  bits<4> Rt2;
2924  let Inst{11-8} = Rt2;
2925}
2926
2927// Clear-Exclusive is for disassembly only.
2928def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2929                   [/* For disassembly only; pattern left blank */]>,
2930            Requires<[IsThumb2, HasV7]>  {
2931  let Inst{31-16} = 0xf3bf;
2932  let Inst{15-14} = 0b10;
2933  let Inst{13} = 0;
2934  let Inst{12} = 0;
2935  let Inst{11-8} = 0b1111;
2936  let Inst{7-4} = 0b0010;
2937  let Inst{3-0} = 0b1111;
2938}
2939
2940//===----------------------------------------------------------------------===//
2941// SJLJ Exception handling intrinsics
2942//   eh_sjlj_setjmp() is an instruction sequence to store the return
2943//   address and save #0 in R0 for the non-longjmp case.
2944//   Since by its nature we may be coming from some other function to get
2945//   here, and we're using the stack frame for the containing function to
2946//   save/restore registers, we can't keep anything live in regs across
2947//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2948//   when we get here from a longjmp(). We force everything out of registers
2949//   except for our own input by listing the relevant registers in Defs. By
2950//   doing so, we also cause the prologue/epilogue code to actively preserve
2951//   all of the callee-saved resgisters, which is exactly what we want.
2952//   $val is a scratch register for our use.
2953let Defs =
2954  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
2955    QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2956  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2957  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2958                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2959                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2960                             Requires<[IsThumb2, HasVFP2]>;
2961}
2962
2963let Defs =
2964  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
2965  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2966  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2967                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2968                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2969                                  Requires<[IsThumb2, NoVFP]>;
2970}
2971
2972
2973//===----------------------------------------------------------------------===//
2974// Control-Flow Instructions
2975//
2976
2977// FIXME: remove when we have a way to marking a MI with these properties.
2978// FIXME: Should pc be an implicit operand like PICADD, etc?
2979let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2980    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2981def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2982                                                   reglist:$regs, variable_ops),
2983                              Size4Bytes, IIC_iLoad_mBr, [],
2984            (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2985                         RegConstraint<"$Rn = $wb">;
2986
2987let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2988let isPredicable = 1 in
2989def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2990                 "b.w\t$target",
2991                 [(br bb:$target)]> {
2992  let Inst{31-27} = 0b11110;
2993  let Inst{15-14} = 0b10;
2994  let Inst{12} = 1;
2995
2996  bits<20> target;
2997  let Inst{26} = target{19};
2998  let Inst{11} = target{18};
2999  let Inst{13} = target{17};
3000  let Inst{21-16} = target{16-11};
3001  let Inst{10-0} = target{10-0};
3002}
3003
3004let isNotDuplicable = 1, isIndirectBranch = 1 in {
3005def t2BR_JT : t2PseudoInst<(outs),
3006          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3007           SizeSpecial, IIC_Br,
3008          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3009
3010// FIXME: Add a non-pc based case that can be predicated.
3011def t2TBB_JT : t2PseudoInst<(outs),
3012        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3013         SizeSpecial, IIC_Br, []>;
3014
3015def t2TBH_JT : t2PseudoInst<(outs),
3016        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3017         SizeSpecial, IIC_Br, []>;
3018
3019def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3020                    "tbb", "\t[$Rn, $Rm]", []> {
3021  bits<4> Rn;
3022  bits<4> Rm;
3023  let Inst{31-20} = 0b111010001101;
3024  let Inst{19-16} = Rn;
3025  let Inst{15-5} = 0b11110000000;
3026  let Inst{4} = 0; // B form
3027  let Inst{3-0} = Rm;
3028}
3029
3030def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3031                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3032  bits<4> Rn;
3033  bits<4> Rm;
3034  let Inst{31-20} = 0b111010001101;
3035  let Inst{19-16} = Rn;
3036  let Inst{15-5} = 0b11110000000;
3037  let Inst{4} = 1; // H form
3038  let Inst{3-0} = Rm;
3039}
3040} // isNotDuplicable, isIndirectBranch
3041
3042} // isBranch, isTerminator, isBarrier
3043
3044// FIXME: should be able to write a pattern for ARMBrcond, but can't use
3045// a two-value operand where a dag node expects two operands. :(
3046let isBranch = 1, isTerminator = 1 in
3047def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3048                "b", ".w\t$target",
3049                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3050  let Inst{31-27} = 0b11110;
3051  let Inst{15-14} = 0b10;
3052  let Inst{12} = 0;
3053
3054  bits<4> p;
3055  let Inst{25-22} = p;
3056
3057  bits<21> target;
3058  let Inst{26} = target{20};
3059  let Inst{11} = target{19};
3060  let Inst{13} = target{18};
3061  let Inst{21-16} = target{17-12};
3062  let Inst{10-0} = target{11-1};
3063}
3064
3065// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3066// it goes here.
3067let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3068  // Darwin version.
3069  let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3070      Uses = [SP] in
3071  def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3072                   Size4Bytes, IIC_Br, [],
3073                   (t2B uncondbrtarget:$dst)>,
3074                 Requires<[IsThumb2, IsDarwin]>;
3075}
3076
3077// IT block
3078let Defs = [ITSTATE] in
3079def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3080                    AddrModeNone, Size2Bytes,  IIC_iALUx,
3081                    "it$mask\t$cc", "", []> {
3082  // 16-bit instruction.
3083  let Inst{31-16} = 0x0000;
3084  let Inst{15-8} = 0b10111111;
3085
3086  bits<4> cc;
3087  bits<4> mask;
3088  let Inst{7-4} = cc;
3089  let Inst{3-0} = mask;
3090}
3091
3092// Branch and Exchange Jazelle -- for disassembly only
3093// Rm = Inst{19-16}
3094def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3095              [/* For disassembly only; pattern left blank */]> {
3096  let Inst{31-27} = 0b11110;
3097  let Inst{26} = 0;
3098  let Inst{25-20} = 0b111100;
3099  let Inst{15-14} = 0b10;
3100  let Inst{12} = 0;
3101
3102  bits<4> func;
3103  let Inst{19-16} = func;
3104}
3105
3106// Change Processor State is a system instruction -- for disassembly and
3107// parsing only.
3108// FIXME: Since the asm parser has currently no clean way to handle optional
3109// operands, create 3 versions of the same instruction. Once there's a clean
3110// framework to represent optional operands, change this behavior.
3111class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3112            !strconcat("cps", asm_op),
3113            [/* For disassembly only; pattern left blank */]> {
3114  bits<2> imod;
3115  bits<3> iflags;
3116  bits<5> mode;
3117  bit M;
3118
3119  let Inst{31-27} = 0b11110;
3120  let Inst{26}    = 0;
3121  let Inst{25-20} = 0b111010;
3122  let Inst{19-16} = 0b1111;
3123  let Inst{15-14} = 0b10;
3124  let Inst{12}    = 0;
3125  let Inst{10-9}  = imod;
3126  let Inst{8}     = M;
3127  let Inst{7-5}   = iflags;
3128  let Inst{4-0}   = mode;
3129}
3130
3131let M = 1 in
3132  def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3133                      "$imod.w\t$iflags, $mode">;
3134let mode = 0, M = 0 in
3135  def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3136                      "$imod.w\t$iflags">;
3137let imod = 0, iflags = 0, M = 1 in
3138  def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3139
3140// A6.3.4 Branches and miscellaneous control
3141// Table A6-14 Change Processor State, and hint instructions
3142// Helper class for disassembly only.
3143class T2I_hint<bits<8> op7_0, string opc, string asm>
3144  : T2I<(outs), (ins), NoItinerary, opc, asm,
3145        [/* For disassembly only; pattern left blank */]> {
3146  let Inst{31-20} = 0xf3a;
3147  let Inst{19-16} = 0b1111;
3148  let Inst{15-14} = 0b10;
3149  let Inst{12} = 0;
3150  let Inst{10-8} = 0b000;
3151  let Inst{7-0} = op7_0;
3152}
3153
3154def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3155def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3156def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3157def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3158def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3159
3160def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3161                [/* For disassembly only; pattern left blank */]> {
3162  let Inst{31-20} = 0xf3a;
3163  let Inst{15-14} = 0b10;
3164  let Inst{12} = 0;
3165  let Inst{10-8} = 0b000;
3166  let Inst{7-4} = 0b1111;
3167
3168  bits<4> opt;
3169  let Inst{3-0} = opt;
3170}
3171
3172// Secure Monitor Call is a system instruction -- for disassembly only
3173// Option = Inst{19-16}
3174def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3175                [/* For disassembly only; pattern left blank */]> {
3176  let Inst{31-27} = 0b11110;
3177  let Inst{26-20} = 0b1111111;
3178  let Inst{15-12} = 0b1000;
3179
3180  bits<4> opt;
3181  let Inst{19-16} = opt;
3182}
3183
3184class T2SRS<bits<12> op31_20,
3185           dag oops, dag iops, InstrItinClass itin,
3186          string opc, string asm, list<dag> pattern>
3187  : T2I<oops, iops, itin, opc, asm, pattern> {
3188  let Inst{31-20} = op31_20{11-0};
3189
3190  bits<5> mode;
3191  let Inst{4-0} = mode{4-0};
3192}
3193
3194// Store Return State is a system instruction -- for disassembly only
3195def t2SRSDBW : T2SRS<0b111010000010,
3196                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3197                   [/* For disassembly only; pattern left blank */]>;
3198def t2SRSDB  : T2SRS<0b111010000000,
3199                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3200                   [/* For disassembly only; pattern left blank */]>;
3201def t2SRSIAW : T2SRS<0b111010011010,
3202                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3203                   [/* For disassembly only; pattern left blank */]>;
3204def t2SRSIA  : T2SRS<0b111010011000,
3205                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3206                   [/* For disassembly only; pattern left blank */]>;
3207
3208// Return From Exception is a system instruction -- for disassembly only
3209
3210class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3211          string opc, string asm, list<dag> pattern>
3212  : T2I<oops, iops, itin, opc, asm, pattern> {
3213  let Inst{31-20} = op31_20{11-0};
3214
3215  bits<4> Rn;
3216  let Inst{19-16} = Rn;
3217  let Inst{15-0} = 0xc000;
3218}
3219
3220def t2RFEDBW : T2RFE<0b111010000011,
3221                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3222                   [/* For disassembly only; pattern left blank */]>;
3223def t2RFEDB  : T2RFE<0b111010000001,
3224                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3225                   [/* For disassembly only; pattern left blank */]>;
3226def t2RFEIAW : T2RFE<0b111010011011,
3227                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3228                   [/* For disassembly only; pattern left blank */]>;
3229def t2RFEIA  : T2RFE<0b111010011001,
3230                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3231                   [/* For disassembly only; pattern left blank */]>;
3232
3233//===----------------------------------------------------------------------===//
3234// Non-Instruction Patterns
3235//
3236
3237// 32-bit immediate using movw + movt.
3238// This is a single pseudo instruction to make it re-materializable.
3239// FIXME: Remove this when we can do generalized remat.
3240let isReMaterializable = 1, isMoveImm = 1 in
3241def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3242                            [(set rGPR:$dst, (i32 imm:$src))]>,
3243                            Requires<[IsThumb, HasV6T2]>;
3244
3245// Pseudo instruction that combines movw + movt + add pc (if pic).
3246// It also makes it possible to rematerialize the instructions.
3247// FIXME: Remove this when we can do generalized remat and when machine licm
3248// can properly the instructions.
3249let isReMaterializable = 1 in {
3250def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3251                                IIC_iMOVix2addpc,
3252                          [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3253                          Requires<[IsThumb2, UseMovt]>;
3254
3255def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3256                              IIC_iMOVix2,
3257                          [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3258                          Requires<[IsThumb2, UseMovt]>;
3259}
3260
3261// ConstantPool, GlobalAddress, and JumpTable
3262def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3263           Requires<[IsThumb2, DontUseMovt]>;
3264def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3265def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3266           Requires<[IsThumb2, UseMovt]>;
3267
3268def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3269            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3270
3271// Pseudo instruction that combines ldr from constpool and add pc. This should
3272// be expanded into two instructions late to allow if-conversion and
3273// scheduling.
3274let canFoldAsLoad = 1, isReMaterializable = 1 in
3275def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3276                   IIC_iLoadiALU,
3277              [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3278                                           imm:$cp))]>,
3279               Requires<[IsThumb2]>;
3280
3281//===----------------------------------------------------------------------===//
3282// Move between special register and ARM core register -- for disassembly only
3283//
3284
3285class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3286          dag oops, dag iops, InstrItinClass itin,
3287          string opc, string asm, list<dag> pattern>
3288  : T2I<oops, iops, itin, opc, asm, pattern> {
3289  let Inst{31-20} = op31_20{11-0};
3290  let Inst{15-14} = op15_14{1-0};
3291  let Inst{12} = op12{0};
3292}
3293
3294class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3295          dag oops, dag iops, InstrItinClass itin,
3296          string opc, string asm, list<dag> pattern>
3297  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3298  bits<4> Rd;
3299  let Inst{11-8} = Rd;
3300  let Inst{19-16} = 0b1111;
3301}
3302
3303def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3304                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3305                [/* For disassembly only; pattern left blank */]>;
3306def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3307                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3308                   [/* For disassembly only; pattern left blank */]>;
3309
3310// Move from ARM core register to Special Register
3311//
3312// No need to have both system and application versions, the encodings are the
3313// same and the assembly parser has no way to distinguish between them. The mask
3314// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3315// the mask with the fields to be accessed in the special register.
3316def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3317                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3318                         NoItinerary, "msr", "\t$mask, $Rn",
3319                         [/* For disassembly only; pattern left blank */]> {
3320  bits<5> mask;
3321  bits<4> Rn;
3322  let Inst{19-16} = Rn;
3323  let Inst{20}    = mask{4}; // R Bit
3324  let Inst{13}    = 0b0;
3325  let Inst{11-8}  = mask{3-0};
3326}
3327
3328//===----------------------------------------------------------------------===//
3329// Move between coprocessor and ARM core register
3330//
3331
3332class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3333                  list<dag> pattern>
3334  : T2Cop<Op, oops, iops,
3335          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3336          pattern> {
3337  let Inst{27-24} = 0b1110;
3338  let Inst{20} = direction;
3339  let Inst{4} = 1;
3340
3341  bits<4> Rt;
3342  bits<4> cop;
3343  bits<3> opc1;
3344  bits<3> opc2;
3345  bits<4> CRm;
3346  bits<4> CRn;
3347
3348  let Inst{15-12} = Rt;
3349  let Inst{11-8}  = cop;
3350  let Inst{23-21} = opc1;
3351  let Inst{7-5}   = opc2;
3352  let Inst{3-0}   = CRm;
3353  let Inst{19-16} = CRn;
3354}
3355
3356class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3357                   list<dag> pattern = []>
3358  : T2Cop<Op, (outs),
3359          (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3360          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3361  let Inst{27-24} = 0b1100;
3362  let Inst{23-21} = 0b010;
3363  let Inst{20} = direction;
3364
3365  bits<4> Rt;
3366  bits<4> Rt2;
3367  bits<4> cop;
3368  bits<4> opc1;
3369  bits<4> CRm;
3370
3371  let Inst{15-12} = Rt;
3372  let Inst{19-16} = Rt2;
3373  let Inst{11-8}  = cop;
3374  let Inst{7-4}   = opc1;
3375  let Inst{3-0}   = CRm;
3376}
3377
3378/* from ARM core register to coprocessor */
3379def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3380           (outs),
3381           (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3382                c_imm:$CRm, i32imm:$opc2),
3383           [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3384                         imm:$CRm, imm:$opc2)]>;
3385def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3386             (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3387                          c_imm:$CRm, i32imm:$opc2),
3388             [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3389                            imm:$CRm, imm:$opc2)]>;
3390
3391/* from coprocessor to ARM core register */
3392def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3393           (outs GPR:$Rt),
3394           (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3395           []>;
3396
3397def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3398             (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
3399                                  c_imm:$CRm, i32imm:$opc2), []>;
3400
3401def : T2v6Pat<(int_arm_mrc  imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3402              (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3403
3404def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3405              (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3406
3407
3408/* from ARM core register to coprocessor */
3409def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3410                        [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3411                                       imm:$CRm)]>;
3412def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3413                           [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3414                                           GPR:$Rt2, imm:$CRm)]>;
3415/* from coprocessor to ARM core register */
3416def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3417
3418def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3419
3420//===----------------------------------------------------------------------===//
3421// Other Coprocessor Instructions.
3422//
3423
3424def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3425                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3426                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3427                 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3428                               imm:$CRm, imm:$opc2)]> {
3429  let Inst{27-24} = 0b1110;
3430
3431  bits<4> opc1;
3432  bits<4> CRn;
3433  bits<4> CRd;
3434  bits<4> cop;
3435  bits<3> opc2;
3436  bits<4> CRm;
3437
3438  let Inst{3-0}   = CRm;
3439  let Inst{4}     = 0;
3440  let Inst{7-5}   = opc2;
3441  let Inst{11-8}  = cop;
3442  let Inst{15-12} = CRd;
3443  let Inst{19-16} = CRn;
3444  let Inst{23-20} = opc1;
3445}
3446
3447def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, i32imm:$opc1,
3448                   c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3449                   "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3450                   [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3451                                  imm:$CRm, imm:$opc2)]> {
3452  let Inst{27-24} = 0b1110;
3453
3454  bits<4> opc1;
3455  bits<4> CRn;
3456  bits<4> CRd;
3457  bits<4> cop;
3458  bits<3> opc2;
3459  bits<4> CRm;
3460
3461  let Inst{3-0}   = CRm;
3462  let Inst{4}     = 0;
3463  let Inst{7-5}   = opc2;
3464  let Inst{11-8}  = cop;
3465  let Inst{15-12} = CRd;
3466  let Inst{19-16} = CRn;
3467  let Inst{23-20} = opc1;
3468}
3469