ARMInstrThumb2.td revision c6788c83b491b502482bf7d9a06b403d07f9e77e 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred : Operand<i32> {
16  let PrintMethod = "printMandatoryPredicateOperand";
17}
18
19// IT block condition mask
20def it_mask : Operand<i32> {
21  let PrintMethod = "printThumbITMask";
22}
23
24// Shifted operands. No register controlled shifts for Thumb2.
25// Note: We do not support rrx shifted operands yet.
26def t2_so_reg : Operand<i32>,    // reg imm
27                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
28                               [shl,srl,sra,rotr]> {
29  let EncoderMethod = "getT2SORegOpValue";
30  let PrintMethod = "printT2SOOperand";
31  let MIOperandInfo = (ops rGPR, i32imm);
32  let DecoderMethod = "DecodeSORegImmOperand";
33}
34
35// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
36def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
37  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
38}]>;
39
40// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
41def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
42  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
43}]>;
44
45// t2_so_imm - Match a 32-bit immediate operand, which is an
46// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
47// immediate splatted into multiple bytes of the word.
48def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
49def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
50    return ARM_AM::getT2SOImmVal(Imm) != -1;
51  }]> {
52  let ParserMatchClass = t2_so_imm_asmoperand;
53  let EncoderMethod = "getT2SOImmOpValue";
54  let DecoderMethod = "DecodeT2SOImm";
55}
56
57// t2_so_imm_not - Match an immediate that is a complement
58// of a t2_so_imm.
59def t2_so_imm_not : Operand<i32>,
60                    PatLeaf<(imm), [{
61  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
62}], t2_so_imm_not_XFORM>;
63
64// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
65def t2_so_imm_neg : Operand<i32>,
66                    PatLeaf<(imm), [{
67  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
68}], t2_so_imm_neg_XFORM>;
69
70/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
71def imm1_31 : Operand<i32>, ImmLeaf<i32, [{
72  return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
73}]>;
74
75/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
76def imm0_4095 : Operand<i32>,
77                ImmLeaf<i32, [{
78  return Imm >= 0 && Imm < 4096;
79}]>;
80
81def imm0_4095_neg : PatLeaf<(i32 imm), [{
82 return (uint32_t)(-N->getZExtValue()) < 4096;
83}], imm_neg_XFORM>;
84
85def imm0_255_neg : PatLeaf<(i32 imm), [{
86  return (uint32_t)(-N->getZExtValue()) < 255;
87}], imm_neg_XFORM>;
88
89def imm0_255_not : PatLeaf<(i32 imm), [{
90  return (uint32_t)(~N->getZExtValue()) < 255;
91}], imm_comp_XFORM>;
92
93def lo5AllOne : PatLeaf<(i32 imm), [{
94  // Returns true if all low 5-bits are 1.
95  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
96}]>;
97
98// Define Thumb2 specific addressing modes.
99
100// t2addrmode_imm12  := reg + imm12
101def t2addrmode_imm12 : Operand<i32>,
102                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
103  let PrintMethod = "printAddrModeImm12Operand";
104  let EncoderMethod = "getAddrModeImm12OpValue";
105  let DecoderMethod = "DecodeT2AddrModeImm12";
106  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
107}
108
109// t2ldrlabel  := imm12
110def t2ldrlabel : Operand<i32> {
111  let EncoderMethod = "getAddrModeImm12OpValue";
112}
113
114
115// ADR instruction labels.
116def t2adrlabel : Operand<i32> {
117  let EncoderMethod = "getT2AdrLabelOpValue";
118}
119
120
121// t2addrmode_imm8  := reg +/- imm8
122def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
123def t2addrmode_imm8 : Operand<i32>,
124                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
125  let PrintMethod = "printT2AddrModeImm8Operand";
126  let EncoderMethod = "getT2AddrModeImm8OpValue";
127  let DecoderMethod = "DecodeT2AddrModeImm8";
128  let ParserMatchClass = MemImm8OffsetAsmOperand;
129  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
130}
131
132def t2am_imm8_offset : Operand<i32>,
133                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
134                                      [], [SDNPWantRoot]> {
135  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
136  let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
137  let DecoderMethod = "DecodeT2Imm8";
138}
139
140// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
141def t2addrmode_imm8s4 : Operand<i32> {
142  let PrintMethod = "printT2AddrModeImm8s4Operand";
143  let EncoderMethod = "getT2AddrModeImm8s4OpValue";
144  let DecoderMethod = "DecodeT2AddrModeImm8s4";
145  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
146}
147
148def t2am_imm8s4_offset : Operand<i32> {
149  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
150  let DecoderMethod = "DecodeT2Imm8S4";
151}
152
153// t2addrmode_so_reg  := reg + (reg << imm2)
154def t2addrmode_so_reg : Operand<i32>,
155                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
156  let PrintMethod = "printT2AddrModeSoRegOperand";
157  let EncoderMethod = "getT2AddrModeSORegOpValue";
158  let DecoderMethod = "DecodeT2AddrModeSOReg";
159  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
160}
161
162// t2addrmode_reg := reg
163// Used by load/store exclusive instructions. Useful to enable right assembly
164// parsing and printing. Not used for any codegen matching.
165//
166def t2addrmode_reg : Operand<i32> {
167  let PrintMethod = "printAddrMode7Operand";
168  let DecoderMethod = "DecodeGPRRegisterClass";
169  let MIOperandInfo = (ops GPR);
170}
171
172//===----------------------------------------------------------------------===//
173// Multiclass helpers...
174//
175
176
177class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
178           string opc, string asm, list<dag> pattern>
179  : T2I<oops, iops, itin, opc, asm, pattern> {
180  bits<4> Rd;
181  bits<12> imm;
182
183  let Inst{11-8}  = Rd;
184  let Inst{26}    = imm{11};
185  let Inst{14-12} = imm{10-8};
186  let Inst{7-0}   = imm{7-0};
187}
188
189
190class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
191           string opc, string asm, list<dag> pattern>
192  : T2sI<oops, iops, itin, opc, asm, pattern> {
193  bits<4> Rd;
194  bits<4> Rn;
195  bits<12> imm;
196
197  let Inst{11-8}  = Rd;
198  let Inst{26}    = imm{11};
199  let Inst{14-12} = imm{10-8};
200  let Inst{7-0}   = imm{7-0};
201}
202
203class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
204           string opc, string asm, list<dag> pattern>
205  : T2I<oops, iops, itin, opc, asm, pattern> {
206  bits<4> Rn;
207  bits<12> imm;
208
209  let Inst{19-16}  = Rn;
210  let Inst{26}    = imm{11};
211  let Inst{14-12} = imm{10-8};
212  let Inst{7-0}   = imm{7-0};
213}
214
215
216class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
217           string opc, string asm, list<dag> pattern>
218  : T2I<oops, iops, itin, opc, asm, pattern> {
219  bits<4> Rd;
220  bits<12> ShiftedRm;
221
222  let Inst{11-8}  = Rd;
223  let Inst{3-0}   = ShiftedRm{3-0};
224  let Inst{5-4}   = ShiftedRm{6-5};
225  let Inst{14-12} = ShiftedRm{11-9};
226  let Inst{7-6}   = ShiftedRm{8-7};
227}
228
229class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
230           string opc, string asm, list<dag> pattern>
231  : T2sI<oops, iops, itin, opc, asm, pattern> {
232  bits<4> Rd;
233  bits<12> ShiftedRm;
234
235  let Inst{11-8}  = Rd;
236  let Inst{3-0}   = ShiftedRm{3-0};
237  let Inst{5-4}   = ShiftedRm{6-5};
238  let Inst{14-12} = ShiftedRm{11-9};
239  let Inst{7-6}   = ShiftedRm{8-7};
240}
241
242class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
243           string opc, string asm, list<dag> pattern>
244  : T2I<oops, iops, itin, opc, asm, pattern> {
245  bits<4> Rn;
246  bits<12> ShiftedRm;
247
248  let Inst{19-16} = Rn;
249  let Inst{3-0}   = ShiftedRm{3-0};
250  let Inst{5-4}   = ShiftedRm{6-5};
251  let Inst{14-12} = ShiftedRm{11-9};
252  let Inst{7-6}   = ShiftedRm{8-7};
253}
254
255class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
256           string opc, string asm, list<dag> pattern>
257  : T2I<oops, iops, itin, opc, asm, pattern> {
258  bits<4> Rd;
259  bits<4> Rm;
260
261  let Inst{11-8}  = Rd;
262  let Inst{3-0}   = Rm;
263}
264
265class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
266           string opc, string asm, list<dag> pattern>
267  : T2sI<oops, iops, itin, opc, asm, pattern> {
268  bits<4> Rd;
269  bits<4> Rm;
270
271  let Inst{11-8}  = Rd;
272  let Inst{3-0}   = Rm;
273}
274
275class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
276           string opc, string asm, list<dag> pattern>
277  : T2I<oops, iops, itin, opc, asm, pattern> {
278  bits<4> Rn;
279  bits<4> Rm;
280
281  let Inst{19-16} = Rn;
282  let Inst{3-0}   = Rm;
283}
284
285
286class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
287           string opc, string asm, list<dag> pattern>
288  : T2I<oops, iops, itin, opc, asm, pattern> {
289  bits<4> Rd;
290  bits<4> Rn;
291  bits<12> imm;
292
293  let Inst{11-8}  = Rd;
294  let Inst{19-16} = Rn;
295  let Inst{26}    = imm{11};
296  let Inst{14-12} = imm{10-8};
297  let Inst{7-0}   = imm{7-0};
298}
299
300class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
301           string opc, string asm, list<dag> pattern>
302  : T2sI<oops, iops, itin, opc, asm, pattern> {
303  bits<4> Rd;
304  bits<4> Rn;
305  bits<12> imm;
306
307  let Inst{11-8}  = Rd;
308  let Inst{19-16} = Rn;
309  let Inst{26}    = imm{11};
310  let Inst{14-12} = imm{10-8};
311  let Inst{7-0}   = imm{7-0};
312}
313
314class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
315           string opc, string asm, list<dag> pattern>
316  : T2I<oops, iops, itin, opc, asm, pattern> {
317  bits<4> Rd;
318  bits<4> Rm;
319  bits<5> imm;
320
321  let Inst{11-8}  = Rd;
322  let Inst{3-0}   = Rm;
323  let Inst{14-12} = imm{4-2};
324  let Inst{7-6}   = imm{1-0};
325}
326
327class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
328           string opc, string asm, list<dag> pattern>
329  : T2sI<oops, iops, itin, opc, asm, pattern> {
330  bits<4> Rd;
331  bits<4> Rm;
332  bits<5> imm;
333
334  let Inst{11-8}  = Rd;
335  let Inst{3-0}   = Rm;
336  let Inst{14-12} = imm{4-2};
337  let Inst{7-6}   = imm{1-0};
338}
339
340class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
341           string opc, string asm, list<dag> pattern>
342  : T2I<oops, iops, itin, opc, asm, pattern> {
343  bits<4> Rd;
344  bits<4> Rn;
345  bits<4> Rm;
346
347  let Inst{11-8}  = Rd;
348  let Inst{19-16} = Rn;
349  let Inst{3-0}   = Rm;
350}
351
352class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
353           string opc, string asm, list<dag> pattern>
354  : T2sI<oops, iops, itin, opc, asm, pattern> {
355  bits<4> Rd;
356  bits<4> Rn;
357  bits<4> Rm;
358
359  let Inst{11-8}  = Rd;
360  let Inst{19-16} = Rn;
361  let Inst{3-0}   = Rm;
362}
363
364class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
365           string opc, string asm, list<dag> pattern>
366  : T2I<oops, iops, itin, opc, asm, pattern> {
367  bits<4> Rd;
368  bits<4> Rn;
369  bits<12> ShiftedRm;
370
371  let Inst{11-8}  = Rd;
372  let Inst{19-16} = Rn;
373  let Inst{3-0}   = ShiftedRm{3-0};
374  let Inst{5-4}   = ShiftedRm{6-5};
375  let Inst{14-12} = ShiftedRm{11-9};
376  let Inst{7-6}   = ShiftedRm{8-7};
377}
378
379class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
380           string opc, string asm, list<dag> pattern>
381  : T2sI<oops, iops, itin, opc, asm, pattern> {
382  bits<4> Rd;
383  bits<4> Rn;
384  bits<12> ShiftedRm;
385
386  let Inst{11-8}  = Rd;
387  let Inst{19-16} = Rn;
388  let Inst{3-0}   = ShiftedRm{3-0};
389  let Inst{5-4}   = ShiftedRm{6-5};
390  let Inst{14-12} = ShiftedRm{11-9};
391  let Inst{7-6}   = ShiftedRm{8-7};
392}
393
394class T2FourReg<dag oops, dag iops, InstrItinClass itin,
395           string opc, string asm, list<dag> pattern>
396  : T2I<oops, iops, itin, opc, asm, pattern> {
397  bits<4> Rd;
398  bits<4> Rn;
399  bits<4> Rm;
400  bits<4> Ra;
401
402  let Inst{19-16} = Rn;
403  let Inst{15-12} = Ra;
404  let Inst{11-8}  = Rd;
405  let Inst{3-0}   = Rm;
406}
407
408class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
409                dag oops, dag iops, InstrItinClass itin,
410                string opc, string asm, list<dag> pattern>
411  : T2I<oops, iops, itin, opc, asm, pattern> {
412  bits<4> RdLo;
413  bits<4> RdHi;
414  bits<4> Rn;
415  bits<4> Rm;
416
417  let Inst{31-23} = 0b111110111;
418  let Inst{22-20} = opc22_20;
419  let Inst{19-16} = Rn;
420  let Inst{15-12} = RdLo;
421  let Inst{11-8}  = RdHi;
422  let Inst{7-4}   = opc7_4;
423  let Inst{3-0}   = Rm;
424}
425
426
427/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
428/// unary operation that produces a value. These are predicable and can be
429/// changed to modify CPSR.
430multiclass T2I_un_irs<bits<4> opcod, string opc,
431                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
432                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
433   // shifted imm
434   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
435                opc, "\t$Rd, $imm",
436                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
437     let isAsCheapAsAMove = Cheap;
438     let isReMaterializable = ReMat;
439     let Inst{31-27} = 0b11110;
440     let Inst{25} = 0;
441     let Inst{24-21} = opcod;
442     let Inst{19-16} = 0b1111; // Rn
443     let Inst{15} = 0;
444   }
445   // register
446   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
447                opc, ".w\t$Rd, $Rm",
448                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
449     let Inst{31-27} = 0b11101;
450     let Inst{26-25} = 0b01;
451     let Inst{24-21} = opcod;
452     let Inst{19-16} = 0b1111; // Rn
453     let Inst{14-12} = 0b000; // imm3
454     let Inst{7-6} = 0b00; // imm2
455     let Inst{5-4} = 0b00; // type
456   }
457   // shifted register
458   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
459                opc, ".w\t$Rd, $ShiftedRm",
460                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
461     let Inst{31-27} = 0b11101;
462     let Inst{26-25} = 0b01;
463     let Inst{24-21} = opcod;
464     let Inst{19-16} = 0b1111; // Rn
465   }
466}
467
468/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
469/// binary operation that produces a value. These are predicable and can be
470/// changed to modify CPSR.
471multiclass T2I_bin_irs<bits<4> opcod, string opc,
472                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
473                       PatFrag opnode, string baseOpc, bit Commutable = 0,
474                       string wide = ""> {
475   // shifted imm
476   def ri : T2sTwoRegImm<
477                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
478                 opc, "\t$Rd, $Rn, $imm",
479                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
480     let Inst{31-27} = 0b11110;
481     let Inst{25} = 0;
482     let Inst{24-21} = opcod;
483     let Inst{15} = 0;
484   }
485   // register
486   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
487                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
488                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
489     let isCommutable = Commutable;
490     let Inst{31-27} = 0b11101;
491     let Inst{26-25} = 0b01;
492     let Inst{24-21} = opcod;
493     let Inst{14-12} = 0b000; // imm3
494     let Inst{7-6} = 0b00; // imm2
495     let Inst{5-4} = 0b00; // type
496   }
497   // shifted register
498   def rs : T2sTwoRegShiftedReg<
499                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
500                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
501                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
502     let Inst{31-27} = 0b11101;
503     let Inst{26-25} = 0b01;
504     let Inst{24-21} = opcod;
505   }
506  // Assembly aliases for optional destination operand when it's the same
507  // as the source operand.
508  def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
509     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
510                                                    t2_so_imm:$imm, pred:$p,
511                                                    cc_out:$s)>;
512  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
513     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
514                                                    rGPR:$Rm, pred:$p,
515                                                    cc_out:$s)>;
516  def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
517     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
518                                                    t2_so_reg:$shift, pred:$p,
519                                                    cc_out:$s)>;
520}
521
522/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
523//  the ".w" suffix to indicate that they are wide.
524multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
525                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
526                         PatFrag opnode, string baseOpc, bit Commutable = 0> :
527    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
528
529/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
530/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
531/// it is equivalent to the T2I_bin_irs counterpart.
532multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
533   // shifted imm
534   def ri : T2sTwoRegImm<
535                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
536                 opc, ".w\t$Rd, $Rn, $imm",
537                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
538     let Inst{31-27} = 0b11110;
539     let Inst{25} = 0;
540     let Inst{24-21} = opcod;
541     let Inst{15} = 0;
542   }
543   // register
544   def rr : T2sThreeReg<
545                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
546                 opc, "\t$Rd, $Rn, $Rm",
547                 [/* For disassembly only; pattern left blank */]> {
548     let Inst{31-27} = 0b11101;
549     let Inst{26-25} = 0b01;
550     let Inst{24-21} = opcod;
551     let Inst{14-12} = 0b000; // imm3
552     let Inst{7-6} = 0b00; // imm2
553     let Inst{5-4} = 0b00; // type
554   }
555   // shifted register
556   def rs : T2sTwoRegShiftedReg<
557                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
558                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
559                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
560     let Inst{31-27} = 0b11101;
561     let Inst{26-25} = 0b01;
562     let Inst{24-21} = opcod;
563   }
564}
565
566/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
567/// instruction modifies the CPSR register.
568let isCodeGenOnly = 1, Defs = [CPSR] in {
569multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
570                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
571                         PatFrag opnode, bit Commutable = 0> {
572   // shifted imm
573   def ri : T2TwoRegImm<
574                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
575                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
576                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
577     let Inst{31-27} = 0b11110;
578     let Inst{25} = 0;
579     let Inst{24-21} = opcod;
580     let Inst{20} = 1; // The S bit.
581     let Inst{15} = 0;
582   }
583   // register
584   def rr : T2ThreeReg<
585                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
586                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
587                [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
588     let isCommutable = Commutable;
589     let Inst{31-27} = 0b11101;
590     let Inst{26-25} = 0b01;
591     let Inst{24-21} = opcod;
592     let Inst{20} = 1; // The S bit.
593     let Inst{14-12} = 0b000; // imm3
594     let Inst{7-6} = 0b00; // imm2
595     let Inst{5-4} = 0b00; // type
596   }
597   // shifted register
598   def rs : T2TwoRegShiftedReg<
599                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
600                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
601                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
602     let Inst{31-27} = 0b11101;
603     let Inst{26-25} = 0b01;
604     let Inst{24-21} = opcod;
605     let Inst{20} = 1; // The S bit.
606   }
607}
608}
609
610/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
611/// patterns for a binary operation that produces a value.
612multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
613                          bit Commutable = 0> {
614   // shifted imm
615   // The register-immediate version is re-materializable. This is useful
616   // in particular for taking the address of a local.
617   let isReMaterializable = 1 in {
618   def ri : T2sTwoRegImm<
619                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
620                 opc, ".w\t$Rd, $Rn, $imm",
621                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
622     let Inst{31-27} = 0b11110;
623     let Inst{25} = 0;
624     let Inst{24} = 1;
625     let Inst{23-21} = op23_21;
626     let Inst{15} = 0;
627   }
628   }
629   // 12-bit imm
630   def ri12 : T2I<
631                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
632                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
633                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
634     bits<4> Rd;
635     bits<4> Rn;
636     bits<12> imm;
637     let Inst{31-27} = 0b11110;
638     let Inst{26} = imm{11};
639     let Inst{25-24} = 0b10;
640     let Inst{23-21} = op23_21;
641     let Inst{20} = 0; // The S bit.
642     let Inst{19-16} = Rn;
643     let Inst{15} = 0;
644     let Inst{14-12} = imm{10-8};
645     let Inst{11-8} = Rd;
646     let Inst{7-0} = imm{7-0};
647   }
648   // register
649   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
650                 opc, ".w\t$Rd, $Rn, $Rm",
651                 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
652     let isCommutable = Commutable;
653     let Inst{31-27} = 0b11101;
654     let Inst{26-25} = 0b01;
655     let Inst{24} = 1;
656     let Inst{23-21} = op23_21;
657     let Inst{14-12} = 0b000; // imm3
658     let Inst{7-6} = 0b00; // imm2
659     let Inst{5-4} = 0b00; // type
660   }
661   // shifted register
662   def rs : T2sTwoRegShiftedReg<
663                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
664                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
665                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
666     let Inst{31-27} = 0b11101;
667     let Inst{26-25} = 0b01;
668     let Inst{24} = 1;
669     let Inst{23-21} = op23_21;
670   }
671}
672
673/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
674/// for a binary operation that produces a value and use the carry
675/// bit. It's not predicable.
676let Uses = [CPSR] in {
677multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
678                             bit Commutable = 0> {
679   // shifted imm
680   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
681                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
682                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
683                 Requires<[IsThumb2]> {
684     let Inst{31-27} = 0b11110;
685     let Inst{25} = 0;
686     let Inst{24-21} = opcod;
687     let Inst{15} = 0;
688   }
689   // register
690   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
691                 opc, ".w\t$Rd, $Rn, $Rm",
692                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
693                 Requires<[IsThumb2]> {
694     let isCommutable = Commutable;
695     let Inst{31-27} = 0b11101;
696     let Inst{26-25} = 0b01;
697     let Inst{24-21} = opcod;
698     let Inst{14-12} = 0b000; // imm3
699     let Inst{7-6} = 0b00; // imm2
700     let Inst{5-4} = 0b00; // type
701   }
702   // shifted register
703   def rs : T2sTwoRegShiftedReg<
704                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
705                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
706                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
707                 Requires<[IsThumb2]> {
708     let Inst{31-27} = 0b11101;
709     let Inst{26-25} = 0b01;
710     let Inst{24-21} = opcod;
711   }
712}
713}
714
715// Carry setting variants
716// NOTE: CPSR def omitted because it will be handled by the custom inserter.
717let usesCustomInserter = 1 in {
718multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
719   // shifted imm
720   def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
721                4, IIC_iALUi,
722                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
723   // register
724   def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
725                4, IIC_iALUr,
726                [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
727     let isCommutable = Commutable;
728   }
729   // shifted register
730   def rs : t2PseudoInst<
731                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
732                4, IIC_iALUsi,
733                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
734}
735}
736
737/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
738/// version is not needed since this is only for codegen.
739let isCodeGenOnly = 1, Defs = [CPSR] in {
740multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
741   // shifted imm
742   def ri : T2TwoRegImm<
743                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
744                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
745                [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
746     let Inst{31-27} = 0b11110;
747     let Inst{25} = 0;
748     let Inst{24-21} = opcod;
749     let Inst{20} = 1; // The S bit.
750     let Inst{15} = 0;
751   }
752   // shifted register
753   def rs : T2TwoRegShiftedReg<
754                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
755                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
756                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
757     let Inst{31-27} = 0b11101;
758     let Inst{26-25} = 0b01;
759     let Inst{24-21} = opcod;
760     let Inst{20} = 1; // The S bit.
761   }
762}
763}
764
765/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
766//  rotate operation that produces a value.
767multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode> {
768   // 5-bit imm
769   def ri : T2sTwoRegShiftImm<
770                 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
771                 opc, ".w\t$Rd, $Rm, $imm",
772                 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> {
773     let Inst{31-27} = 0b11101;
774     let Inst{26-21} = 0b010010;
775     let Inst{19-16} = 0b1111; // Rn
776     let Inst{5-4} = opcod;
777   }
778   // register
779   def rr : T2sThreeReg<
780                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
781                 opc, ".w\t$Rd, $Rn, $Rm",
782                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
783     let Inst{31-27} = 0b11111;
784     let Inst{26-23} = 0b0100;
785     let Inst{22-21} = opcod;
786     let Inst{15-12} = 0b1111;
787     let Inst{7-4} = 0b0000;
788   }
789}
790
791/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
792/// patterns. Similar to T2I_bin_irs except the instruction does not produce
793/// a explicit result, only implicitly set CPSR.
794let isCompare = 1, Defs = [CPSR] in {
795multiclass T2I_cmp_irs<bits<4> opcod, string opc,
796                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
797                       PatFrag opnode> {
798   // shifted imm
799   def ri : T2OneRegCmpImm<
800                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
801                opc, ".w\t$Rn, $imm",
802                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
803     let Inst{31-27} = 0b11110;
804     let Inst{25} = 0;
805     let Inst{24-21} = opcod;
806     let Inst{20} = 1; // The S bit.
807     let Inst{15} = 0;
808     let Inst{11-8} = 0b1111; // Rd
809   }
810   // register
811   def rr : T2TwoRegCmp<
812                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
813                opc, ".w\t$lhs, $rhs",
814                [(opnode GPR:$lhs, rGPR:$rhs)]> {
815     let Inst{31-27} = 0b11101;
816     let Inst{26-25} = 0b01;
817     let Inst{24-21} = opcod;
818     let Inst{20} = 1; // The S bit.
819     let Inst{14-12} = 0b000; // imm3
820     let Inst{11-8} = 0b1111; // Rd
821     let Inst{7-6} = 0b00; // imm2
822     let Inst{5-4} = 0b00; // type
823   }
824   // shifted register
825   def rs : T2OneRegCmpShiftedReg<
826                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
827                opc, ".w\t$Rn, $ShiftedRm",
828                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
829     let Inst{31-27} = 0b11101;
830     let Inst{26-25} = 0b01;
831     let Inst{24-21} = opcod;
832     let Inst{20} = 1; // The S bit.
833     let Inst{11-8} = 0b1111; // Rd
834   }
835}
836}
837
838/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
839multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
840                  InstrItinClass iii, InstrItinClass iis, RegisterClass target,
841                  PatFrag opnode> {
842  def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
843                   opc, ".w\t$Rt, $addr",
844                   [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
845    let Inst{31-27} = 0b11111;
846    let Inst{26-25} = 0b00;
847    let Inst{24} = signed;
848    let Inst{23} = 1;
849    let Inst{22-21} = opcod;
850    let Inst{20} = 1; // load
851
852    bits<4> Rt;
853    let Inst{15-12} = Rt;
854
855    bits<17> addr;
856    let addr{12}    = 1;           // add = TRUE
857    let Inst{19-16} = addr{16-13}; // Rn
858    let Inst{23}    = addr{12};    // U
859    let Inst{11-0}  = addr{11-0};  // imm
860  }
861  def i8  : T2Ii8 <(outs target:$Rt), (ins t2addrmode_imm8:$addr), iii,
862                   opc, "\t$Rt, $addr",
863                   [(set target:$Rt, (opnode t2addrmode_imm8:$addr))]> {
864    let Inst{31-27} = 0b11111;
865    let Inst{26-25} = 0b00;
866    let Inst{24} = signed;
867    let Inst{23} = 0;
868    let Inst{22-21} = opcod;
869    let Inst{20} = 1; // load
870    let Inst{11} = 1;
871    // Offset: index==TRUE, wback==FALSE
872    let Inst{10} = 1; // The P bit.
873    let Inst{8} = 0; // The W bit.
874
875    bits<4> Rt;
876    let Inst{15-12} = Rt;
877
878    bits<13> addr;
879    let Inst{19-16} = addr{12-9}; // Rn
880    let Inst{9}     = addr{8};    // U
881    let Inst{7-0}   = addr{7-0};  // imm
882  }
883  def s   : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis,
884                   opc, ".w\t$Rt, $addr",
885                   [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
886    let Inst{31-27} = 0b11111;
887    let Inst{26-25} = 0b00;
888    let Inst{24} = signed;
889    let Inst{23} = 0;
890    let Inst{22-21} = opcod;
891    let Inst{20} = 1; // load
892    let Inst{11-6} = 0b000000;
893
894    bits<4> Rt;
895    let Inst{15-12} = Rt;
896
897    bits<10> addr;
898    let Inst{19-16} = addr{9-6}; // Rn
899    let Inst{3-0}   = addr{5-2}; // Rm
900    let Inst{5-4}   = addr{1-0}; // imm
901
902    let DecoderMethod = "DecodeT2LoadShift";
903  }
904
905  // FIXME: Is the pci variant actually needed?
906  def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii,
907                   opc, ".w\t$Rt, $addr",
908                   [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
909    let isReMaterializable = 1;
910    let Inst{31-27} = 0b11111;
911    let Inst{26-25} = 0b00;
912    let Inst{24} = signed;
913    let Inst{23} = ?; // add = (U == '1')
914    let Inst{22-21} = opcod;
915    let Inst{20} = 1; // load
916    let Inst{19-16} = 0b1111; // Rn
917    bits<4> Rt;
918    bits<12> addr;
919    let Inst{15-12} = Rt{3-0};
920    let Inst{11-0}  = addr{11-0};
921  }
922}
923
924/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
925multiclass T2I_st<bits<2> opcod, string opc,
926                  InstrItinClass iii, InstrItinClass iis, RegisterClass target,
927                  PatFrag opnode> {
928  def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii,
929                   opc, ".w\t$Rt, $addr",
930                   [(opnode target:$Rt, t2addrmode_imm12:$addr)]> {
931    let Inst{31-27} = 0b11111;
932    let Inst{26-23} = 0b0001;
933    let Inst{22-21} = opcod;
934    let Inst{20} = 0; // !load
935
936    bits<4> Rt;
937    let Inst{15-12} = Rt;
938
939    bits<17> addr;
940    let addr{12}    = 1;           // add = TRUE
941    let Inst{19-16} = addr{16-13}; // Rn
942    let Inst{23}    = addr{12};    // U
943    let Inst{11-0}  = addr{11-0};  // imm
944  }
945  def i8  : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_imm8:$addr), iii,
946                   opc, "\t$Rt, $addr",
947                   [(opnode target:$Rt, t2addrmode_imm8:$addr)]> {
948    let Inst{31-27} = 0b11111;
949    let Inst{26-23} = 0b0000;
950    let Inst{22-21} = opcod;
951    let Inst{20} = 0; // !load
952    let Inst{11} = 1;
953    // Offset: index==TRUE, wback==FALSE
954    let Inst{10} = 1; // The P bit.
955    let Inst{8} = 0; // The W bit.
956
957    bits<4> Rt;
958    let Inst{15-12} = Rt;
959
960    bits<13> addr;
961    let Inst{19-16} = addr{12-9}; // Rn
962    let Inst{9}     = addr{8};    // U
963    let Inst{7-0}   = addr{7-0};  // imm
964  }
965  def s   : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis,
966                   opc, ".w\t$Rt, $addr",
967                   [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> {
968    let Inst{31-27} = 0b11111;
969    let Inst{26-23} = 0b0000;
970    let Inst{22-21} = opcod;
971    let Inst{20} = 0; // !load
972    let Inst{11-6} = 0b000000;
973
974    bits<4> Rt;
975    let Inst{15-12} = Rt;
976
977    bits<10> addr;
978    let Inst{19-16}   = addr{9-6}; // Rn
979    let Inst{3-0} = addr{5-2}; // Rm
980    let Inst{5-4}   = addr{1-0}; // imm
981  }
982}
983
984/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
985/// register and one whose operand is a register rotated by 8/16/24.
986class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
987  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
988             opc, ".w\t$Rd, $Rm$rot",
989             [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
990             Requires<[IsThumb2]> {
991   let Inst{31-27} = 0b11111;
992   let Inst{26-23} = 0b0100;
993   let Inst{22-20} = opcod;
994   let Inst{19-16} = 0b1111; // Rn
995   let Inst{15-12} = 0b1111;
996   let Inst{7} = 1;
997
998   bits<2> rot;
999   let Inst{5-4} = rot{1-0}; // rotate
1000}
1001
1002// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1003class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
1004  : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1005             IIC_iEXTr, opc, "\t$dst, $Rm$rot",
1006            [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1007          Requires<[HasT2ExtractPack, IsThumb2]> {
1008  bits<2> rot;
1009  let Inst{31-27} = 0b11111;
1010  let Inst{26-23} = 0b0100;
1011  let Inst{22-20} = opcod;
1012  let Inst{19-16} = 0b1111; // Rn
1013  let Inst{15-12} = 0b1111;
1014  let Inst{7} = 1;
1015  let Inst{5-4} = rot;
1016}
1017
1018// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1019// supported yet.
1020class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc>
1021  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
1022             opc, "\t$Rd, $Rm$rot", []>,
1023          Requires<[IsThumb2, HasT2ExtractPack]> {
1024  bits<2> rot;
1025  let Inst{31-27} = 0b11111;
1026  let Inst{26-23} = 0b0100;
1027  let Inst{22-20} = opcod;
1028  let Inst{19-16} = 0b1111; // Rn
1029  let Inst{15-12} = 0b1111;
1030  let Inst{7} = 1;
1031  let Inst{5-4} = rot;
1032}
1033
1034/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1035/// register and one whose operand is a register rotated by 8/16/24.
1036class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode>
1037  : T2ThreeReg<(outs rGPR:$Rd),
1038               (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1039               IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1040             [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>,
1041           Requires<[HasT2ExtractPack, IsThumb2]> {
1042  bits<2> rot;
1043  let Inst{31-27} = 0b11111;
1044  let Inst{26-23} = 0b0100;
1045  let Inst{22-20} = opcod;
1046  let Inst{15-12} = 0b1111;
1047  let Inst{7} = 1;
1048  let Inst{5-4} = rot;
1049}
1050
1051class T2I_exta_rrot_np<bits<3> opcod, string opc>
1052  : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1053               IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1054  bits<2> rot;
1055  let Inst{31-27} = 0b11111;
1056  let Inst{26-23} = 0b0100;
1057  let Inst{22-20} = opcod;
1058  let Inst{15-12} = 0b1111;
1059  let Inst{7} = 1;
1060  let Inst{5-4} = rot;
1061}
1062
1063//===----------------------------------------------------------------------===//
1064// Instructions
1065//===----------------------------------------------------------------------===//
1066
1067//===----------------------------------------------------------------------===//
1068//  Miscellaneous Instructions.
1069//
1070
1071class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1072           string asm, list<dag> pattern>
1073  : T2XI<oops, iops, itin, asm, pattern> {
1074  bits<4> Rd;
1075  bits<12> label;
1076
1077  let Inst{11-8}  = Rd;
1078  let Inst{26}    = label{11};
1079  let Inst{14-12} = label{10-8};
1080  let Inst{7-0}   = label{7-0};
1081}
1082
1083// LEApcrel - Load a pc-relative address into a register without offending the
1084// assembler.
1085def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1086              (ins t2adrlabel:$addr, pred:$p),
1087              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1088  let Inst{31-27} = 0b11110;
1089  let Inst{25-24} = 0b10;
1090  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1091  let Inst{22} = 0;
1092  let Inst{20} = 0;
1093  let Inst{19-16} = 0b1111; // Rn
1094  let Inst{15} = 0;
1095
1096  bits<4> Rd;
1097  bits<13> addr;
1098  let Inst{11-8} = Rd;
1099  let Inst{23}    = addr{12};
1100  let Inst{21}    = addr{12};
1101  let Inst{26}    = addr{11};
1102  let Inst{14-12} = addr{10-8};
1103  let Inst{7-0}   = addr{7-0};
1104}
1105
1106let neverHasSideEffects = 1, isReMaterializable = 1 in
1107def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1108                                4, IIC_iALUi, []>;
1109def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1110                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
1111                                4, IIC_iALUi,
1112                                []>;
1113
1114
1115//===----------------------------------------------------------------------===//
1116//  Load / store Instructions.
1117//
1118
1119// Load
1120let canFoldAsLoad = 1, isReMaterializable = 1  in
1121defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR,
1122                      UnOpFrag<(load node:$Src)>>;
1123
1124// Loads with zero extension
1125defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1126                      rGPR, UnOpFrag<(zextloadi16 node:$Src)>>;
1127defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1128                      rGPR, UnOpFrag<(zextloadi8  node:$Src)>>;
1129
1130// Loads with sign extension
1131defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1132                      rGPR, UnOpFrag<(sextloadi16 node:$Src)>>;
1133defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1134                      rGPR, UnOpFrag<(sextloadi8  node:$Src)>>;
1135
1136let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1137// Load doubleword
1138def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1139                        (ins t2addrmode_imm8s4:$addr),
1140                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1141} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1142
1143// zextload i1 -> zextload i8
1144def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1145            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1146def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1147            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1148def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1149            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1150def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1151            (t2LDRBpci  tconstpool:$addr)>;
1152
1153// extload -> zextload
1154// FIXME: Reduce the number of patterns by legalizing extload to zextload
1155// earlier?
1156def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1157            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1158def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1159            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1160def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1161            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1162def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1163            (t2LDRBpci  tconstpool:$addr)>;
1164
1165def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1166            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1167def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1168            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1169def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1170            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1171def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1172            (t2LDRBpci  tconstpool:$addr)>;
1173
1174def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1175            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1176def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1177            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1178def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1179            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1180def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1181            (t2LDRHpci  tconstpool:$addr)>;
1182
1183// FIXME: The destination register of the loads and stores can't be PC, but
1184//        can be SP. We need another regclass (similar to rGPR) to represent
1185//        that. Not a pressing issue since these are selected manually,
1186//        not via pattern.
1187
1188// Indexed loads
1189
1190let mayLoad = 1, neverHasSideEffects = 1 in {
1191def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1192                            (ins t2addrmode_imm8:$addr),
1193                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1194                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1195                            []>;
1196
1197def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1198                            (ins GPR:$base, t2am_imm8_offset:$addr),
1199                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1200                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1201                            []>;
1202
1203def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1204                            (ins t2addrmode_imm8:$addr),
1205                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1206                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1207                            []>;
1208def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1209                            (ins GPR:$base, t2am_imm8_offset:$addr),
1210                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1211                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1212                            []>;
1213
1214def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1215                            (ins t2addrmode_imm8:$addr),
1216                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1217                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1218                            []>;
1219def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1220                            (ins GPR:$base, t2am_imm8_offset:$addr),
1221                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1222                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1223                            []>;
1224
1225def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1226                            (ins t2addrmode_imm8:$addr),
1227                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1228                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1229                            []>;
1230def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1231                            (ins GPR:$base, t2am_imm8_offset:$addr),
1232                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1233                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1234                            []>;
1235
1236def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1237                            (ins t2addrmode_imm8:$addr),
1238                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1239                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1240                            []>;
1241def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1242                            (ins GPR:$base, t2am_imm8_offset:$addr),
1243                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1244                        "ldrsh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1245                            []>;
1246} // mayLoad = 1, neverHasSideEffects = 1
1247
1248// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1249// for disassembly only.
1250// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1251class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1252  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1253          "\t$Rt, $addr", []> {
1254  let Inst{31-27} = 0b11111;
1255  let Inst{26-25} = 0b00;
1256  let Inst{24} = signed;
1257  let Inst{23} = 0;
1258  let Inst{22-21} = type;
1259  let Inst{20} = 1; // load
1260  let Inst{11} = 1;
1261  let Inst{10-8} = 0b110; // PUW.
1262
1263  bits<4> Rt;
1264  bits<13> addr;
1265  let Inst{15-12} = Rt;
1266  let Inst{19-16} = addr{12-9};
1267  let Inst{7-0}   = addr{7-0};
1268}
1269
1270def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1271def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1272def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1273def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1274def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1275
1276// Store
1277defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR,
1278                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1279defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1280                   rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1281defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1282                   rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1283
1284// Store doubleword
1285let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1286def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1287                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1288               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1289
1290// Indexed stores
1291def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPRnopc:$base_wb),
1292                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1293                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1294                         "str", "\t$Rt, [$Rn, $addr]!",
1295                         "$Rn = $base_wb,@earlyclobber $base_wb",
1296             [(set GPRnopc:$base_wb,
1297                   (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1298
1299def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPRnopc:$base_wb),
1300                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1301                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1302                          "str", "\t$Rt, [$Rn], $addr",
1303                          "$Rn = $base_wb,@earlyclobber $base_wb",
1304             [(set GPRnopc:$base_wb,
1305                  (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1306
1307def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPRnopc:$base_wb),
1308                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1309                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1310                        "strh", "\t$Rt, [$Rn, $addr]!",
1311                        "$Rn = $base_wb,@earlyclobber $base_wb",
1312        [(set GPRnopc:$base_wb,
1313              (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1314
1315def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPRnopc:$base_wb),
1316                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1317                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1318                         "strh", "\t$Rt, [$Rn], $addr",
1319                         "$Rn = $base_wb,@earlyclobber $base_wb",
1320       [(set GPRnopc:$base_wb,
1321             (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1322
1323def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPRnopc:$base_wb),
1324                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1325                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1326                        "strb", "\t$Rt, [$Rn, $addr]!",
1327                        "$Rn = $base_wb,@earlyclobber $base_wb",
1328         [(set GPRnopc:$base_wb,
1329               (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1330
1331def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPRnopc:$base_wb),
1332                            (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr),
1333                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1334                         "strb", "\t$Rt, [$Rn], $addr",
1335                         "$Rn = $base_wb,@earlyclobber $base_wb",
1336        [(set GPRnopc:$base_wb,
1337              (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>;
1338
1339// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1340// only.
1341// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1342class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1343  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1344          "\t$Rt, $addr", []> {
1345  let Inst{31-27} = 0b11111;
1346  let Inst{26-25} = 0b00;
1347  let Inst{24} = 0; // not signed
1348  let Inst{23} = 0;
1349  let Inst{22-21} = type;
1350  let Inst{20} = 0; // store
1351  let Inst{11} = 1;
1352  let Inst{10-8} = 0b110; // PUW
1353
1354  bits<4> Rt;
1355  bits<13> addr;
1356  let Inst{15-12} = Rt;
1357  let Inst{19-16} = addr{12-9};
1358  let Inst{7-0}   = addr{7-0};
1359}
1360
1361def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1362def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1363def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1364
1365// ldrd / strd pre / post variants
1366// For disassembly only.
1367
1368def t2LDRD_PRE  : T2Ii8s4Tied<1, 1, 1,
1369                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1370                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1371                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1372
1373def t2LDRD_POST : T2Ii8s4Tied<0, 1, 1,
1374                 (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1375                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1376                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1377
1378def t2STRD_PRE  : T2Ii8s4Tied<1, 1, 0, (outs GPR:$wb),
1379                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1380                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1381
1382def t2STRD_POST : T2Ii8s4Tied<0, 1, 0, (outs GPR:$wb),
1383                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1384                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1385
1386// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1387// data/instruction access.  These are for disassembly only.
1388// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1389// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1390multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1391
1392  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1393                "\t$addr",
1394              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1395    let Inst{31-25} = 0b1111100;
1396    let Inst{24} = instr;
1397    let Inst{22} = 0;
1398    let Inst{21} = write;
1399    let Inst{20} = 1;
1400    let Inst{15-12} = 0b1111;
1401
1402    bits<17> addr;
1403    let addr{12}    = 1;           // add = TRUE
1404    let Inst{19-16} = addr{16-13}; // Rn
1405    let Inst{23}    = addr{12};    // U
1406    let Inst{11-0}  = addr{11-0};  // imm12
1407  }
1408
1409  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1410                "\t$addr",
1411               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1412    let Inst{31-25} = 0b1111100;
1413    let Inst{24} = instr;
1414    let Inst{23} = 0; // U = 0
1415    let Inst{22} = 0;
1416    let Inst{21} = write;
1417    let Inst{20} = 1;
1418    let Inst{15-12} = 0b1111;
1419    let Inst{11-8} = 0b1100;
1420
1421    bits<13> addr;
1422    let Inst{19-16} = addr{12-9}; // Rn
1423    let Inst{7-0}   = addr{7-0};  // imm8
1424  }
1425
1426  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1427               "\t$addr",
1428             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1429    let Inst{31-25} = 0b1111100;
1430    let Inst{24} = instr;
1431    let Inst{23} = 0; // add = TRUE for T1
1432    let Inst{22} = 0;
1433    let Inst{21} = write;
1434    let Inst{20} = 1;
1435    let Inst{15-12} = 0b1111;
1436    let Inst{11-6} = 0000000;
1437
1438    bits<10> addr;
1439    let Inst{19-16} = addr{9-6}; // Rn
1440    let Inst{3-0}   = addr{5-2}; // Rm
1441    let Inst{5-4}   = addr{1-0}; // imm2
1442
1443    let DecoderMethod = "DecodeT2LoadShift";
1444  }
1445}
1446
1447defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1448defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1449defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1450
1451//===----------------------------------------------------------------------===//
1452//  Load / store multiple Instructions.
1453//
1454
1455multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1456                            InstrItinClass itin_upd, bit L_bit> {
1457  def IA :
1458    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1459         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1460    bits<4>  Rn;
1461    bits<16> regs;
1462
1463    let Inst{31-27} = 0b11101;
1464    let Inst{26-25} = 0b00;
1465    let Inst{24-23} = 0b01;     // Increment After
1466    let Inst{22}    = 0;
1467    let Inst{21}    = 0;        // No writeback
1468    let Inst{20}    = L_bit;
1469    let Inst{19-16} = Rn;
1470    let Inst{15-0}  = regs;
1471  }
1472  def IA_UPD :
1473    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1474          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1475    bits<4>  Rn;
1476    bits<16> regs;
1477
1478    let Inst{31-27} = 0b11101;
1479    let Inst{26-25} = 0b00;
1480    let Inst{24-23} = 0b01;     // Increment After
1481    let Inst{22}    = 0;
1482    let Inst{21}    = 1;        // Writeback
1483    let Inst{20}    = L_bit;
1484    let Inst{19-16} = Rn;
1485    let Inst{15-0}  = regs;
1486  }
1487  def DB :
1488    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1489         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1490    bits<4>  Rn;
1491    bits<16> regs;
1492
1493    let Inst{31-27} = 0b11101;
1494    let Inst{26-25} = 0b00;
1495    let Inst{24-23} = 0b10;     // Decrement Before
1496    let Inst{22}    = 0;
1497    let Inst{21}    = 0;        // No writeback
1498    let Inst{20}    = L_bit;
1499    let Inst{19-16} = Rn;
1500    let Inst{15-0}  = regs;
1501  }
1502  def DB_UPD :
1503    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1504          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1505    bits<4>  Rn;
1506    bits<16> regs;
1507
1508    let Inst{31-27} = 0b11101;
1509    let Inst{26-25} = 0b00;
1510    let Inst{24-23} = 0b10;     // Decrement Before
1511    let Inst{22}    = 0;
1512    let Inst{21}    = 1;        // Writeback
1513    let Inst{20}    = L_bit;
1514    let Inst{19-16} = Rn;
1515    let Inst{15-0}  = regs;
1516  }
1517}
1518
1519let neverHasSideEffects = 1 in {
1520
1521let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1522defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1523
1524let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1525defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1526
1527} // neverHasSideEffects
1528
1529
1530//===----------------------------------------------------------------------===//
1531//  Move Instructions.
1532//
1533
1534let neverHasSideEffects = 1 in
1535def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1536                   "mov", ".w\t$Rd, $Rm", []> {
1537  let Inst{31-27} = 0b11101;
1538  let Inst{26-25} = 0b01;
1539  let Inst{24-21} = 0b0010;
1540  let Inst{19-16} = 0b1111; // Rn
1541  let Inst{14-12} = 0b000;
1542  let Inst{7-4} = 0b0000;
1543}
1544
1545// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1546let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1547    AddedComplexity = 1 in
1548def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1549                   "mov", ".w\t$Rd, $imm",
1550                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1551  let Inst{31-27} = 0b11110;
1552  let Inst{25} = 0;
1553  let Inst{24-21} = 0b0010;
1554  let Inst{19-16} = 0b1111; // Rn
1555  let Inst{15} = 0;
1556}
1557
1558def : t2InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1559                                                   pred:$p, cc_out:$s)>;
1560
1561let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1562def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1563                   "movw", "\t$Rd, $imm",
1564                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1565  let Inst{31-27} = 0b11110;
1566  let Inst{25} = 1;
1567  let Inst{24-21} = 0b0010;
1568  let Inst{20} = 0; // The S bit.
1569  let Inst{15} = 0;
1570
1571  bits<4> Rd;
1572  bits<16> imm;
1573
1574  let Inst{11-8}  = Rd;
1575  let Inst{19-16} = imm{15-12};
1576  let Inst{26}    = imm{11};
1577  let Inst{14-12} = imm{10-8};
1578  let Inst{7-0}   = imm{7-0};
1579}
1580
1581def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1582                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1583
1584let Constraints = "$src = $Rd" in {
1585def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1586                    (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1587                    "movt", "\t$Rd, $imm",
1588                    [(set rGPR:$Rd,
1589                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1590  let Inst{31-27} = 0b11110;
1591  let Inst{25} = 1;
1592  let Inst{24-21} = 0b0110;
1593  let Inst{20} = 0; // The S bit.
1594  let Inst{15} = 0;
1595
1596  bits<4> Rd;
1597  bits<16> imm;
1598
1599  let Inst{11-8}  = Rd;
1600  let Inst{19-16} = imm{15-12};
1601  let Inst{26}    = imm{11};
1602  let Inst{14-12} = imm{10-8};
1603  let Inst{7-0}   = imm{7-0};
1604}
1605
1606def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1607                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1608} // Constraints
1609
1610def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1611
1612//===----------------------------------------------------------------------===//
1613//  Extend Instructions.
1614//
1615
1616// Sign extenders
1617
1618def t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1619                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1620def t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1621                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1622def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1623
1624def t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1625                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1626def t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1627                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1628def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1629
1630// TODO: SXT(A){B|H}16
1631
1632// Zero extenders
1633
1634let AddedComplexity = 16 in {
1635def t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1636                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1637def t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1638                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1639def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1640                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1641
1642// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1643//        The transformation should probably be done as a combiner action
1644//        instead so we can include a check for masking back in the upper
1645//        eight bits of the source into the lower eight bits of the result.
1646//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1647//            (t2UXTB16 rGPR:$Src, 3)>,
1648//          Requires<[HasT2ExtractPack, IsThumb2]>;
1649def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1650            (t2UXTB16 rGPR:$Src, 1)>,
1651        Requires<[HasT2ExtractPack, IsThumb2]>;
1652
1653def t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1654                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1655def t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1656                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1657def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1658}
1659
1660//===----------------------------------------------------------------------===//
1661//  Arithmetic Instructions.
1662//
1663
1664defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1665                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1666defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1667                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1668
1669// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1670defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1671                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1672                             BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1673defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1674                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1675                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1676
1677defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1678                          BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1679defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1680                          BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1681defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1682                                                             node:$RHS)>, 1>;
1683defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1684                                                             node:$RHS)>>;
1685
1686// RSB
1687defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1688                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1689defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1690                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1691
1692// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1693// The assume-no-carry-in form uses the negation of the input since add/sub
1694// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1695// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1696// details.
1697// The AddedComplexity preferences the first variant over the others since
1698// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1699let AddedComplexity = 1 in
1700def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1701            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1702def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1703            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1704def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1705            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1706let AddedComplexity = 1 in
1707def : T2Pat<(addc       rGPR:$src, imm0_255_neg:$imm),
1708            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1709def : T2Pat<(addc       rGPR:$src, t2_so_imm_neg:$imm),
1710            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1711// The with-carry-in form matches bitwise not instead of the negation.
1712// Effectively, the inverse interpretation of the carry flag already accounts
1713// for part of the negation.
1714let AddedComplexity = 1 in
1715def : T2Pat<(adde_dead_carry       rGPR:$src, imm0_255_not:$imm),
1716            (t2SBCri    rGPR:$src, imm0_255_not:$imm)>;
1717def : T2Pat<(adde_dead_carry       rGPR:$src, t2_so_imm_not:$imm),
1718            (t2SBCri    rGPR:$src, t2_so_imm_not:$imm)>;
1719let AddedComplexity = 1 in
1720def : T2Pat<(adde_live_carry       rGPR:$src, imm0_255_not:$imm),
1721            (t2SBCSri   rGPR:$src, imm0_255_not:$imm)>;
1722def : T2Pat<(adde_live_carry       rGPR:$src, t2_so_imm_not:$imm),
1723            (t2SBCSri   rGPR:$src, t2_so_imm_not:$imm)>;
1724
1725// Select Bytes -- for disassembly only
1726
1727def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1728                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1729          Requires<[IsThumb2, HasThumb2DSP]> {
1730  let Inst{31-27} = 0b11111;
1731  let Inst{26-24} = 0b010;
1732  let Inst{23} = 0b1;
1733  let Inst{22-20} = 0b010;
1734  let Inst{15-12} = 0b1111;
1735  let Inst{7} = 0b1;
1736  let Inst{6-4} = 0b000;
1737}
1738
1739// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1740// And Miscellaneous operations -- for disassembly only
1741class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1742              list<dag> pat = [/* For disassembly only; pattern left blank */],
1743              dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1744              string asm = "\t$Rd, $Rn, $Rm">
1745  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1746    Requires<[IsThumb2, HasThumb2DSP]> {
1747  let Inst{31-27} = 0b11111;
1748  let Inst{26-23} = 0b0101;
1749  let Inst{22-20} = op22_20;
1750  let Inst{15-12} = 0b1111;
1751  let Inst{7-4} = op7_4;
1752
1753  bits<4> Rd;
1754  bits<4> Rn;
1755  bits<4> Rm;
1756
1757  let Inst{11-8}  = Rd;
1758  let Inst{19-16} = Rn;
1759  let Inst{3-0}   = Rm;
1760}
1761
1762// Saturating add/subtract -- for disassembly only
1763
1764def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1765                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1766                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1767def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1768def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1769def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1770def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd", [],
1771                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1772def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub", [],
1773                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1774def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1775def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1776                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1777                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1778def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1779def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1780def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1781def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1782def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1783def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1784def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1785def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1786
1787// Signed/Unsigned add/subtract -- for disassembly only
1788
1789def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1790def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1791def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1792def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1793def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1794def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1795def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1796def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1797def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1798def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1799def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1800def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1801
1802// Signed/Unsigned halving add/subtract -- for disassembly only
1803
1804def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1805def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1806def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1807def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1808def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1809def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1810def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1811def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1812def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1813def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1814def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1815def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1816
1817// Helper class for disassembly only
1818// A6.3.16 & A6.3.17
1819// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1820class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1821  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1822  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1823  let Inst{31-27} = 0b11111;
1824  let Inst{26-24} = 0b011;
1825  let Inst{23}    = long;
1826  let Inst{22-20} = op22_20;
1827  let Inst{7-4}   = op7_4;
1828}
1829
1830class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1831  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1832  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1833  let Inst{31-27} = 0b11111;
1834  let Inst{26-24} = 0b011;
1835  let Inst{23}    = long;
1836  let Inst{22-20} = op22_20;
1837  let Inst{7-4}   = op7_4;
1838}
1839
1840// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1841
1842def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1843                                           (ins rGPR:$Rn, rGPR:$Rm),
1844                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1845          Requires<[IsThumb2, HasThumb2DSP]> {
1846  let Inst{15-12} = 0b1111;
1847}
1848def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1849                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1850                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1851          Requires<[IsThumb2, HasThumb2DSP]>;
1852
1853// Signed/Unsigned saturate -- for disassembly only
1854
1855class T2SatI<dag oops, dag iops, InstrItinClass itin,
1856           string opc, string asm, list<dag> pattern>
1857  : T2I<oops, iops, itin, opc, asm, pattern> {
1858  bits<4> Rd;
1859  bits<4> Rn;
1860  bits<5> sat_imm;
1861  bits<7> sh;
1862
1863  let Inst{11-8}  = Rd;
1864  let Inst{19-16} = Rn;
1865  let Inst{4-0}   = sat_imm;
1866  let Inst{21}    = sh{5};
1867  let Inst{14-12} = sh{4-2};
1868  let Inst{7-6}   = sh{1-0};
1869}
1870
1871def t2SSAT: T2SatI<
1872              (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1873              NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1874              [/* For disassembly only; pattern left blank */]> {
1875  let Inst{31-27} = 0b11110;
1876  let Inst{25-22} = 0b1100;
1877  let Inst{20} = 0;
1878  let Inst{15} = 0;
1879}
1880
1881def t2SSAT16: T2SatI<
1882                (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1883                "ssat16", "\t$Rd, $sat_imm, $Rn",
1884                [/* For disassembly only; pattern left blank */]>,
1885          Requires<[IsThumb2, HasThumb2DSP]> {
1886  let Inst{31-27} = 0b11110;
1887  let Inst{25-22} = 0b1100;
1888  let Inst{20} = 0;
1889  let Inst{15} = 0;
1890  let Inst{21} = 1;        // sh = '1'
1891  let Inst{14-12} = 0b000; // imm3 = '000'
1892  let Inst{7-6} = 0b00;    // imm2 = '00'
1893}
1894
1895def t2USAT: T2SatI<
1896                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1897                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1898                [/* For disassembly only; pattern left blank */]> {
1899  let Inst{31-27} = 0b11110;
1900  let Inst{25-22} = 0b1110;
1901  let Inst{20} = 0;
1902  let Inst{15} = 0;
1903}
1904
1905def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn),
1906                     NoItinerary,
1907                     "usat16", "\t$Rd, $sat_imm, $Rn",
1908                     [/* For disassembly only; pattern left blank */]>,
1909          Requires<[IsThumb2, HasThumb2DSP]> {
1910  let Inst{31-27} = 0b11110;
1911  let Inst{25-22} = 0b1110;
1912  let Inst{20} = 0;
1913  let Inst{15} = 0;
1914  let Inst{21} = 1;        // sh = '1'
1915  let Inst{14-12} = 0b000; // imm3 = '000'
1916  let Inst{7-6} = 0b00;    // imm2 = '00'
1917}
1918
1919def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1920def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1921
1922//===----------------------------------------------------------------------===//
1923//  Shift and rotate Instructions.
1924//
1925
1926defm t2LSL  : T2I_sh_ir<0b00, "lsl", imm1_31, BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
1927defm t2LSR  : T2I_sh_ir<0b01, "lsr", imm_sr, BinOpFrag<(srl  node:$LHS, node:$RHS)>>;
1928defm t2ASR  : T2I_sh_ir<0b10, "asr", imm_sr, BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
1929defm t2ROR  : T2I_sh_ir<0b11, "ror", imm1_31, BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1930
1931// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1932def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1933          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1934
1935let Uses = [CPSR] in {
1936def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1937                   "rrx", "\t$Rd, $Rm",
1938                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1939  let Inst{31-27} = 0b11101;
1940  let Inst{26-25} = 0b01;
1941  let Inst{24-21} = 0b0010;
1942  let Inst{19-16} = 0b1111; // Rn
1943  let Inst{14-12} = 0b000;
1944  let Inst{7-4} = 0b0011;
1945}
1946}
1947
1948let isCodeGenOnly = 1, Defs = [CPSR] in {
1949def t2MOVsrl_flag : T2TwoRegShiftImm<
1950                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1951                        "lsrs", ".w\t$Rd, $Rm, #1",
1952                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
1953  let Inst{31-27} = 0b11101;
1954  let Inst{26-25} = 0b01;
1955  let Inst{24-21} = 0b0010;
1956  let Inst{20} = 1; // The S bit.
1957  let Inst{19-16} = 0b1111; // Rn
1958  let Inst{5-4} = 0b01; // Shift type.
1959  // Shift amount = Inst{14-12:7-6} = 1.
1960  let Inst{14-12} = 0b000;
1961  let Inst{7-6} = 0b01;
1962}
1963def t2MOVsra_flag : T2TwoRegShiftImm<
1964                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1965                        "asrs", ".w\t$Rd, $Rm, #1",
1966                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
1967  let Inst{31-27} = 0b11101;
1968  let Inst{26-25} = 0b01;
1969  let Inst{24-21} = 0b0010;
1970  let Inst{20} = 1; // The S bit.
1971  let Inst{19-16} = 0b1111; // Rn
1972  let Inst{5-4} = 0b10; // Shift type.
1973  // Shift amount = Inst{14-12:7-6} = 1.
1974  let Inst{14-12} = 0b000;
1975  let Inst{7-6} = 0b01;
1976}
1977}
1978
1979//===----------------------------------------------------------------------===//
1980//  Bitwise Instructions.
1981//
1982
1983defm t2AND  : T2I_bin_w_irs<0b0000, "and",
1984                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1985                            BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
1986defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
1987                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1988                            BinOpFrag<(or  node:$LHS, node:$RHS)>, "t2ORR", 1>;
1989defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
1990                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1991                            BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
1992
1993defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
1994                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
1995                            BinOpFrag<(and node:$LHS, (not node:$RHS))>,
1996                            "t2BIC">;
1997
1998class T2BitFI<dag oops, dag iops, InstrItinClass itin,
1999              string opc, string asm, list<dag> pattern>
2000    : T2I<oops, iops, itin, opc, asm, pattern> {
2001  bits<4> Rd;
2002  bits<5> msb;
2003  bits<5> lsb;
2004
2005  let Inst{11-8}  = Rd;
2006  let Inst{4-0}   = msb{4-0};
2007  let Inst{14-12} = lsb{4-2};
2008  let Inst{7-6}   = lsb{1-0};
2009}
2010
2011class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2012              string opc, string asm, list<dag> pattern>
2013    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2014  bits<4> Rn;
2015
2016  let Inst{19-16} = Rn;
2017}
2018
2019let Constraints = "$src = $Rd" in
2020def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2021                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2022                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2023  let Inst{31-27} = 0b11110;
2024  let Inst{26} = 0; // should be 0.
2025  let Inst{25} = 1;
2026  let Inst{24-20} = 0b10110;
2027  let Inst{19-16} = 0b1111; // Rn
2028  let Inst{15} = 0;
2029  let Inst{5} = 0; // should be 0.
2030
2031  bits<10> imm;
2032  let msb{4-0} = imm{9-5};
2033  let lsb{4-0} = imm{4-0};
2034}
2035
2036def t2SBFX: T2TwoRegBitFI<
2037                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2038                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2039  let Inst{31-27} = 0b11110;
2040  let Inst{25} = 1;
2041  let Inst{24-20} = 0b10100;
2042  let Inst{15} = 0;
2043}
2044
2045def t2UBFX: T2TwoRegBitFI<
2046                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2047                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2048  let Inst{31-27} = 0b11110;
2049  let Inst{25} = 1;
2050  let Inst{24-20} = 0b11100;
2051  let Inst{15} = 0;
2052}
2053
2054// A8.6.18  BFI - Bitfield insert (Encoding T1)
2055let Constraints = "$src = $Rd" in {
2056  def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2057                  (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2058                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2059                  [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2060                                   bf_inv_mask_imm:$imm))]> {
2061    let Inst{31-27} = 0b11110;
2062    let Inst{26} = 0; // should be 0.
2063    let Inst{25} = 1;
2064    let Inst{24-20} = 0b10110;
2065    let Inst{15} = 0;
2066    let Inst{5} = 0; // should be 0.
2067
2068    bits<10> imm;
2069    let msb{4-0} = imm{9-5};
2070    let lsb{4-0} = imm{4-0};
2071  }
2072
2073  // GNU as only supports this form of bfi (w/ 4 arguments)
2074  let isAsmParserOnly = 1 in
2075  def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2076                  (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2077                       width_imm:$width),
2078                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2079                  []> {
2080    let Inst{31-27} = 0b11110;
2081    let Inst{26} = 0; // should be 0.
2082    let Inst{25} = 1;
2083    let Inst{24-20} = 0b10110;
2084    let Inst{15} = 0;
2085    let Inst{5} = 0; // should be 0.
2086
2087    bits<5> lsbit;
2088    bits<5> width;
2089    let msb{4-0} = width; // Custom encoder => lsb+width-1
2090    let lsb{4-0} = lsbit;
2091  }
2092}
2093
2094defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2095                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2096                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>,
2097                          "t2ORN", 0, "">;
2098
2099// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2100let AddedComplexity = 1 in
2101defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2102                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2103                          UnOpFrag<(not node:$Src)>, 1, 1>;
2104
2105
2106let AddedComplexity = 1 in
2107def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2108            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2109
2110// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2111def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2112            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2113            Requires<[IsThumb2]>;
2114
2115def : T2Pat<(t2_so_imm_not:$src),
2116            (t2MVNi t2_so_imm_not:$src)>;
2117
2118//===----------------------------------------------------------------------===//
2119//  Multiply Instructions.
2120//
2121let isCommutable = 1 in
2122def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2123                "mul", "\t$Rd, $Rn, $Rm",
2124                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2125  let Inst{31-27} = 0b11111;
2126  let Inst{26-23} = 0b0110;
2127  let Inst{22-20} = 0b000;
2128  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2129  let Inst{7-4} = 0b0000; // Multiply
2130}
2131
2132def t2MLA: T2FourReg<
2133                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2134                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2135                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2136  let Inst{31-27} = 0b11111;
2137  let Inst{26-23} = 0b0110;
2138  let Inst{22-20} = 0b000;
2139  let Inst{7-4} = 0b0000; // Multiply
2140}
2141
2142def t2MLS: T2FourReg<
2143                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2144                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2145                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2146  let Inst{31-27} = 0b11111;
2147  let Inst{26-23} = 0b0110;
2148  let Inst{22-20} = 0b000;
2149  let Inst{7-4} = 0b0001; // Multiply and Subtract
2150}
2151
2152// Extra precision multiplies with low / high results
2153let neverHasSideEffects = 1 in {
2154let isCommutable = 1 in {
2155def t2SMULL : T2MulLong<0b000, 0b0000,
2156                  (outs rGPR:$RdLo, rGPR:$RdHi),
2157                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2158                   "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2159
2160def t2UMULL : T2MulLong<0b010, 0b0000,
2161                  (outs rGPR:$RdLo, rGPR:$RdHi),
2162                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2163                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2164} // isCommutable
2165
2166// Multiply + accumulate
2167def t2SMLAL : T2MulLong<0b100, 0b0000,
2168                  (outs rGPR:$RdLo, rGPR:$RdHi),
2169                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2170                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2171
2172def t2UMLAL : T2MulLong<0b110, 0b0000,
2173                  (outs rGPR:$RdLo, rGPR:$RdHi),
2174                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2175                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2176
2177def t2UMAAL : T2MulLong<0b110, 0b0110,
2178                  (outs rGPR:$RdLo, rGPR:$RdHi),
2179                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2180                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2181          Requires<[IsThumb2, HasThumb2DSP]>;
2182} // neverHasSideEffects
2183
2184// Rounding variants of the below included for disassembly only
2185
2186// Most significant word multiply
2187def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2188                  "smmul", "\t$Rd, $Rn, $Rm",
2189                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2190          Requires<[IsThumb2, HasThumb2DSP]> {
2191  let Inst{31-27} = 0b11111;
2192  let Inst{26-23} = 0b0110;
2193  let Inst{22-20} = 0b101;
2194  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2195  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2196}
2197
2198def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2199                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
2200          Requires<[IsThumb2, HasThumb2DSP]> {
2201  let Inst{31-27} = 0b11111;
2202  let Inst{26-23} = 0b0110;
2203  let Inst{22-20} = 0b101;
2204  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2205  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2206}
2207
2208def t2SMMLA : T2FourReg<
2209        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2210                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2211                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2212          Requires<[IsThumb2, HasThumb2DSP]> {
2213  let Inst{31-27} = 0b11111;
2214  let Inst{26-23} = 0b0110;
2215  let Inst{22-20} = 0b101;
2216  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2217}
2218
2219def t2SMMLAR: T2FourReg<
2220        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2221                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2222          Requires<[IsThumb2, HasThumb2DSP]> {
2223  let Inst{31-27} = 0b11111;
2224  let Inst{26-23} = 0b0110;
2225  let Inst{22-20} = 0b101;
2226  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2227}
2228
2229def t2SMMLS: T2FourReg<
2230        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2231                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2232                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2233          Requires<[IsThumb2, HasThumb2DSP]> {
2234  let Inst{31-27} = 0b11111;
2235  let Inst{26-23} = 0b0110;
2236  let Inst{22-20} = 0b110;
2237  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2238}
2239
2240def t2SMMLSR:T2FourReg<
2241        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2242                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2243          Requires<[IsThumb2, HasThumb2DSP]> {
2244  let Inst{31-27} = 0b11111;
2245  let Inst{26-23} = 0b0110;
2246  let Inst{22-20} = 0b110;
2247  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2248}
2249
2250multiclass T2I_smul<string opc, PatFrag opnode> {
2251  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2252              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2253              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2254                                      (sext_inreg rGPR:$Rm, i16)))]>,
2255          Requires<[IsThumb2, HasThumb2DSP]> {
2256    let Inst{31-27} = 0b11111;
2257    let Inst{26-23} = 0b0110;
2258    let Inst{22-20} = 0b001;
2259    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2260    let Inst{7-6} = 0b00;
2261    let Inst{5-4} = 0b00;
2262  }
2263
2264  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2265              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2266              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2267                                      (sra rGPR:$Rm, (i32 16))))]>,
2268          Requires<[IsThumb2, HasThumb2DSP]> {
2269    let Inst{31-27} = 0b11111;
2270    let Inst{26-23} = 0b0110;
2271    let Inst{22-20} = 0b001;
2272    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2273    let Inst{7-6} = 0b00;
2274    let Inst{5-4} = 0b01;
2275  }
2276
2277  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2278              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2279              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2280                                      (sext_inreg rGPR:$Rm, i16)))]>,
2281          Requires<[IsThumb2, HasThumb2DSP]> {
2282    let Inst{31-27} = 0b11111;
2283    let Inst{26-23} = 0b0110;
2284    let Inst{22-20} = 0b001;
2285    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2286    let Inst{7-6} = 0b00;
2287    let Inst{5-4} = 0b10;
2288  }
2289
2290  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2291              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2292              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2293                                      (sra rGPR:$Rm, (i32 16))))]>,
2294          Requires<[IsThumb2, HasThumb2DSP]> {
2295    let Inst{31-27} = 0b11111;
2296    let Inst{26-23} = 0b0110;
2297    let Inst{22-20} = 0b001;
2298    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2299    let Inst{7-6} = 0b00;
2300    let Inst{5-4} = 0b11;
2301  }
2302
2303  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2304              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2305              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2306                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2307          Requires<[IsThumb2, HasThumb2DSP]> {
2308    let Inst{31-27} = 0b11111;
2309    let Inst{26-23} = 0b0110;
2310    let Inst{22-20} = 0b011;
2311    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2312    let Inst{7-6} = 0b00;
2313    let Inst{5-4} = 0b00;
2314  }
2315
2316  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2317              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2318              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2319                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2320          Requires<[IsThumb2, HasThumb2DSP]> {
2321    let Inst{31-27} = 0b11111;
2322    let Inst{26-23} = 0b0110;
2323    let Inst{22-20} = 0b011;
2324    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2325    let Inst{7-6} = 0b00;
2326    let Inst{5-4} = 0b01;
2327  }
2328}
2329
2330
2331multiclass T2I_smla<string opc, PatFrag opnode> {
2332  def BB : T2FourReg<
2333        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2334              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2335              [(set rGPR:$Rd, (add rGPR:$Ra,
2336                               (opnode (sext_inreg rGPR:$Rn, i16),
2337                                       (sext_inreg rGPR:$Rm, i16))))]>,
2338          Requires<[IsThumb2, HasThumb2DSP]> {
2339    let Inst{31-27} = 0b11111;
2340    let Inst{26-23} = 0b0110;
2341    let Inst{22-20} = 0b001;
2342    let Inst{7-6} = 0b00;
2343    let Inst{5-4} = 0b00;
2344  }
2345
2346  def BT : T2FourReg<
2347       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2348             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2349             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2350                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2351          Requires<[IsThumb2, HasThumb2DSP]> {
2352    let Inst{31-27} = 0b11111;
2353    let Inst{26-23} = 0b0110;
2354    let Inst{22-20} = 0b001;
2355    let Inst{7-6} = 0b00;
2356    let Inst{5-4} = 0b01;
2357  }
2358
2359  def TB : T2FourReg<
2360        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2361              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2362              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2363                                               (sext_inreg rGPR:$Rm, i16))))]>,
2364          Requires<[IsThumb2, HasThumb2DSP]> {
2365    let Inst{31-27} = 0b11111;
2366    let Inst{26-23} = 0b0110;
2367    let Inst{22-20} = 0b001;
2368    let Inst{7-6} = 0b00;
2369    let Inst{5-4} = 0b10;
2370  }
2371
2372  def TT : T2FourReg<
2373        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2374              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2375             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2376                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2377          Requires<[IsThumb2, HasThumb2DSP]> {
2378    let Inst{31-27} = 0b11111;
2379    let Inst{26-23} = 0b0110;
2380    let Inst{22-20} = 0b001;
2381    let Inst{7-6} = 0b00;
2382    let Inst{5-4} = 0b11;
2383  }
2384
2385  def WB : T2FourReg<
2386        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2387              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2388              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2389                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2390          Requires<[IsThumb2, HasThumb2DSP]> {
2391    let Inst{31-27} = 0b11111;
2392    let Inst{26-23} = 0b0110;
2393    let Inst{22-20} = 0b011;
2394    let Inst{7-6} = 0b00;
2395    let Inst{5-4} = 0b00;
2396  }
2397
2398  def WT : T2FourReg<
2399        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2400              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2401              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2402                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2403          Requires<[IsThumb2, HasThumb2DSP]> {
2404    let Inst{31-27} = 0b11111;
2405    let Inst{26-23} = 0b0110;
2406    let Inst{22-20} = 0b011;
2407    let Inst{7-6} = 0b00;
2408    let Inst{5-4} = 0b01;
2409  }
2410}
2411
2412defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2413defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2414
2415// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2416def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2417         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2418           [/* For disassembly only; pattern left blank */]>,
2419          Requires<[IsThumb2, HasThumb2DSP]>;
2420def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2421         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2422           [/* For disassembly only; pattern left blank */]>,
2423          Requires<[IsThumb2, HasThumb2DSP]>;
2424def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2425         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2426           [/* For disassembly only; pattern left blank */]>,
2427          Requires<[IsThumb2, HasThumb2DSP]>;
2428def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2429         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2430           [/* For disassembly only; pattern left blank */]>,
2431          Requires<[IsThumb2, HasThumb2DSP]>;
2432
2433// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2434// These are for disassembly only.
2435
2436def t2SMUAD: T2ThreeReg_mac<
2437            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2438            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2439          Requires<[IsThumb2, HasThumb2DSP]> {
2440  let Inst{15-12} = 0b1111;
2441}
2442def t2SMUADX:T2ThreeReg_mac<
2443            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2444            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2445          Requires<[IsThumb2, HasThumb2DSP]> {
2446  let Inst{15-12} = 0b1111;
2447}
2448def t2SMUSD: T2ThreeReg_mac<
2449            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2450            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2451          Requires<[IsThumb2, HasThumb2DSP]> {
2452  let Inst{15-12} = 0b1111;
2453}
2454def t2SMUSDX:T2ThreeReg_mac<
2455            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2456            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2457          Requires<[IsThumb2, HasThumb2DSP]> {
2458  let Inst{15-12} = 0b1111;
2459}
2460def t2SMLAD   : T2FourReg_mac<
2461            0, 0b010, 0b0000, (outs rGPR:$Rd),
2462            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2463            "\t$Rd, $Rn, $Rm, $Ra", []>,
2464          Requires<[IsThumb2, HasThumb2DSP]>;
2465def t2SMLADX  : T2FourReg_mac<
2466            0, 0b010, 0b0001, (outs rGPR:$Rd),
2467            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2468            "\t$Rd, $Rn, $Rm, $Ra", []>,
2469          Requires<[IsThumb2, HasThumb2DSP]>;
2470def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2471            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2472            "\t$Rd, $Rn, $Rm, $Ra", []>,
2473          Requires<[IsThumb2, HasThumb2DSP]>;
2474def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2475            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2476            "\t$Rd, $Rn, $Rm, $Ra", []>,
2477          Requires<[IsThumb2, HasThumb2DSP]>;
2478def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2479                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2480                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2481          Requires<[IsThumb2, HasThumb2DSP]>;
2482def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2483                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2484                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2485          Requires<[IsThumb2, HasThumb2DSP]>;
2486def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2487                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2488                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2489          Requires<[IsThumb2, HasThumb2DSP]>;
2490def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2491                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2492                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2493          Requires<[IsThumb2, HasThumb2DSP]>;
2494
2495//===----------------------------------------------------------------------===//
2496//  Division Instructions.
2497//  Signed and unsigned division on v7-M
2498//
2499def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2500                 "sdiv", "\t$Rd, $Rn, $Rm",
2501                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2502                 Requires<[HasDivide, IsThumb2]> {
2503  let Inst{31-27} = 0b11111;
2504  let Inst{26-21} = 0b011100;
2505  let Inst{20} = 0b1;
2506  let Inst{15-12} = 0b1111;
2507  let Inst{7-4} = 0b1111;
2508}
2509
2510def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2511                 "udiv", "\t$Rd, $Rn, $Rm",
2512                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2513                 Requires<[HasDivide, IsThumb2]> {
2514  let Inst{31-27} = 0b11111;
2515  let Inst{26-21} = 0b011101;
2516  let Inst{20} = 0b1;
2517  let Inst{15-12} = 0b1111;
2518  let Inst{7-4} = 0b1111;
2519}
2520
2521//===----------------------------------------------------------------------===//
2522//  Misc. Arithmetic Instructions.
2523//
2524
2525class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2526      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2527  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2528  let Inst{31-27} = 0b11111;
2529  let Inst{26-22} = 0b01010;
2530  let Inst{21-20} = op1;
2531  let Inst{15-12} = 0b1111;
2532  let Inst{7-6} = 0b10;
2533  let Inst{5-4} = op2;
2534  let Rn{3-0} = Rm;
2535}
2536
2537def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2538                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2539
2540def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2541                      "rbit", "\t$Rd, $Rm",
2542                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2543
2544def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2545                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2546
2547def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2548                       "rev16", ".w\t$Rd, $Rm",
2549                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2550
2551def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2552                       "revsh", ".w\t$Rd, $Rm",
2553                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2554
2555def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2556                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2557            (t2REVSH rGPR:$Rm)>;
2558
2559def t2PKHBT : T2ThreeReg<
2560            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2561                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2562                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2563                                      (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2564                                           0xFFFF0000)))]>,
2565                  Requires<[HasT2ExtractPack, IsThumb2]> {
2566  let Inst{31-27} = 0b11101;
2567  let Inst{26-25} = 0b01;
2568  let Inst{24-20} = 0b01100;
2569  let Inst{5} = 0; // BT form
2570  let Inst{4} = 0;
2571
2572  bits<5> sh;
2573  let Inst{14-12} = sh{4-2};
2574  let Inst{7-6}   = sh{1-0};
2575}
2576
2577// Alternate cases for PKHBT where identities eliminate some nodes.
2578def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2579            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2580            Requires<[HasT2ExtractPack, IsThumb2]>;
2581def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2582            (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2583            Requires<[HasT2ExtractPack, IsThumb2]>;
2584
2585// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2586// will match the pattern below.
2587def t2PKHTB : T2ThreeReg<
2588                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2589                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2590                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2591                                       (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2592                                            0xFFFF)))]>,
2593                  Requires<[HasT2ExtractPack, IsThumb2]> {
2594  let Inst{31-27} = 0b11101;
2595  let Inst{26-25} = 0b01;
2596  let Inst{24-20} = 0b01100;
2597  let Inst{5} = 1; // TB form
2598  let Inst{4} = 0;
2599
2600  bits<5> sh;
2601  let Inst{14-12} = sh{4-2};
2602  let Inst{7-6}   = sh{1-0};
2603}
2604
2605// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2606// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2607def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2608            (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2609            Requires<[HasT2ExtractPack, IsThumb2]>;
2610def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2611                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2612            (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2613            Requires<[HasT2ExtractPack, IsThumb2]>;
2614
2615//===----------------------------------------------------------------------===//
2616//  Comparison Instructions...
2617//
2618defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2619                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2620                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2621
2622def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_imm:$imm),
2623            (t2CMPri  GPR:$lhs, t2_so_imm:$imm)>;
2624def : T2Pat<(ARMcmpZ  GPR:$lhs, rGPR:$rhs),
2625            (t2CMPrr  GPR:$lhs, rGPR:$rhs)>;
2626def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_reg:$rhs),
2627            (t2CMPrs  GPR:$lhs, t2_so_reg:$rhs)>;
2628
2629//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2630//       Compare-to-zero still works out, just not the relationals
2631//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2632//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2633defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2634                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2635                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2636
2637//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2638//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2639
2640def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
2641            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2642
2643defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2644                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2645                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2646defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2647                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2648                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2649
2650// Conditional moves
2651// FIXME: should be able to write a pattern for ARMcmov, but can't use
2652// a two-value operand where a dag node expects two operands. :(
2653let neverHasSideEffects = 1 in {
2654def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2655                            (ins rGPR:$false, rGPR:$Rm, pred:$p),
2656                            4, IIC_iCMOVr,
2657   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2658                RegConstraint<"$false = $Rd">;
2659
2660let isMoveImm = 1 in
2661def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2662                            (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2663                   4, IIC_iCMOVi,
2664[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2665                   RegConstraint<"$false = $Rd">;
2666
2667// FIXME: Pseudo-ize these. For now, just mark codegen only.
2668let isCodeGenOnly = 1 in {
2669let isMoveImm = 1 in
2670def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2671                      IIC_iCMOVi,
2672                      "movw", "\t$Rd, $imm", []>,
2673                      RegConstraint<"$false = $Rd"> {
2674  let Inst{31-27} = 0b11110;
2675  let Inst{25} = 1;
2676  let Inst{24-21} = 0b0010;
2677  let Inst{20} = 0; // The S bit.
2678  let Inst{15} = 0;
2679
2680  bits<4> Rd;
2681  bits<16> imm;
2682
2683  let Inst{11-8}  = Rd;
2684  let Inst{19-16} = imm{15-12};
2685  let Inst{26}    = imm{11};
2686  let Inst{14-12} = imm{10-8};
2687  let Inst{7-0}   = imm{7-0};
2688}
2689
2690let isMoveImm = 1 in
2691def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2692                               (ins rGPR:$false, i32imm:$src, pred:$p),
2693                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2694
2695let isMoveImm = 1 in
2696def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2697                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2698[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2699                   imm:$cc, CCR:$ccr))*/]>,
2700                   RegConstraint<"$false = $Rd"> {
2701  let Inst{31-27} = 0b11110;
2702  let Inst{25} = 0;
2703  let Inst{24-21} = 0b0011;
2704  let Inst{20} = 0; // The S bit.
2705  let Inst{19-16} = 0b1111; // Rn
2706  let Inst{15} = 0;
2707}
2708
2709class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2710                   string opc, string asm, list<dag> pattern>
2711  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2712  let Inst{31-27} = 0b11101;
2713  let Inst{26-25} = 0b01;
2714  let Inst{24-21} = 0b0010;
2715  let Inst{20} = 0; // The S bit.
2716  let Inst{19-16} = 0b1111; // Rn
2717  let Inst{5-4} = opcod; // Shift type.
2718}
2719def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2720                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2721                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2722                 RegConstraint<"$false = $Rd">;
2723def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2724                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2725                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2726                 RegConstraint<"$false = $Rd">;
2727def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2728                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2729                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2730                 RegConstraint<"$false = $Rd">;
2731def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2732                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2733                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2734                 RegConstraint<"$false = $Rd">;
2735} // isCodeGenOnly = 1
2736} // neverHasSideEffects
2737
2738//===----------------------------------------------------------------------===//
2739// Atomic operations intrinsics
2740//
2741
2742// memory barriers protect the atomic sequences
2743let hasSideEffects = 1 in {
2744def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2745                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2746                  Requires<[IsThumb, HasDB]> {
2747  bits<4> opt;
2748  let Inst{31-4} = 0xf3bf8f5;
2749  let Inst{3-0} = opt;
2750}
2751}
2752
2753def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2754                  "dsb", "\t$opt",
2755                  [/* For disassembly only; pattern left blank */]>,
2756                  Requires<[IsThumb, HasDB]> {
2757  bits<4> opt;
2758  let Inst{31-4} = 0xf3bf8f4;
2759  let Inst{3-0} = opt;
2760}
2761
2762// ISB has only full system option -- for disassembly only
2763def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2764                  [/* For disassembly only; pattern left blank */]>,
2765                  Requires<[IsThumb2, HasV7]> {
2766  let Inst{31-4} = 0xf3bf8f6;
2767  let Inst{3-0} = 0b1111;
2768}
2769
2770class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2771                InstrItinClass itin, string opc, string asm, string cstr,
2772                list<dag> pattern, bits<4> rt2 = 0b1111>
2773  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2774  let Inst{31-27} = 0b11101;
2775  let Inst{26-20} = 0b0001101;
2776  let Inst{11-8} = rt2;
2777  let Inst{7-6} = 0b01;
2778  let Inst{5-4} = opcod;
2779  let Inst{3-0} = 0b1111;
2780
2781  bits<4> addr;
2782  bits<4> Rt;
2783  let Inst{19-16} = addr;
2784  let Inst{15-12} = Rt;
2785}
2786class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2787                InstrItinClass itin, string opc, string asm, string cstr,
2788                list<dag> pattern, bits<4> rt2 = 0b1111>
2789  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2790  let Inst{31-27} = 0b11101;
2791  let Inst{26-20} = 0b0001100;
2792  let Inst{11-8} = rt2;
2793  let Inst{7-6} = 0b01;
2794  let Inst{5-4} = opcod;
2795
2796  bits<4> Rd;
2797  bits<4> addr;
2798  bits<4> Rt;
2799  let Inst{3-0}  = Rd;
2800  let Inst{19-16} = addr;
2801  let Inst{15-12} = Rt;
2802}
2803
2804let mayLoad = 1 in {
2805def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2806                         AddrModeNone, 4, NoItinerary,
2807                         "ldrexb", "\t$Rt, $addr", "", []>;
2808def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2809                         AddrModeNone, 4, NoItinerary,
2810                         "ldrexh", "\t$Rt, $addr", "", []>;
2811def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2812                       AddrModeNone, 4, NoItinerary,
2813                       "ldrex", "\t$Rt, $addr", "", []> {
2814  let Inst{31-27} = 0b11101;
2815  let Inst{26-20} = 0b0000101;
2816  let Inst{11-8} = 0b1111;
2817  let Inst{7-0} = 0b00000000; // imm8 = 0
2818
2819  bits<4> Rt;
2820  bits<4> addr;
2821  let Inst{19-16} = addr;
2822  let Inst{15-12} = Rt;
2823}
2824let hasExtraDefRegAllocReq = 1 in
2825def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2826                         (ins t2addrmode_reg:$addr),
2827                         AddrModeNone, 4, NoItinerary,
2828                         "ldrexd", "\t$Rt, $Rt2, $addr", "",
2829                         [], {?, ?, ?, ?}> {
2830  bits<4> Rt2;
2831  let Inst{11-8} = Rt2;
2832}
2833}
2834
2835let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2836def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2837                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2838                         AddrModeNone, 4, NoItinerary,
2839                         "strexb", "\t$Rd, $Rt, $addr", "", []>;
2840def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2841                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2842                         AddrModeNone, 4, NoItinerary,
2843                         "strexh", "\t$Rd, $Rt, $addr", "", []>;
2844def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2845                  AddrModeNone, 4, NoItinerary,
2846                  "strex", "\t$Rd, $Rt, $addr", "",
2847                  []> {
2848  let Inst{31-27} = 0b11101;
2849  let Inst{26-20} = 0b0000100;
2850  let Inst{7-0} = 0b00000000; // imm8 = 0
2851
2852  bits<4> Rd;
2853  bits<4> addr;
2854  bits<4> Rt;
2855  let Inst{11-8}  = Rd;
2856  let Inst{19-16} = addr;
2857  let Inst{15-12} = Rt;
2858}
2859}
2860
2861let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2862def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2863                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2864                         AddrModeNone, 4, NoItinerary,
2865                         "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2866                         {?, ?, ?, ?}> {
2867  bits<4> Rt2;
2868  let Inst{11-8} = Rt2;
2869}
2870
2871// Clear-Exclusive is for disassembly only.
2872def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2873                   [/* For disassembly only; pattern left blank */]>,
2874            Requires<[IsThumb2, HasV7]>  {
2875  let Inst{31-16} = 0xf3bf;
2876  let Inst{15-14} = 0b10;
2877  let Inst{13} = 0;
2878  let Inst{12} = 0;
2879  let Inst{11-8} = 0b1111;
2880  let Inst{7-4} = 0b0010;
2881  let Inst{3-0} = 0b1111;
2882}
2883
2884//===----------------------------------------------------------------------===//
2885// SJLJ Exception handling intrinsics
2886//   eh_sjlj_setjmp() is an instruction sequence to store the return
2887//   address and save #0 in R0 for the non-longjmp case.
2888//   Since by its nature we may be coming from some other function to get
2889//   here, and we're using the stack frame for the containing function to
2890//   save/restore registers, we can't keep anything live in regs across
2891//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2892//   when we get here from a longjmp(). We force everything out of registers
2893//   except for our own input by listing the relevant registers in Defs. By
2894//   doing so, we also cause the prologue/epilogue code to actively preserve
2895//   all of the callee-saved resgisters, which is exactly what we want.
2896//   $val is a scratch register for our use.
2897let Defs =
2898  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
2899    QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2900  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2901  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2902                               AddrModeNone, 0, NoItinerary, "", "",
2903                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2904                             Requires<[IsThumb2, HasVFP2]>;
2905}
2906
2907let Defs =
2908  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
2909  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2910  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2911                               AddrModeNone, 0, NoItinerary, "", "",
2912                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2913                                  Requires<[IsThumb2, NoVFP]>;
2914}
2915
2916
2917//===----------------------------------------------------------------------===//
2918// Control-Flow Instructions
2919//
2920
2921// FIXME: remove when we have a way to marking a MI with these properties.
2922// FIXME: Should pc be an implicit operand like PICADD, etc?
2923let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2924    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2925def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2926                                                   reglist:$regs, variable_ops),
2927                              4, IIC_iLoad_mBr, [],
2928            (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2929                         RegConstraint<"$Rn = $wb">;
2930
2931let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2932let isPredicable = 1 in
2933def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2934                 "b.w\t$target",
2935                 [(br bb:$target)]> {
2936  let Inst{31-27} = 0b11110;
2937  let Inst{15-14} = 0b10;
2938  let Inst{12} = 1;
2939
2940  bits<20> target;
2941  let Inst{26} = target{19};
2942  let Inst{11} = target{18};
2943  let Inst{13} = target{17};
2944  let Inst{21-16} = target{16-11};
2945  let Inst{10-0} = target{10-0};
2946}
2947
2948let isNotDuplicable = 1, isIndirectBranch = 1 in {
2949def t2BR_JT : t2PseudoInst<(outs),
2950          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2951           0, IIC_Br,
2952          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2953
2954// FIXME: Add a non-pc based case that can be predicated.
2955def t2TBB_JT : t2PseudoInst<(outs),
2956        (ins GPR:$index, i32imm:$jt, i32imm:$id),
2957         0, IIC_Br, []>;
2958
2959def t2TBH_JT : t2PseudoInst<(outs),
2960        (ins GPR:$index, i32imm:$jt, i32imm:$id),
2961         0, IIC_Br, []>;
2962
2963def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2964                    "tbb", "\t[$Rn, $Rm]", []> {
2965  bits<4> Rn;
2966  bits<4> Rm;
2967  let Inst{31-20} = 0b111010001101;
2968  let Inst{19-16} = Rn;
2969  let Inst{15-5} = 0b11110000000;
2970  let Inst{4} = 0; // B form
2971  let Inst{3-0} = Rm;
2972}
2973
2974def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2975                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
2976  bits<4> Rn;
2977  bits<4> Rm;
2978  let Inst{31-20} = 0b111010001101;
2979  let Inst{19-16} = Rn;
2980  let Inst{15-5} = 0b11110000000;
2981  let Inst{4} = 1; // H form
2982  let Inst{3-0} = Rm;
2983}
2984} // isNotDuplicable, isIndirectBranch
2985
2986} // isBranch, isTerminator, isBarrier
2987
2988// FIXME: should be able to write a pattern for ARMBrcond, but can't use
2989// a two-value operand where a dag node expects two operands. :(
2990let isBranch = 1, isTerminator = 1 in
2991def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
2992                "b", ".w\t$target",
2993                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
2994  let Inst{31-27} = 0b11110;
2995  let Inst{15-14} = 0b10;
2996  let Inst{12} = 0;
2997
2998  bits<4> p;
2999  let Inst{25-22} = p;
3000
3001  bits<21> target;
3002  let Inst{26} = target{20};
3003  let Inst{11} = target{19};
3004  let Inst{13} = target{18};
3005  let Inst{21-16} = target{17-12};
3006  let Inst{10-0} = target{11-1};
3007
3008  let DecoderMethod = "DecodeThumb2BCCInstruction";
3009}
3010
3011// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3012// it goes here.
3013let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3014  // Darwin version.
3015  let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3016      Uses = [SP] in
3017  def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3018                   4, IIC_Br, [],
3019                   (t2B uncondbrtarget:$dst)>,
3020                 Requires<[IsThumb2, IsDarwin]>;
3021}
3022
3023// IT block
3024let Defs = [ITSTATE] in
3025def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3026                    AddrModeNone, 2,  IIC_iALUx,
3027                    "it$mask\t$cc", "", []> {
3028  // 16-bit instruction.
3029  let Inst{31-16} = 0x0000;
3030  let Inst{15-8} = 0b10111111;
3031
3032  bits<4> cc;
3033  bits<4> mask;
3034  let Inst{7-4} = cc;
3035  let Inst{3-0} = mask;
3036}
3037
3038// Branch and Exchange Jazelle -- for disassembly only
3039// Rm = Inst{19-16}
3040def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3041              [/* For disassembly only; pattern left blank */]> {
3042  let Inst{31-27} = 0b11110;
3043  let Inst{26} = 0;
3044  let Inst{25-20} = 0b111100;
3045  let Inst{15-14} = 0b10;
3046  let Inst{12} = 0;
3047
3048  bits<4> func;
3049  let Inst{19-16} = func;
3050}
3051
3052// Compare and branch on zero / non-zero
3053let isBranch = 1, isTerminator = 1 in {
3054  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3055                  "cbz\t$Rn, $target", []>,
3056              T1Misc<{0,0,?,1,?,?,?}>,
3057              Requires<[IsThumb2]> {
3058    // A8.6.27
3059    bits<6> target;
3060    bits<3> Rn;
3061    let Inst{9}   = target{5};
3062    let Inst{7-3} = target{4-0};
3063    let Inst{2-0} = Rn;
3064  }
3065
3066  def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
3067                  "cbnz\t$Rn, $target", []>,
3068              T1Misc<{1,0,?,1,?,?,?}>,
3069              Requires<[IsThumb2]> {
3070    // A8.6.27
3071    bits<6> target;
3072    bits<3> Rn;
3073    let Inst{9}   = target{5};
3074    let Inst{7-3} = target{4-0};
3075    let Inst{2-0} = Rn;
3076  }
3077}
3078
3079
3080// Change Processor State is a system instruction -- for disassembly and
3081// parsing only.
3082// FIXME: Since the asm parser has currently no clean way to handle optional
3083// operands, create 3 versions of the same instruction. Once there's a clean
3084// framework to represent optional operands, change this behavior.
3085class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3086            !strconcat("cps", asm_op),
3087            [/* For disassembly only; pattern left blank */]> {
3088  bits<2> imod;
3089  bits<3> iflags;
3090  bits<5> mode;
3091  bit M;
3092
3093  let Inst{31-27} = 0b11110;
3094  let Inst{26}    = 0;
3095  let Inst{25-20} = 0b111010;
3096  let Inst{19-16} = 0b1111;
3097  let Inst{15-14} = 0b10;
3098  let Inst{12}    = 0;
3099  let Inst{10-9}  = imod;
3100  let Inst{8}     = M;
3101  let Inst{7-5}   = iflags;
3102  let Inst{4-0}   = mode;
3103}
3104
3105let M = 1 in
3106  def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3107                      "$imod.w\t$iflags, $mode">;
3108let mode = 0, M = 0 in
3109  def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3110                      "$imod.w\t$iflags">;
3111let imod = 0, iflags = 0, M = 1 in
3112  def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3113
3114// A6.3.4 Branches and miscellaneous control
3115// Table A6-14 Change Processor State, and hint instructions
3116// Helper class for disassembly only.
3117class T2I_hint<bits<8> op7_0, string opc, string asm>
3118  : T2I<(outs), (ins), NoItinerary, opc, asm,
3119        [/* For disassembly only; pattern left blank */]> {
3120  let Inst{31-20} = 0xf3a;
3121  let Inst{19-16} = 0b1111;
3122  let Inst{15-14} = 0b10;
3123  let Inst{12} = 0;
3124  let Inst{10-8} = 0b000;
3125  let Inst{7-0} = op7_0;
3126}
3127
3128def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3129def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3130def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3131def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3132def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3133
3134def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3135  let Inst{31-20} = 0xf3a;
3136  let Inst{15-14} = 0b10;
3137  let Inst{12} = 0;
3138  let Inst{10-8} = 0b000;
3139  let Inst{7-4} = 0b1111;
3140
3141  bits<4> opt;
3142  let Inst{3-0} = opt;
3143}
3144
3145// Secure Monitor Call is a system instruction -- for disassembly only
3146// Option = Inst{19-16}
3147def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3148                [/* For disassembly only; pattern left blank */]> {
3149  let Inst{31-27} = 0b11110;
3150  let Inst{26-20} = 0b1111111;
3151  let Inst{15-12} = 0b1000;
3152
3153  bits<4> opt;
3154  let Inst{19-16} = opt;
3155}
3156
3157class T2SRS<bits<12> op31_20,
3158           dag oops, dag iops, InstrItinClass itin,
3159          string opc, string asm, list<dag> pattern>
3160  : T2I<oops, iops, itin, opc, asm, pattern> {
3161  let Inst{31-20} = op31_20{11-0};
3162
3163  bits<5> mode;
3164  let Inst{4-0} = mode{4-0};
3165}
3166
3167// Store Return State is a system instruction -- for disassembly only
3168def t2SRSDBW : T2SRS<0b111010000010,
3169                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3170                   [/* For disassembly only; pattern left blank */]>;
3171def t2SRSDB  : T2SRS<0b111010000000,
3172                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3173                   [/* For disassembly only; pattern left blank */]>;
3174def t2SRSIAW : T2SRS<0b111010011010,
3175                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3176                   [/* For disassembly only; pattern left blank */]>;
3177def t2SRSIA  : T2SRS<0b111010011000,
3178                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3179                   [/* For disassembly only; pattern left blank */]>;
3180
3181// Return From Exception is a system instruction -- for disassembly only
3182
3183class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3184          string opc, string asm, list<dag> pattern>
3185  : T2I<oops, iops, itin, opc, asm, pattern> {
3186  let Inst{31-20} = op31_20{11-0};
3187
3188  bits<4> Rn;
3189  let Inst{19-16} = Rn;
3190  let Inst{15-0} = 0xc000;
3191}
3192
3193def t2RFEDBW : T2RFE<0b111010000011,
3194                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3195                   [/* For disassembly only; pattern left blank */]>;
3196def t2RFEDB  : T2RFE<0b111010000001,
3197                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3198                   [/* For disassembly only; pattern left blank */]>;
3199def t2RFEIAW : T2RFE<0b111010011011,
3200                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3201                   [/* For disassembly only; pattern left blank */]>;
3202def t2RFEIA  : T2RFE<0b111010011001,
3203                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3204                   [/* For disassembly only; pattern left blank */]>;
3205
3206//===----------------------------------------------------------------------===//
3207// Non-Instruction Patterns
3208//
3209
3210// 32-bit immediate using movw + movt.
3211// This is a single pseudo instruction to make it re-materializable.
3212// FIXME: Remove this when we can do generalized remat.
3213let isReMaterializable = 1, isMoveImm = 1 in
3214def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3215                            [(set rGPR:$dst, (i32 imm:$src))]>,
3216                            Requires<[IsThumb, HasV6T2]>;
3217
3218// Pseudo instruction that combines movw + movt + add pc (if pic).
3219// It also makes it possible to rematerialize the instructions.
3220// FIXME: Remove this when we can do generalized remat and when machine licm
3221// can properly the instructions.
3222let isReMaterializable = 1 in {
3223def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3224                                IIC_iMOVix2addpc,
3225                          [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3226                          Requires<[IsThumb2, UseMovt]>;
3227
3228def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3229                              IIC_iMOVix2,
3230                          [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3231                          Requires<[IsThumb2, UseMovt]>;
3232}
3233
3234// ConstantPool, GlobalAddress, and JumpTable
3235def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3236           Requires<[IsThumb2, DontUseMovt]>;
3237def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3238def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3239           Requires<[IsThumb2, UseMovt]>;
3240
3241def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3242            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3243
3244// Pseudo instruction that combines ldr from constpool and add pc. This should
3245// be expanded into two instructions late to allow if-conversion and
3246// scheduling.
3247let canFoldAsLoad = 1, isReMaterializable = 1 in
3248def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3249                   IIC_iLoadiALU,
3250              [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3251                                           imm:$cp))]>,
3252               Requires<[IsThumb2]>;
3253
3254//===----------------------------------------------------------------------===//
3255// Move between special register and ARM core register -- for disassembly only
3256//
3257
3258class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3259          dag oops, dag iops, InstrItinClass itin,
3260          string opc, string asm, list<dag> pattern>
3261  : T2I<oops, iops, itin, opc, asm, pattern> {
3262  let Inst{31-20} = op31_20{11-0};
3263  let Inst{15-14} = op15_14{1-0};
3264  let Inst{12} = op12{0};
3265}
3266
3267class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3268          dag oops, dag iops, InstrItinClass itin,
3269          string opc, string asm, list<dag> pattern>
3270  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3271  bits<4> Rd;
3272  let Inst{11-8} = Rd;
3273  let Inst{19-16} = 0b1111;
3274}
3275
3276def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3277                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3278                [/* For disassembly only; pattern left blank */]>;
3279def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3280                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3281                   [/* For disassembly only; pattern left blank */]>;
3282
3283// Move from ARM core register to Special Register
3284//
3285// No need to have both system and application versions, the encodings are the
3286// same and the assembly parser has no way to distinguish between them. The mask
3287// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3288// the mask with the fields to be accessed in the special register.
3289def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3290                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3291                         NoItinerary, "msr", "\t$mask, $Rn",
3292                         [/* For disassembly only; pattern left blank */]> {
3293  bits<5> mask;
3294  bits<4> Rn;
3295  let Inst{19-16} = Rn;
3296  let Inst{20}    = mask{4}; // R Bit
3297  let Inst{13}    = 0b0;
3298  let Inst{11-8}  = mask{3-0};
3299}
3300
3301//===----------------------------------------------------------------------===//
3302// Move between coprocessor and ARM core register
3303//
3304
3305class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3306                  list<dag> pattern>
3307  : T2Cop<Op, oops, iops,
3308          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3309          pattern> {
3310  let Inst{27-24} = 0b1110;
3311  let Inst{20} = direction;
3312  let Inst{4} = 1;
3313
3314  bits<4> Rt;
3315  bits<4> cop;
3316  bits<3> opc1;
3317  bits<3> opc2;
3318  bits<4> CRm;
3319  bits<4> CRn;
3320
3321  let Inst{15-12} = Rt;
3322  let Inst{11-8}  = cop;
3323  let Inst{23-21} = opc1;
3324  let Inst{7-5}   = opc2;
3325  let Inst{3-0}   = CRm;
3326  let Inst{19-16} = CRn;
3327}
3328
3329class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3330                   list<dag> pattern = []>
3331  : T2Cop<Op, (outs),
3332          (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3333          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3334  let Inst{27-24} = 0b1100;
3335  let Inst{23-21} = 0b010;
3336  let Inst{20} = direction;
3337
3338  bits<4> Rt;
3339  bits<4> Rt2;
3340  bits<4> cop;
3341  bits<4> opc1;
3342  bits<4> CRm;
3343
3344  let Inst{15-12} = Rt;
3345  let Inst{19-16} = Rt2;
3346  let Inst{11-8}  = cop;
3347  let Inst{7-4}   = opc1;
3348  let Inst{3-0}   = CRm;
3349}
3350
3351/* from ARM core register to coprocessor */
3352def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3353           (outs),
3354           (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3355                c_imm:$CRm, imm0_7:$opc2),
3356           [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3357                         imm:$CRm, imm:$opc2)]>;
3358def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3359             (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3360                          c_imm:$CRm, imm0_7:$opc2),
3361             [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3362                            imm:$CRm, imm:$opc2)]>;
3363
3364/* from coprocessor to ARM core register */
3365def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3366             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3367                                  c_imm:$CRm, imm0_7:$opc2), []>;
3368
3369def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3370             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3371                                  c_imm:$CRm, imm0_7:$opc2), []>;
3372
3373def : T2v6Pat<(int_arm_mrc  imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3374              (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3375
3376def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3377              (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3378
3379
3380/* from ARM core register to coprocessor */
3381def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3382                        [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3383                                       imm:$CRm)]>;
3384def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3385                           [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3386                                           GPR:$Rt2, imm:$CRm)]>;
3387/* from coprocessor to ARM core register */
3388def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3389
3390def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3391
3392//===----------------------------------------------------------------------===//
3393// Other Coprocessor Instructions.
3394//
3395
3396def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3397                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3398                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3399                 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3400                               imm:$CRm, imm:$opc2)]> {
3401  let Inst{27-24} = 0b1110;
3402
3403  bits<4> opc1;
3404  bits<4> CRn;
3405  bits<4> CRd;
3406  bits<4> cop;
3407  bits<3> opc2;
3408  bits<4> CRm;
3409
3410  let Inst{3-0}   = CRm;
3411  let Inst{4}     = 0;
3412  let Inst{7-5}   = opc2;
3413  let Inst{11-8}  = cop;
3414  let Inst{15-12} = CRd;
3415  let Inst{19-16} = CRn;
3416  let Inst{23-20} = opc1;
3417}
3418
3419def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3420                   c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3421                   "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3422                   [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3423                                  imm:$CRm, imm:$opc2)]> {
3424  let Inst{27-24} = 0b1110;
3425
3426  bits<4> opc1;
3427  bits<4> CRn;
3428  bits<4> CRd;
3429  bits<4> cop;
3430  bits<3> opc2;
3431  bits<4> CRm;
3432
3433  let Inst{3-0}   = CRm;
3434  let Inst{4}     = 0;
3435  let Inst{7-5}   = opc2;
3436  let Inst{11-8}  = cop;
3437  let Inst{15-12} = CRd;
3438  let Inst{19-16} = CRn;
3439  let Inst{23-20} = opc1;
3440}
3441
3442
3443
3444//===----------------------------------------------------------------------===//
3445// Non-Instruction Patterns
3446//
3447
3448// SXT/UXT with no rotate
3449let AddedComplexity = 16 in {
3450def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>,
3451           Requires<[IsThumb2]>;
3452def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>,
3453           Requires<[IsThumb2]>;
3454def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>,
3455           Requires<[HasT2ExtractPack, IsThumb2]>;
3456def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)),
3457            (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3458           Requires<[HasT2ExtractPack, IsThumb2]>;
3459def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)),
3460            (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3461           Requires<[HasT2ExtractPack, IsThumb2]>;
3462}
3463
3464def : T2Pat<(sext_inreg rGPR:$Src, i8),  (t2SXTB rGPR:$Src, 0)>,
3465           Requires<[IsThumb2]>;
3466def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>,
3467           Requires<[IsThumb2]>;
3468def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)),
3469            (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>,
3470           Requires<[HasT2ExtractPack, IsThumb2]>;
3471def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
3472            (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>,
3473           Requires<[HasT2ExtractPack, IsThumb2]>;
3474