ARMInstrThumb2.td revision 7c4f7dd43a84b233f94a1fe44faff42ac46b906d 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// Shifted operands. No register controlled shifts for Thumb2.
15// Note: We do not support rrx shifted operands yet.
16def t2_so_reg : Operand<i32>,    // reg imm
17                ComplexPattern<i32, 2, "SelectShifterOperand",
18                               [shl,srl,sra,rotr]> {
19  let PrintMethod = "printSOOperand";
20  let MIOperandInfo = (ops GPR, i32imm);
21}
22
23def LO16 : SDNodeXForm<imm, [{
24  // Transformation function: shift the immediate value down into the low bits.
25  return getI32Imm((unsigned short)N->getZExtValue());
26}]>;
27
28def HI16 : SDNodeXForm<imm, [{
29  // Transformation function: shift the immediate value down into the low bits.
30  return getI32Imm((unsigned)N->getZExtValue() >> 16);
31}]>;
32
33def imm16high : PatLeaf<(i32 imm), [{
34  // Returns true if all bits out of the [31..16] range are 0.
35  return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue());
36}], HI16>;
37
38def imm16high0xffff : PatLeaf<(i32 imm), [{
39  // Returns true if lo 16 bits are set and this is a 32-bit value. 
40  return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL);
41}], HI16>;
42
43def imm0_4095 : PatLeaf<(i32 imm), [{ 
44  return (uint32_t)N->getZExtValue() < 4096; 
45}]>; 
46
47def imm0_4095_neg : PatLeaf<(i32 imm), [{ 
48 return (uint32_t)-N->getZExtValue() < 4096; 
49}], imm_neg_XFORM>; 
50
51def imm0_65535 : PatLeaf<(i32 imm), [{ 
52  return N->getZExtValue() < 65536; 
53}]>; 
54
55// A6.3.2 Modified immediate constants in Thumb instructions (#<const>)
56// FIXME: Move it the the addrmode matcher code.
57def t2_so_imm : PatLeaf<(i32 imm), [{
58  uint64_t v = N->getZExtValue();
59  if (v == 0 || v > 0xffffffffUL) return false;
60  // variant1 - 0b0000x - 8-bit which could be zero (not supported for now)
61
62  // variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room
63  unsigned hi16 = (unsigned)(v >> 16);
64  unsigned lo16 = (unsigned)(v & 0xffffUL);
65  bool valid = (hi16 == lo16) && (
66    (v & 0x00ff00ffUL) == 0 ||        // type 0001x
67    (v & 0xff00ff00UL) == 0 ||        // type 0010x
68    ((lo16 >> 8) == (lo16 & 0xff)));  // type 0011x
69  if (valid) return true;
70
71  // variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room
72  unsigned shift = CountLeadingZeros_32(v);
73  uint64_t mask = (0xff000000ULL >> shift);
74  // If valid, it is type 01000 + shift
75  return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0);
76}]>;
77
78
79//===----------------------------------------------------------------------===//
80//  Thumb-2 to cover the functionality of the ARM instruction set.
81//
82
83/// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a
84//  binary operation that produces a value.
85multiclass T2I_bin_irs<string opc, PatFrag opnode> {
86   // shifted imm
87   def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
88                       !strconcat(opc, " $dst, $lhs, $rhs"),
89                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
90                      Requires<[HasThumb2]>;
91   // register
92   def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
93                       !strconcat(opc, " $dst, $lhs, $rhs"),
94                       [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 
95                      Requires<[HasThumb2]>;
96   // shifted register
97   def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
98                       !strconcat(opc, " $dst, $lhs, $rhs"),
99                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 
100                      Requires<[HasThumb2]>;
101}
102
103/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
104/// instruction modifies the CPSR register.
105let Defs = [CPSR] in {
106multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
107   // shifted imm
108   def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
109                       !strconcat(opc, "s $dst, $lhs, $rhs"),
110                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
111                      Requires<[HasThumb2]>;
112
113   // register
114   def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
115                       !strconcat(opc, "s $dst, $lhs, $rhs"),
116                       [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 
117                      Requires<[HasThumb2]>;
118
119   // shifted register
120   def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
121                       !strconcat(opc, "s $dst, $lhs, $rhs"),
122                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 
123                      Requires<[HasThumb2]>;
124}
125}
126
127/// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the
128/// instruction can optionally set the CPSR register.
129let Uses = [CPSR] in {
130multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
131   // shifted imm
132   def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s),
133                       !strconcat(opc, "${s} $dst, $lhs, $rhs"),
134                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
135                      Requires<[HasThumb2]>;
136
137   // register
138   def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
139                       !strconcat(opc, "${s} $dst, $lhs, $rhs"),
140                       [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 
141                      Requires<[HasThumb2]>;
142
143   // shifted register
144   def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
145                       !strconcat(opc, "${s} $dst, $lhs, $rhs"),
146                       [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 
147                      Requires<[HasThumb2]>;
148}
149}
150
151//===----------------------------------------------------------------------===//
152//  Arithmetic Instructions.
153//
154
155//===----------------------------------------------------------------------===//
156//  Move Instructions.
157//
158def tMOVi16  : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
159                          "movw $dst, $src",
160                          [(set GPR:$dst, imm0_65535:$src)]>, 
161                         Requires<[HasThumb2]>;
162
163let isTwoAddress = 1 in
164def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
165                          "movt $dst, $imm",
166                          [(set GPR:$dst, (or (and GPR:$src, 0xffff), 
167                                              imm16high:$imm))]>,
168                         Requires<[HasThumb2]>;
169
170def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2),
171          (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
172         Requires<[HasThumb2]>;
173
174def : Pat<(i32 imm:$imm),
175          (tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
176         Requires<[HasThumb2]>;
177
178//===----------------------------------------------------------------------===//
179//  Arithmetic Instructions.
180//
181defm t2ADD  : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
182defm t2SUB  : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
183
184def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
185                          "add $dst, $lhs, $rhs", 
186                          [(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>,
187                         Requires<[HasThumb2]>; 
188def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 
189                          "sub $dst, $lhs, $rhs",
190                          [(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>,
191                         Requires<[HasThumb2]>;
192
193defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
194defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
195
196defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
197defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
198
199
200def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 
201                      "mls $dst, $a, $b, $c", 
202                      [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
203                     Requires<[HasThumb2]>;
204
205def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2),
206                        "orn $dst, $src1, $src2",
207                        [(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>,
208                       Requires<[HasThumb2]>;
209