ARMInstrThumb2.td revision bd91ea53f823fe71c0b67b9a4552984a8b361820
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printMandatoryPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant 53// bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72// Break t2_so_imm's up into two pieces. This handles immediates with up to 16 73// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12] 74// to get the first/second pieces. 75def t2_so_imm2part : Operand<i32>, 76 PatLeaf<(imm), [{ 77 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue()); 78 }]> { 79} 80 81def t2_so_imm2part_1 : SDNodeXForm<imm, [{ 82 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue()); 83 return CurDAG->getTargetConstant(V, MVT::i32); 84}]>; 85 86def t2_so_imm2part_2 : SDNodeXForm<imm, [{ 87 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue()); 88 return CurDAG->getTargetConstant(V, MVT::i32); 89}]>; 90 91def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ 92 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue()); 93 }]> { 94} 95 96def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{ 97 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue()); 98 return CurDAG->getTargetConstant(V, MVT::i32); 99}]>; 100 101def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{ 102 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue()); 103 return CurDAG->getTargetConstant(V, MVT::i32); 104}]>; 105 106/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 107def imm1_31 : PatLeaf<(i32 imm), [{ 108 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 109}]>; 110 111/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 112def imm0_4095 : Operand<i32>, 113 PatLeaf<(i32 imm), [{ 114 return (uint32_t)N->getZExtValue() < 4096; 115}]>; 116 117def imm0_4095_neg : PatLeaf<(i32 imm), [{ 118 return (uint32_t)(-N->getZExtValue()) < 4096; 119}], imm_neg_XFORM>; 120 121def imm0_255_neg : PatLeaf<(i32 imm), [{ 122 return (uint32_t)(-N->getZExtValue()) < 255; 123}], imm_neg_XFORM>; 124 125// Define Thumb2 specific addressing modes. 126 127// t2addrmode_imm12 := reg + imm12 128def t2addrmode_imm12 : Operand<i32>, 129 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 130 let PrintMethod = "printT2AddrModeImm12Operand"; 131 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 132} 133 134// t2addrmode_imm8 := reg +/- imm8 135def t2addrmode_imm8 : Operand<i32>, 136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 137 let PrintMethod = "printT2AddrModeImm8Operand"; 138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 139} 140 141def t2am_imm8_offset : Operand<i32>, 142 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 143 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 144} 145 146// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 147def t2addrmode_imm8s4 : Operand<i32>, 148 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 149 let PrintMethod = "printT2AddrModeImm8s4Operand"; 150 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 151} 152 153def t2am_imm8s4_offset : Operand<i32> { 154 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 155} 156 157// t2addrmode_so_reg := reg + (reg << imm2) 158def t2addrmode_so_reg : Operand<i32>, 159 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 160 let PrintMethod = "printT2AddrModeSoRegOperand"; 161 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 162} 163 164 165//===----------------------------------------------------------------------===// 166// Multiclass helpers... 167// 168 169/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 170/// unary operation that produces a value. These are predicable and can be 171/// changed to modify CPSR. 172multiclass T2I_un_irs<bits<4> opcod, string opc, PatFrag opnode, 173 bit Cheap = 0, bit ReMat = 0> { 174 // shifted imm 175 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 176 opc, "\t$dst, $src", 177 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 178 let isAsCheapAsAMove = Cheap; 179 let isReMaterializable = ReMat; 180 let Inst{31-27} = 0b11110; 181 let Inst{25} = 0; 182 let Inst{24-21} = opcod; 183 let Inst{20} = ?; // The S bit. 184 let Inst{19-16} = 0b1111; // Rn 185 let Inst{15} = 0; 186 } 187 // register 188 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 189 opc, ".w\t$dst, $src", 190 [(set GPR:$dst, (opnode GPR:$src))]> { 191 let Inst{31-27} = 0b11101; 192 let Inst{26-25} = 0b01; 193 let Inst{24-21} = opcod; 194 let Inst{20} = ?; // The S bit. 195 let Inst{19-16} = 0b1111; // Rn 196 let Inst{14-12} = 0b000; // imm3 197 let Inst{7-6} = 0b00; // imm2 198 let Inst{5-4} = 0b00; // type 199 } 200 // shifted register 201 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iMOVsi, 202 opc, ".w\t$dst, $src", 203 [(set GPR:$dst, (opnode t2_so_reg:$src))]> { 204 let Inst{31-27} = 0b11101; 205 let Inst{26-25} = 0b01; 206 let Inst{24-21} = opcod; 207 let Inst{20} = ?; // The S bit. 208 let Inst{19-16} = 0b1111; // Rn 209 } 210} 211 212/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 213// binary operation that produces a value. These are predicable and can be 214/// changed to modify CPSR. 215multiclass T2I_bin_irs<bits<4> opcod, string opc, PatFrag opnode, 216 bit Commutable = 0, string wide =""> { 217 // shifted imm 218 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 219 opc, "\t$dst, $lhs, $rhs", 220 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 221 let Inst{31-27} = 0b11110; 222 let Inst{25} = 0; 223 let Inst{24-21} = opcod; 224 let Inst{20} = ?; // The S bit. 225 let Inst{15} = 0; 226 } 227 // register 228 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 229 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 230 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 231 let isCommutable = Commutable; 232 let Inst{31-27} = 0b11101; 233 let Inst{26-25} = 0b01; 234 let Inst{24-21} = opcod; 235 let Inst{20} = ?; // The S bit. 236 let Inst{14-12} = 0b000; // imm3 237 let Inst{7-6} = 0b00; // imm2 238 let Inst{5-4} = 0b00; // type 239 } 240 // shifted register 241 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 242 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 243 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 244 let Inst{31-27} = 0b11101; 245 let Inst{26-25} = 0b01; 246 let Inst{24-21} = opcod; 247 let Inst{20} = ?; // The S bit. 248 } 249} 250 251/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 252// the ".w" prefix to indicate that they are wide. 253multiclass T2I_bin_w_irs<bits<4> opcod, string opc, PatFrag opnode, 254 bit Commutable = 0> : 255 T2I_bin_irs<opcod, opc, opnode, Commutable, ".w">; 256 257/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 258/// reversed. It doesn't define the 'rr' form since it's handled by its 259/// T2I_bin_irs counterpart. 260multiclass T2I_rbin_is<bits<4> opcod, string opc, PatFrag opnode> { 261 // shifted imm 262 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 263 opc, ".w\t$dst, $rhs, $lhs", 264 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> { 265 let Inst{31-27} = 0b11110; 266 let Inst{25} = 0; 267 let Inst{24-21} = opcod; 268 let Inst{20} = 0; // The S bit. 269 let Inst{15} = 0; 270 } 271 // shifted register 272 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 273 opc, "\t$dst, $rhs, $lhs", 274 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> { 275 let Inst{31-27} = 0b11101; 276 let Inst{26-25} = 0b01; 277 let Inst{24-21} = opcod; 278 let Inst{20} = 0; // The S bit. 279 } 280} 281 282/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 283/// instruction modifies the CPSR register. 284let Defs = [CPSR] in { 285multiclass T2I_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode, 286 bit Commutable = 0> { 287 // shifted imm 288 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 289 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 290 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 291 let Inst{31-27} = 0b11110; 292 let Inst{25} = 0; 293 let Inst{24-21} = opcod; 294 let Inst{20} = 1; // The S bit. 295 let Inst{15} = 0; 296 } 297 // register 298 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 299 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 300 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 301 let isCommutable = Commutable; 302 let Inst{31-27} = 0b11101; 303 let Inst{26-25} = 0b01; 304 let Inst{24-21} = opcod; 305 let Inst{20} = 1; // The S bit. 306 let Inst{14-12} = 0b000; // imm3 307 let Inst{7-6} = 0b00; // imm2 308 let Inst{5-4} = 0b00; // type 309 } 310 // shifted register 311 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 312 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 313 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 314 let Inst{31-27} = 0b11101; 315 let Inst{26-25} = 0b01; 316 let Inst{24-21} = opcod; 317 let Inst{20} = 1; // The S bit. 318 } 319} 320} 321 322/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 323/// patterns for a binary operation that produces a value. 324multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 325 bit Commutable = 0> { 326 // shifted imm 327 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 328 opc, ".w\t$dst, $lhs, $rhs", 329 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 330 let Inst{31-27} = 0b11110; 331 let Inst{25} = 0; 332 let Inst{24} = 1; 333 let Inst{23-21} = op23_21; 334 let Inst{20} = 0; // The S bit. 335 let Inst{15} = 0; 336 } 337 // 12-bit imm 338 def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, 339 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", 340 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { 341 let Inst{31-27} = 0b11110; 342 let Inst{25} = 1; 343 let Inst{24} = 0; 344 let Inst{23-21} = op23_21; 345 let Inst{20} = 0; // The S bit. 346 let Inst{15} = 0; 347 } 348 // register 349 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 350 opc, ".w\t$dst, $lhs, $rhs", 351 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 352 let isCommutable = Commutable; 353 let Inst{31-27} = 0b11101; 354 let Inst{26-25} = 0b01; 355 let Inst{24} = 1; 356 let Inst{23-21} = op23_21; 357 let Inst{20} = 0; // The S bit. 358 let Inst{14-12} = 0b000; // imm3 359 let Inst{7-6} = 0b00; // imm2 360 let Inst{5-4} = 0b00; // type 361 } 362 // shifted register 363 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 364 opc, ".w\t$dst, $lhs, $rhs", 365 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 366 let Inst{31-27} = 0b11101; 367 let Inst{26-25} = 0b01; 368 let Inst{24} = 1; 369 let Inst{23-21} = op23_21; 370 let Inst{20} = 0; // The S bit. 371 } 372} 373 374/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 375/// for a binary operation that produces a value and use the carry 376/// bit. It's not predicable. 377let Uses = [CPSR] in { 378multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 379 bit Commutable = 0> { 380 // shifted imm 381 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 382 opc, "\t$dst, $lhs, $rhs", 383 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 384 Requires<[IsThumb2]> { 385 let Inst{31-27} = 0b11110; 386 let Inst{25} = 0; 387 let Inst{24-21} = opcod; 388 let Inst{20} = 0; // The S bit. 389 let Inst{15} = 0; 390 } 391 // register 392 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 393 opc, ".w\t$dst, $lhs, $rhs", 394 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 395 Requires<[IsThumb2]> { 396 let isCommutable = Commutable; 397 let Inst{31-27} = 0b11101; 398 let Inst{26-25} = 0b01; 399 let Inst{24-21} = opcod; 400 let Inst{20} = 0; // The S bit. 401 let Inst{14-12} = 0b000; // imm3 402 let Inst{7-6} = 0b00; // imm2 403 let Inst{5-4} = 0b00; // type 404 } 405 // shifted register 406 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 407 opc, ".w\t$dst, $lhs, $rhs", 408 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 409 Requires<[IsThumb2]> { 410 let Inst{31-27} = 0b11101; 411 let Inst{26-25} = 0b01; 412 let Inst{24-21} = opcod; 413 let Inst{20} = 0; // The S bit. 414 } 415} 416 417// Carry setting variants 418let Defs = [CPSR] in { 419multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, 420 bit Commutable = 0> { 421 // shifted imm 422 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 423 opc, "\t$dst, $lhs, $rhs", 424 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 425 Requires<[IsThumb2]> { 426 let Inst{31-27} = 0b11110; 427 let Inst{25} = 0; 428 let Inst{24-21} = opcod; 429 let Inst{20} = 1; // The S bit. 430 let Inst{15} = 0; 431 } 432 // register 433 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 434 opc, ".w\t$dst, $lhs, $rhs", 435 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 436 Requires<[IsThumb2]> { 437 let isCommutable = Commutable; 438 let Inst{31-27} = 0b11101; 439 let Inst{26-25} = 0b01; 440 let Inst{24-21} = opcod; 441 let Inst{20} = 1; // The S bit. 442 let Inst{14-12} = 0b000; // imm3 443 let Inst{7-6} = 0b00; // imm2 444 let Inst{5-4} = 0b00; // type 445 } 446 // shifted register 447 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 448 opc, ".w\t$dst, $lhs, $rhs", 449 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 450 Requires<[IsThumb2]> { 451 let Inst{31-27} = 0b11101; 452 let Inst{26-25} = 0b01; 453 let Inst{24-21} = opcod; 454 let Inst{20} = 1; // The S bit. 455 } 456} 457} 458} 459 460/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 461let Defs = [CPSR] in { 462multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { 463 // shifted imm 464 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 465 IIC_iALUi, 466 !strconcat(opc, "${s}.w\t$dst, $rhs, $lhs"), 467 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]> { 468 let Inst{31-27} = 0b11110; 469 let Inst{25} = 0; 470 let Inst{24-21} = opcod; 471 let Inst{20} = 1; // The S bit. 472 let Inst{15} = 0; 473 } 474 // shifted register 475 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 476 IIC_iALUsi, 477 !strconcat(opc, "${s}\t$dst, $rhs, $lhs"), 478 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]> { 479 let Inst{31-27} = 0b11101; 480 let Inst{26-25} = 0b01; 481 let Inst{24-21} = opcod; 482 let Inst{20} = 1; // The S bit. 483 } 484} 485} 486 487/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 488// rotate operation that produces a value. 489multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> { 490 // 5-bit imm 491 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 492 opc, ".w\t$dst, $lhs, $rhs", 493 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]> { 494 let Inst{31-27} = 0b11101; 495 let Inst{26-21} = 0b010010; 496 let Inst{19-16} = 0b1111; // Rn 497 let Inst{5-4} = opcod; 498 } 499 // register 500 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iMOVsr, 501 opc, ".w\t$dst, $lhs, $rhs", 502 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 503 let Inst{31-27} = 0b11111; 504 let Inst{26-23} = 0b0100; 505 let Inst{22-21} = opcod; 506 let Inst{15-12} = 0b1111; 507 let Inst{7-4} = 0b0000; 508 } 509} 510 511/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 512/// patterns. Similar to T2I_bin_irs except the instruction does not produce 513/// a explicit result, only implicitly set CPSR. 514let Defs = [CPSR] in { 515multiclass T2I_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> { 516 // shifted imm 517 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iCMPi, 518 opc, ".w\t$lhs, $rhs", 519 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> { 520 let Inst{31-27} = 0b11110; 521 let Inst{25} = 0; 522 let Inst{24-21} = opcod; 523 let Inst{20} = 1; // The S bit. 524 let Inst{15} = 0; 525 let Inst{11-8} = 0b1111; // Rd 526 } 527 // register 528 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 529 opc, ".w\t$lhs, $rhs", 530 [(opnode GPR:$lhs, GPR:$rhs)]> { 531 let Inst{31-27} = 0b11101; 532 let Inst{26-25} = 0b01; 533 let Inst{24-21} = opcod; 534 let Inst{20} = 1; // The S bit. 535 let Inst{14-12} = 0b000; // imm3 536 let Inst{11-8} = 0b1111; // Rd 537 let Inst{7-6} = 0b00; // imm2 538 let Inst{5-4} = 0b00; // type 539 } 540 // shifted register 541 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iCMPsi, 542 opc, ".w\t$lhs, $rhs", 543 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> { 544 let Inst{31-27} = 0b11101; 545 let Inst{26-25} = 0b01; 546 let Inst{24-21} = opcod; 547 let Inst{20} = 1; // The S bit. 548 let Inst{11-8} = 0b1111; // Rd 549 } 550} 551} 552 553/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 554multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> { 555 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi, 556 opc, ".w\t$dst, $addr", 557 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> { 558 let Inst{31-27} = 0b11111; 559 let Inst{26-25} = 0b00; 560 let Inst{24} = signed; 561 let Inst{23} = 1; 562 let Inst{22-21} = opcod; 563 let Inst{20} = 1; // load 564 } 565 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, 566 opc, "\t$dst, $addr", 567 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> { 568 let Inst{31-27} = 0b11111; 569 let Inst{26-25} = 0b00; 570 let Inst{24} = signed; 571 let Inst{23} = 0; 572 let Inst{22-21} = opcod; 573 let Inst{20} = 1; // load 574 let Inst{11} = 1; 575 // Offset: index==TRUE, wback==FALSE 576 let Inst{10} = 1; // The P bit. 577 let Inst{8} = 0; // The W bit. 578 } 579 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr, 580 opc, ".w\t$dst, $addr", 581 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> { 582 let Inst{31-27} = 0b11111; 583 let Inst{26-25} = 0b00; 584 let Inst{24} = signed; 585 let Inst{23} = 0; 586 let Inst{22-21} = opcod; 587 let Inst{20} = 1; // load 588 let Inst{11-6} = 0b000000; 589 } 590 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 591 opc, ".w\t$dst, $addr", 592 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> { 593 let isReMaterializable = 1; 594 let Inst{31-27} = 0b11111; 595 let Inst{26-25} = 0b00; 596 let Inst{24} = signed; 597 let Inst{23} = ?; // add = (U == '1') 598 let Inst{22-21} = opcod; 599 let Inst{20} = 1; // load 600 let Inst{19-16} = 0b1111; // Rn 601 } 602} 603 604/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 605multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> { 606 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei, 607 opc, ".w\t$src, $addr", 608 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> { 609 let Inst{31-27} = 0b11111; 610 let Inst{26-23} = 0b0001; 611 let Inst{22-21} = opcod; 612 let Inst{20} = 0; // !load 613 } 614 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei, 615 opc, "\t$src, $addr", 616 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> { 617 let Inst{31-27} = 0b11111; 618 let Inst{26-23} = 0b0000; 619 let Inst{22-21} = opcod; 620 let Inst{20} = 0; // !load 621 let Inst{11} = 1; 622 // Offset: index==TRUE, wback==FALSE 623 let Inst{10} = 1; // The P bit. 624 let Inst{8} = 0; // The W bit. 625 } 626 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer, 627 opc, ".w\t$src, $addr", 628 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> { 629 let Inst{31-27} = 0b11111; 630 let Inst{26-23} = 0b0000; 631 let Inst{22-21} = opcod; 632 let Inst{20} = 0; // !load 633 let Inst{11-6} = 0b000000; 634 } 635} 636 637/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 638/// register and one whose operand is a register rotated by 8/16/24. 639multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> { 640 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 641 opc, ".w\t$dst, $src", 642 [(set GPR:$dst, (opnode GPR:$src))]>, 643 Requires<[HasT2ExtractPack]> { 644 let Inst{31-27} = 0b11111; 645 let Inst{26-23} = 0b0100; 646 let Inst{22-20} = opcod; 647 let Inst{19-16} = 0b1111; // Rn 648 let Inst{15-12} = 0b1111; 649 let Inst{7} = 1; 650 let Inst{5-4} = 0b00; // rotate 651 } 652 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 653 opc, ".w\t$dst, $src, ror $rot", 654 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, 655 Requires<[HasT2ExtractPack]> { 656 let Inst{31-27} = 0b11111; 657 let Inst{26-23} = 0b0100; 658 let Inst{22-20} = opcod; 659 let Inst{19-16} = 0b1111; // Rn 660 let Inst{15-12} = 0b1111; 661 let Inst{7} = 1; 662 let Inst{5-4} = {?,?}; // rotate 663 } 664} 665 666// SXTB16 and UXTB16 do not need the .w qualifier. 667multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> { 668 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 669 opc, "\t$dst, $src", 670 [(set GPR:$dst, (opnode GPR:$src))]>, 671 Requires<[HasT2ExtractPack]> { 672 let Inst{31-27} = 0b11111; 673 let Inst{26-23} = 0b0100; 674 let Inst{22-20} = opcod; 675 let Inst{19-16} = 0b1111; // Rn 676 let Inst{15-12} = 0b1111; 677 let Inst{7} = 1; 678 let Inst{5-4} = 0b00; // rotate 679 } 680 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 681 opc, "\t$dst, $src, ror $rot", 682 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, 683 Requires<[HasT2ExtractPack]> { 684 let Inst{31-27} = 0b11111; 685 let Inst{26-23} = 0b0100; 686 let Inst{22-20} = opcod; 687 let Inst{19-16} = 0b1111; // Rn 688 let Inst{15-12} = 0b1111; 689 let Inst{7} = 1; 690 let Inst{5-4} = {?,?}; // rotate 691 } 692} 693 694// DO variant - disassembly only, no pattern 695 696multiclass T2I_unary_rrot_DO<bits<3> opcod, string opc> { 697 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 698 opc, "\t$dst, $src", []> { 699 let Inst{31-27} = 0b11111; 700 let Inst{26-23} = 0b0100; 701 let Inst{22-20} = opcod; 702 let Inst{19-16} = 0b1111; // Rn 703 let Inst{15-12} = 0b1111; 704 let Inst{7} = 1; 705 let Inst{5-4} = 0b00; // rotate 706 } 707 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, 708 opc, "\t$dst, $src, ror $rot", []> { 709 let Inst{31-27} = 0b11111; 710 let Inst{26-23} = 0b0100; 711 let Inst{22-20} = opcod; 712 let Inst{19-16} = 0b1111; // Rn 713 let Inst{15-12} = 0b1111; 714 let Inst{7} = 1; 715 let Inst{5-4} = {?,?}; // rotate 716 } 717} 718 719/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 720/// register and one whose operand is a register rotated by 8/16/24. 721multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> { 722 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 723 opc, "\t$dst, $LHS, $RHS", 724 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, 725 Requires<[HasT2ExtractPack]> { 726 let Inst{31-27} = 0b11111; 727 let Inst{26-23} = 0b0100; 728 let Inst{22-20} = opcod; 729 let Inst{15-12} = 0b1111; 730 let Inst{7} = 1; 731 let Inst{5-4} = 0b00; // rotate 732 } 733 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 734 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", 735 [(set GPR:$dst, (opnode GPR:$LHS, 736 (rotr GPR:$RHS, rot_imm:$rot)))]>, 737 Requires<[HasT2ExtractPack]> { 738 let Inst{31-27} = 0b11111; 739 let Inst{26-23} = 0b0100; 740 let Inst{22-20} = opcod; 741 let Inst{15-12} = 0b1111; 742 let Inst{7} = 1; 743 let Inst{5-4} = {?,?}; // rotate 744 } 745} 746 747// DO variant - disassembly only, no pattern 748 749multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> { 750 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, 751 opc, "\t$dst, $LHS, $RHS", []> { 752 let Inst{31-27} = 0b11111; 753 let Inst{26-23} = 0b0100; 754 let Inst{22-20} = opcod; 755 let Inst{15-12} = 0b1111; 756 let Inst{7} = 1; 757 let Inst{5-4} = 0b00; // rotate 758 } 759 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 760 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> { 761 let Inst{31-27} = 0b11111; 762 let Inst{26-23} = 0b0100; 763 let Inst{22-20} = opcod; 764 let Inst{15-12} = 0b1111; 765 let Inst{7} = 1; 766 let Inst{5-4} = {?,?}; // rotate 767 } 768} 769 770//===----------------------------------------------------------------------===// 771// Instructions 772//===----------------------------------------------------------------------===// 773 774//===----------------------------------------------------------------------===// 775// Miscellaneous Instructions. 776// 777 778// LEApcrel - Load a pc-relative address into a register without offending the 779// assembler. 780def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 781 "adr$p.w\t$dst, #$label", []> { 782 let Inst{31-27} = 0b11110; 783 let Inst{25-24} = 0b10; 784 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 785 let Inst{22} = 0; 786 let Inst{20} = 0; 787 let Inst{19-16} = 0b1111; // Rn 788 let Inst{15} = 0; 789} 790def t2LEApcrelJT : T2XI<(outs GPR:$dst), 791 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, 792 "adr$p.w\t$dst, #${label}_${id}", []> { 793 let Inst{31-27} = 0b11110; 794 let Inst{25-24} = 0b10; 795 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 796 let Inst{22} = 0; 797 let Inst{20} = 0; 798 let Inst{19-16} = 0b1111; // Rn 799 let Inst{15} = 0; 800} 801 802// ADD r, sp, {so_imm|i12} 803def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 804 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> { 805 let Inst{31-27} = 0b11110; 806 let Inst{25} = 0; 807 let Inst{24-21} = 0b1000; 808 let Inst{20} = ?; // The S bit. 809 let Inst{19-16} = 0b1101; // Rn = sp 810 let Inst{15} = 0; 811} 812def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 813 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> { 814 let Inst{31-27} = 0b11110; 815 let Inst{25} = 1; 816 let Inst{24-21} = 0b0000; 817 let Inst{20} = 0; // The S bit. 818 let Inst{19-16} = 0b1101; // Rn = sp 819 let Inst{15} = 0; 820} 821 822// ADD r, sp, so_reg 823def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 824 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> { 825 let Inst{31-27} = 0b11101; 826 let Inst{26-25} = 0b01; 827 let Inst{24-21} = 0b1000; 828 let Inst{20} = ?; // The S bit. 829 let Inst{19-16} = 0b1101; // Rn = sp 830 let Inst{15} = 0; 831} 832 833// SUB r, sp, {so_imm|i12} 834def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 835 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> { 836 let Inst{31-27} = 0b11110; 837 let Inst{25} = 0; 838 let Inst{24-21} = 0b1101; 839 let Inst{20} = ?; // The S bit. 840 let Inst{19-16} = 0b1101; // Rn = sp 841 let Inst{15} = 0; 842} 843def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 844 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> { 845 let Inst{31-27} = 0b11110; 846 let Inst{25} = 1; 847 let Inst{24-21} = 0b0101; 848 let Inst{20} = 0; // The S bit. 849 let Inst{19-16} = 0b1101; // Rn = sp 850 let Inst{15} = 0; 851} 852 853// SUB r, sp, so_reg 854def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 855 IIC_iALUsi, 856 "sub", "\t$dst, $sp, $rhs", []> { 857 let Inst{31-27} = 0b11101; 858 let Inst{26-25} = 0b01; 859 let Inst{24-21} = 0b1101; 860 let Inst{20} = ?; // The S bit. 861 let Inst{19-16} = 0b1101; // Rn = sp 862 let Inst{15} = 0; 863} 864 865// Signed and unsigned division on v7-M 866def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, 867 "sdiv", "\t$dst, $a, $b", 868 [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>, 869 Requires<[HasDivide]> { 870 let Inst{31-27} = 0b11111; 871 let Inst{26-21} = 0b011100; 872 let Inst{20} = 0b1; 873 let Inst{15-12} = 0b1111; 874 let Inst{7-4} = 0b1111; 875} 876 877def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, 878 "udiv", "\t$dst, $a, $b", 879 [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>, 880 Requires<[HasDivide]> { 881 let Inst{31-27} = 0b11111; 882 let Inst{26-21} = 0b011101; 883 let Inst{20} = 0b1; 884 let Inst{15-12} = 0b1111; 885 let Inst{7-4} = 0b1111; 886} 887 888// Pseudo instruction that will expand into a t2SUBrSPi + a copy. 889let usesCustomInserter = 1 in { // Expanded after instruction selection. 890def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 891 NoItinerary, "${:comment} sub.w\t$dst, $sp, $imm", []>; 892def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 893 NoItinerary, "${:comment} subw\t$dst, $sp, $imm", []>; 894def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 895 NoItinerary, "${:comment} sub\t$dst, $sp, $rhs", []>; 896} // usesCustomInserter 897 898 899//===----------------------------------------------------------------------===// 900// Load / store Instructions. 901// 902 903// Load 904let canFoldAsLoad = 1, isReMaterializable = 1 in 905defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>; 906 907// Loads with zero extension 908defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 909defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 910 911// Loads with sign extension 912defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 913defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 914 915let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 916// Load doubleword 917def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2), 918 (ins t2addrmode_imm8s4:$addr), 919 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>; 920def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs GPR:$dst1, GPR:$dst2), 921 (ins i32imm:$addr), IIC_iLoadi, 922 "ldrd", "\t$dst1, $addr", []> { 923 let Inst{19-16} = 0b1111; // Rn 924} 925} 926 927// zextload i1 -> zextload i8 928def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 929 (t2LDRBi12 t2addrmode_imm12:$addr)>; 930def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 931 (t2LDRBi8 t2addrmode_imm8:$addr)>; 932def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 933 (t2LDRBs t2addrmode_so_reg:$addr)>; 934def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 935 (t2LDRBpci tconstpool:$addr)>; 936 937// extload -> zextload 938// FIXME: Reduce the number of patterns by legalizing extload to zextload 939// earlier? 940def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 941 (t2LDRBi12 t2addrmode_imm12:$addr)>; 942def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 943 (t2LDRBi8 t2addrmode_imm8:$addr)>; 944def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 945 (t2LDRBs t2addrmode_so_reg:$addr)>; 946def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 947 (t2LDRBpci tconstpool:$addr)>; 948 949def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 950 (t2LDRBi12 t2addrmode_imm12:$addr)>; 951def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 952 (t2LDRBi8 t2addrmode_imm8:$addr)>; 953def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 954 (t2LDRBs t2addrmode_so_reg:$addr)>; 955def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 956 (t2LDRBpci tconstpool:$addr)>; 957 958def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 959 (t2LDRHi12 t2addrmode_imm12:$addr)>; 960def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 961 (t2LDRHi8 t2addrmode_imm8:$addr)>; 962def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 963 (t2LDRHs t2addrmode_so_reg:$addr)>; 964def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 965 (t2LDRHpci tconstpool:$addr)>; 966 967// Indexed loads 968let mayLoad = 1 in { 969def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb), 970 (ins t2addrmode_imm8:$addr), 971 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 972 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", 973 []>; 974 975def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb), 976 (ins GPR:$base, t2am_imm8_offset:$offset), 977 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 978 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", 979 []>; 980 981def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 982 (ins t2addrmode_imm8:$addr), 983 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 984 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", 985 []>; 986def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 987 (ins GPR:$base, t2am_imm8_offset:$offset), 988 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 989 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", 990 []>; 991 992def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 993 (ins t2addrmode_imm8:$addr), 994 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 995 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", 996 []>; 997def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 998 (ins GPR:$base, t2am_imm8_offset:$offset), 999 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1000 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", 1001 []>; 1002 1003def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1004 (ins t2addrmode_imm8:$addr), 1005 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1006 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", 1007 []>; 1008def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1009 (ins GPR:$base, t2am_imm8_offset:$offset), 1010 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1011 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", 1012 []>; 1013 1014def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1015 (ins t2addrmode_imm8:$addr), 1016 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1017 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", 1018 []>; 1019def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1020 (ins GPR:$base, t2am_imm8_offset:$offset), 1021 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1022 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", 1023 []>; 1024} 1025 1026// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are 1027// for disassembly only. 1028// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1029class T2IldT<bit signed, bits<2> type, string opc> 1030 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc, 1031 "\t$dst, $addr", []> { 1032 let Inst{31-27} = 0b11111; 1033 let Inst{26-25} = 0b00; 1034 let Inst{24} = signed; 1035 let Inst{23} = 0; 1036 let Inst{22-21} = type; 1037 let Inst{20} = 1; // load 1038 let Inst{11} = 1; 1039 let Inst{10-8} = 0b110; // PUW. 1040} 1041 1042def t2LDRT : T2IldT<0, 0b10, "ldrt">; 1043def t2LDRBT : T2IldT<0, 0b00, "ldrbt">; 1044def t2LDRHT : T2IldT<0, 0b01, "ldrht">; 1045def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">; 1046def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">; 1047 1048// Store 1049defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 1050defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1051defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1052 1053// Store doubleword 1054let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in 1055def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1056 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), 1057 IIC_iStorer, "strd", "\t$src1, $addr", []>; 1058 1059// Indexed stores 1060def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb), 1061 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1062 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1063 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 1064 [(set GPR:$base_wb, 1065 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1066 1067def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb), 1068 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1069 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1070 "str", "\t$src, [$base], $offset", "$base = $base_wb", 1071 [(set GPR:$base_wb, 1072 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1073 1074def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb), 1075 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1076 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1077 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 1078 [(set GPR:$base_wb, 1079 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1080 1081def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb), 1082 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1083 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1084 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 1085 [(set GPR:$base_wb, 1086 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1087 1088def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb), 1089 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1090 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1091 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 1092 [(set GPR:$base_wb, 1093 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1094 1095def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb), 1096 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1097 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1098 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 1099 [(set GPR:$base_wb, 1100 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1101 1102// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1103// only. 1104// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1105class T2IstT<bits<2> type, string opc> 1106 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc, 1107 "\t$src, $addr", []> { 1108 let Inst{31-27} = 0b11111; 1109 let Inst{26-25} = 0b00; 1110 let Inst{24} = 0; // not signed 1111 let Inst{23} = 0; 1112 let Inst{22-21} = type; 1113 let Inst{20} = 0; // store 1114 let Inst{11} = 1; 1115 let Inst{10-8} = 0b110; // PUW 1116} 1117 1118def t2STRT : T2IstT<0b10, "strt">; 1119def t2STRBT : T2IstT<0b00, "strbt">; 1120def t2STRHT : T2IstT<0b01, "strht">; 1121 1122// ldrd / strd pre / post variants 1123// For disassembly only. 1124 1125def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1126 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1127 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>; 1128 1129def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1130 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1131 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>; 1132 1133def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs), 1134 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1135 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>; 1136 1137def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs), 1138 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1139 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>; 1140 1141// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1142// data/instruction access. These are for disassembly only. 1143// 1144// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 1145// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 1146multiclass T2Ipl<bit instr, bit write, string opc> { 1147 1148 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc, 1149 "\t[$base, $imm]", []> { 1150 let Inst{31-25} = 0b1111100; 1151 let Inst{24} = instr; 1152 let Inst{23} = 1; // U = 1 1153 let Inst{22} = 0; 1154 let Inst{21} = write; 1155 let Inst{20} = 1; 1156 let Inst{15-12} = 0b1111; 1157 } 1158 1159 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1160 "\t[$base, $imm]", []> { 1161 let Inst{31-25} = 0b1111100; 1162 let Inst{24} = instr; 1163 let Inst{23} = 0; // U = 0 1164 let Inst{22} = 0; 1165 let Inst{21} = write; 1166 let Inst{20} = 1; 1167 let Inst{15-12} = 0b1111; 1168 let Inst{11-8} = 0b1100; 1169 } 1170 1171 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1172 "\t[pc, $imm]", []> { 1173 let Inst{31-25} = 0b1111100; 1174 let Inst{24} = instr; 1175 let Inst{23} = ?; // add = (U == 1) 1176 let Inst{22} = 0; 1177 let Inst{21} = write; 1178 let Inst{20} = 1; 1179 let Inst{19-16} = 0b1111; // Rn = 0b1111 1180 let Inst{15-12} = 0b1111; 1181 } 1182 1183 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc, 1184 "\t[$base, $a]", []> { 1185 let Inst{31-25} = 0b1111100; 1186 let Inst{24} = instr; 1187 let Inst{23} = 0; // add = TRUE for T1 1188 let Inst{22} = 0; 1189 let Inst{21} = write; 1190 let Inst{20} = 1; 1191 let Inst{15-12} = 0b1111; 1192 let Inst{11-6} = 0000000; 1193 let Inst{5-4} = 0b00; // no shift is applied 1194 } 1195 1196 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc, 1197 "\t[$base, $a, lsl $shamt]", []> { 1198 let Inst{31-25} = 0b1111100; 1199 let Inst{24} = instr; 1200 let Inst{23} = 0; // add = TRUE for T1 1201 let Inst{22} = 0; 1202 let Inst{21} = write; 1203 let Inst{20} = 1; 1204 let Inst{15-12} = 0b1111; 1205 let Inst{11-6} = 0000000; 1206 } 1207} 1208 1209defm t2PLD : T2Ipl<0, 0, "pld">; 1210defm t2PLDW : T2Ipl<0, 1, "pldw">; 1211defm t2PLI : T2Ipl<1, 0, "pli">; 1212 1213//===----------------------------------------------------------------------===// 1214// Load / store multiple Instructions. 1215// 1216 1217let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 1218def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1219 reglist:$dsts, variable_ops), IIC_iLoadm, 1220 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { 1221 let Inst{31-27} = 0b11101; 1222 let Inst{26-25} = 0b00; 1223 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1224 let Inst{22} = 0; 1225 let Inst{21} = 0; // The W bit. 1226 let Inst{20} = 1; // Load 1227} 1228 1229def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1230 reglist:$dsts, variable_ops), IIC_iLoadm, 1231 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", 1232 "$addr.addr = $wb", []> { 1233 let Inst{31-27} = 0b11101; 1234 let Inst{26-25} = 0b00; 1235 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1236 let Inst{22} = 0; 1237 let Inst{21} = 1; // The W bit. 1238 let Inst{20} = 1; // Load 1239} 1240} // mayLoad, hasExtraDefRegAllocReq 1241 1242let mayStore = 1, hasExtraSrcRegAllocReq = 1 in { 1243def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1244 reglist:$srcs, variable_ops), IIC_iStorem, 1245 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { 1246 let Inst{31-27} = 0b11101; 1247 let Inst{26-25} = 0b00; 1248 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1249 let Inst{22} = 0; 1250 let Inst{21} = 0; // The W bit. 1251 let Inst{20} = 0; // Store 1252} 1253 1254def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1255 reglist:$srcs, variable_ops), 1256 IIC_iStorem, 1257 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs", 1258 "$addr.addr = $wb", []> { 1259 let Inst{31-27} = 0b11101; 1260 let Inst{26-25} = 0b00; 1261 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1262 let Inst{22} = 0; 1263 let Inst{21} = 1; // The W bit. 1264 let Inst{20} = 0; // Store 1265} 1266} // mayStore, hasExtraSrcRegAllocReq 1267 1268//===----------------------------------------------------------------------===// 1269// Move Instructions. 1270// 1271 1272let neverHasSideEffects = 1 in 1273def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 1274 "mov", ".w\t$dst, $src", []> { 1275 let Inst{31-27} = 0b11101; 1276 let Inst{26-25} = 0b01; 1277 let Inst{24-21} = 0b0010; 1278 let Inst{20} = ?; // The S bit. 1279 let Inst{19-16} = 0b1111; // Rn 1280 let Inst{14-12} = 0b000; 1281 let Inst{7-4} = 0b0000; 1282} 1283 1284// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1285let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in 1286def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 1287 "mov", ".w\t$dst, $src", 1288 [(set GPR:$dst, t2_so_imm:$src)]> { 1289 let Inst{31-27} = 0b11110; 1290 let Inst{25} = 0; 1291 let Inst{24-21} = 0b0010; 1292 let Inst{20} = ?; // The S bit. 1293 let Inst{19-16} = 0b1111; // Rn 1294 let Inst{15} = 0; 1295} 1296 1297let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1298def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 1299 "movw", "\t$dst, $src", 1300 [(set GPR:$dst, imm0_65535:$src)]> { 1301 let Inst{31-27} = 0b11110; 1302 let Inst{25} = 1; 1303 let Inst{24-21} = 0b0010; 1304 let Inst{20} = 0; // The S bit. 1305 let Inst{15} = 0; 1306} 1307 1308let Constraints = "$src = $dst" in 1309def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iMOVi, 1310 "movt", "\t$dst, $imm", 1311 [(set GPR:$dst, 1312 (or (and GPR:$src, 0xffff), lo16AllZero:$imm))]> { 1313 let Inst{31-27} = 0b11110; 1314 let Inst{25} = 1; 1315 let Inst{24-21} = 0b0110; 1316 let Inst{20} = 0; // The S bit. 1317 let Inst{15} = 0; 1318} 1319 1320def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>; 1321 1322//===----------------------------------------------------------------------===// 1323// Extend Instructions. 1324// 1325 1326// Sign extenders 1327 1328defm t2SXTB : T2I_unary_rrot<0b100, "sxtb", 1329 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1330defm t2SXTH : T2I_unary_rrot<0b000, "sxth", 1331 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1332defm t2SXTB16 : T2I_unary_rrot_DO<0b010, "sxtb16">; 1333 1334defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab", 1335 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1336defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah", 1337 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1338defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">; 1339 1340// TODO: SXT(A){B|H}16 - done for disassembly only 1341 1342// Zero extenders 1343 1344let AddedComplexity = 16 in { 1345defm t2UXTB : T2I_unary_rrot<0b101, "uxtb", 1346 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1347defm t2UXTH : T2I_unary_rrot<0b001, "uxth", 1348 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1349defm t2UXTB16 : T2I_unary_rrot_nw<0b011, "uxtb16", 1350 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1351 1352def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 1353 (t2UXTB16r_rot GPR:$Src, 24)>; 1354def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 1355 (t2UXTB16r_rot GPR:$Src, 8)>; 1356 1357defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab", 1358 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1359defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah", 1360 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1361defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">; 1362} 1363 1364//===----------------------------------------------------------------------===// 1365// Arithmetic Instructions. 1366// 1367 1368defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1369 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1370defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1371 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1372 1373// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1374defm t2ADDS : T2I_bin_s_irs <0b1000, "add", 1375 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 1376defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", 1377 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1378 1379defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1380 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; 1381defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1382 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; 1383defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc", 1384 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; 1385defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc", 1386 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>; 1387 1388// RSB 1389defm t2RSB : T2I_rbin_is <0b1110, "rsb", 1390 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1391defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", 1392 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1393 1394// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1395let AddedComplexity = 1 in 1396def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1397 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1398def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1399 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1400def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1401 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1402 1403// Select Bytes -- for disassembly only 1404 1405def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel", 1406 "\t$dst, $a, $b", []> { 1407 let Inst{31-27} = 0b11111; 1408 let Inst{26-24} = 0b010; 1409 let Inst{23} = 0b1; 1410 let Inst{22-20} = 0b010; 1411 let Inst{15-12} = 0b1111; 1412 let Inst{7} = 0b1; 1413 let Inst{6-4} = 0b000; 1414} 1415 1416// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1417// And Miscellaneous operations -- for disassembly only 1418class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc> 1419 : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, opc, 1420 "\t$dst, $a, $b", [/* For disassembly only; pattern left blank */]> { 1421 let Inst{31-27} = 0b11111; 1422 let Inst{26-23} = 0b0101; 1423 let Inst{22-20} = op22_20; 1424 let Inst{15-12} = 0b1111; 1425 let Inst{7-4} = op7_4; 1426} 1427 1428// Saturating add/subtract -- for disassembly only 1429 1430def t2QADD : T2I_pam<0b000, 0b1000, "qadd">; 1431def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1432def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1433def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1434def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">; 1435def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">; 1436def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1437def t2QSUB : T2I_pam<0b000, 0b1010, "qsub">; 1438def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1439def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1440def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1441def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1442def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1443def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1444def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1445def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1446 1447// Signed/Unsigned add/subtract -- for disassembly only 1448 1449def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1450def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1451def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1452def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1453def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1454def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1455def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1456def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 1457def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 1458def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 1459def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 1460def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 1461 1462// Signed/Unsigned halving add/subtract -- for disassembly only 1463 1464def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1465def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 1466def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 1467def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 1468def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 1469def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 1470def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 1471def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 1472def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 1473def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 1474def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 1475def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 1476 1477// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 1478 1479def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1480 NoItinerary, "usad8", "\t$dst, $a, $b", []> { 1481 let Inst{15-12} = 0b1111; 1482} 1483def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs GPR:$dst), 1484 (ins GPR:$a, GPR:$b, GPR:$acc), NoItinerary, "usada8", 1485 "\t$dst, $a, $b, $acc", []>; 1486 1487// Signed/Unsigned saturate -- for disassembly only 1488 1489def t2SSATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1490 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, lsl $shamt", 1491 [/* For disassembly only; pattern left blank */]> { 1492 let Inst{31-27} = 0b11110; 1493 let Inst{25-22} = 0b1100; 1494 let Inst{20} = 0; 1495 let Inst{15} = 0; 1496 let Inst{21} = 0; // sh = '0' 1497} 1498 1499def t2SSATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1500 NoItinerary, "ssat", "\t$dst, $bit_pos, $a, asr $shamt", 1501 [/* For disassembly only; pattern left blank */]> { 1502 let Inst{31-27} = 0b11110; 1503 let Inst{25-22} = 0b1100; 1504 let Inst{20} = 0; 1505 let Inst{15} = 0; 1506 let Inst{21} = 1; // sh = '1' 1507} 1508 1509def t2SSAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary, 1510 "ssat16", "\t$dst, $bit_pos, $a", 1511 [/* For disassembly only; pattern left blank */]> { 1512 let Inst{31-27} = 0b11110; 1513 let Inst{25-22} = 0b1100; 1514 let Inst{20} = 0; 1515 let Inst{15} = 0; 1516 let Inst{21} = 1; // sh = '1' 1517 let Inst{14-12} = 0b000; // imm3 = '000' 1518 let Inst{7-6} = 0b00; // imm2 = '00' 1519} 1520 1521def t2USATlsl : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1522 NoItinerary, "usat", "\t$dst, $bit_pos, $a, lsl $shamt", 1523 [/* For disassembly only; pattern left blank */]> { 1524 let Inst{31-27} = 0b11110; 1525 let Inst{25-22} = 0b1110; 1526 let Inst{20} = 0; 1527 let Inst{15} = 0; 1528 let Inst{21} = 0; // sh = '0' 1529} 1530 1531def t2USATasr : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos,GPR:$a,i32imm:$shamt), 1532 NoItinerary, "usat", "\t$dst, $bit_pos, $a, asr $shamt", 1533 [/* For disassembly only; pattern left blank */]> { 1534 let Inst{31-27} = 0b11110; 1535 let Inst{25-22} = 0b1110; 1536 let Inst{20} = 0; 1537 let Inst{15} = 0; 1538 let Inst{21} = 1; // sh = '1' 1539} 1540 1541def t2USAT16 : T2I<(outs GPR:$dst), (ins i32imm:$bit_pos, GPR:$a), NoItinerary, 1542 "usat16", "\t$dst, $bit_pos, $a", 1543 [/* For disassembly only; pattern left blank */]> { 1544 let Inst{31-27} = 0b11110; 1545 let Inst{25-22} = 0b1110; 1546 let Inst{20} = 0; 1547 let Inst{15} = 0; 1548 let Inst{21} = 1; // sh = '1' 1549 let Inst{14-12} = 0b000; // imm3 = '000' 1550 let Inst{7-6} = 0b00; // imm2 = '00' 1551} 1552 1553//===----------------------------------------------------------------------===// 1554// Shift and rotate Instructions. 1555// 1556 1557defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 1558defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 1559defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 1560defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 1561 1562let Uses = [CPSR] in { 1563def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1564 "rrx", "\t$dst, $src", 1565 [(set GPR:$dst, (ARMrrx GPR:$src))]> { 1566 let Inst{31-27} = 0b11101; 1567 let Inst{26-25} = 0b01; 1568 let Inst{24-21} = 0b0010; 1569 let Inst{20} = ?; // The S bit. 1570 let Inst{19-16} = 0b1111; // Rn 1571 let Inst{14-12} = 0b000; 1572 let Inst{7-4} = 0b0011; 1573} 1574} 1575 1576let Defs = [CPSR] in { 1577def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1578 "lsrs.w\t$dst, $src, #1", 1579 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]> { 1580 let Inst{31-27} = 0b11101; 1581 let Inst{26-25} = 0b01; 1582 let Inst{24-21} = 0b0010; 1583 let Inst{20} = 1; // The S bit. 1584 let Inst{19-16} = 0b1111; // Rn 1585 let Inst{5-4} = 0b01; // Shift type. 1586 // Shift amount = Inst{14-12:7-6} = 1. 1587 let Inst{14-12} = 0b000; 1588 let Inst{7-6} = 0b01; 1589} 1590def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 1591 "asrs.w\t$dst, $src, #1", 1592 [(set GPR:$dst, (ARMsra_flag GPR:$src))]> { 1593 let Inst{31-27} = 0b11101; 1594 let Inst{26-25} = 0b01; 1595 let Inst{24-21} = 0b0010; 1596 let Inst{20} = 1; // The S bit. 1597 let Inst{19-16} = 0b1111; // Rn 1598 let Inst{5-4} = 0b10; // Shift type. 1599 // Shift amount = Inst{14-12:7-6} = 1. 1600 let Inst{14-12} = 0b000; 1601 let Inst{7-6} = 0b01; 1602} 1603} 1604 1605//===----------------------------------------------------------------------===// 1606// Bitwise Instructions. 1607// 1608 1609defm t2AND : T2I_bin_w_irs<0b0000, "and", 1610 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 1611defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 1612 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 1613defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 1614 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 1615 1616defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 1617 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1618 1619let Constraints = "$src = $dst" in 1620def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 1621 IIC_iUNAsi, "bfc", "\t$dst, $imm", 1622 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]> { 1623 let Inst{31-27} = 0b11110; 1624 let Inst{25} = 1; 1625 let Inst{24-20} = 0b10110; 1626 let Inst{19-16} = 0b1111; // Rn 1627 let Inst{15} = 0; 1628} 1629 1630def t2SBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1631 IIC_iALUi, "sbfx", "\t$dst, $src, $lsb, $width", []> { 1632 let Inst{31-27} = 0b11110; 1633 let Inst{25} = 1; 1634 let Inst{24-20} = 0b10100; 1635 let Inst{15} = 0; 1636} 1637 1638def t2UBFX : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1639 IIC_iALUi, "ubfx", "\t$dst, $src, $lsb, $width", []> { 1640 let Inst{31-27} = 0b11110; 1641 let Inst{25} = 1; 1642 let Inst{24-20} = 0b11100; 1643 let Inst{15} = 0; 1644} 1645 1646// A8.6.18 BFI - Bitfield insert (Encoding T1) 1647// Added for disassembler with the pattern field purposely left blank. 1648// FIXME: Utilize this instruction in codgen. 1649def t2BFI : T2I<(outs GPR:$dst), (ins GPR:$src, imm0_31:$lsb, imm0_31:$width), 1650 IIC_iALUi, "bfi", "\t$dst, $src, $lsb, $width", []> { 1651 let Inst{31-27} = 0b11110; 1652 let Inst{25} = 1; 1653 let Inst{24-20} = 0b10110; 1654 let Inst{15} = 0; 1655} 1656 1657defm t2ORN : T2I_bin_irs<0b0011, "orn", BinOpFrag<(or node:$LHS, 1658 (not node:$RHS))>>; 1659 1660// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 1661let AddedComplexity = 1 in 1662defm t2MVN : T2I_un_irs <0b0011, "mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 1663 1664 1665def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 1666 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 1667 1668// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 1669def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 1670 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>, 1671 Requires<[IsThumb2]>; 1672 1673def : T2Pat<(t2_so_imm_not:$src), 1674 (t2MVNi t2_so_imm_not:$src)>; 1675 1676//===----------------------------------------------------------------------===// 1677// Multiply Instructions. 1678// 1679let isCommutable = 1 in 1680def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1681 "mul", "\t$dst, $a, $b", 1682 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]> { 1683 let Inst{31-27} = 0b11111; 1684 let Inst{26-23} = 0b0110; 1685 let Inst{22-20} = 0b000; 1686 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1687 let Inst{7-4} = 0b0000; // Multiply 1688} 1689 1690def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1691 "mla", "\t$dst, $a, $b, $c", 1692 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]> { 1693 let Inst{31-27} = 0b11111; 1694 let Inst{26-23} = 0b0110; 1695 let Inst{22-20} = 0b000; 1696 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1697 let Inst{7-4} = 0b0000; // Multiply 1698} 1699 1700def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1701 "mls", "\t$dst, $a, $b, $c", 1702 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]> { 1703 let Inst{31-27} = 0b11111; 1704 let Inst{26-23} = 0b0110; 1705 let Inst{22-20} = 0b000; 1706 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1707 let Inst{7-4} = 0b0001; // Multiply and Subtract 1708} 1709 1710// Extra precision multiplies with low / high results 1711let neverHasSideEffects = 1 in { 1712let isCommutable = 1 in { 1713def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 1714 "smull", "\t$ldst, $hdst, $a, $b", []> { 1715 let Inst{31-27} = 0b11111; 1716 let Inst{26-23} = 0b0111; 1717 let Inst{22-20} = 0b000; 1718 let Inst{7-4} = 0b0000; 1719} 1720 1721def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMUL64, 1722 "umull", "\t$ldst, $hdst, $a, $b", []> { 1723 let Inst{31-27} = 0b11111; 1724 let Inst{26-23} = 0b0111; 1725 let Inst{22-20} = 0b010; 1726 let Inst{7-4} = 0b0000; 1727} 1728} // isCommutable 1729 1730// Multiply + accumulate 1731def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1732 "smlal", "\t$ldst, $hdst, $a, $b", []>{ 1733 let Inst{31-27} = 0b11111; 1734 let Inst{26-23} = 0b0111; 1735 let Inst{22-20} = 0b100; 1736 let Inst{7-4} = 0b0000; 1737} 1738 1739def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1740 "umlal", "\t$ldst, $hdst, $a, $b", []>{ 1741 let Inst{31-27} = 0b11111; 1742 let Inst{26-23} = 0b0111; 1743 let Inst{22-20} = 0b110; 1744 let Inst{7-4} = 0b0000; 1745} 1746 1747def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMAC64, 1748 "umaal", "\t$ldst, $hdst, $a, $b", []>{ 1749 let Inst{31-27} = 0b11111; 1750 let Inst{26-23} = 0b0111; 1751 let Inst{22-20} = 0b110; 1752 let Inst{7-4} = 0b0110; 1753} 1754} // neverHasSideEffects 1755 1756// Rounding variants of the below included for disassembly only 1757 1758// Most significant word multiply 1759def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1760 "smmul", "\t$dst, $a, $b", 1761 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]> { 1762 let Inst{31-27} = 0b11111; 1763 let Inst{26-23} = 0b0110; 1764 let Inst{22-20} = 0b101; 1765 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1766 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1767} 1768 1769def t2SMMULR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1770 "smmulr", "\t$dst, $a, $b", []> { 1771 let Inst{31-27} = 0b11111; 1772 let Inst{26-23} = 0b0110; 1773 let Inst{22-20} = 0b101; 1774 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1775 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1776} 1777 1778def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1779 "smmla", "\t$dst, $a, $b, $c", 1780 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]> { 1781 let Inst{31-27} = 0b11111; 1782 let Inst{26-23} = 0b0110; 1783 let Inst{22-20} = 0b101; 1784 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1785 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1786} 1787 1788def t2SMMLAR : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1789 "smmlar", "\t$dst, $a, $b, $c", []> { 1790 let Inst{31-27} = 0b11111; 1791 let Inst{26-23} = 0b0110; 1792 let Inst{22-20} = 0b101; 1793 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1794 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1795} 1796 1797def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1798 "smmls", "\t$dst, $a, $b, $c", 1799 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]> { 1800 let Inst{31-27} = 0b11111; 1801 let Inst{26-23} = 0b0110; 1802 let Inst{22-20} = 0b110; 1803 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1804 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1805} 1806 1807def t2SMMLSR : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMAC32, 1808 "smmlsr", "\t$dst, $a, $b, $c", []> { 1809 let Inst{31-27} = 0b11111; 1810 let Inst{26-23} = 0b0110; 1811 let Inst{22-20} = 0b110; 1812 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1813 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1814} 1815 1816multiclass T2I_smul<string opc, PatFrag opnode> { 1817 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1818 !strconcat(opc, "bb"), "\t$dst, $a, $b", 1819 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1820 (sext_inreg GPR:$b, i16)))]> { 1821 let Inst{31-27} = 0b11111; 1822 let Inst{26-23} = 0b0110; 1823 let Inst{22-20} = 0b001; 1824 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1825 let Inst{7-6} = 0b00; 1826 let Inst{5-4} = 0b00; 1827 } 1828 1829 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1830 !strconcat(opc, "bt"), "\t$dst, $a, $b", 1831 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 1832 (sra GPR:$b, (i32 16))))]> { 1833 let Inst{31-27} = 0b11111; 1834 let Inst{26-23} = 0b0110; 1835 let Inst{22-20} = 0b001; 1836 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1837 let Inst{7-6} = 0b00; 1838 let Inst{5-4} = 0b01; 1839 } 1840 1841 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1842 !strconcat(opc, "tb"), "\t$dst, $a, $b", 1843 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1844 (sext_inreg GPR:$b, i16)))]> { 1845 let Inst{31-27} = 0b11111; 1846 let Inst{26-23} = 0b0110; 1847 let Inst{22-20} = 0b001; 1848 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1849 let Inst{7-6} = 0b00; 1850 let Inst{5-4} = 0b10; 1851 } 1852 1853 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL32, 1854 !strconcat(opc, "tt"), "\t$dst, $a, $b", 1855 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 1856 (sra GPR:$b, (i32 16))))]> { 1857 let Inst{31-27} = 0b11111; 1858 let Inst{26-23} = 0b0110; 1859 let Inst{22-20} = 0b001; 1860 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1861 let Inst{7-6} = 0b00; 1862 let Inst{5-4} = 0b11; 1863 } 1864 1865 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 1866 !strconcat(opc, "wb"), "\t$dst, $a, $b", 1867 [(set GPR:$dst, (sra (opnode GPR:$a, 1868 (sext_inreg GPR:$b, i16)), (i32 16)))]> { 1869 let Inst{31-27} = 0b11111; 1870 let Inst{26-23} = 0b0110; 1871 let Inst{22-20} = 0b011; 1872 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1873 let Inst{7-6} = 0b00; 1874 let Inst{5-4} = 0b00; 1875 } 1876 1877 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMUL16, 1878 !strconcat(opc, "wt"), "\t$dst, $a, $b", 1879 [(set GPR:$dst, (sra (opnode GPR:$a, 1880 (sra GPR:$b, (i32 16))), (i32 16)))]> { 1881 let Inst{31-27} = 0b11111; 1882 let Inst{26-23} = 0b0110; 1883 let Inst{22-20} = 0b011; 1884 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1885 let Inst{7-6} = 0b00; 1886 let Inst{5-4} = 0b01; 1887 } 1888} 1889 1890 1891multiclass T2I_smla<string opc, PatFrag opnode> { 1892 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1893 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", 1894 [(set GPR:$dst, (add GPR:$acc, 1895 (opnode (sext_inreg GPR:$a, i16), 1896 (sext_inreg GPR:$b, i16))))]> { 1897 let Inst{31-27} = 0b11111; 1898 let Inst{26-23} = 0b0110; 1899 let Inst{22-20} = 0b001; 1900 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1901 let Inst{7-6} = 0b00; 1902 let Inst{5-4} = 0b00; 1903 } 1904 1905 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1906 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", 1907 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 1908 (sra GPR:$b, (i32 16)))))]> { 1909 let Inst{31-27} = 0b11111; 1910 let Inst{26-23} = 0b0110; 1911 let Inst{22-20} = 0b001; 1912 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1913 let Inst{7-6} = 0b00; 1914 let Inst{5-4} = 0b01; 1915 } 1916 1917 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1918 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", 1919 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1920 (sext_inreg GPR:$b, i16))))]> { 1921 let Inst{31-27} = 0b11111; 1922 let Inst{26-23} = 0b0110; 1923 let Inst{22-20} = 0b001; 1924 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1925 let Inst{7-6} = 0b00; 1926 let Inst{5-4} = 0b10; 1927 } 1928 1929 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1930 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", 1931 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 1932 (sra GPR:$b, (i32 16)))))]> { 1933 let Inst{31-27} = 0b11111; 1934 let Inst{26-23} = 0b0110; 1935 let Inst{22-20} = 0b001; 1936 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1937 let Inst{7-6} = 0b00; 1938 let Inst{5-4} = 0b11; 1939 } 1940 1941 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1942 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", 1943 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1944 (sext_inreg GPR:$b, i16)), (i32 16))))]> { 1945 let Inst{31-27} = 0b11111; 1946 let Inst{26-23} = 0b0110; 1947 let Inst{22-20} = 0b011; 1948 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1949 let Inst{7-6} = 0b00; 1950 let Inst{5-4} = 0b00; 1951 } 1952 1953 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC16, 1954 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", 1955 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 1956 (sra GPR:$b, (i32 16))), (i32 16))))]> { 1957 let Inst{31-27} = 0b11111; 1958 let Inst{26-23} = 0b0110; 1959 let Inst{22-20} = 0b011; 1960 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1961 let Inst{7-6} = 0b00; 1962 let Inst{5-4} = 0b01; 1963 } 1964} 1965 1966defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1967defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 1968 1969// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only 1970def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs GPR:$ldst,GPR:$hdst), 1971 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b", 1972 [/* For disassembly only; pattern left blank */]>; 1973def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs GPR:$ldst,GPR:$hdst), 1974 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b", 1975 [/* For disassembly only; pattern left blank */]>; 1976def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs GPR:$ldst,GPR:$hdst), 1977 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b", 1978 [/* For disassembly only; pattern left blank */]>; 1979def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs GPR:$ldst,GPR:$hdst), 1980 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b", 1981 [/* For disassembly only; pattern left blank */]>; 1982 1983// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 1984// These are for disassembly only. 1985 1986def t2SMUAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1987 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> { 1988 let Inst{15-12} = 0b1111; 1989} 1990def t2SMUADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1991 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> { 1992 let Inst{15-12} = 0b1111; 1993} 1994def t2SMUSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1995 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> { 1996 let Inst{15-12} = 0b1111; 1997} 1998def t2SMUSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), (ins GPR:$a, GPR:$b), 1999 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> { 2000 let Inst{15-12} = 0b1111; 2001} 2002def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs GPR:$dst), 2003 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlad", 2004 "\t$dst, $a, $b, $acc", []>; 2005def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs GPR:$dst), 2006 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smladx", 2007 "\t$dst, $a, $b, $acc", []>; 2008def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs GPR:$dst), 2009 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsd", 2010 "\t$dst, $a, $b, $acc", []>; 2011def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs GPR:$dst), 2012 (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMAC32, "smlsdx", 2013 "\t$dst, $a, $b, $acc", []>; 2014def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs GPR:$ldst,GPR:$hdst), 2015 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlald", 2016 "\t$ldst, $hdst, $a, $b", []>; 2017def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs GPR:$ldst,GPR:$hdst), 2018 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlaldx", 2019 "\t$ldst, $hdst, $a, $b", []>; 2020def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs GPR:$ldst,GPR:$hdst), 2021 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsld", 2022 "\t$ldst, $hdst, $a, $b", []>; 2023def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs GPR:$ldst,GPR:$hdst), 2024 (ins GPR:$a,GPR:$b), IIC_iMAC64, "smlsldx", 2025 "\t$ldst, $hdst, $a, $b", []>; 2026 2027//===----------------------------------------------------------------------===// 2028// Misc. Arithmetic Instructions. 2029// 2030 2031class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2032 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2033 : T2I<oops, iops, itin, opc, asm, pattern> { 2034 let Inst{31-27} = 0b11111; 2035 let Inst{26-22} = 0b01010; 2036 let Inst{21-20} = op1; 2037 let Inst{15-12} = 0b1111; 2038 let Inst{7-6} = 0b10; 2039 let Inst{5-4} = op2; 2040} 2041 2042def t2CLZ : T2I_misc<0b11, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2043 "clz", "\t$dst, $src", [(set GPR:$dst, (ctlz GPR:$src))]>; 2044 2045def t2RBIT : T2I_misc<0b01, 0b10, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2046 "rbit", "\t$dst, $src", 2047 [(set GPR:$dst, (ARMrbit GPR:$src))]>; 2048 2049def t2REV : T2I_misc<0b01, 0b00, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2050 "rev", ".w\t$dst, $src", [(set GPR:$dst, (bswap GPR:$src))]>; 2051 2052def t2REV16 : T2I_misc<0b01, 0b01, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2053 "rev16", ".w\t$dst, $src", 2054 [(set GPR:$dst, 2055 (or (and (srl GPR:$src, (i32 8)), 0xFF), 2056 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 2057 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 2058 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 2059 2060def t2REVSH : T2I_misc<0b01, 0b11, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, 2061 "revsh", ".w\t$dst, $src", 2062 [(set GPR:$dst, 2063 (sext_inreg 2064 (or (srl (and GPR:$src, 0xFF00), (i32 8)), 2065 (shl GPR:$src, (i32 8))), i16))]>; 2066 2067def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2068 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt", 2069 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 2070 (and (shl GPR:$src2, (i32 imm:$shamt)), 2071 0xFFFF0000)))]>, 2072 Requires<[HasT2ExtractPack]> { 2073 let Inst{31-27} = 0b11101; 2074 let Inst{26-25} = 0b01; 2075 let Inst{24-20} = 0b01100; 2076 let Inst{5} = 0; // BT form 2077 let Inst{4} = 0; 2078} 2079 2080// Alternate cases for PKHBT where identities eliminate some nodes. 2081def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 2082 (t2PKHBT GPR:$src1, GPR:$src2, 0)>, 2083 Requires<[HasT2ExtractPack]>; 2084def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 2085 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>, 2086 Requires<[HasT2ExtractPack]>; 2087 2088def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 2089 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt", 2090 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 2091 (and (sra GPR:$src2, imm16_31:$shamt), 2092 0xFFFF)))]>, 2093 Requires<[HasT2ExtractPack]> { 2094 let Inst{31-27} = 0b11101; 2095 let Inst{26-25} = 0b01; 2096 let Inst{24-20} = 0b01100; 2097 let Inst{5} = 1; // TB form 2098 let Inst{4} = 0; 2099} 2100 2101// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2102// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2103def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 2104 (t2PKHTB GPR:$src1, GPR:$src2, 16)>, 2105 Requires<[HasT2ExtractPack]>; 2106def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 2107 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 2108 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>, 2109 Requires<[HasT2ExtractPack]>; 2110 2111//===----------------------------------------------------------------------===// 2112// Comparison Instructions... 2113// 2114 2115defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2116 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 2117defm t2CMPz : T2I_cmp_irs<0b1101, "cmp", 2118 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 2119 2120//FIXME: Disable CMN, as CCodes are backwards from compare expectations 2121// Compare-to-zero still works out, just not the relationals 2122//defm t2CMN : T2I_cmp_irs<0b1000, "cmn", 2123// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2124defm t2CMNz : T2I_cmp_irs<0b1000, "cmn", 2125 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 2126 2127//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2128// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2129 2130def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 2131 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>; 2132 2133defm t2TST : T2I_cmp_irs<0b0000, "tst", 2134 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 2135defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2136 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 2137 2138// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 2139// Short range conditional branch. Looks awesome for loops. Need to figure 2140// out how to use this one. 2141 2142 2143// Conditional moves 2144// FIXME: should be able to write a pattern for ARMcmov, but can't use 2145// a two-value operand where a dag node expects two operands. :( 2146def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iCMOVr, 2147 "mov", ".w\t$dst, $true", 2148 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 2149 RegConstraint<"$false = $dst"> { 2150 let Inst{31-27} = 0b11101; 2151 let Inst{26-25} = 0b01; 2152 let Inst{24-21} = 0b0010; 2153 let Inst{20} = 0; // The S bit. 2154 let Inst{19-16} = 0b1111; // Rn 2155 let Inst{14-12} = 0b000; 2156 let Inst{7-4} = 0b0000; 2157} 2158 2159def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 2160 IIC_iCMOVi, "mov", ".w\t$dst, $true", 2161[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 2162 RegConstraint<"$false = $dst"> { 2163 let Inst{31-27} = 0b11110; 2164 let Inst{25} = 0; 2165 let Inst{24-21} = 0b0010; 2166 let Inst{20} = 0; // The S bit. 2167 let Inst{19-16} = 0b1111; // Rn 2168 let Inst{15} = 0; 2169} 2170 2171class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2172 string opc, string asm, list<dag> pattern> 2173 : T2I<oops, iops, itin, opc, asm, pattern> { 2174 let Inst{31-27} = 0b11101; 2175 let Inst{26-25} = 0b01; 2176 let Inst{24-21} = 0b0010; 2177 let Inst{20} = 0; // The S bit. 2178 let Inst{19-16} = 0b1111; // Rn 2179 let Inst{5-4} = opcod; // Shift type. 2180} 2181def t2MOVCClsl : T2I_movcc_sh<0b00, (outs GPR:$dst), 2182 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2183 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>, 2184 RegConstraint<"$false = $dst">; 2185def t2MOVCClsr : T2I_movcc_sh<0b01, (outs GPR:$dst), 2186 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2187 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>, 2188 RegConstraint<"$false = $dst">; 2189def t2MOVCCasr : T2I_movcc_sh<0b10, (outs GPR:$dst), 2190 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2191 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>, 2192 RegConstraint<"$false = $dst">; 2193def t2MOVCCror : T2I_movcc_sh<0b11, (outs GPR:$dst), 2194 (ins GPR:$false, GPR:$true, i32imm:$rhs), 2195 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>, 2196 RegConstraint<"$false = $dst">; 2197 2198//===----------------------------------------------------------------------===// 2199// Atomic operations intrinsics 2200// 2201 2202// memory barriers protect the atomic sequences 2203let hasSideEffects = 1 in { 2204def t2Int_MemBarrierV7 : AInoP<(outs), (ins), 2205 ThumbFrm, NoItinerary, 2206 "dmb", "", 2207 [(ARMMemBarrierV7)]>, 2208 Requires<[IsThumb2]> { 2209 let Inst{31-4} = 0xF3BF8F5; 2210 // FIXME: add support for options other than a full system DMB 2211 let Inst{3-0} = 0b1111; 2212} 2213 2214def t2Int_SyncBarrierV7 : AInoP<(outs), (ins), 2215 ThumbFrm, NoItinerary, 2216 "dsb", "", 2217 [(ARMSyncBarrierV7)]>, 2218 Requires<[IsThumb2]> { 2219 let Inst{31-4} = 0xF3BF8F4; 2220 // FIXME: add support for options other than a full system DSB 2221 let Inst{3-0} = 0b1111; 2222} 2223} 2224 2225// Helper class for multiclass T2MemB -- for disassembly only 2226class T2I_memb<string opc, string asm> 2227 : T2I<(outs), (ins), NoItinerary, opc, asm, 2228 [/* For disassembly only; pattern left blank */]>, 2229 Requires<[IsThumb2, HasV7]> { 2230 let Inst{31-20} = 0xf3b; 2231 let Inst{15-14} = 0b10; 2232 let Inst{12} = 0; 2233} 2234 2235multiclass T2MemB<bits<4> op7_4, string opc> { 2236 2237 def st : T2I_memb<opc, "\tst"> { 2238 let Inst{7-4} = op7_4; 2239 let Inst{3-0} = 0b1110; 2240 } 2241 2242 def ish : T2I_memb<opc, "\tish"> { 2243 let Inst{7-4} = op7_4; 2244 let Inst{3-0} = 0b1011; 2245 } 2246 2247 def ishst : T2I_memb<opc, "\tishst"> { 2248 let Inst{7-4} = op7_4; 2249 let Inst{3-0} = 0b1010; 2250 } 2251 2252 def nsh : T2I_memb<opc, "\tnsh"> { 2253 let Inst{7-4} = op7_4; 2254 let Inst{3-0} = 0b0111; 2255 } 2256 2257 def nshst : T2I_memb<opc, "\tnshst"> { 2258 let Inst{7-4} = op7_4; 2259 let Inst{3-0} = 0b0110; 2260 } 2261 2262 def osh : T2I_memb<opc, "\tosh"> { 2263 let Inst{7-4} = op7_4; 2264 let Inst{3-0} = 0b0011; 2265 } 2266 2267 def oshst : T2I_memb<opc, "\toshst"> { 2268 let Inst{7-4} = op7_4; 2269 let Inst{3-0} = 0b0010; 2270 } 2271} 2272 2273// These DMB variants are for disassembly only. 2274defm t2DMB : T2MemB<0b0101, "dmb">; 2275 2276// These DSB variants are for disassembly only. 2277defm t2DSB : T2MemB<0b0100, "dsb">; 2278 2279// ISB has only full system option -- for disassembly only 2280def t2ISBsy : T2I_memb<"isb", ""> { 2281 let Inst{7-4} = 0b0110; 2282 let Inst{3-0} = 0b1111; 2283} 2284 2285class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2286 InstrItinClass itin, string opc, string asm, string cstr, 2287 list<dag> pattern, bits<4> rt2 = 0b1111> 2288 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2289 let Inst{31-27} = 0b11101; 2290 let Inst{26-20} = 0b0001101; 2291 let Inst{11-8} = rt2; 2292 let Inst{7-6} = 0b01; 2293 let Inst{5-4} = opcod; 2294 let Inst{3-0} = 0b1111; 2295} 2296class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2297 InstrItinClass itin, string opc, string asm, string cstr, 2298 list<dag> pattern, bits<4> rt2 = 0b1111> 2299 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2300 let Inst{31-27} = 0b11101; 2301 let Inst{26-20} = 0b0001100; 2302 let Inst{11-8} = rt2; 2303 let Inst{7-6} = 0b01; 2304 let Inst{5-4} = opcod; 2305} 2306 2307let mayLoad = 1 in { 2308def t2LDREXB : T2I_ldrex<0b00, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2309 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]", 2310 "", []>; 2311def t2LDREXH : T2I_ldrex<0b01, (outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2312 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]", 2313 "", []>; 2314def t2LDREX : Thumb2I<(outs GPR:$dest), (ins GPR:$ptr), AddrModeNone, 2315 Size4Bytes, NoItinerary, 2316 "ldrex", "\t$dest, [$ptr]", "", 2317 []> { 2318 let Inst{31-27} = 0b11101; 2319 let Inst{26-20} = 0b0000101; 2320 let Inst{11-8} = 0b1111; 2321 let Inst{7-0} = 0b00000000; // imm8 = 0 2322} 2323def t2LDREXD : T2I_ldrex<0b11, (outs GPR:$dest, GPR:$dest2), (ins GPR:$ptr), 2324 AddrModeNone, Size4Bytes, NoItinerary, 2325 "ldrexd", "\t$dest, $dest2, [$ptr]", "", 2326 [], {?, ?, ?, ?}>; 2327} 2328 2329let mayStore = 1, Constraints = "@earlyclobber $success" in { 2330def t2STREXB : T2I_strex<0b00, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2331 AddrModeNone, Size4Bytes, NoItinerary, 2332 "strexb", "\t$success, $src, [$ptr]", "", []>; 2333def t2STREXH : T2I_strex<0b01, (outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2334 AddrModeNone, Size4Bytes, NoItinerary, 2335 "strexh", "\t$success, $src, [$ptr]", "", []>; 2336def t2STREX : Thumb2I<(outs GPR:$success), (ins GPR:$src, GPR:$ptr), 2337 AddrModeNone, Size4Bytes, NoItinerary, 2338 "strex", "\t$success, $src, [$ptr]", "", 2339 []> { 2340 let Inst{31-27} = 0b11101; 2341 let Inst{26-20} = 0b0000100; 2342 let Inst{7-0} = 0b00000000; // imm8 = 0 2343} 2344def t2STREXD : T2I_strex<0b11, (outs GPR:$success), 2345 (ins GPR:$src, GPR:$src2, GPR:$ptr), 2346 AddrModeNone, Size4Bytes, NoItinerary, 2347 "strexd", "\t$success, $src, $src2, [$ptr]", "", [], 2348 {?, ?, ?, ?}>; 2349} 2350 2351// Clear-Exclusive is for disassembly only. 2352def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", 2353 [/* For disassembly only; pattern left blank */]>, 2354 Requires<[IsARM, HasV7]> { 2355 let Inst{31-20} = 0xf3b; 2356 let Inst{15-14} = 0b10; 2357 let Inst{12} = 0; 2358 let Inst{7-4} = 0b0010; 2359} 2360 2361//===----------------------------------------------------------------------===// 2362// TLS Instructions 2363// 2364 2365// __aeabi_read_tp preserves the registers r1-r3. 2366let isCall = 1, 2367 Defs = [R0, R12, LR, CPSR] in { 2368 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 2369 "bl\t__aeabi_read_tp", 2370 [(set R0, ARMthread_pointer)]> { 2371 let Inst{31-27} = 0b11110; 2372 let Inst{15-14} = 0b11; 2373 let Inst{12} = 1; 2374 } 2375} 2376 2377//===----------------------------------------------------------------------===// 2378// SJLJ Exception handling intrinsics 2379// eh_sjlj_setjmp() is an instruction sequence to store the return 2380// address and save #0 in R0 for the non-longjmp case. 2381// Since by its nature we may be coming from some other function to get 2382// here, and we're using the stack frame for the containing function to 2383// save/restore registers, we can't keep anything live in regs across 2384// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 2385// when we get here from a longjmp(). We force everthing out of registers 2386// except for our own input by listing the relevant registers in Defs. By 2387// doing so, we also cause the prologue/epilogue code to actively preserve 2388// all of the callee-saved resgisters, which is exactly what we want. 2389// The current SP is passed in $val, and we reuse the reg as a scratch. 2390let Defs = 2391 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 2392 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 2393 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 2394 D31 ] in { 2395 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val), 2396 AddrModeNone, SizeSpecial, NoItinerary, 2397 "str\t$val, [$src, #8]\t${:comment} begin eh.setjmp\n" 2398 "\tmov\t$val, pc\n" 2399 "\tadds\t$val, #9\n" 2400 "\tstr\t$val, [$src, #4]\n" 2401 "\tmovs\tr0, #0\n" 2402 "\tb\t1f\n" 2403 "\tmovs\tr0, #1\t${:comment} end eh.setjmp\n" 2404 "1:", "", 2405 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>, 2406 Requires<[IsThumb2, HasVFP2]>; 2407} 2408 2409let Defs = 2410 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ] in { 2411 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins GPR:$src, tGPR:$val), 2412 AddrModeNone, SizeSpecial, NoItinerary, 2413 "str\t$val, [$src, #8]\t${:comment} begin eh.setjmp\n" 2414 "\tmov\t$val, pc\n" 2415 "\tadds\t$val, #9\n" 2416 "\tstr\t$val, [$src, #4]\n" 2417 "\tmovs\tr0, #0\n" 2418 "\tb\t1f\n" 2419 "\tmovs\tr0, #1\t${:comment} end eh.setjmp\n" 2420 "1:", "", 2421 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, tGPR:$val))]>, 2422 Requires<[IsThumb2, NoVFP]>; 2423} 2424 2425 2426//===----------------------------------------------------------------------===// 2427// Control-Flow Instructions 2428// 2429 2430// FIXME: remove when we have a way to marking a MI with these properties. 2431// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 2432// operand list. 2433// FIXME: Should pc be an implicit operand like PICADD, etc? 2434let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2435 hasExtraDefRegAllocReq = 1 in 2436 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 2437 reglist:$dsts, variable_ops), IIC_Br, 2438 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", 2439 "$addr.addr = $wb", []> { 2440 let Inst{31-27} = 0b11101; 2441 let Inst{26-25} = 0b00; 2442 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 2443 let Inst{22} = 0; 2444 let Inst{21} = 1; // The W bit. 2445 let Inst{20} = 1; // Load 2446} 2447 2448let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 2449let isPredicable = 1 in 2450def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 2451 "b.w\t$target", 2452 [(br bb:$target)]> { 2453 let Inst{31-27} = 0b11110; 2454 let Inst{15-14} = 0b10; 2455 let Inst{12} = 1; 2456} 2457 2458let isNotDuplicable = 1, isIndirectBranch = 1 in { 2459def t2BR_JT : 2460 T2JTI<(outs), 2461 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 2462 IIC_Br, "mov\tpc, $target\n$jt", 2463 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> { 2464 let Inst{31-27} = 0b11101; 2465 let Inst{26-20} = 0b0100100; 2466 let Inst{19-16} = 0b1111; 2467 let Inst{14-12} = 0b000; 2468 let Inst{11-8} = 0b1111; // Rd = pc 2469 let Inst{7-4} = 0b0000; 2470} 2471 2472// FIXME: Add a non-pc based case that can be predicated. 2473def t2TBB : 2474 T2JTI<(outs), 2475 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2476 IIC_Br, "tbb\t$index\n$jt", []> { 2477 let Inst{31-27} = 0b11101; 2478 let Inst{26-20} = 0b0001101; 2479 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2480 let Inst{15-8} = 0b11110000; 2481 let Inst{7-4} = 0b0000; // B form 2482} 2483 2484def t2TBH : 2485 T2JTI<(outs), 2486 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2487 IIC_Br, "tbh\t$index\n$jt", []> { 2488 let Inst{31-27} = 0b11101; 2489 let Inst{26-20} = 0b0001101; 2490 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2491 let Inst{15-8} = 0b11110000; 2492 let Inst{7-4} = 0b0001; // H form 2493} 2494 2495// Generic versions of the above two instructions, for disassembly only 2496 2497def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2498 "tbb", "\t[$a, $b]", []>{ 2499 let Inst{31-27} = 0b11101; 2500 let Inst{26-20} = 0b0001101; 2501 let Inst{15-8} = 0b11110000; 2502 let Inst{7-4} = 0b0000; // B form 2503} 2504 2505def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2506 "tbh", "\t[$a, $b, lsl #1]", []> { 2507 let Inst{31-27} = 0b11101; 2508 let Inst{26-20} = 0b0001101; 2509 let Inst{15-8} = 0b11110000; 2510 let Inst{7-4} = 0b0001; // H form 2511} 2512} // isNotDuplicable, isIndirectBranch 2513 2514} // isBranch, isTerminator, isBarrier 2515 2516// FIXME: should be able to write a pattern for ARMBrcond, but can't use 2517// a two-value operand where a dag node expects two operands. :( 2518let isBranch = 1, isTerminator = 1 in 2519def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 2520 "b", ".w\t$target", 2521 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 2522 let Inst{31-27} = 0b11110; 2523 let Inst{15-14} = 0b10; 2524 let Inst{12} = 0; 2525} 2526 2527 2528// IT block 2529def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 2530 AddrModeNone, Size2Bytes, IIC_iALUx, 2531 "it$mask\t$cc", "", []> { 2532 // 16-bit instruction. 2533 let Inst{31-16} = 0x0000; 2534 let Inst{15-8} = 0b10111111; 2535} 2536 2537// Branch and Exchange Jazelle -- for disassembly only 2538// Rm = Inst{19-16} 2539def t2BXJ : T2I<(outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2540 [/* For disassembly only; pattern left blank */]> { 2541 let Inst{31-27} = 0b11110; 2542 let Inst{26} = 0; 2543 let Inst{25-20} = 0b111100; 2544 let Inst{15-14} = 0b10; 2545 let Inst{12} = 0; 2546} 2547 2548// Change Processor State is a system instruction -- for disassembly only. 2549// The singleton $opt operand contains the following information: 2550// opt{4-0} = mode from Inst{4-0} 2551// opt{5} = changemode from Inst{17} 2552// opt{8-6} = AIF from Inst{8-6} 2553// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable 2554def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt", 2555 [/* For disassembly only; pattern left blank */]> { 2556 let Inst{31-27} = 0b11110; 2557 let Inst{26} = 0; 2558 let Inst{25-20} = 0b111010; 2559 let Inst{15-14} = 0b10; 2560 let Inst{12} = 0; 2561} 2562 2563// A6.3.4 Branches and miscellaneous control 2564// Table A6-14 Change Processor State, and hint instructions 2565// Helper class for disassembly only. 2566class T2I_hint<bits<8> op7_0, string opc, string asm> 2567 : T2I<(outs), (ins), NoItinerary, opc, asm, 2568 [/* For disassembly only; pattern left blank */]> { 2569 let Inst{31-20} = 0xf3a; 2570 let Inst{15-14} = 0b10; 2571 let Inst{12} = 0; 2572 let Inst{10-8} = 0b000; 2573 let Inst{7-0} = op7_0; 2574} 2575 2576def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 2577def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 2578def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 2579def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 2580def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 2581 2582def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt", 2583 [/* For disassembly only; pattern left blank */]> { 2584 let Inst{31-20} = 0xf3a; 2585 let Inst{15-14} = 0b10; 2586 let Inst{12} = 0; 2587 let Inst{10-8} = 0b000; 2588 let Inst{7-4} = 0b1111; 2589} 2590 2591// Secure Monitor Call is a system instruction -- for disassembly only 2592// Option = Inst{19-16} 2593def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", 2594 [/* For disassembly only; pattern left blank */]> { 2595 let Inst{31-27} = 0b11110; 2596 let Inst{26-20} = 0b1111111; 2597 let Inst{15-12} = 0b1000; 2598} 2599 2600// Store Return State is a system instruction -- for disassembly only 2601def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode", 2602 [/* For disassembly only; pattern left blank */]> { 2603 let Inst{31-27} = 0b11101; 2604 let Inst{26-20} = 0b0000010; // W = 1 2605} 2606 2607def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode", 2608 [/* For disassembly only; pattern left blank */]> { 2609 let Inst{31-27} = 0b11101; 2610 let Inst{26-20} = 0b0000000; // W = 0 2611} 2612 2613def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode", 2614 [/* For disassembly only; pattern left blank */]> { 2615 let Inst{31-27} = 0b11101; 2616 let Inst{26-20} = 0b0011010; // W = 1 2617} 2618 2619def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode", 2620 [/* For disassembly only; pattern left blank */]> { 2621 let Inst{31-27} = 0b11101; 2622 let Inst{26-20} = 0b0011000; // W = 0 2623} 2624 2625// Return From Exception is a system instruction -- for disassembly only 2626def t2RFEDBW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfedb", "\t$base!", 2627 [/* For disassembly only; pattern left blank */]> { 2628 let Inst{31-27} = 0b11101; 2629 let Inst{26-20} = 0b0000011; // W = 1 2630} 2631 2632def t2RFEDB : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeab", "\t$base", 2633 [/* For disassembly only; pattern left blank */]> { 2634 let Inst{31-27} = 0b11101; 2635 let Inst{26-20} = 0b0000001; // W = 0 2636} 2637 2638def t2RFEIAW : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base!", 2639 [/* For disassembly only; pattern left blank */]> { 2640 let Inst{31-27} = 0b11101; 2641 let Inst{26-20} = 0b0011011; // W = 1 2642} 2643 2644def t2RFEIA : T2I<(outs), (ins GPR:$base), NoItinerary, "rfeia", "\t$base", 2645 [/* For disassembly only; pattern left blank */]> { 2646 let Inst{31-27} = 0b11101; 2647 let Inst{26-20} = 0b0011001; // W = 0 2648} 2649 2650//===----------------------------------------------------------------------===// 2651// Non-Instruction Patterns 2652// 2653 2654// Two piece so_imms. 2655def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS), 2656 (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2657 (t2_so_imm2part_2 imm:$RHS))>; 2658def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS), 2659 (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2660 (t2_so_imm2part_2 imm:$RHS))>; 2661def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS), 2662 (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2663 (t2_so_imm2part_2 imm:$RHS))>; 2664def : T2Pat<(add GPR:$LHS, t2_so_neg_imm2part:$RHS), 2665 (t2SUBri (t2SUBri GPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)), 2666 (t2_so_neg_imm2part_2 imm:$RHS))>; 2667 2668// 32-bit immediate using movw + movt. 2669// This is a single pseudo instruction to make it re-materializable. Remove 2670// when we can do generalized remat. 2671let isReMaterializable = 1 in 2672def t2MOVi32imm : T2Ix2<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVi, 2673 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}", 2674 [(set GPR:$dst, (i32 imm:$src))]>; 2675 2676// ConstantPool, GlobalAddress, and JumpTable 2677def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 2678 Requires<[IsThumb2, DontUseMovt]>; 2679def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 2680def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 2681 Requires<[IsThumb2, UseMovt]>; 2682 2683def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 2684 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 2685 2686// Pseudo instruction that combines ldr from constpool and add pc. This should 2687// be expanded into two instructions late to allow if-conversion and 2688// scheduling. 2689let canFoldAsLoad = 1, isReMaterializable = 1 in 2690def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 2691 NoItinerary, "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 2692 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 2693 imm:$cp))]>, 2694 Requires<[IsThumb2]>; 2695 2696//===----------------------------------------------------------------------===// 2697// Move between special register and ARM core register -- for disassembly only 2698// 2699 2700// Rd = Instr{11-8} 2701def t2MRS : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr", 2702 [/* For disassembly only; pattern left blank */]> { 2703 let Inst{31-27} = 0b11110; 2704 let Inst{26} = 0; 2705 let Inst{25-21} = 0b11111; 2706 let Inst{20} = 0; // The R bit. 2707 let Inst{15-14} = 0b10; 2708 let Inst{12} = 0; 2709} 2710 2711// Rd = Instr{11-8} 2712def t2MRSsys : T2I<(outs GPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr", 2713 [/* For disassembly only; pattern left blank */]> { 2714 let Inst{31-27} = 0b11110; 2715 let Inst{26} = 0; 2716 let Inst{25-21} = 0b11111; 2717 let Inst{20} = 1; // The R bit. 2718 let Inst{15-14} = 0b10; 2719 let Inst{12} = 0; 2720} 2721 2722// Rn = Inst{19-16} 2723def t2MSR : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr", 2724 "\tcpsr$mask, $src", 2725 [/* For disassembly only; pattern left blank */]> { 2726 let Inst{31-27} = 0b11110; 2727 let Inst{26} = 0; 2728 let Inst{25-21} = 0b11100; 2729 let Inst{20} = 0; // The R bit. 2730 let Inst{15-14} = 0b10; 2731 let Inst{12} = 0; 2732} 2733 2734// Rn = Inst{19-16} 2735def t2MSRsys : T2I<(outs), (ins GPR:$src, msr_mask:$mask), NoItinerary, "msr", 2736 "\tspsr$mask, $src", 2737 [/* For disassembly only; pattern left blank */]> { 2738 let Inst{31-27} = 0b11110; 2739 let Inst{26} = 0; 2740 let Inst{25-21} = 0b11100; 2741 let Inst{20} = 1; // The R bit. 2742 let Inst{15-14} = 0b10; 2743 let Inst{12} = 0; 2744} 2745