ARMInstrThumb2.td revision 5d42c567c901508e80ab10ddba1bb30a5007d742
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printMandatoryPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops rGPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant 53// bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]>; 55 56// t2_so_imm_not - Match an immediate that is a complement 57// of a t2_so_imm. 58def t2_so_imm_not : Operand<i32>, 59 PatLeaf<(imm), [{ 60 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 61}], t2_so_imm_not_XFORM>; 62 63// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 64def t2_so_imm_neg : Operand<i32>, 65 PatLeaf<(imm), [{ 66 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 67}], t2_so_imm_neg_XFORM>; 68 69// Break t2_so_imm's up into two pieces. This handles immediates with up to 16 70// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12] 71// to get the first/second pieces. 72def t2_so_imm2part : Operand<i32>, 73 PatLeaf<(imm), [{ 74 return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue()); 75 }]> { 76} 77 78def t2_so_imm2part_1 : SDNodeXForm<imm, [{ 79 unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue()); 80 return CurDAG->getTargetConstant(V, MVT::i32); 81}]>; 82 83def t2_so_imm2part_2 : SDNodeXForm<imm, [{ 84 unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue()); 85 return CurDAG->getTargetConstant(V, MVT::i32); 86}]>; 87 88def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{ 89 return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue()); 90 }]> { 91} 92 93def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{ 94 unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue()); 95 return CurDAG->getTargetConstant(V, MVT::i32); 96}]>; 97 98def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{ 99 unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue()); 100 return CurDAG->getTargetConstant(V, MVT::i32); 101}]>; 102 103/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 104def imm1_31 : PatLeaf<(i32 imm), [{ 105 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 106}]>; 107 108/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 109def imm0_4095 : Operand<i32>, 110 PatLeaf<(i32 imm), [{ 111 return (uint32_t)N->getZExtValue() < 4096; 112}]>; 113 114def imm0_4095_neg : PatLeaf<(i32 imm), [{ 115 return (uint32_t)(-N->getZExtValue()) < 4096; 116}], imm_neg_XFORM>; 117 118def imm0_255_neg : PatLeaf<(i32 imm), [{ 119 return (uint32_t)(-N->getZExtValue()) < 255; 120}], imm_neg_XFORM>; 121 122def imm0_255_not : PatLeaf<(i32 imm), [{ 123 return (uint32_t)(~N->getZExtValue()) < 255; 124}], imm_comp_XFORM>; 125 126// Define Thumb2 specific addressing modes. 127 128// t2addrmode_imm12 := reg + imm12 129def t2addrmode_imm12 : Operand<i32>, 130 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 131 let PrintMethod = "printT2AddrModeImm12Operand"; 132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 133} 134 135// t2addrmode_imm8 := reg +/- imm8 136def t2addrmode_imm8 : Operand<i32>, 137 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 138 let PrintMethod = "printT2AddrModeImm8Operand"; 139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 140} 141 142def t2am_imm8_offset : Operand<i32>, 143 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 144 [], [SDNPWantRoot]> { 145 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 146} 147 148// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 149def t2addrmode_imm8s4 : Operand<i32> { 150 let PrintMethod = "printT2AddrModeImm8s4Operand"; 151 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 152} 153 154def t2am_imm8s4_offset : Operand<i32> { 155 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 156} 157 158// t2addrmode_so_reg := reg + (reg << imm2) 159def t2addrmode_so_reg : Operand<i32>, 160 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 161 let PrintMethod = "printT2AddrModeSoRegOperand"; 162 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 163} 164 165 166//===----------------------------------------------------------------------===// 167// Multiclass helpers... 168// 169 170/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 171/// unary operation that produces a value. These are predicable and can be 172/// changed to modify CPSR. 173multiclass T2I_un_irs<bits<4> opcod, string opc, 174 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 175 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { 176 // shifted imm 177 def i : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), iii, 178 opc, "\t$dst, $src", 179 [(set rGPR:$dst, (opnode t2_so_imm:$src))]> { 180 let isAsCheapAsAMove = Cheap; 181 let isReMaterializable = ReMat; 182 let Inst{31-27} = 0b11110; 183 let Inst{25} = 0; 184 let Inst{24-21} = opcod; 185 let Inst{20} = ?; // The S bit. 186 let Inst{19-16} = 0b1111; // Rn 187 let Inst{15} = 0; 188 } 189 // register 190 def r : T2sI<(outs rGPR:$dst), (ins rGPR:$src), iir, 191 opc, ".w\t$dst, $src", 192 [(set rGPR:$dst, (opnode rGPR:$src))]> { 193 let Inst{31-27} = 0b11101; 194 let Inst{26-25} = 0b01; 195 let Inst{24-21} = opcod; 196 let Inst{20} = ?; // The S bit. 197 let Inst{19-16} = 0b1111; // Rn 198 let Inst{14-12} = 0b000; // imm3 199 let Inst{7-6} = 0b00; // imm2 200 let Inst{5-4} = 0b00; // type 201 } 202 // shifted register 203 def s : T2sI<(outs rGPR:$dst), (ins t2_so_reg:$src), iis, 204 opc, ".w\t$dst, $src", 205 [(set rGPR:$dst, (opnode t2_so_reg:$src))]> { 206 let Inst{31-27} = 0b11101; 207 let Inst{26-25} = 0b01; 208 let Inst{24-21} = opcod; 209 let Inst{20} = ?; // The S bit. 210 let Inst{19-16} = 0b1111; // Rn 211 } 212} 213 214/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 215/// binary operation that produces a value. These are predicable and can be 216/// changed to modify CPSR. 217multiclass T2I_bin_irs<bits<4> opcod, string opc, 218 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 219 PatFrag opnode, bit Commutable = 0, string wide = ""> { 220 // shifted imm 221 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), iii, 222 opc, "\t$dst, $lhs, $rhs", 223 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]> { 224 let Inst{31-27} = 0b11110; 225 let Inst{25} = 0; 226 let Inst{24-21} = opcod; 227 let Inst{20} = ?; // The S bit. 228 let Inst{15} = 0; 229 } 230 // register 231 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), iir, 232 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 233 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { 234 let isCommutable = Commutable; 235 let Inst{31-27} = 0b11101; 236 let Inst{26-25} = 0b01; 237 let Inst{24-21} = opcod; 238 let Inst{20} = ?; // The S bit. 239 let Inst{14-12} = 0b000; // imm3 240 let Inst{7-6} = 0b00; // imm2 241 let Inst{5-4} = 0b00; // type 242 } 243 // shifted register 244 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), iis, 245 opc, !strconcat(wide, "\t$dst, $lhs, $rhs"), 246 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]> { 247 let Inst{31-27} = 0b11101; 248 let Inst{26-25} = 0b01; 249 let Inst{24-21} = opcod; 250 let Inst{20} = ?; // The S bit. 251 } 252} 253 254/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 255// the ".w" prefix to indicate that they are wide. 256multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 257 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 258 PatFrag opnode, bit Commutable = 0> : 259 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">; 260 261/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 262/// reversed. The 'rr' form is only defined for the disassembler; for codegen 263/// it is equivalent to the T2I_bin_irs counterpart. 264multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { 265 // shifted imm 266 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 267 opc, ".w\t$dst, $rhs, $lhs", 268 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { 269 let Inst{31-27} = 0b11110; 270 let Inst{25} = 0; 271 let Inst{24-21} = opcod; 272 let Inst{20} = ?; // The S bit. 273 let Inst{15} = 0; 274 } 275 // register 276 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, rGPR:$lhs), IIC_iALUr, 277 opc, "\t$dst, $rhs, $lhs", 278 [/* For disassembly only; pattern left blank */]> { 279 let Inst{31-27} = 0b11101; 280 let Inst{26-25} = 0b01; 281 let Inst{24-21} = opcod; 282 let Inst{20} = ?; // The S bit. 283 let Inst{14-12} = 0b000; // imm3 284 let Inst{7-6} = 0b00; // imm2 285 let Inst{5-4} = 0b00; // type 286 } 287 // shifted register 288 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 289 opc, "\t$dst, $rhs, $lhs", 290 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { 291 let Inst{31-27} = 0b11101; 292 let Inst{26-25} = 0b01; 293 let Inst{24-21} = opcod; 294 let Inst{20} = ?; // The S bit. 295 } 296} 297 298/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 299/// instruction modifies the CPSR register. 300let Defs = [CPSR] in { 301multiclass T2I_bin_s_irs<bits<4> opcod, string opc, 302 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 303 PatFrag opnode, bit Commutable = 0> { 304 // shifted imm 305 def ri : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), iii, 306 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 307 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 308 let Inst{31-27} = 0b11110; 309 let Inst{25} = 0; 310 let Inst{24-21} = opcod; 311 let Inst{20} = 1; // The S bit. 312 let Inst{15} = 0; 313 } 314 // register 315 def rr : T2I<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), iir, 316 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 317 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { 318 let isCommutable = Commutable; 319 let Inst{31-27} = 0b11101; 320 let Inst{26-25} = 0b01; 321 let Inst{24-21} = opcod; 322 let Inst{20} = 1; // The S bit. 323 let Inst{14-12} = 0b000; // imm3 324 let Inst{7-6} = 0b00; // imm2 325 let Inst{5-4} = 0b00; // type 326 } 327 // shifted register 328 def rs : T2I<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), iis, 329 !strconcat(opc, "s"), ".w\t$dst, $lhs, $rhs", 330 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 331 let Inst{31-27} = 0b11101; 332 let Inst{26-25} = 0b01; 333 let Inst{24-21} = opcod; 334 let Inst{20} = 1; // The S bit. 335 } 336} 337} 338 339/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 340/// patterns for a binary operation that produces a value. 341multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 342 bit Commutable = 0> { 343 // shifted imm 344 // The register-immediate version is re-materializable. This is useful 345 // in particular for taking the address of a local. 346 let isReMaterializable = 1 in { 347 def ri : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 348 opc, ".w\t$dst, $lhs, $rhs", 349 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]> { 350 let Inst{31-27} = 0b11110; 351 let Inst{25} = 0; 352 let Inst{24} = 1; 353 let Inst{23-21} = op23_21; 354 let Inst{20} = 0; // The S bit. 355 let Inst{15} = 0; 356 } 357 } 358 // 12-bit imm 359 def ri12 : T2I<(outs rGPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALUi, 360 !strconcat(opc, "w"), "\t$dst, $lhs, $rhs", 361 [(set rGPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]> { 362 let Inst{31-27} = 0b11110; 363 let Inst{25} = 1; 364 let Inst{24} = 0; 365 let Inst{23-21} = op23_21; 366 let Inst{20} = 0; // The S bit. 367 let Inst{15} = 0; 368 } 369 // register 370 def rr : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, rGPR:$rhs), IIC_iALUr, 371 opc, ".w\t$dst, $lhs, $rhs", 372 [(set rGPR:$dst, (opnode GPR:$lhs, rGPR:$rhs))]> { 373 let isCommutable = Commutable; 374 let Inst{31-27} = 0b11101; 375 let Inst{26-25} = 0b01; 376 let Inst{24} = 1; 377 let Inst{23-21} = op23_21; 378 let Inst{20} = 0; // The S bit. 379 let Inst{14-12} = 0b000; // imm3 380 let Inst{7-6} = 0b00; // imm2 381 let Inst{5-4} = 0b00; // type 382 } 383 // shifted register 384 def rs : T2sI<(outs rGPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 385 opc, ".w\t$dst, $lhs, $rhs", 386 [(set rGPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]> { 387 let Inst{31-27} = 0b11101; 388 let Inst{26-25} = 0b01; 389 let Inst{24} = 1; 390 let Inst{23-21} = op23_21; 391 let Inst{20} = 0; // The S bit. 392 } 393} 394 395/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 396/// for a binary operation that produces a value and use the carry 397/// bit. It's not predicable. 398let Uses = [CPSR] in { 399multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 400 bit Commutable = 0> { 401 // shifted imm 402 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 403 opc, "\t$dst, $lhs, $rhs", 404 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>, 405 Requires<[IsThumb2]> { 406 let Inst{31-27} = 0b11110; 407 let Inst{25} = 0; 408 let Inst{24-21} = opcod; 409 let Inst{20} = 0; // The S bit. 410 let Inst{15} = 0; 411 } 412 // register 413 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr, 414 opc, ".w\t$dst, $lhs, $rhs", 415 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>, 416 Requires<[IsThumb2]> { 417 let isCommutable = Commutable; 418 let Inst{31-27} = 0b11101; 419 let Inst{26-25} = 0b01; 420 let Inst{24-21} = opcod; 421 let Inst{20} = 0; // The S bit. 422 let Inst{14-12} = 0b000; // imm3 423 let Inst{7-6} = 0b00; // imm2 424 let Inst{5-4} = 0b00; // type 425 } 426 // shifted register 427 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 428 opc, ".w\t$dst, $lhs, $rhs", 429 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>, 430 Requires<[IsThumb2]> { 431 let Inst{31-27} = 0b11101; 432 let Inst{26-25} = 0b01; 433 let Inst{24-21} = opcod; 434 let Inst{20} = 0; // The S bit. 435 } 436} 437 438// Carry setting variants 439let Defs = [CPSR] in { 440multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode, 441 bit Commutable = 0> { 442 // shifted imm 443 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_imm:$rhs), IIC_iALUi, 444 opc, "\t$dst, $lhs, $rhs", 445 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_imm:$rhs))]>, 446 Requires<[IsThumb2]> { 447 let Inst{31-27} = 0b11110; 448 let Inst{25} = 0; 449 let Inst{24-21} = opcod; 450 let Inst{20} = 1; // The S bit. 451 let Inst{15} = 0; 452 } 453 // register 454 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iALUr, 455 opc, ".w\t$dst, $lhs, $rhs", 456 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]>, 457 Requires<[IsThumb2]> { 458 let isCommutable = Commutable; 459 let Inst{31-27} = 0b11101; 460 let Inst{26-25} = 0b01; 461 let Inst{24-21} = opcod; 462 let Inst{20} = 1; // The S bit. 463 let Inst{14-12} = 0b000; // imm3 464 let Inst{7-6} = 0b00; // imm2 465 let Inst{5-4} = 0b00; // type 466 } 467 // shifted register 468 def rs : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, t2_so_reg:$rhs), IIC_iALUsi, 469 opc, ".w\t$dst, $lhs, $rhs", 470 [(set rGPR:$dst, (opnode rGPR:$lhs, t2_so_reg:$rhs))]>, 471 Requires<[IsThumb2]> { 472 let Inst{31-27} = 0b11101; 473 let Inst{26-25} = 0b01; 474 let Inst{24-21} = opcod; 475 let Inst{20} = 1; // The S bit. 476 } 477} 478} 479} 480 481/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register 482/// version is not needed since this is only for codegen. 483let Defs = [CPSR] in { 484multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { 485 // shifted imm 486 def ri : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_imm:$lhs), IIC_iALUi, 487 !strconcat(opc, "s"), ".w\t$dst, $rhs, $lhs", 488 [(set rGPR:$dst, (opnode t2_so_imm:$lhs, rGPR:$rhs))]> { 489 let Inst{31-27} = 0b11110; 490 let Inst{25} = 0; 491 let Inst{24-21} = opcod; 492 let Inst{20} = 1; // The S bit. 493 let Inst{15} = 0; 494 } 495 // shifted register 496 def rs : T2I<(outs rGPR:$dst), (ins rGPR:$rhs, t2_so_reg:$lhs), IIC_iALUsi, 497 !strconcat(opc, "s"), "\t$dst, $rhs, $lhs", 498 [(set rGPR:$dst, (opnode t2_so_reg:$lhs, rGPR:$rhs))]> { 499 let Inst{31-27} = 0b11101; 500 let Inst{26-25} = 0b01; 501 let Inst{24-21} = opcod; 502 let Inst{20} = 1; // The S bit. 503 } 504} 505} 506 507/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 508// rotate operation that produces a value. 509multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> { 510 // 5-bit imm 511 def ri : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 512 opc, ".w\t$dst, $lhs, $rhs", 513 [(set rGPR:$dst, (opnode rGPR:$lhs, imm1_31:$rhs))]> { 514 let Inst{31-27} = 0b11101; 515 let Inst{26-21} = 0b010010; 516 let Inst{19-16} = 0b1111; // Rn 517 let Inst{5-4} = opcod; 518 } 519 // register 520 def rr : T2sI<(outs rGPR:$dst), (ins rGPR:$lhs, rGPR:$rhs), IIC_iMOVsr, 521 opc, ".w\t$dst, $lhs, $rhs", 522 [(set rGPR:$dst, (opnode rGPR:$lhs, rGPR:$rhs))]> { 523 let Inst{31-27} = 0b11111; 524 let Inst{26-23} = 0b0100; 525 let Inst{22-21} = opcod; 526 let Inst{15-12} = 0b1111; 527 let Inst{7-4} = 0b0000; 528 } 529} 530 531/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 532/// patterns. Similar to T2I_bin_irs except the instruction does not produce 533/// a explicit result, only implicitly set CPSR. 534let isCompare = 1, Defs = [CPSR] in { 535multiclass T2I_cmp_irs<bits<4> opcod, string opc, 536 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 537 PatFrag opnode> { 538 // shifted imm 539 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), iii, 540 opc, ".w\t$lhs, $rhs", 541 [(opnode GPR:$lhs, t2_so_imm:$rhs)]> { 542 let Inst{31-27} = 0b11110; 543 let Inst{25} = 0; 544 let Inst{24-21} = opcod; 545 let Inst{20} = 1; // The S bit. 546 let Inst{15} = 0; 547 let Inst{11-8} = 0b1111; // Rd 548 } 549 // register 550 def rr : T2I<(outs), (ins GPR:$lhs, rGPR:$rhs), iir, 551 opc, ".w\t$lhs, $rhs", 552 [(opnode GPR:$lhs, rGPR:$rhs)]> { 553 let Inst{31-27} = 0b11101; 554 let Inst{26-25} = 0b01; 555 let Inst{24-21} = opcod; 556 let Inst{20} = 1; // The S bit. 557 let Inst{14-12} = 0b000; // imm3 558 let Inst{11-8} = 0b1111; // Rd 559 let Inst{7-6} = 0b00; // imm2 560 let Inst{5-4} = 0b00; // type 561 } 562 // shifted register 563 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), iis, 564 opc, ".w\t$lhs, $rhs", 565 [(opnode GPR:$lhs, t2_so_reg:$rhs)]> { 566 let Inst{31-27} = 0b11101; 567 let Inst{26-25} = 0b01; 568 let Inst{24-21} = opcod; 569 let Inst{20} = 1; // The S bit. 570 let Inst{11-8} = 0b1111; // Rd 571 } 572} 573} 574 575/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 576multiclass T2I_ld<bit signed, bits<2> opcod, string opc, PatFrag opnode> { 577 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoadi, 578 opc, ".w\t$dst, $addr", 579 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]> { 580 let Inst{31-27} = 0b11111; 581 let Inst{26-25} = 0b00; 582 let Inst{24} = signed; 583 let Inst{23} = 1; 584 let Inst{22-21} = opcod; 585 let Inst{20} = 1; // load 586 } 587 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, 588 opc, "\t$dst, $addr", 589 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]> { 590 let Inst{31-27} = 0b11111; 591 let Inst{26-25} = 0b00; 592 let Inst{24} = signed; 593 let Inst{23} = 0; 594 let Inst{22-21} = opcod; 595 let Inst{20} = 1; // load 596 let Inst{11} = 1; 597 // Offset: index==TRUE, wback==FALSE 598 let Inst{10} = 1; // The P bit. 599 let Inst{8} = 0; // The W bit. 600 } 601 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoadr, 602 opc, ".w\t$dst, $addr", 603 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]> { 604 let Inst{31-27} = 0b11111; 605 let Inst{26-25} = 0b00; 606 let Inst{24} = signed; 607 let Inst{23} = 0; 608 let Inst{22-21} = opcod; 609 let Inst{20} = 1; // load 610 let Inst{11-6} = 0b000000; 611 } 612 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 613 opc, ".w\t$dst, $addr", 614 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]> { 615 let isReMaterializable = 1; 616 let Inst{31-27} = 0b11111; 617 let Inst{26-25} = 0b00; 618 let Inst{24} = signed; 619 let Inst{23} = ?; // add = (U == '1') 620 let Inst{22-21} = opcod; 621 let Inst{20} = 1; // load 622 let Inst{19-16} = 0b1111; // Rn 623 } 624} 625 626/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 627multiclass T2I_st<bits<2> opcod, string opc, PatFrag opnode> { 628 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStorei, 629 opc, ".w\t$src, $addr", 630 [(opnode GPR:$src, t2addrmode_imm12:$addr)]> { 631 let Inst{31-27} = 0b11111; 632 let Inst{26-23} = 0b0001; 633 let Inst{22-21} = opcod; 634 let Inst{20} = 0; // !load 635 } 636 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStorei, 637 opc, "\t$src, $addr", 638 [(opnode GPR:$src, t2addrmode_imm8:$addr)]> { 639 let Inst{31-27} = 0b11111; 640 let Inst{26-23} = 0b0000; 641 let Inst{22-21} = opcod; 642 let Inst{20} = 0; // !load 643 let Inst{11} = 1; 644 // Offset: index==TRUE, wback==FALSE 645 let Inst{10} = 1; // The P bit. 646 let Inst{8} = 0; // The W bit. 647 } 648 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStorer, 649 opc, ".w\t$src, $addr", 650 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]> { 651 let Inst{31-27} = 0b11111; 652 let Inst{26-23} = 0b0000; 653 let Inst{22-21} = opcod; 654 let Inst{20} = 0; // !load 655 let Inst{11-6} = 0b000000; 656 } 657} 658 659/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 660/// register and one whose operand is a register rotated by 8/16/24. 661multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> { 662 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 663 opc, ".w\t$dst, $src", 664 [(set rGPR:$dst, (opnode rGPR:$src))]> { 665 let Inst{31-27} = 0b11111; 666 let Inst{26-23} = 0b0100; 667 let Inst{22-20} = opcod; 668 let Inst{19-16} = 0b1111; // Rn 669 let Inst{15-12} = 0b1111; 670 let Inst{7} = 1; 671 let Inst{5-4} = 0b00; // rotate 672 } 673 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi, 674 opc, ".w\t$dst, $src, ror $rot", 675 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]> { 676 let Inst{31-27} = 0b11111; 677 let Inst{26-23} = 0b0100; 678 let Inst{22-20} = opcod; 679 let Inst{19-16} = 0b1111; // Rn 680 let Inst{15-12} = 0b1111; 681 let Inst{7} = 1; 682 let Inst{5-4} = {?,?}; // rotate 683 } 684} 685 686// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 687multiclass T2I_unary_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> { 688 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 689 opc, "\t$dst, $src", 690 [(set rGPR:$dst, (opnode rGPR:$src))]>, 691 Requires<[HasT2ExtractPack]> { 692 let Inst{31-27} = 0b11111; 693 let Inst{26-23} = 0b0100; 694 let Inst{22-20} = opcod; 695 let Inst{19-16} = 0b1111; // Rn 696 let Inst{15-12} = 0b1111; 697 let Inst{7} = 1; 698 let Inst{5-4} = 0b00; // rotate 699 } 700 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi, 701 opc, "\t$dst, $src, ror $rot", 702 [(set rGPR:$dst, (opnode (rotr rGPR:$src, rot_imm:$rot)))]>, 703 Requires<[HasT2ExtractPack]> { 704 let Inst{31-27} = 0b11111; 705 let Inst{26-23} = 0b0100; 706 let Inst{22-20} = opcod; 707 let Inst{19-16} = 0b1111; // Rn 708 let Inst{15-12} = 0b1111; 709 let Inst{7} = 1; 710 let Inst{5-4} = {?,?}; // rotate 711 } 712} 713 714// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 715// supported yet. 716multiclass T2I_unary_rrot_sxtb16<bits<3> opcod, string opc> { 717 def r : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 718 opc, "\t$dst, $src", []> { 719 let Inst{31-27} = 0b11111; 720 let Inst{26-23} = 0b0100; 721 let Inst{22-20} = opcod; 722 let Inst{19-16} = 0b1111; // Rn 723 let Inst{15-12} = 0b1111; 724 let Inst{7} = 1; 725 let Inst{5-4} = 0b00; // rotate 726 } 727 def r_rot : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$rot), IIC_iUNAsi, 728 opc, "\t$dst, $src, ror $rot", []> { 729 let Inst{31-27} = 0b11111; 730 let Inst{26-23} = 0b0100; 731 let Inst{22-20} = opcod; 732 let Inst{19-16} = 0b1111; // Rn 733 let Inst{15-12} = 0b1111; 734 let Inst{7} = 1; 735 let Inst{5-4} = {?,?}; // rotate 736 } 737} 738 739/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 740/// register and one whose operand is a register rotated by 8/16/24. 741multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> { 742 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iALUr, 743 opc, "\t$dst, $LHS, $RHS", 744 [(set rGPR:$dst, (opnode rGPR:$LHS, rGPR:$RHS))]>, 745 Requires<[HasT2ExtractPack]> { 746 let Inst{31-27} = 0b11111; 747 let Inst{26-23} = 0b0100; 748 let Inst{22-20} = opcod; 749 let Inst{15-12} = 0b1111; 750 let Inst{7} = 1; 751 let Inst{5-4} = 0b00; // rotate 752 } 753 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot), 754 IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", 755 [(set rGPR:$dst, (opnode rGPR:$LHS, 756 (rotr rGPR:$RHS, rot_imm:$rot)))]>, 757 Requires<[HasT2ExtractPack]> { 758 let Inst{31-27} = 0b11111; 759 let Inst{26-23} = 0b0100; 760 let Inst{22-20} = opcod; 761 let Inst{15-12} = 0b1111; 762 let Inst{7} = 1; 763 let Inst{5-4} = {?,?}; // rotate 764 } 765} 766 767// DO variant - disassembly only, no pattern 768 769multiclass T2I_bin_rrot_DO<bits<3> opcod, string opc> { 770 def rr : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS), IIC_iEXTAr, 771 opc, "\t$dst, $LHS, $RHS", []> { 772 let Inst{31-27} = 0b11111; 773 let Inst{26-23} = 0b0100; 774 let Inst{22-20} = opcod; 775 let Inst{15-12} = 0b1111; 776 let Inst{7} = 1; 777 let Inst{5-4} = 0b00; // rotate 778 } 779 def rr_rot : T2I<(outs rGPR:$dst), (ins rGPR:$LHS, rGPR:$RHS, i32imm:$rot), 780 IIC_iEXTAsr, opc, "\t$dst, $LHS, $RHS, ror $rot", []> { 781 let Inst{31-27} = 0b11111; 782 let Inst{26-23} = 0b0100; 783 let Inst{22-20} = opcod; 784 let Inst{15-12} = 0b1111; 785 let Inst{7} = 1; 786 let Inst{5-4} = {?,?}; // rotate 787 } 788} 789 790//===----------------------------------------------------------------------===// 791// Instructions 792//===----------------------------------------------------------------------===// 793 794//===----------------------------------------------------------------------===// 795// Miscellaneous Instructions. 796// 797 798// LEApcrel - Load a pc-relative address into a register without offending the 799// assembler. 800let neverHasSideEffects = 1 in { 801let isReMaterializable = 1 in 802def t2LEApcrel : T2XI<(outs rGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 803 "adr${p}.w\t$dst, #$label", []> { 804 let Inst{31-27} = 0b11110; 805 let Inst{25-24} = 0b10; 806 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 807 let Inst{22} = 0; 808 let Inst{20} = 0; 809 let Inst{19-16} = 0b1111; // Rn 810 let Inst{15} = 0; 811} 812} // neverHasSideEffects 813def t2LEApcrelJT : T2XI<(outs rGPR:$dst), 814 (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi, 815 "adr${p}.w\t$dst, #${label}_${id}", []> { 816 let Inst{31-27} = 0b11110; 817 let Inst{25-24} = 0b10; 818 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 819 let Inst{22} = 0; 820 let Inst{20} = 0; 821 let Inst{19-16} = 0b1111; // Rn 822 let Inst{15} = 0; 823} 824 825// ADD r, sp, {so_imm|i12} 826def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 827 IIC_iALUi, "add", ".w\t$dst, $sp, $imm", []> { 828 let Inst{31-27} = 0b11110; 829 let Inst{25} = 0; 830 let Inst{24-21} = 0b1000; 831 let Inst{20} = ?; // The S bit. 832 let Inst{19-16} = 0b1101; // Rn = sp 833 let Inst{15} = 0; 834} 835def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 836 IIC_iALUi, "addw", "\t$dst, $sp, $imm", []> { 837 let Inst{31-27} = 0b11110; 838 let Inst{25} = 1; 839 let Inst{24-21} = 0b0000; 840 let Inst{20} = 0; // The S bit. 841 let Inst{19-16} = 0b1101; // Rn = sp 842 let Inst{15} = 0; 843} 844 845// ADD r, sp, so_reg 846def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 847 IIC_iALUsi, "add", ".w\t$dst, $sp, $rhs", []> { 848 let Inst{31-27} = 0b11101; 849 let Inst{26-25} = 0b01; 850 let Inst{24-21} = 0b1000; 851 let Inst{20} = ?; // The S bit. 852 let Inst{19-16} = 0b1101; // Rn = sp 853 let Inst{15} = 0; 854} 855 856// SUB r, sp, {so_imm|i12} 857def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 858 IIC_iALUi, "sub", ".w\t$dst, $sp, $imm", []> { 859 let Inst{31-27} = 0b11110; 860 let Inst{25} = 0; 861 let Inst{24-21} = 0b1101; 862 let Inst{20} = ?; // The S bit. 863 let Inst{19-16} = 0b1101; // Rn = sp 864 let Inst{15} = 0; 865} 866def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), 867 IIC_iALUi, "subw", "\t$dst, $sp, $imm", []> { 868 let Inst{31-27} = 0b11110; 869 let Inst{25} = 1; 870 let Inst{24-21} = 0b0101; 871 let Inst{20} = 0; // The S bit. 872 let Inst{19-16} = 0b1101; // Rn = sp 873 let Inst{15} = 0; 874} 875 876// SUB r, sp, so_reg 877def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 878 IIC_iALUsi, 879 "sub", "\t$dst, $sp, $rhs", []> { 880 let Inst{31-27} = 0b11101; 881 let Inst{26-25} = 0b01; 882 let Inst{24-21} = 0b1101; 883 let Inst{20} = ?; // The S bit. 884 let Inst{19-16} = 0b1101; // Rn = sp 885 let Inst{15} = 0; 886} 887 888// Signed and unsigned division on v7-M 889def t2SDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi, 890 "sdiv", "\t$dst, $a, $b", 891 [(set rGPR:$dst, (sdiv rGPR:$a, rGPR:$b))]>, 892 Requires<[HasDivide]> { 893 let Inst{31-27} = 0b11111; 894 let Inst{26-21} = 0b011100; 895 let Inst{20} = 0b1; 896 let Inst{15-12} = 0b1111; 897 let Inst{7-4} = 0b1111; 898} 899 900def t2UDIV : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iALUi, 901 "udiv", "\t$dst, $a, $b", 902 [(set rGPR:$dst, (udiv rGPR:$a, rGPR:$b))]>, 903 Requires<[HasDivide]> { 904 let Inst{31-27} = 0b11111; 905 let Inst{26-21} = 0b011101; 906 let Inst{20} = 0b1; 907 let Inst{15-12} = 0b1111; 908 let Inst{7-4} = 0b1111; 909} 910 911//===----------------------------------------------------------------------===// 912// Load / store Instructions. 913// 914 915// Load 916let canFoldAsLoad = 1, isReMaterializable = 1 in 917defm t2LDR : T2I_ld<0, 0b10, "ldr", UnOpFrag<(load node:$Src)>>; 918 919// Loads with zero extension 920defm t2LDRH : T2I_ld<0, 0b01, "ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 921defm t2LDRB : T2I_ld<0, 0b00, "ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 922 923// Loads with sign extension 924defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 925defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 926 927let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 928// Load doubleword 929def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2), 930 (ins t2addrmode_imm8s4:$addr), 931 IIC_iLoadi, "ldrd", "\t$dst1, $addr", []>; 932def t2LDRDpci : T2Ii8s4<1, 0, 1, (outs rGPR:$dst1, rGPR:$dst2), 933 (ins i32imm:$addr), IIC_iLoadi, 934 "ldrd", "\t$dst1, $addr", []> { 935 let Inst{19-16} = 0b1111; // Rn 936} 937} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 938 939// zextload i1 -> zextload i8 940def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 941 (t2LDRBi12 t2addrmode_imm12:$addr)>; 942def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 943 (t2LDRBi8 t2addrmode_imm8:$addr)>; 944def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 945 (t2LDRBs t2addrmode_so_reg:$addr)>; 946def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 947 (t2LDRBpci tconstpool:$addr)>; 948 949// extload -> zextload 950// FIXME: Reduce the number of patterns by legalizing extload to zextload 951// earlier? 952def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 953 (t2LDRBi12 t2addrmode_imm12:$addr)>; 954def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 955 (t2LDRBi8 t2addrmode_imm8:$addr)>; 956def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 957 (t2LDRBs t2addrmode_so_reg:$addr)>; 958def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 959 (t2LDRBpci tconstpool:$addr)>; 960 961def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 962 (t2LDRBi12 t2addrmode_imm12:$addr)>; 963def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 964 (t2LDRBi8 t2addrmode_imm8:$addr)>; 965def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 966 (t2LDRBs t2addrmode_so_reg:$addr)>; 967def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 968 (t2LDRBpci tconstpool:$addr)>; 969 970def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 971 (t2LDRHi12 t2addrmode_imm12:$addr)>; 972def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 973 (t2LDRHi8 t2addrmode_imm8:$addr)>; 974def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 975 (t2LDRHs t2addrmode_so_reg:$addr)>; 976def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 977 (t2LDRHpci tconstpool:$addr)>; 978 979// FIXME: The destination register of the loads and stores can't be PC, but 980// can be SP. We need another regclass (similar to rGPR) to represent 981// that. Not a pressing issue since these are selected manually, 982// not via pattern. 983 984// Indexed loads 985let mayLoad = 1, neverHasSideEffects = 1 in { 986def t2LDR_PRE : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$dst, GPR:$base_wb), 987 (ins t2addrmode_imm8:$addr), 988 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 989 "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", 990 []>; 991 992def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$dst, GPR:$base_wb), 993 (ins GPR:$base, t2am_imm8_offset:$offset), 994 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 995 "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", 996 []>; 997 998def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 999 (ins t2addrmode_imm8:$addr), 1000 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1001 "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", 1002 []>; 1003def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1004 (ins GPR:$base, t2am_imm8_offset:$offset), 1005 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1006 "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", 1007 []>; 1008 1009def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1010 (ins t2addrmode_imm8:$addr), 1011 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1012 "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", 1013 []>; 1014def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1015 (ins GPR:$base, t2am_imm8_offset:$offset), 1016 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1017 "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", 1018 []>; 1019 1020def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1021 (ins t2addrmode_imm8:$addr), 1022 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1023 "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", 1024 []>; 1025def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1026 (ins GPR:$base, t2am_imm8_offset:$offset), 1027 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1028 "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", 1029 []>; 1030 1031def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$dst, GPR:$base_wb), 1032 (ins t2addrmode_imm8:$addr), 1033 AddrModeT2_i8, IndexModePre, IIC_iLoadiu, 1034 "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", 1035 []>; 1036def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$base_wb), 1037 (ins GPR:$base, t2am_imm8_offset:$offset), 1038 AddrModeT2_i8, IndexModePost, IIC_iLoadiu, 1039 "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", 1040 []>; 1041} // mayLoad = 1, neverHasSideEffects = 1 1042 1043// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are 1044// for disassembly only. 1045// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1046class T2IldT<bit signed, bits<2> type, string opc> 1047 : T2Ii8<(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoadi, opc, 1048 "\t$dst, $addr", []> { 1049 let Inst{31-27} = 0b11111; 1050 let Inst{26-25} = 0b00; 1051 let Inst{24} = signed; 1052 let Inst{23} = 0; 1053 let Inst{22-21} = type; 1054 let Inst{20} = 1; // load 1055 let Inst{11} = 1; 1056 let Inst{10-8} = 0b110; // PUW. 1057} 1058 1059def t2LDRT : T2IldT<0, 0b10, "ldrt">; 1060def t2LDRBT : T2IldT<0, 0b00, "ldrbt">; 1061def t2LDRHT : T2IldT<0, 0b01, "ldrht">; 1062def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt">; 1063def t2LDRSHT : T2IldT<1, 0b01, "ldrsht">; 1064 1065// Store 1066defm t2STR :T2I_st<0b10,"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 1067defm t2STRB:T2I_st<0b00,"strb",BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1068defm t2STRH:T2I_st<0b01,"strh",BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1069 1070// Store doubleword 1071let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1072def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1073 (ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr), 1074 IIC_iStorer, "strd", "\t$src1, $addr", []>; 1075 1076// Indexed stores 1077def t2STR_PRE : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb), 1078 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1079 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1080 "str", "\t$src, [$base, $offset]!", "$base = $base_wb", 1081 [(set GPR:$base_wb, 1082 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1083 1084def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb), 1085 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1086 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1087 "str", "\t$src, [$base], $offset", "$base = $base_wb", 1088 [(set GPR:$base_wb, 1089 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1090 1091def t2STRH_PRE : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb), 1092 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1093 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1094 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb", 1095 [(set GPR:$base_wb, 1096 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1097 1098def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb), 1099 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1100 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1101 "strh", "\t$src, [$base], $offset", "$base = $base_wb", 1102 [(set GPR:$base_wb, 1103 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1104 1105def t2STRB_PRE : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb), 1106 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1107 AddrModeT2_i8, IndexModePre, IIC_iStoreiu, 1108 "strb", "\t$src, [$base, $offset]!", "$base = $base_wb", 1109 [(set GPR:$base_wb, 1110 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1111 1112def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb), 1113 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 1114 AddrModeT2_i8, IndexModePost, IIC_iStoreiu, 1115 "strb", "\t$src, [$base], $offset", "$base = $base_wb", 1116 [(set GPR:$base_wb, 1117 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 1118 1119// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1120// only. 1121// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1122class T2IstT<bits<2> type, string opc> 1123 : T2Ii8<(outs GPR:$src), (ins t2addrmode_imm8:$addr), IIC_iStorei, opc, 1124 "\t$src, $addr", []> { 1125 let Inst{31-27} = 0b11111; 1126 let Inst{26-25} = 0b00; 1127 let Inst{24} = 0; // not signed 1128 let Inst{23} = 0; 1129 let Inst{22-21} = type; 1130 let Inst{20} = 0; // store 1131 let Inst{11} = 1; 1132 let Inst{10-8} = 0b110; // PUW 1133} 1134 1135def t2STRT : T2IstT<0b10, "strt">; 1136def t2STRBT : T2IstT<0b00, "strbt">; 1137def t2STRHT : T2IstT<0b01, "strht">; 1138 1139// ldrd / strd pre / post variants 1140// For disassembly only. 1141 1142def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1143 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1144 "ldrd", "\t$dst1, $dst2, [$base, $imm]!", []>; 1145 1146def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$dst1, GPR:$dst2), 1147 (ins GPR:$base, t2am_imm8s4_offset:$imm), NoItinerary, 1148 "ldrd", "\t$dst1, $dst2, [$base], $imm", []>; 1149 1150def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs), 1151 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1152 NoItinerary, "strd", "\t$src1, $src2, [$base, $imm]!", []>; 1153 1154def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs), 1155 (ins GPR:$src1, GPR:$src2, GPR:$base, t2am_imm8s4_offset:$imm), 1156 NoItinerary, "strd", "\t$src1, $src2, [$base], $imm", []>; 1157 1158// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1159// data/instruction access. These are for disassembly only. 1160// 1161// A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0. 1162// The neg_zero operand translates -0 to -1, -1 to -2, ..., etc. 1163multiclass T2Ipl<bit instr, bit write, string opc> { 1164 1165 def i12 : T2I<(outs), (ins GPR:$base, i32imm:$imm), IIC_iLoadi, opc, 1166 "\t[$base, $imm]", []> { 1167 let Inst{31-25} = 0b1111100; 1168 let Inst{24} = instr; 1169 let Inst{23} = 1; // U = 1 1170 let Inst{22} = 0; 1171 let Inst{21} = write; 1172 let Inst{20} = 1; 1173 let Inst{15-12} = 0b1111; 1174 } 1175 1176 def i8 : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1177 "\t[$base, $imm]", []> { 1178 let Inst{31-25} = 0b1111100; 1179 let Inst{24} = instr; 1180 let Inst{23} = 0; // U = 0 1181 let Inst{22} = 0; 1182 let Inst{21} = write; 1183 let Inst{20} = 1; 1184 let Inst{15-12} = 0b1111; 1185 let Inst{11-8} = 0b1100; 1186 } 1187 1188 def pci : T2I<(outs), (ins GPR:$base, neg_zero:$imm), IIC_iLoadi, opc, 1189 "\t[pc, $imm]", []> { 1190 let Inst{31-25} = 0b1111100; 1191 let Inst{24} = instr; 1192 let Inst{23} = ?; // add = (U == 1) 1193 let Inst{22} = 0; 1194 let Inst{21} = write; 1195 let Inst{20} = 1; 1196 let Inst{19-16} = 0b1111; // Rn = 0b1111 1197 let Inst{15-12} = 0b1111; 1198 } 1199 1200 def r : T2I<(outs), (ins GPR:$base, GPR:$a), IIC_iLoadi, opc, 1201 "\t[$base, $a]", []> { 1202 let Inst{31-25} = 0b1111100; 1203 let Inst{24} = instr; 1204 let Inst{23} = 0; // add = TRUE for T1 1205 let Inst{22} = 0; 1206 let Inst{21} = write; 1207 let Inst{20} = 1; 1208 let Inst{15-12} = 0b1111; 1209 let Inst{11-6} = 0000000; 1210 let Inst{5-4} = 0b00; // no shift is applied 1211 } 1212 1213 def s : T2I<(outs), (ins GPR:$base, GPR:$a, i32imm:$shamt), IIC_iLoadi, opc, 1214 "\t[$base, $a, lsl $shamt]", []> { 1215 let Inst{31-25} = 0b1111100; 1216 let Inst{24} = instr; 1217 let Inst{23} = 0; // add = TRUE for T1 1218 let Inst{22} = 0; 1219 let Inst{21} = write; 1220 let Inst{20} = 1; 1221 let Inst{15-12} = 0b1111; 1222 let Inst{11-6} = 0000000; 1223 } 1224} 1225 1226defm t2PLD : T2Ipl<0, 0, "pld">; 1227defm t2PLDW : T2Ipl<0, 1, "pldw">; 1228defm t2PLI : T2Ipl<1, 0, "pli">; 1229 1230//===----------------------------------------------------------------------===// 1231// Load / store multiple Instructions. 1232// 1233 1234let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1235def t2LDM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1236 reglist:$dsts, variable_ops), IIC_iLoadm, 1237 "ldm${addr:submode}${p}${addr:wide}\t$addr, $dsts", []> { 1238 let Inst{31-27} = 0b11101; 1239 let Inst{26-25} = 0b00; 1240 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1241 let Inst{22} = 0; 1242 let Inst{21} = 0; // The W bit. 1243 let Inst{20} = 1; // Load 1244} 1245 1246def t2LDM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1247 reglist:$dsts, variable_ops), IIC_iLoadm, 1248 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", 1249 "$addr.addr = $wb", []> { 1250 let Inst{31-27} = 0b11101; 1251 let Inst{26-25} = 0b00; 1252 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1253 let Inst{22} = 0; 1254 let Inst{21} = 1; // The W bit. 1255 let Inst{20} = 1; // Load 1256} 1257} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq 1258 1259let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 1260def t2STM : T2XI<(outs), (ins addrmode4:$addr, pred:$p, 1261 reglist:$srcs, variable_ops), IIC_iStorem, 1262 "stm${addr:submode}${p}${addr:wide}\t$addr, $srcs", []> { 1263 let Inst{31-27} = 0b11101; 1264 let Inst{26-25} = 0b00; 1265 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1266 let Inst{22} = 0; 1267 let Inst{21} = 0; // The W bit. 1268 let Inst{20} = 0; // Store 1269} 1270 1271def t2STM_UPD : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 1272 reglist:$srcs, variable_ops), 1273 IIC_iStorem, 1274 "stm${addr:submode}${p}${addr:wide}\t$addr!, $srcs", 1275 "$addr.addr = $wb", []> { 1276 let Inst{31-27} = 0b11101; 1277 let Inst{26-25} = 0b00; 1278 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 1279 let Inst{22} = 0; 1280 let Inst{21} = 1; // The W bit. 1281 let Inst{20} = 0; // Store 1282} 1283} // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq 1284 1285//===----------------------------------------------------------------------===// 1286// Move Instructions. 1287// 1288 1289let neverHasSideEffects = 1 in 1290def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 1291 "mov", ".w\t$dst, $src", []> { 1292 let Inst{31-27} = 0b11101; 1293 let Inst{26-25} = 0b01; 1294 let Inst{24-21} = 0b0010; 1295 let Inst{20} = ?; // The S bit. 1296 let Inst{19-16} = 0b1111; // Rn 1297 let Inst{14-12} = 0b000; 1298 let Inst{7-4} = 0b0000; 1299} 1300 1301// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1302let isReMaterializable = 1, isAsCheapAsAMove = 1, AddedComplexity = 1 in 1303def t2MOVi : T2sI<(outs rGPR:$dst), (ins t2_so_imm:$src), IIC_iMOVi, 1304 "mov", ".w\t$dst, $src", 1305 [(set rGPR:$dst, t2_so_imm:$src)]> { 1306 let Inst{31-27} = 0b11110; 1307 let Inst{25} = 0; 1308 let Inst{24-21} = 0b0010; 1309 let Inst{20} = ?; // The S bit. 1310 let Inst{19-16} = 0b1111; // Rn 1311 let Inst{15} = 0; 1312} 1313 1314let isReMaterializable = 1, isAsCheapAsAMove = 1 in 1315def t2MOVi16 : T2I<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVi, 1316 "movw", "\t$dst, $src", 1317 [(set rGPR:$dst, imm0_65535:$src)]> { 1318 let Inst{31-27} = 0b11110; 1319 let Inst{25} = 1; 1320 let Inst{24-21} = 0b0010; 1321 let Inst{20} = 0; // The S bit. 1322 let Inst{15} = 0; 1323} 1324 1325let Constraints = "$src = $dst" in 1326def t2MOVTi16 : T2I<(outs rGPR:$dst), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi, 1327 "movt", "\t$dst, $imm", 1328 [(set rGPR:$dst, 1329 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { 1330 let Inst{31-27} = 0b11110; 1331 let Inst{25} = 1; 1332 let Inst{24-21} = 0b0110; 1333 let Inst{20} = 0; // The S bit. 1334 let Inst{15} = 0; 1335} 1336 1337def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1338 1339//===----------------------------------------------------------------------===// 1340// Extend Instructions. 1341// 1342 1343// Sign extenders 1344 1345defm t2SXTB : T2I_unary_rrot<0b100, "sxtb", 1346 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1347defm t2SXTH : T2I_unary_rrot<0b000, "sxth", 1348 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1349defm t2SXTB16 : T2I_unary_rrot_sxtb16<0b010, "sxtb16">; 1350 1351defm t2SXTAB : T2I_bin_rrot<0b100, "sxtab", 1352 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1353defm t2SXTAH : T2I_bin_rrot<0b000, "sxtah", 1354 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1355defm t2SXTAB16 : T2I_bin_rrot_DO<0b010, "sxtab16">; 1356 1357// TODO: SXT(A){B|H}16 - done for disassembly only 1358 1359// Zero extenders 1360 1361let AddedComplexity = 16 in { 1362defm t2UXTB : T2I_unary_rrot<0b101, "uxtb", 1363 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1364defm t2UXTH : T2I_unary_rrot<0b001, "uxth", 1365 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1366defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16", 1367 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1368 1369// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1370// The transformation should probably be done as a combiner action 1371// instead so we can include a check for masking back in the upper 1372// eight bits of the source into the lower eight bits of the result. 1373//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 1374// (t2UXTB16r_rot rGPR:$Src, 24)>, Requires<[HasT2ExtractPack]>; 1375def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 1376 (t2UXTB16r_rot rGPR:$Src, 8)>, Requires<[HasT2ExtractPack]>; 1377 1378defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab", 1379 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1380defm t2UXTAH : T2I_bin_rrot<0b001, "uxtah", 1381 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1382defm t2UXTAB16 : T2I_bin_rrot_DO<0b011, "uxtab16">; 1383} 1384 1385//===----------------------------------------------------------------------===// 1386// Arithmetic Instructions. 1387// 1388 1389defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1390 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1391defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1392 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1393 1394// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1395defm t2ADDS : T2I_bin_s_irs <0b1000, "add", 1396 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1397 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 1398defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", 1399 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1400 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1401 1402defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1403 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>; 1404defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1405 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; 1406defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc", 1407 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; 1408defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc", 1409 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>; 1410 1411// RSB 1412defm t2RSB : T2I_rbin_irs <0b1110, "rsb", 1413 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1414defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", 1415 BinOpFrag<(subc node:$LHS, node:$RHS)>>; 1416 1417// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1418// The assume-no-carry-in form uses the negation of the input since add/sub 1419// assume opposite meanings of the carry flag (i.e., carry == !borrow). 1420// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 1421// details. 1422// The AddedComplexity preferences the first variant over the others since 1423// it can be shrunk to a 16-bit wide encoding, while the others cannot. 1424let AddedComplexity = 1 in 1425def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1426 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1427def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1428 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1429def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1430 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1431let AddedComplexity = 1 in 1432def : T2Pat<(addc rGPR:$src, imm0_255_neg:$imm), 1433 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; 1434def : T2Pat<(addc rGPR:$src, t2_so_imm_neg:$imm), 1435 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 1436// The with-carry-in form matches bitwise not instead of the negation. 1437// Effectively, the inverse interpretation of the carry flag already accounts 1438// for part of the negation. 1439let AddedComplexity = 1 in 1440def : T2Pat<(adde rGPR:$src, imm0_255_not:$imm), 1441 (t2SBCSri rGPR:$src, imm0_255_not:$imm)>; 1442def : T2Pat<(adde rGPR:$src, t2_so_imm_not:$imm), 1443 (t2SBCSri rGPR:$src, t2_so_imm_not:$imm)>; 1444 1445// Select Bytes -- for disassembly only 1446 1447def t2SEL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), NoItinerary, "sel", 1448 "\t$dst, $a, $b", []> { 1449 let Inst{31-27} = 0b11111; 1450 let Inst{26-24} = 0b010; 1451 let Inst{23} = 0b1; 1452 let Inst{22-20} = 0b010; 1453 let Inst{15-12} = 0b1111; 1454 let Inst{7} = 0b1; 1455 let Inst{6-4} = 0b000; 1456} 1457 1458// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1459// And Miscellaneous operations -- for disassembly only 1460class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 1461 list<dag> pat = [/* For disassembly only; pattern left blank */]> 1462 : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), NoItinerary, opc, 1463 "\t$dst, $a, $b", pat> { 1464 let Inst{31-27} = 0b11111; 1465 let Inst{26-23} = 0b0101; 1466 let Inst{22-20} = op22_20; 1467 let Inst{15-12} = 0b1111; 1468 let Inst{7-4} = op7_4; 1469} 1470 1471// Saturating add/subtract -- for disassembly only 1472 1473def t2QADD : T2I_pam<0b000, 0b1000, "qadd", 1474 [(set rGPR:$dst, (int_arm_qadd rGPR:$a, rGPR:$b))]>; 1475def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1476def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1477def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1478def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd">; 1479def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub">; 1480def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1481def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", 1482 [(set rGPR:$dst, (int_arm_qsub rGPR:$a, rGPR:$b))]>; 1483def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1484def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1485def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1486def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1487def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1488def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1489def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1490def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1491 1492// Signed/Unsigned add/subtract -- for disassembly only 1493 1494def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1495def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1496def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1497def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1498def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1499def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1500def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1501def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 1502def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 1503def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 1504def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 1505def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 1506 1507// Signed/Unsigned halving add/subtract -- for disassembly only 1508 1509def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1510def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 1511def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 1512def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 1513def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 1514def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 1515def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 1516def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 1517def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 1518def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 1519def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 1520def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 1521 1522// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only 1523 1524def t2USAD8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst), 1525 (ins rGPR:$a, rGPR:$b), 1526 NoItinerary, "usad8", "\t$dst, $a, $b", []> { 1527 let Inst{15-12} = 0b1111; 1528} 1529def t2USADA8 : T2I_mac<0, 0b111, 0b0000, (outs rGPR:$dst), 1530 (ins rGPR:$a, rGPR:$b, rGPR:$acc), NoItinerary, "usada8", 1531 "\t$dst, $a, $b, $acc", []>; 1532 1533// Signed/Unsigned saturate -- for disassembly only 1534 1535def t2SSAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh), 1536 NoItinerary, "ssat", "\t$dst, $bit_pos, $a$sh", 1537 [/* For disassembly only; pattern left blank */]> { 1538 let Inst{31-27} = 0b11110; 1539 let Inst{25-22} = 0b1100; 1540 let Inst{20} = 0; 1541 let Inst{15} = 0; 1542} 1543 1544def t2SSAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary, 1545 "ssat16", "\t$dst, $bit_pos, $a", 1546 [/* For disassembly only; pattern left blank */]> { 1547 let Inst{31-27} = 0b11110; 1548 let Inst{25-22} = 0b1100; 1549 let Inst{20} = 0; 1550 let Inst{15} = 0; 1551 let Inst{21} = 1; // sh = '1' 1552 let Inst{14-12} = 0b000; // imm3 = '000' 1553 let Inst{7-6} = 0b00; // imm2 = '00' 1554} 1555 1556def t2USAT: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a, shift_imm:$sh), 1557 NoItinerary, "usat", "\t$dst, $bit_pos, $a$sh", 1558 [/* For disassembly only; pattern left blank */]> { 1559 let Inst{31-27} = 0b11110; 1560 let Inst{25-22} = 0b1110; 1561 let Inst{20} = 0; 1562 let Inst{15} = 0; 1563} 1564 1565def t2USAT16: T2I<(outs rGPR:$dst), (ins i32imm:$bit_pos, rGPR:$a), NoItinerary, 1566 "usat16", "\t$dst, $bit_pos, $a", 1567 [/* For disassembly only; pattern left blank */]> { 1568 let Inst{31-27} = 0b11110; 1569 let Inst{25-22} = 0b1110; 1570 let Inst{20} = 0; 1571 let Inst{15} = 0; 1572 let Inst{21} = 1; // sh = '1' 1573 let Inst{14-12} = 0b000; // imm3 = '000' 1574 let Inst{7-6} = 0b00; // imm2 = '00' 1575} 1576 1577def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>; 1578def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>; 1579 1580//===----------------------------------------------------------------------===// 1581// Shift and rotate Instructions. 1582// 1583 1584defm t2LSL : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 1585defm t2LSR : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 1586defm t2ASR : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 1587defm t2ROR : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 1588 1589let Uses = [CPSR] in { 1590def t2MOVrx : T2sI<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi, 1591 "rrx", "\t$dst, $src", 1592 [(set rGPR:$dst, (ARMrrx rGPR:$src))]> { 1593 let Inst{31-27} = 0b11101; 1594 let Inst{26-25} = 0b01; 1595 let Inst{24-21} = 0b0010; 1596 let Inst{20} = ?; // The S bit. 1597 let Inst{19-16} = 0b1111; // Rn 1598 let Inst{14-12} = 0b000; 1599 let Inst{7-4} = 0b0011; 1600} 1601} 1602 1603let Defs = [CPSR] in { 1604def t2MOVsrl_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi, 1605 "lsrs", ".w\t$dst, $src, #1", 1606 [(set rGPR:$dst, (ARMsrl_flag rGPR:$src))]> { 1607 let Inst{31-27} = 0b11101; 1608 let Inst{26-25} = 0b01; 1609 let Inst{24-21} = 0b0010; 1610 let Inst{20} = 1; // The S bit. 1611 let Inst{19-16} = 0b1111; // Rn 1612 let Inst{5-4} = 0b01; // Shift type. 1613 // Shift amount = Inst{14-12:7-6} = 1. 1614 let Inst{14-12} = 0b000; 1615 let Inst{7-6} = 0b01; 1616} 1617def t2MOVsra_flag : T2I<(outs rGPR:$dst), (ins rGPR:$src), IIC_iMOVsi, 1618 "asrs", ".w\t$dst, $src, #1", 1619 [(set rGPR:$dst, (ARMsra_flag rGPR:$src))]> { 1620 let Inst{31-27} = 0b11101; 1621 let Inst{26-25} = 0b01; 1622 let Inst{24-21} = 0b0010; 1623 let Inst{20} = 1; // The S bit. 1624 let Inst{19-16} = 0b1111; // Rn 1625 let Inst{5-4} = 0b10; // Shift type. 1626 // Shift amount = Inst{14-12:7-6} = 1. 1627 let Inst{14-12} = 0b000; 1628 let Inst{7-6} = 0b01; 1629} 1630} 1631 1632//===----------------------------------------------------------------------===// 1633// Bitwise Instructions. 1634// 1635 1636defm t2AND : T2I_bin_w_irs<0b0000, "and", 1637 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1638 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 1639defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 1640 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1641 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 1642defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 1643 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1644 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 1645 1646defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 1647 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1648 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 1649 1650defm t2ANDS : T2I_bin_s_irs<0b0000, "and", 1651 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1652 BinOpFrag<(ARMand node:$LHS, node:$RHS)>, 1>; 1653 1654let Constraints = "$src = $dst" in 1655def t2BFC : T2I<(outs rGPR:$dst), (ins rGPR:$src, bf_inv_mask_imm:$imm), 1656 IIC_iUNAsi, "bfc", "\t$dst, $imm", 1657 [(set rGPR:$dst, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 1658 let Inst{31-27} = 0b11110; 1659 let Inst{25} = 1; 1660 let Inst{24-20} = 0b10110; 1661 let Inst{19-16} = 0b1111; // Rn 1662 let Inst{15} = 0; 1663} 1664 1665def t2SBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), 1666 IIC_iBITi, "sbfx", "\t$dst, $src, $lsb, $width", []> { 1667 let Inst{31-27} = 0b11110; 1668 let Inst{25} = 1; 1669 let Inst{24-20} = 0b10100; 1670 let Inst{15} = 0; 1671} 1672 1673def t2UBFX: T2I<(outs rGPR:$dst), (ins rGPR:$src, imm0_31:$lsb, imm0_31:$width), 1674 IIC_iBITi, "ubfx", "\t$dst, $src, $lsb, $width", []> { 1675 let Inst{31-27} = 0b11110; 1676 let Inst{25} = 1; 1677 let Inst{24-20} = 0b11100; 1678 let Inst{15} = 0; 1679} 1680 1681// A8.6.18 BFI - Bitfield insert (Encoding T1) 1682let Constraints = "$src = $dst" in 1683def t2BFI : T2I<(outs rGPR:$dst), 1684 (ins rGPR:$src, rGPR:$val, bf_inv_mask_imm:$imm), 1685 IIC_iBITi, "bfi", "\t$dst, $val, $imm", 1686 [(set rGPR:$dst, (ARMbfi rGPR:$src, rGPR:$val, 1687 bf_inv_mask_imm:$imm))]> { 1688 let Inst{31-27} = 0b11110; 1689 let Inst{25} = 1; 1690 let Inst{24-20} = 0b10110; 1691 let Inst{15} = 0; 1692} 1693 1694defm t2ORN : T2I_bin_irs<0b0011, "orn", 1695 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 1696 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; 1697 1698// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 1699let AddedComplexity = 1 in 1700defm t2MVN : T2I_un_irs <0b0011, "mvn", 1701 IIC_iMOVi, IIC_iMOVr, IIC_iMOVsi, 1702 UnOpFrag<(not node:$Src)>, 1, 1>; 1703 1704 1705let AddedComplexity = 1 in 1706def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 1707 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 1708 1709// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 1710def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 1711 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 1712 Requires<[IsThumb2]>; 1713 1714def : T2Pat<(t2_so_imm_not:$src), 1715 (t2MVNi t2_so_imm_not:$src)>; 1716 1717//===----------------------------------------------------------------------===// 1718// Multiply Instructions. 1719// 1720let isCommutable = 1 in 1721def t2MUL: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1722 "mul", "\t$dst, $a, $b", 1723 [(set rGPR:$dst, (mul rGPR:$a, rGPR:$b))]> { 1724 let Inst{31-27} = 0b11111; 1725 let Inst{26-23} = 0b0110; 1726 let Inst{22-20} = 0b000; 1727 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1728 let Inst{7-4} = 0b0000; // Multiply 1729} 1730 1731def t2MLA: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1732 "mla", "\t$dst, $a, $b, $c", 1733 [(set rGPR:$dst, (add (mul rGPR:$a, rGPR:$b), rGPR:$c))]> { 1734 let Inst{31-27} = 0b11111; 1735 let Inst{26-23} = 0b0110; 1736 let Inst{22-20} = 0b000; 1737 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1738 let Inst{7-4} = 0b0000; // Multiply 1739} 1740 1741def t2MLS: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1742 "mls", "\t$dst, $a, $b, $c", 1743 [(set rGPR:$dst, (sub rGPR:$c, (mul rGPR:$a, rGPR:$b)))]> { 1744 let Inst{31-27} = 0b11111; 1745 let Inst{26-23} = 0b0110; 1746 let Inst{22-20} = 0b000; 1747 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1748 let Inst{7-4} = 0b0001; // Multiply and Subtract 1749} 1750 1751// Extra precision multiplies with low / high results 1752let neverHasSideEffects = 1 in { 1753let isCommutable = 1 in { 1754def t2SMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), 1755 (ins rGPR:$a, rGPR:$b), IIC_iMUL64, 1756 "smull", "\t$ldst, $hdst, $a, $b", []> { 1757 let Inst{31-27} = 0b11111; 1758 let Inst{26-23} = 0b0111; 1759 let Inst{22-20} = 0b000; 1760 let Inst{7-4} = 0b0000; 1761} 1762 1763def t2UMULL : T2I<(outs rGPR:$ldst, rGPR:$hdst), 1764 (ins rGPR:$a, rGPR:$b), IIC_iMUL64, 1765 "umull", "\t$ldst, $hdst, $a, $b", []> { 1766 let Inst{31-27} = 0b11111; 1767 let Inst{26-23} = 0b0111; 1768 let Inst{22-20} = 0b010; 1769 let Inst{7-4} = 0b0000; 1770} 1771} // isCommutable 1772 1773// Multiply + accumulate 1774def t2SMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), 1775 (ins rGPR:$a, rGPR:$b), IIC_iMAC64, 1776 "smlal", "\t$ldst, $hdst, $a, $b", []>{ 1777 let Inst{31-27} = 0b11111; 1778 let Inst{26-23} = 0b0111; 1779 let Inst{22-20} = 0b100; 1780 let Inst{7-4} = 0b0000; 1781} 1782 1783def t2UMLAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), 1784 (ins rGPR:$a, rGPR:$b), IIC_iMAC64, 1785 "umlal", "\t$ldst, $hdst, $a, $b", []>{ 1786 let Inst{31-27} = 0b11111; 1787 let Inst{26-23} = 0b0111; 1788 let Inst{22-20} = 0b110; 1789 let Inst{7-4} = 0b0000; 1790} 1791 1792def t2UMAAL : T2I<(outs rGPR:$ldst, rGPR:$hdst), 1793 (ins rGPR:$a, rGPR:$b), IIC_iMAC64, 1794 "umaal", "\t$ldst, $hdst, $a, $b", []>{ 1795 let Inst{31-27} = 0b11111; 1796 let Inst{26-23} = 0b0111; 1797 let Inst{22-20} = 0b110; 1798 let Inst{7-4} = 0b0110; 1799} 1800} // neverHasSideEffects 1801 1802// Rounding variants of the below included for disassembly only 1803 1804// Most significant word multiply 1805def t2SMMUL : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1806 "smmul", "\t$dst, $a, $b", 1807 [(set rGPR:$dst, (mulhs rGPR:$a, rGPR:$b))]> { 1808 let Inst{31-27} = 0b11111; 1809 let Inst{26-23} = 0b0110; 1810 let Inst{22-20} = 0b101; 1811 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1812 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1813} 1814 1815def t2SMMULR : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1816 "smmulr", "\t$dst, $a, $b", []> { 1817 let Inst{31-27} = 0b11111; 1818 let Inst{26-23} = 0b0110; 1819 let Inst{22-20} = 0b101; 1820 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1821 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1822} 1823 1824def t2SMMLA : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1825 "smmla", "\t$dst, $a, $b, $c", 1826 [(set rGPR:$dst, (add (mulhs rGPR:$a, rGPR:$b), rGPR:$c))]> { 1827 let Inst{31-27} = 0b11111; 1828 let Inst{26-23} = 0b0110; 1829 let Inst{22-20} = 0b101; 1830 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1831 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1832} 1833 1834def t2SMMLAR: T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1835 "smmlar", "\t$dst, $a, $b, $c", []> { 1836 let Inst{31-27} = 0b11111; 1837 let Inst{26-23} = 0b0110; 1838 let Inst{22-20} = 0b101; 1839 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1840 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1841} 1842 1843def t2SMMLS: T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1844 "smmls", "\t$dst, $a, $b, $c", 1845 [(set rGPR:$dst, (sub rGPR:$c, (mulhs rGPR:$a, rGPR:$b)))]> { 1846 let Inst{31-27} = 0b11111; 1847 let Inst{26-23} = 0b0110; 1848 let Inst{22-20} = 0b110; 1849 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1850 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 1851} 1852 1853def t2SMMLSR:T2I <(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$c), IIC_iMAC32, 1854 "smmlsr", "\t$dst, $a, $b, $c", []> { 1855 let Inst{31-27} = 0b11111; 1856 let Inst{26-23} = 0b0110; 1857 let Inst{22-20} = 0b110; 1858 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1859 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 1860} 1861 1862multiclass T2I_smul<string opc, PatFrag opnode> { 1863 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1864 !strconcat(opc, "bb"), "\t$dst, $a, $b", 1865 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16), 1866 (sext_inreg rGPR:$b, i16)))]> { 1867 let Inst{31-27} = 0b11111; 1868 let Inst{26-23} = 0b0110; 1869 let Inst{22-20} = 0b001; 1870 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1871 let Inst{7-6} = 0b00; 1872 let Inst{5-4} = 0b00; 1873 } 1874 1875 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1876 !strconcat(opc, "bt"), "\t$dst, $a, $b", 1877 [(set rGPR:$dst, (opnode (sext_inreg rGPR:$a, i16), 1878 (sra rGPR:$b, (i32 16))))]> { 1879 let Inst{31-27} = 0b11111; 1880 let Inst{26-23} = 0b0110; 1881 let Inst{22-20} = 0b001; 1882 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1883 let Inst{7-6} = 0b00; 1884 let Inst{5-4} = 0b01; 1885 } 1886 1887 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1888 !strconcat(opc, "tb"), "\t$dst, $a, $b", 1889 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)), 1890 (sext_inreg rGPR:$b, i16)))]> { 1891 let Inst{31-27} = 0b11111; 1892 let Inst{26-23} = 0b0110; 1893 let Inst{22-20} = 0b001; 1894 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1895 let Inst{7-6} = 0b00; 1896 let Inst{5-4} = 0b10; 1897 } 1898 1899 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL32, 1900 !strconcat(opc, "tt"), "\t$dst, $a, $b", 1901 [(set rGPR:$dst, (opnode (sra rGPR:$a, (i32 16)), 1902 (sra rGPR:$b, (i32 16))))]> { 1903 let Inst{31-27} = 0b11111; 1904 let Inst{26-23} = 0b0110; 1905 let Inst{22-20} = 0b001; 1906 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1907 let Inst{7-6} = 0b00; 1908 let Inst{5-4} = 0b11; 1909 } 1910 1911 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16, 1912 !strconcat(opc, "wb"), "\t$dst, $a, $b", 1913 [(set rGPR:$dst, (sra (opnode rGPR:$a, 1914 (sext_inreg rGPR:$b, i16)), (i32 16)))]> { 1915 let Inst{31-27} = 0b11111; 1916 let Inst{26-23} = 0b0110; 1917 let Inst{22-20} = 0b011; 1918 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1919 let Inst{7-6} = 0b00; 1920 let Inst{5-4} = 0b00; 1921 } 1922 1923 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), IIC_iMUL16, 1924 !strconcat(opc, "wt"), "\t$dst, $a, $b", 1925 [(set rGPR:$dst, (sra (opnode rGPR:$a, 1926 (sra rGPR:$b, (i32 16))), (i32 16)))]> { 1927 let Inst{31-27} = 0b11111; 1928 let Inst{26-23} = 0b0110; 1929 let Inst{22-20} = 0b011; 1930 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 1931 let Inst{7-6} = 0b00; 1932 let Inst{5-4} = 0b01; 1933 } 1934} 1935 1936 1937multiclass T2I_smla<string opc, PatFrag opnode> { 1938 def BB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 1939 !strconcat(opc, "bb"), "\t$dst, $a, $b, $acc", 1940 [(set rGPR:$dst, (add rGPR:$acc, 1941 (opnode (sext_inreg rGPR:$a, i16), 1942 (sext_inreg rGPR:$b, i16))))]> { 1943 let Inst{31-27} = 0b11111; 1944 let Inst{26-23} = 0b0110; 1945 let Inst{22-20} = 0b001; 1946 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1947 let Inst{7-6} = 0b00; 1948 let Inst{5-4} = 0b00; 1949 } 1950 1951 def BT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 1952 !strconcat(opc, "bt"), "\t$dst, $a, $b, $acc", 1953 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sext_inreg rGPR:$a, i16), 1954 (sra rGPR:$b, (i32 16)))))]> { 1955 let Inst{31-27} = 0b11111; 1956 let Inst{26-23} = 0b0110; 1957 let Inst{22-20} = 0b001; 1958 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1959 let Inst{7-6} = 0b00; 1960 let Inst{5-4} = 0b01; 1961 } 1962 1963 def TB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 1964 !strconcat(opc, "tb"), "\t$dst, $a, $b, $acc", 1965 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)), 1966 (sext_inreg rGPR:$b, i16))))]> { 1967 let Inst{31-27} = 0b11111; 1968 let Inst{26-23} = 0b0110; 1969 let Inst{22-20} = 0b001; 1970 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1971 let Inst{7-6} = 0b00; 1972 let Inst{5-4} = 0b10; 1973 } 1974 1975 def TT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 1976 !strconcat(opc, "tt"), "\t$dst, $a, $b, $acc", 1977 [(set rGPR:$dst, (add rGPR:$acc, (opnode (sra rGPR:$a, (i32 16)), 1978 (sra rGPR:$b, (i32 16)))))]> { 1979 let Inst{31-27} = 0b11111; 1980 let Inst{26-23} = 0b0110; 1981 let Inst{22-20} = 0b001; 1982 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1983 let Inst{7-6} = 0b00; 1984 let Inst{5-4} = 0b11; 1985 } 1986 1987 def WB : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 1988 !strconcat(opc, "wb"), "\t$dst, $a, $b, $acc", 1989 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a, 1990 (sext_inreg rGPR:$b, i16)), (i32 16))))]> { 1991 let Inst{31-27} = 0b11111; 1992 let Inst{26-23} = 0b0110; 1993 let Inst{22-20} = 0b011; 1994 let Inst{15-12} = {?, ?, ?, ?}; // Ra 1995 let Inst{7-6} = 0b00; 1996 let Inst{5-4} = 0b00; 1997 } 1998 1999 def WT : T2I<(outs rGPR:$dst), (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC16, 2000 !strconcat(opc, "wt"), "\t$dst, $a, $b, $acc", 2001 [(set rGPR:$dst, (add rGPR:$acc, (sra (opnode rGPR:$a, 2002 (sra rGPR:$b, (i32 16))), (i32 16))))]> { 2003 let Inst{31-27} = 0b11111; 2004 let Inst{26-23} = 0b0110; 2005 let Inst{22-20} = 0b011; 2006 let Inst{15-12} = {?, ?, ?, ?}; // Ra 2007 let Inst{7-6} = 0b00; 2008 let Inst{5-4} = 0b01; 2009 } 2010} 2011 2012defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2013defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2014 2015// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only 2016def t2SMLALBB : T2I_mac<1, 0b100, 0b1000, (outs rGPR:$ldst,rGPR:$hdst), 2017 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbb", "\t$ldst, $hdst, $a, $b", 2018 [/* For disassembly only; pattern left blank */]>; 2019def t2SMLALBT : T2I_mac<1, 0b100, 0b1001, (outs rGPR:$ldst,rGPR:$hdst), 2020 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlalbt", "\t$ldst, $hdst, $a, $b", 2021 [/* For disassembly only; pattern left blank */]>; 2022def t2SMLALTB : T2I_mac<1, 0b100, 0b1010, (outs rGPR:$ldst,rGPR:$hdst), 2023 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltb", "\t$ldst, $hdst, $a, $b", 2024 [/* For disassembly only; pattern left blank */]>; 2025def t2SMLALTT : T2I_mac<1, 0b100, 0b1011, (outs rGPR:$ldst,rGPR:$hdst), 2026 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaltt", "\t$ldst, $hdst, $a, $b", 2027 [/* For disassembly only; pattern left blank */]>; 2028 2029// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2030// These are for disassembly only. 2031 2032def t2SMUAD: T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), 2033 IIC_iMAC32, "smuad", "\t$dst, $a, $b", []> { 2034 let Inst{15-12} = 0b1111; 2035} 2036def t2SMUADX:T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), 2037 IIC_iMAC32, "smuadx", "\t$dst, $a, $b", []> { 2038 let Inst{15-12} = 0b1111; 2039} 2040def t2SMUSD: T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), 2041 IIC_iMAC32, "smusd", "\t$dst, $a, $b", []> { 2042 let Inst{15-12} = 0b1111; 2043} 2044def t2SMUSDX:T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), (ins rGPR:$a, rGPR:$b), 2045 IIC_iMAC32, "smusdx", "\t$dst, $a, $b", []> { 2046 let Inst{15-12} = 0b1111; 2047} 2048def t2SMLAD : T2I_mac<0, 0b010, 0b0000, (outs rGPR:$dst), 2049 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlad", 2050 "\t$dst, $a, $b, $acc", []>; 2051def t2SMLADX : T2I_mac<0, 0b010, 0b0001, (outs rGPR:$dst), 2052 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smladx", 2053 "\t$dst, $a, $b, $acc", []>; 2054def t2SMLSD : T2I_mac<0, 0b100, 0b0000, (outs rGPR:$dst), 2055 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsd", 2056 "\t$dst, $a, $b, $acc", []>; 2057def t2SMLSDX : T2I_mac<0, 0b100, 0b0001, (outs rGPR:$dst), 2058 (ins rGPR:$a, rGPR:$b, rGPR:$acc), IIC_iMAC32, "smlsdx", 2059 "\t$dst, $a, $b, $acc", []>; 2060def t2SMLALD : T2I_mac<1, 0b100, 0b1100, (outs rGPR:$ldst,rGPR:$hdst), 2061 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlald", 2062 "\t$ldst, $hdst, $a, $b", []>; 2063def t2SMLALDX : T2I_mac<1, 0b100, 0b1101, (outs rGPR:$ldst,rGPR:$hdst), 2064 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlaldx", 2065 "\t$ldst, $hdst, $a, $b", []>; 2066def t2SMLSLD : T2I_mac<1, 0b101, 0b1100, (outs rGPR:$ldst,rGPR:$hdst), 2067 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsld", 2068 "\t$ldst, $hdst, $a, $b", []>; 2069def t2SMLSLDX : T2I_mac<1, 0b101, 0b1101, (outs rGPR:$ldst,rGPR:$hdst), 2070 (ins rGPR:$a,rGPR:$b), IIC_iMAC64, "smlsldx", 2071 "\t$ldst, $hdst, $a, $b", []>; 2072 2073//===----------------------------------------------------------------------===// 2074// Misc. Arithmetic Instructions. 2075// 2076 2077class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2078 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2079 : T2I<oops, iops, itin, opc, asm, pattern> { 2080 let Inst{31-27} = 0b11111; 2081 let Inst{26-22} = 0b01010; 2082 let Inst{21-20} = op1; 2083 let Inst{15-12} = 0b1111; 2084 let Inst{7-6} = 0b10; 2085 let Inst{5-4} = op2; 2086} 2087 2088def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 2089 "clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>; 2090 2091def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 2092 "rbit", "\t$dst, $src", 2093 [(set rGPR:$dst, (ARMrbit rGPR:$src))]>; 2094 2095def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 2096 "rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>; 2097 2098def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 2099 "rev16", ".w\t$dst, $src", 2100 [(set rGPR:$dst, 2101 (or (and (srl rGPR:$src, (i32 8)), 0xFF), 2102 (or (and (shl rGPR:$src, (i32 8)), 0xFF00), 2103 (or (and (srl rGPR:$src, (i32 8)), 0xFF0000), 2104 (and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>; 2105 2106def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr, 2107 "revsh", ".w\t$dst, $src", 2108 [(set rGPR:$dst, 2109 (sext_inreg 2110 (or (srl (and rGPR:$src, 0xFF00), (i32 8)), 2111 (shl rGPR:$src, (i32 8))), i16))]>; 2112 2113def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh), 2114 IIC_iBITsi, "pkhbt", "\t$dst, $src1, $src2$sh", 2115 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF), 2116 (and (shl rGPR:$src2, lsl_amt:$sh), 2117 0xFFFF0000)))]>, 2118 Requires<[HasT2ExtractPack]> { 2119 let Inst{31-27} = 0b11101; 2120 let Inst{26-25} = 0b01; 2121 let Inst{24-20} = 0b01100; 2122 let Inst{5} = 0; // BT form 2123 let Inst{4} = 0; 2124} 2125 2126// Alternate cases for PKHBT where identities eliminate some nodes. 2127def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 2128 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 2129 Requires<[HasT2ExtractPack]>; 2130def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 2131 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>, 2132 Requires<[HasT2ExtractPack]>; 2133 2134// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2135// will match the pattern below. 2136def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh), 2137 IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh", 2138 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000), 2139 (and (sra rGPR:$src2, asr_amt:$sh), 2140 0xFFFF)))]>, 2141 Requires<[HasT2ExtractPack]> { 2142 let Inst{31-27} = 0b11101; 2143 let Inst{26-25} = 0b01; 2144 let Inst{24-20} = 0b01100; 2145 let Inst{5} = 1; // TB form 2146 let Inst{4} = 0; 2147} 2148 2149// Alternate cases for PKHTB where identities eliminate some nodes. Note that 2150// a shift amount of 0 is *not legal* here, it is PKHBT instead. 2151def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), 2152 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>, 2153 Requires<[HasT2ExtractPack]>; 2154def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 2155 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 2156 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>, 2157 Requires<[HasT2ExtractPack]>; 2158 2159//===----------------------------------------------------------------------===// 2160// Comparison Instructions... 2161// 2162defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2163 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2164 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 2165defm t2CMPz : T2I_cmp_irs<0b1101, "cmp", 2166 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2167 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 2168 2169//FIXME: Disable CMN, as CCodes are backwards from compare expectations 2170// Compare-to-zero still works out, just not the relationals 2171//defm t2CMN : T2I_cmp_irs<0b1000, "cmn", 2172// BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2173defm t2CMNz : T2I_cmp_irs<0b1000, "cmn", 2174 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2175 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 2176 2177//def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2178// (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2179 2180def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 2181 (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>; 2182 2183defm t2TST : T2I_cmp_irs<0b0000, "tst", 2184 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2185 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 2186defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2187 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2188 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 2189 2190// Conditional moves 2191// FIXME: should be able to write a pattern for ARMcmov, but can't use 2192// a two-value operand where a dag node expects two operands. :( 2193let neverHasSideEffects = 1 in { 2194def t2MOVCCr : T2I<(outs rGPR:$dst), (ins rGPR:$false, rGPR:$true), IIC_iCMOVr, 2195 "mov", ".w\t$dst, $true", 2196 [/*(set rGPR:$dst, (ARMcmov rGPR:$false, rGPR:$true, imm:$cc, CCR:$ccr))*/]>, 2197 RegConstraint<"$false = $dst"> { 2198 let Inst{31-27} = 0b11101; 2199 let Inst{26-25} = 0b01; 2200 let Inst{24-21} = 0b0010; 2201 let Inst{20} = 0; // The S bit. 2202 let Inst{19-16} = 0b1111; // Rn 2203 let Inst{14-12} = 0b000; 2204 let Inst{7-4} = 0b0000; 2205} 2206 2207def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true), 2208 IIC_iCMOVi, "mov", ".w\t$dst, $true", 2209[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 2210 RegConstraint<"$false = $dst"> { 2211 let Inst{31-27} = 0b11110; 2212 let Inst{25} = 0; 2213 let Inst{24-21} = 0b0010; 2214 let Inst{20} = 0; // The S bit. 2215 let Inst{19-16} = 0b1111; // Rn 2216 let Inst{15} = 0; 2217} 2218 2219class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2220 string opc, string asm, list<dag> pattern> 2221 : T2I<oops, iops, itin, opc, asm, pattern> { 2222 let Inst{31-27} = 0b11101; 2223 let Inst{26-25} = 0b01; 2224 let Inst{24-21} = 0b0010; 2225 let Inst{20} = 0; // The S bit. 2226 let Inst{19-16} = 0b1111; // Rn 2227 let Inst{5-4} = opcod; // Shift type. 2228} 2229def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$dst), 2230 (ins rGPR:$false, rGPR:$true, i32imm:$rhs), 2231 IIC_iCMOVsi, "lsl", ".w\t$dst, $true, $rhs", []>, 2232 RegConstraint<"$false = $dst">; 2233def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$dst), 2234 (ins rGPR:$false, rGPR:$true, i32imm:$rhs), 2235 IIC_iCMOVsi, "lsr", ".w\t$dst, $true, $rhs", []>, 2236 RegConstraint<"$false = $dst">; 2237def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$dst), 2238 (ins rGPR:$false, rGPR:$true, i32imm:$rhs), 2239 IIC_iCMOVsi, "asr", ".w\t$dst, $true, $rhs", []>, 2240 RegConstraint<"$false = $dst">; 2241def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$dst), 2242 (ins rGPR:$false, rGPR:$true, i32imm:$rhs), 2243 IIC_iCMOVsi, "ror", ".w\t$dst, $true, $rhs", []>, 2244 RegConstraint<"$false = $dst">; 2245} // neverHasSideEffects 2246 2247//===----------------------------------------------------------------------===// 2248// Atomic operations intrinsics 2249// 2250 2251// memory barriers protect the atomic sequences 2252let hasSideEffects = 1 in { 2253def t2DMBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dmb", "", 2254 [(ARMMemBarrier)]>, Requires<[IsThumb, HasDB]> { 2255 let Inst{31-4} = 0xF3BF8F5; 2256 // FIXME: add support for options other than a full system DMB 2257 let Inst{3-0} = 0b1111; 2258} 2259 2260def t2DSBsy : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "dsb", "", 2261 [(ARMSyncBarrier)]>, Requires<[IsThumb, HasDB]> { 2262 let Inst{31-4} = 0xF3BF8F4; 2263 // FIXME: add support for options other than a full system DSB 2264 let Inst{3-0} = 0b1111; 2265} 2266} 2267 2268// Helper class for multiclass T2MemB -- for disassembly only 2269class T2I_memb<string opc, string asm> 2270 : T2I<(outs), (ins), NoItinerary, opc, asm, 2271 [/* For disassembly only; pattern left blank */]>, 2272 Requires<[IsThumb2, HasV7]> { 2273 let Inst{31-20} = 0xf3b; 2274 let Inst{15-14} = 0b10; 2275 let Inst{12} = 0; 2276} 2277 2278multiclass T2MemB<bits<4> op7_4, string opc> { 2279 2280 def st : T2I_memb<opc, "\tst"> { 2281 let Inst{7-4} = op7_4; 2282 let Inst{3-0} = 0b1110; 2283 } 2284 2285 def ish : T2I_memb<opc, "\tish"> { 2286 let Inst{7-4} = op7_4; 2287 let Inst{3-0} = 0b1011; 2288 } 2289 2290 def ishst : T2I_memb<opc, "\tishst"> { 2291 let Inst{7-4} = op7_4; 2292 let Inst{3-0} = 0b1010; 2293 } 2294 2295 def nsh : T2I_memb<opc, "\tnsh"> { 2296 let Inst{7-4} = op7_4; 2297 let Inst{3-0} = 0b0111; 2298 } 2299 2300 def nshst : T2I_memb<opc, "\tnshst"> { 2301 let Inst{7-4} = op7_4; 2302 let Inst{3-0} = 0b0110; 2303 } 2304 2305 def osh : T2I_memb<opc, "\tosh"> { 2306 let Inst{7-4} = op7_4; 2307 let Inst{3-0} = 0b0011; 2308 } 2309 2310 def oshst : T2I_memb<opc, "\toshst"> { 2311 let Inst{7-4} = op7_4; 2312 let Inst{3-0} = 0b0010; 2313 } 2314} 2315 2316// These DMB variants are for disassembly only. 2317defm t2DMB : T2MemB<0b0101, "dmb">; 2318 2319// These DSB variants are for disassembly only. 2320defm t2DSB : T2MemB<0b0100, "dsb">; 2321 2322// ISB has only full system option -- for disassembly only 2323def t2ISBsy : T2I_memb<"isb", ""> { 2324 let Inst{7-4} = 0b0110; 2325 let Inst{3-0} = 0b1111; 2326} 2327 2328class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2329 InstrItinClass itin, string opc, string asm, string cstr, 2330 list<dag> pattern, bits<4> rt2 = 0b1111> 2331 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2332 let Inst{31-27} = 0b11101; 2333 let Inst{26-20} = 0b0001101; 2334 let Inst{11-8} = rt2; 2335 let Inst{7-6} = 0b01; 2336 let Inst{5-4} = opcod; 2337 let Inst{3-0} = 0b1111; 2338} 2339class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, 2340 InstrItinClass itin, string opc, string asm, string cstr, 2341 list<dag> pattern, bits<4> rt2 = 0b1111> 2342 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2343 let Inst{31-27} = 0b11101; 2344 let Inst{26-20} = 0b0001100; 2345 let Inst{11-8} = rt2; 2346 let Inst{7-6} = 0b01; 2347 let Inst{5-4} = opcod; 2348} 2349 2350let mayLoad = 1 in { 2351def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone, 2352 Size4Bytes, NoItinerary, "ldrexb", "\t$dest, [$ptr]", 2353 "", []>; 2354def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone, 2355 Size4Bytes, NoItinerary, "ldrexh", "\t$dest, [$ptr]", 2356 "", []>; 2357def t2LDREX : Thumb2I<(outs rGPR:$dest), (ins rGPR:$ptr), AddrModeNone, 2358 Size4Bytes, NoItinerary, 2359 "ldrex", "\t$dest, [$ptr]", "", 2360 []> { 2361 let Inst{31-27} = 0b11101; 2362 let Inst{26-20} = 0b0000101; 2363 let Inst{11-8} = 0b1111; 2364 let Inst{7-0} = 0b00000000; // imm8 = 0 2365} 2366def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$dest, rGPR:$dest2), (ins rGPR:$ptr), 2367 AddrModeNone, Size4Bytes, NoItinerary, 2368 "ldrexd", "\t$dest, $dest2, [$ptr]", "", 2369 [], {?, ?, ?, ?}>; 2370} 2371 2372let mayStore = 1, Constraints = "@earlyclobber $success" in { 2373def t2STREXB : T2I_strex<0b00, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr), 2374 AddrModeNone, Size4Bytes, NoItinerary, 2375 "strexb", "\t$success, $src, [$ptr]", "", []>; 2376def t2STREXH : T2I_strex<0b01, (outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr), 2377 AddrModeNone, Size4Bytes, NoItinerary, 2378 "strexh", "\t$success, $src, [$ptr]", "", []>; 2379def t2STREX : Thumb2I<(outs rGPR:$success), (ins rGPR:$src, rGPR:$ptr), 2380 AddrModeNone, Size4Bytes, NoItinerary, 2381 "strex", "\t$success, $src, [$ptr]", "", 2382 []> { 2383 let Inst{31-27} = 0b11101; 2384 let Inst{26-20} = 0b0000100; 2385 let Inst{7-0} = 0b00000000; // imm8 = 0 2386} 2387def t2STREXD : T2I_strex<0b11, (outs rGPR:$success), 2388 (ins rGPR:$src, rGPR:$src2, rGPR:$ptr), 2389 AddrModeNone, Size4Bytes, NoItinerary, 2390 "strexd", "\t$success, $src, $src2, [$ptr]", "", [], 2391 {?, ?, ?, ?}>; 2392} 2393 2394// Clear-Exclusive is for disassembly only. 2395def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", 2396 [/* For disassembly only; pattern left blank */]>, 2397 Requires<[IsARM, HasV7]> { 2398 let Inst{31-20} = 0xf3b; 2399 let Inst{15-14} = 0b10; 2400 let Inst{12} = 0; 2401 let Inst{7-4} = 0b0010; 2402} 2403 2404//===----------------------------------------------------------------------===// 2405// TLS Instructions 2406// 2407 2408// __aeabi_read_tp preserves the registers r1-r3. 2409let isCall = 1, 2410 Defs = [R0, R12, LR, CPSR] in { 2411 def t2TPsoft : T2XI<(outs), (ins), IIC_Br, 2412 "bl\t__aeabi_read_tp", 2413 [(set R0, ARMthread_pointer)]> { 2414 let Inst{31-27} = 0b11110; 2415 let Inst{15-14} = 0b11; 2416 let Inst{12} = 1; 2417 } 2418} 2419 2420//===----------------------------------------------------------------------===// 2421// SJLJ Exception handling intrinsics 2422// eh_sjlj_setjmp() is an instruction sequence to store the return 2423// address and save #0 in R0 for the non-longjmp case. 2424// Since by its nature we may be coming from some other function to get 2425// here, and we're using the stack frame for the containing function to 2426// save/restore registers, we can't keep anything live in regs across 2427// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 2428// when we get here from a longjmp(). We force everthing out of registers 2429// except for our own input by listing the relevant registers in Defs. By 2430// doing so, we also cause the prologue/epilogue code to actively preserve 2431// all of the callee-saved resgisters, which is exactly what we want. 2432// $val is a scratch register for our use. 2433let Defs = 2434 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0, 2435 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 2436 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, 2437 D31 ], hasSideEffects = 1, isBarrier = 1 in { 2438 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 2439 AddrModeNone, SizeSpecial, NoItinerary, 2440 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t" 2441 "adds\t$val, #7\n\t" 2442 "str\t$val, [$src, #4]\n\t" 2443 "movs\tr0, #0\n\t" 2444 "b\t1f\n\t" 2445 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t" 2446 "1:", "", 2447 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 2448 Requires<[IsThumb2, HasVFP2]>; 2449} 2450 2451let Defs = 2452 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ], 2453 hasSideEffects = 1, isBarrier = 1 in { 2454 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 2455 AddrModeNone, SizeSpecial, NoItinerary, 2456 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t" 2457 "adds\t$val, #7\n\t" 2458 "str\t$val, [$src, #4]\n\t" 2459 "movs\tr0, #0\n\t" 2460 "b\t1f\n\t" 2461 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t" 2462 "1:", "", 2463 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 2464 Requires<[IsThumb2, NoVFP]>; 2465} 2466 2467 2468//===----------------------------------------------------------------------===// 2469// Control-Flow Instructions 2470// 2471 2472// FIXME: remove when we have a way to marking a MI with these properties. 2473// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 2474// operand list. 2475// FIXME: Should pc be an implicit operand like PICADD, etc? 2476let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 2477 hasExtraDefRegAllocReq = 1 in 2478 def t2LDM_RET : T2XIt<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p, 2479 reglist:$dsts, variable_ops), 2480 IIC_iLoadmBr, 2481 "ldm${addr:submode}${p}${addr:wide}\t$addr!, $dsts", 2482 "$addr.addr = $wb", []> { 2483 let Inst{31-27} = 0b11101; 2484 let Inst{26-25} = 0b00; 2485 let Inst{24-23} = {?, ?}; // IA: '01', DB: '10' 2486 let Inst{22} = 0; 2487 let Inst{21} = 1; // The W bit. 2488 let Inst{20} = 1; // Load 2489} 2490 2491let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 2492let isPredicable = 1 in 2493def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br, 2494 "b.w\t$target", 2495 [(br bb:$target)]> { 2496 let Inst{31-27} = 0b11110; 2497 let Inst{15-14} = 0b10; 2498 let Inst{12} = 1; 2499} 2500 2501let isNotDuplicable = 1, isIndirectBranch = 1 in { 2502def t2BR_JT : 2503 T2JTI<(outs), 2504 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 2505 IIC_Br, "mov\tpc, $target$jt", 2506 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]> { 2507 let Inst{31-27} = 0b11101; 2508 let Inst{26-20} = 0b0100100; 2509 let Inst{19-16} = 0b1111; 2510 let Inst{14-12} = 0b000; 2511 let Inst{11-8} = 0b1111; // Rd = pc 2512 let Inst{7-4} = 0b0000; 2513} 2514 2515// FIXME: Add a non-pc based case that can be predicated. 2516def t2TBB : 2517 T2JTI<(outs), 2518 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2519 IIC_Br, "tbb\t$index$jt", []> { 2520 let Inst{31-27} = 0b11101; 2521 let Inst{26-20} = 0b0001101; 2522 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2523 let Inst{15-8} = 0b11110000; 2524 let Inst{7-4} = 0b0000; // B form 2525} 2526 2527def t2TBH : 2528 T2JTI<(outs), 2529 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 2530 IIC_Br, "tbh\t$index$jt", []> { 2531 let Inst{31-27} = 0b11101; 2532 let Inst{26-20} = 0b0001101; 2533 let Inst{19-16} = 0b1111; // Rn = pc (table follows this instruction) 2534 let Inst{15-8} = 0b11110000; 2535 let Inst{7-4} = 0b0001; // H form 2536} 2537 2538// Generic versions of the above two instructions, for disassembly only 2539 2540def t2TBBgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2541 "tbb", "\t[$a, $b]", []>{ 2542 let Inst{31-27} = 0b11101; 2543 let Inst{26-20} = 0b0001101; 2544 let Inst{15-8} = 0b11110000; 2545 let Inst{7-4} = 0b0000; // B form 2546} 2547 2548def t2TBHgen : T2I<(outs), (ins GPR:$a, GPR:$b), IIC_Br, 2549 "tbh", "\t[$a, $b, lsl #1]", []> { 2550 let Inst{31-27} = 0b11101; 2551 let Inst{26-20} = 0b0001101; 2552 let Inst{15-8} = 0b11110000; 2553 let Inst{7-4} = 0b0001; // H form 2554} 2555} // isNotDuplicable, isIndirectBranch 2556 2557} // isBranch, isTerminator, isBarrier 2558 2559// FIXME: should be able to write a pattern for ARMBrcond, but can't use 2560// a two-value operand where a dag node expects two operands. :( 2561let isBranch = 1, isTerminator = 1 in 2562def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 2563 "b", ".w\t$target", 2564 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 2565 let Inst{31-27} = 0b11110; 2566 let Inst{15-14} = 0b10; 2567 let Inst{12} = 0; 2568} 2569 2570 2571// IT block 2572let Defs = [ITSTATE] in 2573def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 2574 AddrModeNone, Size2Bytes, IIC_iALUx, 2575 "it$mask\t$cc", "", []> { 2576 // 16-bit instruction. 2577 let Inst{31-16} = 0x0000; 2578 let Inst{15-8} = 0b10111111; 2579} 2580 2581// Branch and Exchange Jazelle -- for disassembly only 2582// Rm = Inst{19-16} 2583def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", 2584 [/* For disassembly only; pattern left blank */]> { 2585 let Inst{31-27} = 0b11110; 2586 let Inst{26} = 0; 2587 let Inst{25-20} = 0b111100; 2588 let Inst{15-14} = 0b10; 2589 let Inst{12} = 0; 2590} 2591 2592// Change Processor State is a system instruction -- for disassembly only. 2593// The singleton $opt operand contains the following information: 2594// opt{4-0} = mode from Inst{4-0} 2595// opt{5} = changemode from Inst{17} 2596// opt{8-6} = AIF from Inst{8-6} 2597// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable 2598def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt", 2599 [/* For disassembly only; pattern left blank */]> { 2600 let Inst{31-27} = 0b11110; 2601 let Inst{26} = 0; 2602 let Inst{25-20} = 0b111010; 2603 let Inst{15-14} = 0b10; 2604 let Inst{12} = 0; 2605} 2606 2607// A6.3.4 Branches and miscellaneous control 2608// Table A6-14 Change Processor State, and hint instructions 2609// Helper class for disassembly only. 2610class T2I_hint<bits<8> op7_0, string opc, string asm> 2611 : T2I<(outs), (ins), NoItinerary, opc, asm, 2612 [/* For disassembly only; pattern left blank */]> { 2613 let Inst{31-20} = 0xf3a; 2614 let Inst{15-14} = 0b10; 2615 let Inst{12} = 0; 2616 let Inst{10-8} = 0b000; 2617 let Inst{7-0} = op7_0; 2618} 2619 2620def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 2621def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 2622def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 2623def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 2624def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 2625 2626def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt", 2627 [/* For disassembly only; pattern left blank */]> { 2628 let Inst{31-20} = 0xf3a; 2629 let Inst{15-14} = 0b10; 2630 let Inst{12} = 0; 2631 let Inst{10-8} = 0b000; 2632 let Inst{7-4} = 0b1111; 2633} 2634 2635// Secure Monitor Call is a system instruction -- for disassembly only 2636// Option = Inst{19-16} 2637def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt", 2638 [/* For disassembly only; pattern left blank */]> { 2639 let Inst{31-27} = 0b11110; 2640 let Inst{26-20} = 0b1111111; 2641 let Inst{15-12} = 0b1000; 2642} 2643 2644// Store Return State is a system instruction -- for disassembly only 2645def t2SRSDBW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode", 2646 [/* For disassembly only; pattern left blank */]> { 2647 let Inst{31-27} = 0b11101; 2648 let Inst{26-20} = 0b0000010; // W = 1 2649} 2650 2651def t2SRSDB : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode", 2652 [/* For disassembly only; pattern left blank */]> { 2653 let Inst{31-27} = 0b11101; 2654 let Inst{26-20} = 0b0000000; // W = 0 2655} 2656 2657def t2SRSIAW : T2I<(outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode", 2658 [/* For disassembly only; pattern left blank */]> { 2659 let Inst{31-27} = 0b11101; 2660 let Inst{26-20} = 0b0011010; // W = 1 2661} 2662 2663def t2SRSIA : T2I<(outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode", 2664 [/* For disassembly only; pattern left blank */]> { 2665 let Inst{31-27} = 0b11101; 2666 let Inst{26-20} = 0b0011000; // W = 0 2667} 2668 2669// Return From Exception is a system instruction -- for disassembly only 2670def t2RFEDBW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfedb", "\t$base!", 2671 [/* For disassembly only; pattern left blank */]> { 2672 let Inst{31-27} = 0b11101; 2673 let Inst{26-20} = 0b0000011; // W = 1 2674} 2675 2676def t2RFEDB : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeab", "\t$base", 2677 [/* For disassembly only; pattern left blank */]> { 2678 let Inst{31-27} = 0b11101; 2679 let Inst{26-20} = 0b0000001; // W = 0 2680} 2681 2682def t2RFEIAW : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base!", 2683 [/* For disassembly only; pattern left blank */]> { 2684 let Inst{31-27} = 0b11101; 2685 let Inst{26-20} = 0b0011011; // W = 1 2686} 2687 2688def t2RFEIA : T2I<(outs), (ins rGPR:$base), NoItinerary, "rfeia", "\t$base", 2689 [/* For disassembly only; pattern left blank */]> { 2690 let Inst{31-27} = 0b11101; 2691 let Inst{26-20} = 0b0011001; // W = 0 2692} 2693 2694//===----------------------------------------------------------------------===// 2695// Non-Instruction Patterns 2696// 2697 2698// Two piece so_imms. 2699def : T2Pat<(or rGPR:$LHS, t2_so_imm2part:$RHS), 2700 (t2ORRri (t2ORRri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2701 (t2_so_imm2part_2 imm:$RHS))>; 2702def : T2Pat<(xor rGPR:$LHS, t2_so_imm2part:$RHS), 2703 (t2EORri (t2EORri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2704 (t2_so_imm2part_2 imm:$RHS))>; 2705def : T2Pat<(add rGPR:$LHS, t2_so_imm2part:$RHS), 2706 (t2ADDri (t2ADDri rGPR:$LHS, (t2_so_imm2part_1 imm:$RHS)), 2707 (t2_so_imm2part_2 imm:$RHS))>; 2708def : T2Pat<(add rGPR:$LHS, t2_so_neg_imm2part:$RHS), 2709 (t2SUBri (t2SUBri rGPR:$LHS, (t2_so_neg_imm2part_1 imm:$RHS)), 2710 (t2_so_neg_imm2part_2 imm:$RHS))>; 2711 2712// 32-bit immediate using movw + movt. 2713// This is a single pseudo instruction to make it re-materializable. 2714// FIXME: Remove this when we can do generalized remat. 2715let isReMaterializable = 1 in 2716def t2MOVi32imm : T2Ix2<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 2717 "movw", "\t$dst, ${src:lo16}\n\tmovt${p}\t$dst, ${src:hi16}", 2718 [(set rGPR:$dst, (i32 imm:$src))]>; 2719 2720// ConstantPool, GlobalAddress, and JumpTable 2721def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 2722 Requires<[IsThumb2, DontUseMovt]>; 2723def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 2724def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 2725 Requires<[IsThumb2, UseMovt]>; 2726 2727def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 2728 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 2729 2730// Pseudo instruction that combines ldr from constpool and add pc. This should 2731// be expanded into two instructions late to allow if-conversion and 2732// scheduling. 2733let canFoldAsLoad = 1, isReMaterializable = 1 in 2734def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 2735 IIC_iLoadiALU, 2736 "${:comment} ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 2737 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 2738 imm:$cp))]>, 2739 Requires<[IsThumb2]>; 2740 2741//===----------------------------------------------------------------------===// 2742// Move between special register and ARM core register -- for disassembly only 2743// 2744 2745// Rd = Instr{11-8} 2746def t2MRS : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, cpsr", 2747 [/* For disassembly only; pattern left blank */]> { 2748 let Inst{31-27} = 0b11110; 2749 let Inst{26} = 0; 2750 let Inst{25-21} = 0b11111; 2751 let Inst{20} = 0; // The R bit. 2752 let Inst{15-14} = 0b10; 2753 let Inst{12} = 0; 2754} 2755 2756// Rd = Instr{11-8} 2757def t2MRSsys : T2I<(outs rGPR:$dst), (ins), NoItinerary, "mrs", "\t$dst, spsr", 2758 [/* For disassembly only; pattern left blank */]> { 2759 let Inst{31-27} = 0b11110; 2760 let Inst{26} = 0; 2761 let Inst{25-21} = 0b11111; 2762 let Inst{20} = 1; // The R bit. 2763 let Inst{15-14} = 0b10; 2764 let Inst{12} = 0; 2765} 2766 2767// Rn = Inst{19-16} 2768def t2MSR : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr", 2769 "\tcpsr$mask, $src", 2770 [/* For disassembly only; pattern left blank */]> { 2771 let Inst{31-27} = 0b11110; 2772 let Inst{26} = 0; 2773 let Inst{25-21} = 0b11100; 2774 let Inst{20} = 0; // The R bit. 2775 let Inst{15-14} = 0b10; 2776 let Inst{12} = 0; 2777} 2778 2779// Rn = Inst{19-16} 2780def t2MSRsys : T2I<(outs), (ins rGPR:$src, msr_mask:$mask), NoItinerary, "msr", 2781 "\tspsr$mask, $src", 2782 [/* For disassembly only; pattern left blank */]> { 2783 let Inst{31-27} = 0b11110; 2784 let Inst{26} = 0; 2785 let Inst{25-21} = 0b11100; 2786 let Inst{20} = 1; // The R bit. 2787 let Inst{15-14} = 0b10; 2788 let Inst{12} = 0; 2789} 2790