ARMInstrThumb2.td revision 45f3929ef0dcdf281a10f23e031ffaba7664e7c0 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred : Operand<i32> {
16  let PrintMethod = "printMandatoryPredicateOperand";
17}
18
19// IT block condition mask
20def it_mask : Operand<i32> {
21  let PrintMethod = "printThumbITMask";
22}
23
24// Shifted operands. No register controlled shifts for Thumb2.
25// Note: We do not support rrx shifted operands yet.
26def t2_so_reg : Operand<i32>,    // reg imm
27                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
28                               [shl,srl,sra,rotr]> {
29  let EncoderMethod = "getT2SORegOpValue";
30  let PrintMethod = "printT2SOOperand";
31  let MIOperandInfo = (ops rGPR, i32imm);
32}
33
34// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
37}]>;
38
39// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
42}]>;
43
44// t2_so_imm - Match a 32-bit immediate operand, which is an
45// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46// immediate splatted into multiple bytes of the word.
47def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
48def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
49    return ARM_AM::getT2SOImmVal(Imm) != -1;
50  }]> {
51  let ParserMatchClass = t2_so_imm_asmoperand;
52  let EncoderMethod = "getT2SOImmOpValue";
53}
54
55// t2_so_imm_not - Match an immediate that is a complement
56// of a t2_so_imm.
57def t2_so_imm_not : Operand<i32>,
58                    PatLeaf<(imm), [{
59  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60}], t2_so_imm_not_XFORM>;
61
62// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
63def t2_so_imm_neg : Operand<i32>,
64                    PatLeaf<(imm), [{
65  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
66}], t2_so_imm_neg_XFORM>;
67
68/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
69def imm1_31 : ImmLeaf<i32, [{
70  return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
71}]>;
72
73/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
74def imm0_4095 : Operand<i32>,
75                ImmLeaf<i32, [{
76  return Imm >= 0 && Imm < 4096;
77}]>;
78
79def imm0_4095_neg : PatLeaf<(i32 imm), [{
80 return (uint32_t)(-N->getZExtValue()) < 4096;
81}], imm_neg_XFORM>;
82
83def imm0_255_neg : PatLeaf<(i32 imm), [{
84  return (uint32_t)(-N->getZExtValue()) < 255;
85}], imm_neg_XFORM>;
86
87def imm0_255_not : PatLeaf<(i32 imm), [{
88  return (uint32_t)(~N->getZExtValue()) < 255;
89}], imm_comp_XFORM>;
90
91def lo5AllOne : PatLeaf<(i32 imm), [{
92  // Returns true if all low 5-bits are 1.
93  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
94}]>;
95
96// Define Thumb2 specific addressing modes.
97
98// t2addrmode_imm12  := reg + imm12
99def t2addrmode_imm12 : Operand<i32>,
100                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
101  let PrintMethod = "printAddrModeImm12Operand";
102  let EncoderMethod = "getAddrModeImm12OpValue";
103  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
104  let ParserMatchClass = MemMode5AsmOperand;
105}
106
107// t2ldrlabel  := imm12
108def t2ldrlabel : Operand<i32> {
109  let EncoderMethod = "getAddrModeImm12OpValue";
110}
111
112
113// ADR instruction labels.
114def t2adrlabel : Operand<i32> {
115  let EncoderMethod = "getT2AdrLabelOpValue";
116}
117
118
119// t2addrmode_imm8  := reg +/- imm8
120def t2addrmode_imm8 : Operand<i32>,
121                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
122  let PrintMethod = "printT2AddrModeImm8Operand";
123  let EncoderMethod = "getT2AddrModeImm8OpValue";
124  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
125  let ParserMatchClass = MemMode5AsmOperand;
126}
127
128def t2am_imm8_offset : Operand<i32>,
129                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
130                                      [], [SDNPWantRoot]> {
131  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
132  let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
133  let ParserMatchClass = MemMode5AsmOperand;
134}
135
136// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
137def t2addrmode_imm8s4 : Operand<i32> {
138  let PrintMethod = "printT2AddrModeImm8s4Operand";
139  let EncoderMethod = "getT2AddrModeImm8s4OpValue";
140  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141  let ParserMatchClass = MemMode5AsmOperand;
142}
143
144def t2am_imm8s4_offset : Operand<i32> {
145  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
146}
147
148// t2addrmode_so_reg  := reg + (reg << imm2)
149def t2addrmode_so_reg : Operand<i32>,
150                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
151  let PrintMethod = "printT2AddrModeSoRegOperand";
152  let EncoderMethod = "getT2AddrModeSORegOpValue";
153  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
154  let ParserMatchClass = MemMode5AsmOperand;
155}
156
157// t2addrmode_reg := reg
158// Used by load/store exclusive instructions. Useful to enable right assembly
159// parsing and printing. Not used for any codegen matching.
160//
161def t2addrmode_reg : Operand<i32> {
162  let PrintMethod = "printAddrMode7Operand";
163  let MIOperandInfo = (ops GPR);
164  let ParserMatchClass = MemMode7AsmOperand;
165}
166
167//===----------------------------------------------------------------------===//
168// Multiclass helpers...
169//
170
171
172class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
173           string opc, string asm, list<dag> pattern>
174  : T2I<oops, iops, itin, opc, asm, pattern> {
175  bits<4> Rd;
176  bits<12> imm;
177
178  let Inst{11-8}  = Rd;
179  let Inst{26}    = imm{11};
180  let Inst{14-12} = imm{10-8};
181  let Inst{7-0}   = imm{7-0};
182}
183
184
185class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
186           string opc, string asm, list<dag> pattern>
187  : T2sI<oops, iops, itin, opc, asm, pattern> {
188  bits<4> Rd;
189  bits<4> Rn;
190  bits<12> imm;
191
192  let Inst{11-8}  = Rd;
193  let Inst{26}    = imm{11};
194  let Inst{14-12} = imm{10-8};
195  let Inst{7-0}   = imm{7-0};
196}
197
198class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
199           string opc, string asm, list<dag> pattern>
200  : T2I<oops, iops, itin, opc, asm, pattern> {
201  bits<4> Rn;
202  bits<12> imm;
203
204  let Inst{19-16}  = Rn;
205  let Inst{26}    = imm{11};
206  let Inst{14-12} = imm{10-8};
207  let Inst{7-0}   = imm{7-0};
208}
209
210
211class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
212           string opc, string asm, list<dag> pattern>
213  : T2I<oops, iops, itin, opc, asm, pattern> {
214  bits<4> Rd;
215  bits<12> ShiftedRm;
216
217  let Inst{11-8}  = Rd;
218  let Inst{3-0}   = ShiftedRm{3-0};
219  let Inst{5-4}   = ShiftedRm{6-5};
220  let Inst{14-12} = ShiftedRm{11-9};
221  let Inst{7-6}   = ShiftedRm{8-7};
222}
223
224class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
225           string opc, string asm, list<dag> pattern>
226  : T2sI<oops, iops, itin, opc, asm, pattern> {
227  bits<4> Rd;
228  bits<12> ShiftedRm;
229
230  let Inst{11-8}  = Rd;
231  let Inst{3-0}   = ShiftedRm{3-0};
232  let Inst{5-4}   = ShiftedRm{6-5};
233  let Inst{14-12} = ShiftedRm{11-9};
234  let Inst{7-6}   = ShiftedRm{8-7};
235}
236
237class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
238           string opc, string asm, list<dag> pattern>
239  : T2I<oops, iops, itin, opc, asm, pattern> {
240  bits<4> Rn;
241  bits<12> ShiftedRm;
242
243  let Inst{19-16} = Rn;
244  let Inst{3-0}   = ShiftedRm{3-0};
245  let Inst{5-4}   = ShiftedRm{6-5};
246  let Inst{14-12} = ShiftedRm{11-9};
247  let Inst{7-6}   = ShiftedRm{8-7};
248}
249
250class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
251           string opc, string asm, list<dag> pattern>
252  : T2I<oops, iops, itin, opc, asm, pattern> {
253  bits<4> Rd;
254  bits<4> Rm;
255
256  let Inst{11-8}  = Rd;
257  let Inst{3-0}   = Rm;
258}
259
260class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
261           string opc, string asm, list<dag> pattern>
262  : T2sI<oops, iops, itin, opc, asm, pattern> {
263  bits<4> Rd;
264  bits<4> Rm;
265
266  let Inst{11-8}  = Rd;
267  let Inst{3-0}   = Rm;
268}
269
270class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
271           string opc, string asm, list<dag> pattern>
272  : T2I<oops, iops, itin, opc, asm, pattern> {
273  bits<4> Rn;
274  bits<4> Rm;
275
276  let Inst{19-16} = Rn;
277  let Inst{3-0}   = Rm;
278}
279
280
281class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
282           string opc, string asm, list<dag> pattern>
283  : T2I<oops, iops, itin, opc, asm, pattern> {
284  bits<4> Rd;
285  bits<4> Rn;
286  bits<12> imm;
287
288  let Inst{11-8}  = Rd;
289  let Inst{19-16} = Rn;
290  let Inst{26}    = imm{11};
291  let Inst{14-12} = imm{10-8};
292  let Inst{7-0}   = imm{7-0};
293}
294
295class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
296           string opc, string asm, list<dag> pattern>
297  : T2sI<oops, iops, itin, opc, asm, pattern> {
298  bits<4> Rd;
299  bits<4> Rn;
300  bits<12> imm;
301
302  let Inst{11-8}  = Rd;
303  let Inst{19-16} = Rn;
304  let Inst{26}    = imm{11};
305  let Inst{14-12} = imm{10-8};
306  let Inst{7-0}   = imm{7-0};
307}
308
309class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
310           string opc, string asm, list<dag> pattern>
311  : T2I<oops, iops, itin, opc, asm, pattern> {
312  bits<4> Rd;
313  bits<4> Rm;
314  bits<5> imm;
315
316  let Inst{11-8}  = Rd;
317  let Inst{3-0}   = Rm;
318  let Inst{14-12} = imm{4-2};
319  let Inst{7-6}   = imm{1-0};
320}
321
322class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
323           string opc, string asm, list<dag> pattern>
324  : T2sI<oops, iops, itin, opc, asm, pattern> {
325  bits<4> Rd;
326  bits<4> Rm;
327  bits<5> imm;
328
329  let Inst{11-8}  = Rd;
330  let Inst{3-0}   = Rm;
331  let Inst{14-12} = imm{4-2};
332  let Inst{7-6}   = imm{1-0};
333}
334
335class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
336           string opc, string asm, list<dag> pattern>
337  : T2I<oops, iops, itin, opc, asm, pattern> {
338  bits<4> Rd;
339  bits<4> Rn;
340  bits<4> Rm;
341
342  let Inst{11-8}  = Rd;
343  let Inst{19-16} = Rn;
344  let Inst{3-0}   = Rm;
345}
346
347class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
348           string opc, string asm, list<dag> pattern>
349  : T2sI<oops, iops, itin, opc, asm, pattern> {
350  bits<4> Rd;
351  bits<4> Rn;
352  bits<4> Rm;
353
354  let Inst{11-8}  = Rd;
355  let Inst{19-16} = Rn;
356  let Inst{3-0}   = Rm;
357}
358
359class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
360           string opc, string asm, list<dag> pattern>
361  : T2I<oops, iops, itin, opc, asm, pattern> {
362  bits<4> Rd;
363  bits<4> Rn;
364  bits<12> ShiftedRm;
365
366  let Inst{11-8}  = Rd;
367  let Inst{19-16} = Rn;
368  let Inst{3-0}   = ShiftedRm{3-0};
369  let Inst{5-4}   = ShiftedRm{6-5};
370  let Inst{14-12} = ShiftedRm{11-9};
371  let Inst{7-6}   = ShiftedRm{8-7};
372}
373
374class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
375           string opc, string asm, list<dag> pattern>
376  : T2sI<oops, iops, itin, opc, asm, pattern> {
377  bits<4> Rd;
378  bits<4> Rn;
379  bits<12> ShiftedRm;
380
381  let Inst{11-8}  = Rd;
382  let Inst{19-16} = Rn;
383  let Inst{3-0}   = ShiftedRm{3-0};
384  let Inst{5-4}   = ShiftedRm{6-5};
385  let Inst{14-12} = ShiftedRm{11-9};
386  let Inst{7-6}   = ShiftedRm{8-7};
387}
388
389class T2FourReg<dag oops, dag iops, InstrItinClass itin,
390           string opc, string asm, list<dag> pattern>
391  : T2I<oops, iops, itin, opc, asm, pattern> {
392  bits<4> Rd;
393  bits<4> Rn;
394  bits<4> Rm;
395  bits<4> Ra;
396
397  let Inst{19-16} = Rn;
398  let Inst{15-12} = Ra;
399  let Inst{11-8}  = Rd;
400  let Inst{3-0}   = Rm;
401}
402
403class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
404                dag oops, dag iops, InstrItinClass itin,
405                string opc, string asm, list<dag> pattern>
406  : T2I<oops, iops, itin, opc, asm, pattern> {
407  bits<4> RdLo;
408  bits<4> RdHi;
409  bits<4> Rn;
410  bits<4> Rm;
411
412  let Inst{31-23} = 0b111110111;
413  let Inst{22-20} = opc22_20;
414  let Inst{19-16} = Rn;
415  let Inst{15-12} = RdLo;
416  let Inst{11-8}  = RdHi;
417  let Inst{7-4}   = opc7_4;
418  let Inst{3-0}   = Rm;
419}
420
421
422/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
423/// unary operation that produces a value. These are predicable and can be
424/// changed to modify CPSR.
425multiclass T2I_un_irs<bits<4> opcod, string opc,
426                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
427                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
428   // shifted imm
429   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
430                opc, "\t$Rd, $imm",
431                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
432     let isAsCheapAsAMove = Cheap;
433     let isReMaterializable = ReMat;
434     let Inst{31-27} = 0b11110;
435     let Inst{25} = 0;
436     let Inst{24-21} = opcod;
437     let Inst{19-16} = 0b1111; // Rn
438     let Inst{15} = 0;
439   }
440   // register
441   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
442                opc, ".w\t$Rd, $Rm",
443                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
444     let Inst{31-27} = 0b11101;
445     let Inst{26-25} = 0b01;
446     let Inst{24-21} = opcod;
447     let Inst{19-16} = 0b1111; // Rn
448     let Inst{14-12} = 0b000; // imm3
449     let Inst{7-6} = 0b00; // imm2
450     let Inst{5-4} = 0b00; // type
451   }
452   // shifted register
453   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
454                opc, ".w\t$Rd, $ShiftedRm",
455                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
456     let Inst{31-27} = 0b11101;
457     let Inst{26-25} = 0b01;
458     let Inst{24-21} = opcod;
459     let Inst{19-16} = 0b1111; // Rn
460   }
461}
462
463/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
464/// binary operation that produces a value. These are predicable and can be
465/// changed to modify CPSR.
466multiclass T2I_bin_irs<bits<4> opcod, string opc,
467                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
468                       PatFrag opnode, string baseOpc, bit Commutable = 0,
469                       string wide = ""> {
470   // shifted imm
471   def ri : T2sTwoRegImm<
472                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
473                 opc, "\t$Rd, $Rn, $imm",
474                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
475     let Inst{31-27} = 0b11110;
476     let Inst{25} = 0;
477     let Inst{24-21} = opcod;
478     let Inst{15} = 0;
479   }
480   // register
481   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
482                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
483                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
484     let isCommutable = Commutable;
485     let Inst{31-27} = 0b11101;
486     let Inst{26-25} = 0b01;
487     let Inst{24-21} = opcod;
488     let Inst{14-12} = 0b000; // imm3
489     let Inst{7-6} = 0b00; // imm2
490     let Inst{5-4} = 0b00; // type
491   }
492   // shifted register
493   def rs : T2sTwoRegShiftedReg<
494                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
495                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
496                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
497     let Inst{31-27} = 0b11101;
498     let Inst{26-25} = 0b01;
499     let Inst{24-21} = opcod;
500   }
501  // Assembly aliases for optional destination operand when it's the same
502  // as the source operand.
503  def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
504     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
505                                                    t2_so_imm:$imm, pred:$p,
506                                                    cc_out:$s)>,
507     Requires<[IsThumb2]>;
508  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
509     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
510                                                    rGPR:$Rm, pred:$p,
511                                                    cc_out:$s)>,
512     Requires<[IsThumb2]>;
513  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
514     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
515                                                    t2_so_reg:$shift, pred:$p,
516                                                    cc_out:$s)>,
517     Requires<[IsThumb2]>;
518}
519
520/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
521//  the ".w" suffix to indicate that they are wide.
522multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
523                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
524                         PatFrag opnode, string baseOpc, bit Commutable = 0> :
525    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
526
527/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
528/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
529/// it is equivalent to the T2I_bin_irs counterpart.
530multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
531   // shifted imm
532   def ri : T2sTwoRegImm<
533                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
534                 opc, ".w\t$Rd, $Rn, $imm",
535                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
536     let Inst{31-27} = 0b11110;
537     let Inst{25} = 0;
538     let Inst{24-21} = opcod;
539     let Inst{15} = 0;
540   }
541   // register
542   def rr : T2sThreeReg<
543                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
544                 opc, "\t$Rd, $Rn, $Rm",
545                 [/* For disassembly only; pattern left blank */]> {
546     let Inst{31-27} = 0b11101;
547     let Inst{26-25} = 0b01;
548     let Inst{24-21} = opcod;
549     let Inst{14-12} = 0b000; // imm3
550     let Inst{7-6} = 0b00; // imm2
551     let Inst{5-4} = 0b00; // type
552   }
553   // shifted register
554   def rs : T2sTwoRegShiftedReg<
555                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
556                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
557                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
558     let Inst{31-27} = 0b11101;
559     let Inst{26-25} = 0b01;
560     let Inst{24-21} = opcod;
561   }
562}
563
564/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
565/// instruction modifies the CPSR register.
566let isCodeGenOnly = 1, Defs = [CPSR] in {
567multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
568                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
569                         PatFrag opnode, bit Commutable = 0> {
570   // shifted imm
571   def ri : T2TwoRegImm<
572                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
573                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
574                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
575     let Inst{31-27} = 0b11110;
576     let Inst{25} = 0;
577     let Inst{24-21} = opcod;
578     let Inst{20} = 1; // The S bit.
579     let Inst{15} = 0;
580   }
581   // register
582   def rr : T2ThreeReg<
583                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
584                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
585                [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
586     let isCommutable = Commutable;
587     let Inst{31-27} = 0b11101;
588     let Inst{26-25} = 0b01;
589     let Inst{24-21} = opcod;
590     let Inst{20} = 1; // The S bit.
591     let Inst{14-12} = 0b000; // imm3
592     let Inst{7-6} = 0b00; // imm2
593     let Inst{5-4} = 0b00; // type
594   }
595   // shifted register
596   def rs : T2TwoRegShiftedReg<
597                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
598                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
599                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
600     let Inst{31-27} = 0b11101;
601     let Inst{26-25} = 0b01;
602     let Inst{24-21} = opcod;
603     let Inst{20} = 1; // The S bit.
604   }
605}
606}
607
608/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
609/// patterns for a binary operation that produces a value.
610multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
611                          bit Commutable = 0> {
612   // shifted imm
613   // The register-immediate version is re-materializable. This is useful
614   // in particular for taking the address of a local.
615   let isReMaterializable = 1 in {
616   def ri : T2sTwoRegImm<
617                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
618                 opc, ".w\t$Rd, $Rn, $imm",
619                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
620     let Inst{31-27} = 0b11110;
621     let Inst{25} = 0;
622     let Inst{24} = 1;
623     let Inst{23-21} = op23_21;
624     let Inst{15} = 0;
625   }
626   }
627   // 12-bit imm
628   def ri12 : T2I<
629                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
630                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
631                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
632     bits<4> Rd;
633     bits<4> Rn;
634     bits<12> imm;
635     let Inst{31-27} = 0b11110;
636     let Inst{26} = imm{11};
637     let Inst{25-24} = 0b10;
638     let Inst{23-21} = op23_21;
639     let Inst{20} = 0; // The S bit.
640     let Inst{19-16} = Rn;
641     let Inst{15} = 0;
642     let Inst{14-12} = imm{10-8};
643     let Inst{11-8} = Rd;
644     let Inst{7-0} = imm{7-0};
645   }
646   // register
647   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
648                 opc, ".w\t$Rd, $Rn, $Rm",
649                 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
650     let isCommutable = Commutable;
651     let Inst{31-27} = 0b11101;
652     let Inst{26-25} = 0b01;
653     let Inst{24} = 1;
654     let Inst{23-21} = op23_21;
655     let Inst{14-12} = 0b000; // imm3
656     let Inst{7-6} = 0b00; // imm2
657     let Inst{5-4} = 0b00; // type
658   }
659   // shifted register
660   def rs : T2sTwoRegShiftedReg<
661                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
662                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
663                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
664     let Inst{31-27} = 0b11101;
665     let Inst{26-25} = 0b01;
666     let Inst{24} = 1;
667     let Inst{23-21} = op23_21;
668   }
669}
670
671/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
672/// for a binary operation that produces a value and use the carry
673/// bit. It's not predicable.
674let Uses = [CPSR] in {
675multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
676                             bit Commutable = 0> {
677   // shifted imm
678   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
679                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
680                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
681                 Requires<[IsThumb2]> {
682     let Inst{31-27} = 0b11110;
683     let Inst{25} = 0;
684     let Inst{24-21} = opcod;
685     let Inst{15} = 0;
686   }
687   // register
688   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
689                 opc, ".w\t$Rd, $Rn, $Rm",
690                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
691                 Requires<[IsThumb2]> {
692     let isCommutable = Commutable;
693     let Inst{31-27} = 0b11101;
694     let Inst{26-25} = 0b01;
695     let Inst{24-21} = opcod;
696     let Inst{14-12} = 0b000; // imm3
697     let Inst{7-6} = 0b00; // imm2
698     let Inst{5-4} = 0b00; // type
699   }
700   // shifted register
701   def rs : T2sTwoRegShiftedReg<
702                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
703                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
704                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
705                 Requires<[IsThumb2]> {
706     let Inst{31-27} = 0b11101;
707     let Inst{26-25} = 0b01;
708     let Inst{24-21} = opcod;
709   }
710}
711}
712
713// Carry setting variants
714// NOTE: CPSR def omitted because it will be handled by the custom inserter.
715let usesCustomInserter = 1 in {
716multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
717   // shifted imm
718   def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
719                4, IIC_iALUi,
720                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
721   // register
722   def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
723                4, IIC_iALUr,
724                [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
725     let isCommutable = Commutable;
726   }
727   // shifted register
728   def rs : t2PseudoInst<
729                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
730                4, IIC_iALUsi,
731                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
732}
733}
734
735/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
736/// version is not needed since this is only for codegen.
737let isCodeGenOnly = 1, Defs = [CPSR] in {
738multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
739   // shifted imm
740   def ri : T2TwoRegImm<
741                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
742                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
743                [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
744     let Inst{31-27} = 0b11110;
745     let Inst{25} = 0;
746     let Inst{24-21} = opcod;
747     let Inst{20} = 1; // The S bit.
748     let Inst{15} = 0;
749   }
750   // shifted register
751   def rs : T2TwoRegShiftedReg<
752                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
753                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
754                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
755     let Inst{31-27} = 0b11101;
756     let Inst{26-25} = 0b01;
757     let Inst{24-21} = opcod;
758     let Inst{20} = 1; // The S bit.
759   }
760}
761}
762
763/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
764//  rotate operation that produces a value.
765multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
766   // 5-bit imm
767   def ri : T2sTwoRegShiftImm<
768                 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
769                 opc, ".w\t$Rd, $Rm, $imm",
770                 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
771     let Inst{31-27} = 0b11101;
772     let Inst{26-21} = 0b010010;
773     let Inst{19-16} = 0b1111; // Rn
774     let Inst{5-4} = opcod;
775   }
776   // register
777   def rr : T2sThreeReg<
778                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
779                 opc, ".w\t$Rd, $Rn, $Rm",
780                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
781     let Inst{31-27} = 0b11111;
782     let Inst{26-23} = 0b0100;
783     let Inst{22-21} = opcod;
784     let Inst{15-12} = 0b1111;
785     let Inst{7-4} = 0b0000;
786   }
787}
788
789/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
790/// patterns. Similar to T2I_bin_irs except the instruction does not produce
791/// a explicit result, only implicitly set CPSR.
792let isCompare = 1, Defs = [CPSR] in {
793multiclass T2I_cmp_irs<bits<4> opcod, string opc,
794                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
795                       PatFrag opnode> {
796   // shifted imm
797   def ri : T2OneRegCmpImm<
798                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
799                opc, ".w\t$Rn, $imm",
800                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
801     let Inst{31-27} = 0b11110;
802     let Inst{25} = 0;
803     let Inst{24-21} = opcod;
804     let Inst{20} = 1; // The S bit.
805     let Inst{15} = 0;
806     let Inst{11-8} = 0b1111; // Rd
807   }
808   // register
809   def rr : T2TwoRegCmp<
810                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
811                opc, ".w\t$lhs, $rhs",
812                [(opnode GPR:$lhs, rGPR:$rhs)]> {
813     let Inst{31-27} = 0b11101;
814     let Inst{26-25} = 0b01;
815     let Inst{24-21} = opcod;
816     let Inst{20} = 1; // The S bit.
817     let Inst{14-12} = 0b000; // imm3
818     let Inst{11-8} = 0b1111; // Rd
819     let Inst{7-6} = 0b00; // imm2
820     let Inst{5-4} = 0b00; // type
821   }
822   // shifted register
823   def rs : T2OneRegCmpShiftedReg<
824                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
825                opc, ".w\t$Rn, $ShiftedRm",
826                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
827     let Inst{31-27} = 0b11101;
828     let Inst{26-25} = 0b01;
829     let Inst{24-21} = opcod;
830     let Inst{20} = 1; // The S bit.
831     let Inst{11-8} = 0b1111; // Rd
832   }
833}
834}
835
836/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
837multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
838                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
839  def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
840                   opc, ".w\t$Rt, $addr",
841                   [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
842    let Inst{31-27} = 0b11111;
843    let Inst{26-25} = 0b00;
844    let Inst{24} = signed;
845    let Inst{23} = 1;
846    let Inst{22-21} = opcod;
847    let Inst{20} = 1; // load
848
849    bits<4> Rt;
850    let Inst{15-12} = Rt;
851
852    bits<17> addr;
853    let addr{12}    = 1;           // add = TRUE
854    let Inst{19-16} = addr{16-13}; // Rn
855    let Inst{23}    = addr{12};    // U
856    let Inst{11-0}  = addr{11-0};  // imm
857  }
858  def i8  : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
859                   opc, "\t$Rt, $addr",
860                   [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
861    let Inst{31-27} = 0b11111;
862    let Inst{26-25} = 0b00;
863    let Inst{24} = signed;
864    let Inst{23} = 0;
865    let Inst{22-21} = opcod;
866    let Inst{20} = 1; // load
867    let Inst{11} = 1;
868    // Offset: index==TRUE, wback==FALSE
869    let Inst{10} = 1; // The P bit.
870    let Inst{8} = 0; // The W bit.
871
872    bits<4> Rt;
873    let Inst{15-12} = Rt;
874
875    bits<13> addr;
876    let Inst{19-16} = addr{12-9}; // Rn
877    let Inst{9}     = addr{8};    // U
878    let Inst{7-0}   = addr{7-0};  // imm
879  }
880  def s   : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
881                   opc, ".w\t$Rt, $addr",
882                   [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
883    let Inst{31-27} = 0b11111;
884    let Inst{26-25} = 0b00;
885    let Inst{24} = signed;
886    let Inst{23} = 0;
887    let Inst{22-21} = opcod;
888    let Inst{20} = 1; // load
889    let Inst{11-6} = 0b000000;
890
891    bits<4> Rt;
892    let Inst{15-12} = Rt;
893
894    bits<10> addr;
895    let Inst{19-16} = addr{9-6}; // Rn
896    let Inst{3-0}   = addr{5-2}; // Rm
897    let Inst{5-4}   = addr{1-0}; // imm
898  }
899
900  // FIXME: Is the pci variant actually needed?
901  def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
902                   opc, ".w\t$Rt, $addr",
903                   [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
904    let isReMaterializable = 1;
905    let Inst{31-27} = 0b11111;
906    let Inst{26-25} = 0b00;
907    let Inst{24} = signed;
908    let Inst{23} = ?; // add = (U == '1')
909    let Inst{22-21} = opcod;
910    let Inst{20} = 1; // load
911    let Inst{19-16} = 0b1111; // Rn
912    bits<4> Rt;
913    bits<12> addr;
914    let Inst{15-12} = Rt{3-0};
915    let Inst{11-0}  = addr{11-0};
916  }
917}
918
919/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
920multiclass T2I_st<bits<2> opcod, string opc,
921                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
922  def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
923                   opc, ".w\t$Rt, $addr",
924                   [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
925    let Inst{31-27} = 0b11111;
926    let Inst{26-23} = 0b0001;
927    let Inst{22-21} = opcod;
928    let Inst{20} = 0; // !load
929
930    bits<4> Rt;
931    let Inst{15-12} = Rt;
932
933    bits<17> addr;
934    let addr{12}    = 1;           // add = TRUE
935    let Inst{19-16} = addr{16-13}; // Rn
936    let Inst{23}    = addr{12};    // U
937    let Inst{11-0}  = addr{11-0};  // imm
938  }
939  def i8  : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
940                   opc, "\t$Rt, $addr",
941                   [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
942    let Inst{31-27} = 0b11111;
943    let Inst{26-23} = 0b0000;
944    let Inst{22-21} = opcod;
945    let Inst{20} = 0; // !load
946    let Inst{11} = 1;
947    // Offset: index==TRUE, wback==FALSE
948    let Inst{10} = 1; // The P bit.
949    let Inst{8} = 0; // The W bit.
950
951    bits<4> Rt;
952    let Inst{15-12} = Rt;
953
954    bits<13> addr;
955    let Inst{19-16} = addr{12-9}; // Rn
956    let Inst{9}     = addr{8};    // U
957    let Inst{7-0}   = addr{7-0};  // imm
958  }
959  def s   : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
960                   opc, ".w\t$Rt, $addr",
961                   [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
962    let Inst{31-27} = 0b11111;
963    let Inst{26-23} = 0b0000;
964    let Inst{22-21} = opcod;
965    let Inst{20} = 0; // !load
966    let Inst{11-6} = 0b000000;
967
968    bits<4> Rt;
969    let Inst{15-12} = Rt;
970
971    bits<10> addr;
972    let Inst{19-16}   = addr{9-6}; // Rn
973    let Inst{3-0} = addr{5-2}; // Rm
974    let Inst{5-4}   = addr{1-0}; // imm
975  }
976}
977
978/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
979/// register and one whose operand is a register rotated by 8/16/24.
980multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
981  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
982                  opc, ".w\t$Rd, $Rm",
983                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
984     let Inst{31-27} = 0b11111;
985     let Inst{26-23} = 0b0100;
986     let Inst{22-20} = opcod;
987     let Inst{19-16} = 0b1111; // Rn
988     let Inst{15-12} = 0b1111;
989     let Inst{7} = 1;
990     let Inst{5-4} = 0b00; // rotate
991   }
992  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
993                  opc, ".w\t$Rd, $Rm$rot",
994                 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
995     let Inst{31-27} = 0b11111;
996     let Inst{26-23} = 0b0100;
997     let Inst{22-20} = opcod;
998     let Inst{19-16} = 0b1111; // Rn
999     let Inst{15-12} = 0b1111;
1000     let Inst{7} = 1;
1001
1002     bits<2> rot;
1003     let Inst{5-4} = rot{1-0}; // rotate
1004   }
1005}
1006
1007// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1008multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1009  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1010                  opc, "\t$Rd, $Rm",
1011                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1012                 Requires<[HasT2ExtractPack, IsThumb2]> {
1013     let Inst{31-27} = 0b11111;
1014     let Inst{26-23} = 0b0100;
1015     let Inst{22-20} = opcod;
1016     let Inst{19-16} = 0b1111; // Rn
1017     let Inst{15-12} = 0b1111;
1018     let Inst{7} = 1;
1019     let Inst{5-4} = 0b00; // rotate
1020   }
1021  def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1022                  IIC_iEXTr, opc, "\t$dst, $Rm$rot",
1023                 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1024                 Requires<[HasT2ExtractPack, IsThumb2]> {
1025     let Inst{31-27} = 0b11111;
1026     let Inst{26-23} = 0b0100;
1027     let Inst{22-20} = opcod;
1028     let Inst{19-16} = 0b1111; // Rn
1029     let Inst{15-12} = 0b1111;
1030     let Inst{7} = 1;
1031
1032     bits<2> rot;
1033     let Inst{5-4} = rot{1-0}; // rotate
1034   }
1035}
1036
1037// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1038// supported yet.
1039multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1040  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1041                  opc, "\t$Rd, $Rm", []>,
1042          Requires<[IsThumb2, HasT2ExtractPack]> {
1043     let Inst{31-27} = 0b11111;
1044     let Inst{26-23} = 0b0100;
1045     let Inst{22-20} = opcod;
1046     let Inst{19-16} = 0b1111; // Rn
1047     let Inst{15-12} = 0b1111;
1048     let Inst{7} = 1;
1049     let Inst{5-4} = 0b00; // rotate
1050   }
1051  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1052                  opc, "\t$Rd, $Rm, ror $rot", []>,
1053          Requires<[IsThumb2, HasT2ExtractPack]> {
1054     let Inst{31-27} = 0b11111;
1055     let Inst{26-23} = 0b0100;
1056     let Inst{22-20} = opcod;
1057     let Inst{19-16} = 0b1111; // Rn
1058     let Inst{15-12} = 0b1111;
1059     let Inst{7} = 1;
1060
1061      bits<2> rot;
1062      let Inst{5-4} = rot{1-0}; // rotate
1063   }
1064}
1065
1066/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1067/// register and one whose operand is a register rotated by 8/16/24.
1068multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1069  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1070                  opc, "\t$Rd, $Rn, $Rm",
1071                  [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1072                  Requires<[HasT2ExtractPack, IsThumb2]> {
1073     let Inst{31-27} = 0b11111;
1074     let Inst{26-23} = 0b0100;
1075     let Inst{22-20} = opcod;
1076     let Inst{15-12} = 0b1111;
1077     let Inst{7} = 1;
1078     let Inst{5-4} = 0b00; // rotate
1079   }
1080  def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1081                  (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1082                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot",
1083                  [(set rGPR:$Rd, (opnode rGPR:$Rn,
1084                                          (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1085                  Requires<[HasT2ExtractPack, IsThumb2]> {
1086     let Inst{31-27} = 0b11111;
1087     let Inst{26-23} = 0b0100;
1088     let Inst{22-20} = opcod;
1089     let Inst{15-12} = 0b1111;
1090     let Inst{7} = 1;
1091
1092     bits<2> rot;
1093     let Inst{5-4} = rot{1-0}; // rotate
1094   }
1095}
1096
1097multiclass T2I_exta_rrot_np<bits<3> opcod, string opc> {
1098  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1099                  opc, "\t$Rd, $Rn, $Rm", []> {
1100     let Inst{31-27} = 0b11111;
1101     let Inst{26-23} = 0b0100;
1102     let Inst{22-20} = opcod;
1103     let Inst{15-12} = 0b1111;
1104     let Inst{7} = 1;
1105     let Inst{5-4} = 0b00; // rotate
1106   }
1107  def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot),
1108                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> {
1109     let Inst{31-27} = 0b11111;
1110     let Inst{26-23} = 0b0100;
1111     let Inst{22-20} = opcod;
1112     let Inst{15-12} = 0b1111;
1113     let Inst{7} = 1;
1114
1115     bits<2> rot;
1116     let Inst{5-4} = rot{1-0}; // rotate
1117   }
1118}
1119
1120//===----------------------------------------------------------------------===//
1121// Instructions
1122//===----------------------------------------------------------------------===//
1123
1124//===----------------------------------------------------------------------===//
1125//  Miscellaneous Instructions.
1126//
1127
1128class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1129           string asm, list<dag> pattern>
1130  : T2XI<oops, iops, itin, asm, pattern> {
1131  bits<4> Rd;
1132  bits<12> label;
1133
1134  let Inst{11-8}  = Rd;
1135  let Inst{26}    = label{11};
1136  let Inst{14-12} = label{10-8};
1137  let Inst{7-0}   = label{7-0};
1138}
1139
1140// LEApcrel - Load a pc-relative address into a register without offending the
1141// assembler.
1142def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1143              (ins t2adrlabel:$addr, pred:$p),
1144              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1145  let Inst{31-27} = 0b11110;
1146  let Inst{25-24} = 0b10;
1147  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1148  let Inst{22} = 0;
1149  let Inst{20} = 0;
1150  let Inst{19-16} = 0b1111; // Rn
1151  let Inst{15} = 0;
1152
1153  bits<4> Rd;
1154  bits<13> addr;
1155  let Inst{11-8} = Rd;
1156  let Inst{23}    = addr{12};
1157  let Inst{21}    = addr{12};
1158  let Inst{26}    = addr{11};
1159  let Inst{14-12} = addr{10-8};
1160  let Inst{7-0}   = addr{7-0};
1161}
1162
1163let neverHasSideEffects = 1, isReMaterializable = 1 in
1164def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1165                                4, IIC_iALUi, []>;
1166def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1167                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
1168                                4, IIC_iALUi,
1169                                []>;
1170
1171
1172//===----------------------------------------------------------------------===//
1173//  Load / store Instructions.
1174//
1175
1176// Load
1177let canFoldAsLoad = 1, isReMaterializable = 1  in
1178defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1179                      UnOpFrag<(load node:$Src)>>;
1180
1181// Loads with zero extension
1182defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1183                      UnOpFrag<(zextloadi16 node:$Src)>>;
1184defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1185                      UnOpFrag<(zextloadi8  node:$Src)>>;
1186
1187// Loads with sign extension
1188defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1189                      UnOpFrag<(sextloadi16 node:$Src)>>;
1190defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1191                      UnOpFrag<(sextloadi8  node:$Src)>>;
1192
1193let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1194// Load doubleword
1195def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1196                        (ins t2addrmode_imm8s4:$addr),
1197                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1198} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1199
1200// zextload i1 -> zextload i8
1201def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1202            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1203def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1204            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1205def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1206            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1207def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1208            (t2LDRBpci  tconstpool:$addr)>;
1209
1210// extload -> zextload
1211// FIXME: Reduce the number of patterns by legalizing extload to zextload
1212// earlier?
1213def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1214            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1215def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1216            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1217def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1218            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1219def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1220            (t2LDRBpci  tconstpool:$addr)>;
1221
1222def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1223            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1224def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1225            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1226def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1227            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1228def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1229            (t2LDRBpci  tconstpool:$addr)>;
1230
1231def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1232            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1233def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1234            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1235def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1236            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1237def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1238            (t2LDRHpci  tconstpool:$addr)>;
1239
1240// FIXME: The destination register of the loads and stores can't be PC, but
1241//        can be SP. We need another regclass (similar to rGPR) to represent
1242//        that. Not a pressing issue since these are selected manually,
1243//        not via pattern.
1244
1245// Indexed loads
1246
1247let mayLoad = 1, neverHasSideEffects = 1 in {
1248def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1249                            (ins t2addrmode_imm8:$addr),
1250                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1251                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1252                            []>;
1253
1254def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1255                            (ins GPR:$base, t2am_imm8_offset:$addr),
1256                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1257                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1258                            []>;
1259
1260def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1261                            (ins t2addrmode_imm8:$addr),
1262                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1263                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1264                            []>;
1265def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1266                            (ins GPR:$base, t2am_imm8_offset:$addr),
1267                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1268                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1269                            []>;
1270
1271def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1272                            (ins t2addrmode_imm8:$addr),
1273                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1274                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1275                            []>;
1276def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1277                            (ins GPR:$base, t2am_imm8_offset:$addr),
1278                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1279                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1280                            []>;
1281
1282def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1283                            (ins t2addrmode_imm8:$addr),
1284                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1285                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1286                            []>;
1287def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1288                            (ins GPR:$base, t2am_imm8_offset:$addr),
1289                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1290                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1291                            []>;
1292
1293def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1294                            (ins t2addrmode_imm8:$addr),
1295                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1296                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1297                            []>;
1298def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1299                            (ins GPR:$base, t2am_imm8_offset:$addr),
1300                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1301                        "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1302                            []>;
1303} // mayLoad = 1, neverHasSideEffects = 1
1304
1305// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1306// for disassembly only.
1307// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1308class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1309  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1310          "\t$Rt, $addr", []> {
1311  let Inst{31-27} = 0b11111;
1312  let Inst{26-25} = 0b00;
1313  let Inst{24} = signed;
1314  let Inst{23} = 0;
1315  let Inst{22-21} = type;
1316  let Inst{20} = 1; // load
1317  let Inst{11} = 1;
1318  let Inst{10-8} = 0b110; // PUW.
1319
1320  bits<4> Rt;
1321  bits<13> addr;
1322  let Inst{15-12} = Rt;
1323  let Inst{19-16} = addr{12-9};
1324  let Inst{7-0}   = addr{7-0};
1325}
1326
1327def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1328def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1329def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1330def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1331def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1332
1333// Store
1334defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1335                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1336defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1337                   BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1338defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1339                   BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1340
1341// Store doubleword
1342let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1343def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1344                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1345               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1346
1347// Indexed stores
1348def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1349                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1350                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1351                         "str", "\t$Rt, [$Rn, $addr]!",
1352                         "$Rn = $base_wb,@earlyclobber $base_wb",
1353             [(set GPR:$base_wb,
1354                   (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1355
1356def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1357                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1358                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1359                          "str", "\t$Rt, [$Rn], $addr",
1360                          "$Rn = $base_wb,@earlyclobber $base_wb",
1361             [(set GPR:$base_wb,
1362                  (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1363
1364def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1365                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1366                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1367                        "strh", "\t$Rt, [$Rn, $addr]!",
1368                        "$Rn = $base_wb,@earlyclobber $base_wb",
1369        [(set GPR:$base_wb,
1370              (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1371
1372def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1373                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1374                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1375                         "strh", "\t$Rt, [$Rn], $addr",
1376                         "$Rn = $base_wb,@earlyclobber $base_wb",
1377       [(set GPR:$base_wb,
1378             (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1379
1380def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1381                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1382                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1383                        "strb", "\t$Rt, [$Rn, $addr]!",
1384                        "$Rn = $base_wb,@earlyclobber $base_wb",
1385         [(set GPR:$base_wb,
1386               (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1387
1388def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1389                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1390                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1391                         "strb", "\t$Rt, [$Rn], $addr",
1392                         "$Rn = $base_wb,@earlyclobber $base_wb",
1393        [(set GPR:$base_wb,
1394              (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1395
1396// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1397// only.
1398// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1399class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1400  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1401          "\t$Rt, $addr", []> {
1402  let Inst{31-27} = 0b11111;
1403  let Inst{26-25} = 0b00;
1404  let Inst{24} = 0; // not signed
1405  let Inst{23} = 0;
1406  let Inst{22-21} = type;
1407  let Inst{20} = 0; // store
1408  let Inst{11} = 1;
1409  let Inst{10-8} = 0b110; // PUW
1410
1411  bits<4> Rt;
1412  bits<13> addr;
1413  let Inst{15-12} = Rt;
1414  let Inst{19-16} = addr{12-9};
1415  let Inst{7-0}   = addr{7-0};
1416}
1417
1418def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1419def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1420def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1421
1422// ldrd / strd pre / post variants
1423// For disassembly only.
1424
1425def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1426                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1427                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1428
1429def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1430                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1431                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1432
1433def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs),
1434                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1435                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1436
1437def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1438                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1439                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1440
1441// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1442// data/instruction access.  These are for disassembly only.
1443// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1444// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1445multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1446
1447  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1448                "\t$addr",
1449              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1450    let Inst{31-25} = 0b1111100;
1451    let Inst{24} = instr;
1452    let Inst{22} = 0;
1453    let Inst{21} = write;
1454    let Inst{20} = 1;
1455    let Inst{15-12} = 0b1111;
1456
1457    bits<17> addr;
1458    let addr{12}    = 1;           // add = TRUE
1459    let Inst{19-16} = addr{16-13}; // Rn
1460    let Inst{23}    = addr{12};    // U
1461    let Inst{11-0}  = addr{11-0};  // imm12
1462  }
1463
1464  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1465                "\t$addr",
1466               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1467    let Inst{31-25} = 0b1111100;
1468    let Inst{24} = instr;
1469    let Inst{23} = 0; // U = 0
1470    let Inst{22} = 0;
1471    let Inst{21} = write;
1472    let Inst{20} = 1;
1473    let Inst{15-12} = 0b1111;
1474    let Inst{11-8} = 0b1100;
1475
1476    bits<13> addr;
1477    let Inst{19-16} = addr{12-9}; // Rn
1478    let Inst{7-0}   = addr{7-0};  // imm8
1479  }
1480
1481  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1482               "\t$addr",
1483             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1484    let Inst{31-25} = 0b1111100;
1485    let Inst{24} = instr;
1486    let Inst{23} = 0; // add = TRUE for T1
1487    let Inst{22} = 0;
1488    let Inst{21} = write;
1489    let Inst{20} = 1;
1490    let Inst{15-12} = 0b1111;
1491    let Inst{11-6} = 0000000;
1492
1493    bits<10> addr;
1494    let Inst{19-16} = addr{9-6}; // Rn
1495    let Inst{3-0}   = addr{5-2}; // Rm
1496    let Inst{5-4}   = addr{1-0}; // imm2
1497  }
1498}
1499
1500defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1501defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1502defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1503
1504//===----------------------------------------------------------------------===//
1505//  Load / store multiple Instructions.
1506//
1507
1508multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1509                            InstrItinClass itin_upd, bit L_bit> {
1510  def IA :
1511    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1512         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1513    bits<4>  Rn;
1514    bits<16> regs;
1515
1516    let Inst{31-27} = 0b11101;
1517    let Inst{26-25} = 0b00;
1518    let Inst{24-23} = 0b01;     // Increment After
1519    let Inst{22}    = 0;
1520    let Inst{21}    = 0;        // No writeback
1521    let Inst{20}    = L_bit;
1522    let Inst{19-16} = Rn;
1523    let Inst{15-0}  = regs;
1524  }
1525  def IA_UPD :
1526    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1527          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1528    bits<4>  Rn;
1529    bits<16> regs;
1530
1531    let Inst{31-27} = 0b11101;
1532    let Inst{26-25} = 0b00;
1533    let Inst{24-23} = 0b01;     // Increment After
1534    let Inst{22}    = 0;
1535    let Inst{21}    = 1;        // Writeback
1536    let Inst{20}    = L_bit;
1537    let Inst{19-16} = Rn;
1538    let Inst{15-0}  = regs;
1539  }
1540  def DB :
1541    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1542         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1543    bits<4>  Rn;
1544    bits<16> regs;
1545
1546    let Inst{31-27} = 0b11101;
1547    let Inst{26-25} = 0b00;
1548    let Inst{24-23} = 0b10;     // Decrement Before
1549    let Inst{22}    = 0;
1550    let Inst{21}    = 0;        // No writeback
1551    let Inst{20}    = L_bit;
1552    let Inst{19-16} = Rn;
1553    let Inst{15-0}  = regs;
1554  }
1555  def DB_UPD :
1556    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1557          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1558    bits<4>  Rn;
1559    bits<16> regs;
1560
1561    let Inst{31-27} = 0b11101;
1562    let Inst{26-25} = 0b00;
1563    let Inst{24-23} = 0b10;     // Decrement Before
1564    let Inst{22}    = 0;
1565    let Inst{21}    = 1;        // Writeback
1566    let Inst{20}    = L_bit;
1567    let Inst{19-16} = Rn;
1568    let Inst{15-0}  = regs;
1569  }
1570}
1571
1572let neverHasSideEffects = 1 in {
1573
1574let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1575defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1576
1577let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1578defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1579
1580} // neverHasSideEffects
1581
1582
1583//===----------------------------------------------------------------------===//
1584//  Move Instructions.
1585//
1586
1587let neverHasSideEffects = 1 in
1588def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1589                   "mov", ".w\t$Rd, $Rm", []> {
1590  let Inst{31-27} = 0b11101;
1591  let Inst{26-25} = 0b01;
1592  let Inst{24-21} = 0b0010;
1593  let Inst{19-16} = 0b1111; // Rn
1594  let Inst{14-12} = 0b000;
1595  let Inst{7-4} = 0b0000;
1596}
1597
1598// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1599let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1600    AddedComplexity = 1 in
1601def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1602                   "mov", ".w\t$Rd, $imm",
1603                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1604  let Inst{31-27} = 0b11110;
1605  let Inst{25} = 0;
1606  let Inst{24-21} = 0b0010;
1607  let Inst{19-16} = 0b1111; // Rn
1608  let Inst{15} = 0;
1609}
1610
1611def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1612                                                 pred:$p, cc_out:$s)>,
1613                Requires<[IsThumb2]>;
1614
1615let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1616def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
1617                   "movw", "\t$Rd, $imm",
1618                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1619  let Inst{31-27} = 0b11110;
1620  let Inst{25} = 1;
1621  let Inst{24-21} = 0b0010;
1622  let Inst{20} = 0; // The S bit.
1623  let Inst{15} = 0;
1624
1625  bits<4> Rd;
1626  bits<16> imm;
1627
1628  let Inst{11-8}  = Rd;
1629  let Inst{19-16} = imm{15-12};
1630  let Inst{26}    = imm{11};
1631  let Inst{14-12} = imm{10-8};
1632  let Inst{7-0}   = imm{7-0};
1633}
1634
1635def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1636                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1637
1638let Constraints = "$src = $Rd" in {
1639def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1640                    (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
1641                    "movt", "\t$Rd, $imm",
1642                    [(set rGPR:$Rd,
1643                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1644  let Inst{31-27} = 0b11110;
1645  let Inst{25} = 1;
1646  let Inst{24-21} = 0b0110;
1647  let Inst{20} = 0; // The S bit.
1648  let Inst{15} = 0;
1649
1650  bits<4> Rd;
1651  bits<16> imm;
1652
1653  let Inst{11-8}  = Rd;
1654  let Inst{19-16} = imm{15-12};
1655  let Inst{26}    = imm{11};
1656  let Inst{14-12} = imm{10-8};
1657  let Inst{7-0}   = imm{7-0};
1658}
1659
1660def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1661                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1662} // Constraints
1663
1664def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1665
1666//===----------------------------------------------------------------------===//
1667//  Extend Instructions.
1668//
1669
1670// Sign extenders
1671
1672defm t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1673                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1674defm t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1675                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1676defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1677
1678defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1679                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1680defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1681                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1682defm t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
1683
1684// TODO: SXT(A){B|H}16 - done for disassembly only
1685
1686// Zero extenders
1687
1688let AddedComplexity = 16 in {
1689defm t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1690                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1691defm t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1692                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1693defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1694                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1695
1696// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1697//        The transformation should probably be done as a combiner action
1698//        instead so we can include a check for masking back in the upper
1699//        eight bits of the source into the lower eight bits of the result.
1700//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1701//            (t2UXTB16r_rot rGPR:$Src, 3)>,
1702//          Requires<[HasT2ExtractPack, IsThumb2]>;
1703def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1704            (t2UXTB16r_rot rGPR:$Src, 1)>,
1705        Requires<[HasT2ExtractPack, IsThumb2]>;
1706
1707defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1708                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1709defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1710                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1711defm t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">;
1712}
1713
1714//===----------------------------------------------------------------------===//
1715//  Arithmetic Instructions.
1716//
1717
1718defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1719                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1720defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1721                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1722
1723// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1724defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1725                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1726                             BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1727defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1728                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1729                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1730
1731defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1732                          BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1733defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1734                          BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1735defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1736                                                             node:$RHS)>, 1>;
1737defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1738                                                             node:$RHS)>>;
1739
1740// RSB
1741defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1742                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1743defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1744                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1745
1746// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1747// The assume-no-carry-in form uses the negation of the input since add/sub
1748// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1749// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1750// details.
1751// The AddedComplexity preferences the first variant over the others since
1752// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1753let AddedComplexity = 1 in
1754def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1755            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1756def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1757            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1758def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1759            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1760let AddedComplexity = 1 in
1761def : T2Pat<(addc       rGPR:$src, imm0_255_neg:$imm),
1762            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1763def : T2Pat<(addc       rGPR:$src, t2_so_imm_neg:$imm),
1764            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1765// The with-carry-in form matches bitwise not instead of the negation.
1766// Effectively, the inverse interpretation of the carry flag already accounts
1767// for part of the negation.
1768let AddedComplexity = 1 in
1769def : T2Pat<(adde_dead_carry       rGPR:$src, imm0_255_not:$imm),
1770            (t2SBCri    rGPR:$src, imm0_255_not:$imm)>;
1771def : T2Pat<(adde_dead_carry       rGPR:$src, t2_so_imm_not:$imm),
1772            (t2SBCri    rGPR:$src, t2_so_imm_not:$imm)>;
1773let AddedComplexity = 1 in
1774def : T2Pat<(adde_live_carry       rGPR:$src, imm0_255_not:$imm),
1775            (t2SBCSri   rGPR:$src, imm0_255_not:$imm)>;
1776def : T2Pat<(adde_live_carry       rGPR:$src, t2_so_imm_not:$imm),
1777            (t2SBCSri   rGPR:$src, t2_so_imm_not:$imm)>;
1778
1779// Select Bytes -- for disassembly only
1780
1781def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1782                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
1783          Requires<[IsThumb2, HasThumb2DSP]> {
1784  let Inst{31-27} = 0b11111;
1785  let Inst{26-24} = 0b010;
1786  let Inst{23} = 0b1;
1787  let Inst{22-20} = 0b010;
1788  let Inst{15-12} = 0b1111;
1789  let Inst{7} = 0b1;
1790  let Inst{6-4} = 0b000;
1791}
1792
1793// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1794// And Miscellaneous operations -- for disassembly only
1795class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1796              list<dag> pat = [/* For disassembly only; pattern left blank */],
1797              dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1798              string asm = "\t$Rd, $Rn, $Rm">
1799  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
1800    Requires<[IsThumb2, HasThumb2DSP]> {
1801  let Inst{31-27} = 0b11111;
1802  let Inst{26-23} = 0b0101;
1803  let Inst{22-20} = op22_20;
1804  let Inst{15-12} = 0b1111;
1805  let Inst{7-4} = op7_4;
1806
1807  bits<4> Rd;
1808  bits<4> Rn;
1809  bits<4> Rm;
1810
1811  let Inst{11-8}  = Rd;
1812  let Inst{19-16} = Rn;
1813  let Inst{3-0}   = Rm;
1814}
1815
1816// Saturating add/subtract -- for disassembly only
1817
1818def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1819                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1820                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1821def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1822def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1823def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1824def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd", [],
1825                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1826def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub", [],
1827                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1828def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1829def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1830                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1831                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1832def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1833def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1834def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1835def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1836def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1837def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1838def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1839def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1840
1841// Signed/Unsigned add/subtract -- for disassembly only
1842
1843def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1844def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1845def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1846def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1847def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1848def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1849def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1850def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1851def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1852def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1853def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1854def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1855
1856// Signed/Unsigned halving add/subtract -- for disassembly only
1857
1858def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1859def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1860def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1861def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1862def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1863def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1864def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1865def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1866def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1867def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1868def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1869def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1870
1871// Helper class for disassembly only
1872// A6.3.16 & A6.3.17
1873// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1874class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1875  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1876  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1877  let Inst{31-27} = 0b11111;
1878  let Inst{26-24} = 0b011;
1879  let Inst{23}    = long;
1880  let Inst{22-20} = op22_20;
1881  let Inst{7-4}   = op7_4;
1882}
1883
1884class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1885  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1886  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1887  let Inst{31-27} = 0b11111;
1888  let Inst{26-24} = 0b011;
1889  let Inst{23}    = long;
1890  let Inst{22-20} = op22_20;
1891  let Inst{7-4}   = op7_4;
1892}
1893
1894// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1895
1896def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1897                                           (ins rGPR:$Rn, rGPR:$Rm),
1898                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
1899          Requires<[IsThumb2, HasThumb2DSP]> {
1900  let Inst{15-12} = 0b1111;
1901}
1902def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1903                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1904                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
1905          Requires<[IsThumb2, HasThumb2DSP]>;
1906
1907// Signed/Unsigned saturate -- for disassembly only
1908
1909class T2SatI<dag oops, dag iops, InstrItinClass itin,
1910           string opc, string asm, list<dag> pattern>
1911  : T2I<oops, iops, itin, opc, asm, pattern> {
1912  bits<4> Rd;
1913  bits<4> Rn;
1914  bits<5> sat_imm;
1915  bits<7> sh;
1916
1917  let Inst{11-8}  = Rd;
1918  let Inst{19-16} = Rn;
1919  let Inst{4-0}   = sat_imm;
1920  let Inst{21}    = sh{5};
1921  let Inst{14-12} = sh{4-2};
1922  let Inst{7-6}   = sh{1-0};
1923}
1924
1925def t2SSAT: T2SatI<
1926              (outs rGPR:$Rd), (ins imm1_32:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1927              NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1928              [/* For disassembly only; pattern left blank */]> {
1929  let Inst{31-27} = 0b11110;
1930  let Inst{25-22} = 0b1100;
1931  let Inst{20} = 0;
1932  let Inst{15} = 0;
1933}
1934
1935def t2SSAT16: T2SatI<
1936                (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary,
1937                "ssat16", "\t$Rd, $sat_imm, $Rn",
1938                [/* For disassembly only; pattern left blank */]>,
1939          Requires<[IsThumb2, HasThumb2DSP]> {
1940  let Inst{31-27} = 0b11110;
1941  let Inst{25-22} = 0b1100;
1942  let Inst{20} = 0;
1943  let Inst{15} = 0;
1944  let Inst{21} = 1;        // sh = '1'
1945  let Inst{14-12} = 0b000; // imm3 = '000'
1946  let Inst{7-6} = 0b00;    // imm2 = '00'
1947}
1948
1949def t2USAT: T2SatI<
1950                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1951                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1952                [/* For disassembly only; pattern left blank */]> {
1953  let Inst{31-27} = 0b11110;
1954  let Inst{25-22} = 0b1110;
1955  let Inst{20} = 0;
1956  let Inst{15} = 0;
1957}
1958
1959def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
1960                     NoItinerary,
1961                     "usat16", "\t$dst, $sat_imm, $Rn",
1962                     [/* For disassembly only; pattern left blank */]>,
1963          Requires<[IsThumb2, HasThumb2DSP]> {
1964  let Inst{31-27} = 0b11110;
1965  let Inst{25-22} = 0b1110;
1966  let Inst{20} = 0;
1967  let Inst{15} = 0;
1968  let Inst{21} = 1;        // sh = '1'
1969  let Inst{14-12} = 0b000; // imm3 = '000'
1970  let Inst{7-6} = 0b00;    // imm2 = '00'
1971}
1972
1973def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1974def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1975
1976//===----------------------------------------------------------------------===//
1977//  Shift and rotate Instructions.
1978//
1979
1980defm t2LSL  : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
1981defm t2LSR  : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl  node:$LHS, node:$RHS)>>;
1982defm t2ASR  : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
1983defm t2ROR  : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1984
1985// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1986def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1987          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1988
1989let Uses = [CPSR] in {
1990def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1991                   "rrx", "\t$Rd, $Rm",
1992                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1993  let Inst{31-27} = 0b11101;
1994  let Inst{26-25} = 0b01;
1995  let Inst{24-21} = 0b0010;
1996  let Inst{19-16} = 0b1111; // Rn
1997  let Inst{14-12} = 0b000;
1998  let Inst{7-4} = 0b0011;
1999}
2000}
2001
2002let isCodeGenOnly = 1, Defs = [CPSR] in {
2003def t2MOVsrl_flag : T2TwoRegShiftImm<
2004                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2005                        "lsrs", ".w\t$Rd, $Rm, #1",
2006                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2007  let Inst{31-27} = 0b11101;
2008  let Inst{26-25} = 0b01;
2009  let Inst{24-21} = 0b0010;
2010  let Inst{20} = 1; // The S bit.
2011  let Inst{19-16} = 0b1111; // Rn
2012  let Inst{5-4} = 0b01; // Shift type.
2013  // Shift amount = Inst{14-12:7-6} = 1.
2014  let Inst{14-12} = 0b000;
2015  let Inst{7-6} = 0b01;
2016}
2017def t2MOVsra_flag : T2TwoRegShiftImm<
2018                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2019                        "asrs", ".w\t$Rd, $Rm, #1",
2020                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2021  let Inst{31-27} = 0b11101;
2022  let Inst{26-25} = 0b01;
2023  let Inst{24-21} = 0b0010;
2024  let Inst{20} = 1; // The S bit.
2025  let Inst{19-16} = 0b1111; // Rn
2026  let Inst{5-4} = 0b10; // Shift type.
2027  // Shift amount = Inst{14-12:7-6} = 1.
2028  let Inst{14-12} = 0b000;
2029  let Inst{7-6} = 0b01;
2030}
2031}
2032
2033//===----------------------------------------------------------------------===//
2034//  Bitwise Instructions.
2035//
2036
2037defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2038                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2039                            BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2040defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
2041                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2042                            BinOpFrag<(or  node:$LHS, node:$RHS)>, "t2ORR", 1>;
2043defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
2044                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2045                            BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2046
2047defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
2048                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2049                            BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2050                            "t2BIC">;
2051
2052class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2053              string opc, string asm, list<dag> pattern>
2054    : T2I<oops, iops, itin, opc, asm, pattern> {
2055  bits<4> Rd;
2056  bits<5> msb;
2057  bits<5> lsb;
2058
2059  let Inst{11-8}  = Rd;
2060  let Inst{4-0}   = msb{4-0};
2061  let Inst{14-12} = lsb{4-2};
2062  let Inst{7-6}   = lsb{1-0};
2063}
2064
2065class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2066              string opc, string asm, list<dag> pattern>
2067    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2068  bits<4> Rn;
2069
2070  let Inst{19-16} = Rn;
2071}
2072
2073let Constraints = "$src = $Rd" in
2074def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2075                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2076                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2077  let Inst{31-27} = 0b11110;
2078  let Inst{26} = 0; // should be 0.
2079  let Inst{25} = 1;
2080  let Inst{24-20} = 0b10110;
2081  let Inst{19-16} = 0b1111; // Rn
2082  let Inst{15} = 0;
2083  let Inst{5} = 0; // should be 0.
2084
2085  bits<10> imm;
2086  let msb{4-0} = imm{9-5};
2087  let lsb{4-0} = imm{4-0};
2088}
2089
2090def t2SBFX: T2TwoRegBitFI<
2091                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2092                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2093  let Inst{31-27} = 0b11110;
2094  let Inst{25} = 1;
2095  let Inst{24-20} = 0b10100;
2096  let Inst{15} = 0;
2097}
2098
2099def t2UBFX: T2TwoRegBitFI<
2100                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2101                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2102  let Inst{31-27} = 0b11110;
2103  let Inst{25} = 1;
2104  let Inst{24-20} = 0b11100;
2105  let Inst{15} = 0;
2106}
2107
2108// A8.6.18  BFI - Bitfield insert (Encoding T1)
2109let Constraints = "$src = $Rd" in {
2110  def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2111                  (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2112                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2113                  [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2114                                   bf_inv_mask_imm:$imm))]> {
2115    let Inst{31-27} = 0b11110;
2116    let Inst{26} = 0; // should be 0.
2117    let Inst{25} = 1;
2118    let Inst{24-20} = 0b10110;
2119    let Inst{15} = 0;
2120    let Inst{5} = 0; // should be 0.
2121
2122    bits<10> imm;
2123    let msb{4-0} = imm{9-5};
2124    let lsb{4-0} = imm{4-0};
2125  }
2126
2127  // GNU as only supports this form of bfi (w/ 4 arguments)
2128  let isAsmParserOnly = 1 in
2129  def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2130                  (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2131                       width_imm:$width),
2132                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2133                  []> {
2134    let Inst{31-27} = 0b11110;
2135    let Inst{26} = 0; // should be 0.
2136    let Inst{25} = 1;
2137    let Inst{24-20} = 0b10110;
2138    let Inst{15} = 0;
2139    let Inst{5} = 0; // should be 0.
2140
2141    bits<5> lsbit;
2142    bits<5> width;
2143    let msb{4-0} = width; // Custom encoder => lsb+width-1
2144    let lsb{4-0} = lsbit;
2145  }
2146}
2147
2148defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2149                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2150                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>,
2151                          "t2ORN", 0, "">;
2152
2153// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2154let AddedComplexity = 1 in
2155defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2156                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2157                          UnOpFrag<(not node:$Src)>, 1, 1>;
2158
2159
2160let AddedComplexity = 1 in
2161def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2162            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2163
2164// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2165def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2166            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2167            Requires<[IsThumb2]>;
2168
2169def : T2Pat<(t2_so_imm_not:$src),
2170            (t2MVNi t2_so_imm_not:$src)>;
2171
2172//===----------------------------------------------------------------------===//
2173//  Multiply Instructions.
2174//
2175let isCommutable = 1 in
2176def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2177                "mul", "\t$Rd, $Rn, $Rm",
2178                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2179  let Inst{31-27} = 0b11111;
2180  let Inst{26-23} = 0b0110;
2181  let Inst{22-20} = 0b000;
2182  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2183  let Inst{7-4} = 0b0000; // Multiply
2184}
2185
2186def t2MLA: T2FourReg<
2187                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2188                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2189                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2190  let Inst{31-27} = 0b11111;
2191  let Inst{26-23} = 0b0110;
2192  let Inst{22-20} = 0b000;
2193  let Inst{7-4} = 0b0000; // Multiply
2194}
2195
2196def t2MLS: T2FourReg<
2197                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2198                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2199                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2200  let Inst{31-27} = 0b11111;
2201  let Inst{26-23} = 0b0110;
2202  let Inst{22-20} = 0b000;
2203  let Inst{7-4} = 0b0001; // Multiply and Subtract
2204}
2205
2206// Extra precision multiplies with low / high results
2207let neverHasSideEffects = 1 in {
2208let isCommutable = 1 in {
2209def t2SMULL : T2MulLong<0b000, 0b0000,
2210                  (outs rGPR:$Rd, rGPR:$Ra),
2211                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2212                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2213
2214def t2UMULL : T2MulLong<0b010, 0b0000,
2215                  (outs rGPR:$RdLo, rGPR:$RdHi),
2216                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2217                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2218} // isCommutable
2219
2220// Multiply + accumulate
2221def t2SMLAL : T2MulLong<0b100, 0b0000,
2222                  (outs rGPR:$RdLo, rGPR:$RdHi),
2223                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2224                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2225
2226def t2UMLAL : T2MulLong<0b110, 0b0000,
2227                  (outs rGPR:$RdLo, rGPR:$RdHi),
2228                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2229                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2230
2231def t2UMAAL : T2MulLong<0b110, 0b0110,
2232                  (outs rGPR:$RdLo, rGPR:$RdHi),
2233                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2234                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2235          Requires<[IsThumb2, HasThumb2DSP]>;
2236} // neverHasSideEffects
2237
2238// Rounding variants of the below included for disassembly only
2239
2240// Most significant word multiply
2241def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2242                  "smmul", "\t$Rd, $Rn, $Rm",
2243                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
2244          Requires<[IsThumb2, HasThumb2DSP]> {
2245  let Inst{31-27} = 0b11111;
2246  let Inst{26-23} = 0b0110;
2247  let Inst{22-20} = 0b101;
2248  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2249  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2250}
2251
2252def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2253                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
2254          Requires<[IsThumb2, HasThumb2DSP]> {
2255  let Inst{31-27} = 0b11111;
2256  let Inst{26-23} = 0b0110;
2257  let Inst{22-20} = 0b101;
2258  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2259  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2260}
2261
2262def t2SMMLA : T2FourReg<
2263        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2264                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2265                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
2266          Requires<[IsThumb2, HasThumb2DSP]> {
2267  let Inst{31-27} = 0b11111;
2268  let Inst{26-23} = 0b0110;
2269  let Inst{22-20} = 0b101;
2270  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2271}
2272
2273def t2SMMLAR: T2FourReg<
2274        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2275                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
2276          Requires<[IsThumb2, HasThumb2DSP]> {
2277  let Inst{31-27} = 0b11111;
2278  let Inst{26-23} = 0b0110;
2279  let Inst{22-20} = 0b101;
2280  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2281}
2282
2283def t2SMMLS: T2FourReg<
2284        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2285                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2286                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
2287          Requires<[IsThumb2, HasThumb2DSP]> {
2288  let Inst{31-27} = 0b11111;
2289  let Inst{26-23} = 0b0110;
2290  let Inst{22-20} = 0b110;
2291  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2292}
2293
2294def t2SMMLSR:T2FourReg<
2295        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2296                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
2297          Requires<[IsThumb2, HasThumb2DSP]> {
2298  let Inst{31-27} = 0b11111;
2299  let Inst{26-23} = 0b0110;
2300  let Inst{22-20} = 0b110;
2301  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2302}
2303
2304multiclass T2I_smul<string opc, PatFrag opnode> {
2305  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2306              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2307              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2308                                      (sext_inreg rGPR:$Rm, i16)))]>,
2309          Requires<[IsThumb2, HasThumb2DSP]> {
2310    let Inst{31-27} = 0b11111;
2311    let Inst{26-23} = 0b0110;
2312    let Inst{22-20} = 0b001;
2313    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2314    let Inst{7-6} = 0b00;
2315    let Inst{5-4} = 0b00;
2316  }
2317
2318  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2319              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2320              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2321                                      (sra rGPR:$Rm, (i32 16))))]>,
2322          Requires<[IsThumb2, HasThumb2DSP]> {
2323    let Inst{31-27} = 0b11111;
2324    let Inst{26-23} = 0b0110;
2325    let Inst{22-20} = 0b001;
2326    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2327    let Inst{7-6} = 0b00;
2328    let Inst{5-4} = 0b01;
2329  }
2330
2331  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2332              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2333              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2334                                      (sext_inreg rGPR:$Rm, i16)))]>,
2335          Requires<[IsThumb2, HasThumb2DSP]> {
2336    let Inst{31-27} = 0b11111;
2337    let Inst{26-23} = 0b0110;
2338    let Inst{22-20} = 0b001;
2339    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2340    let Inst{7-6} = 0b00;
2341    let Inst{5-4} = 0b10;
2342  }
2343
2344  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2345              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2346              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2347                                      (sra rGPR:$Rm, (i32 16))))]>,
2348          Requires<[IsThumb2, HasThumb2DSP]> {
2349    let Inst{31-27} = 0b11111;
2350    let Inst{26-23} = 0b0110;
2351    let Inst{22-20} = 0b001;
2352    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2353    let Inst{7-6} = 0b00;
2354    let Inst{5-4} = 0b11;
2355  }
2356
2357  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2358              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2359              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2360                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
2361          Requires<[IsThumb2, HasThumb2DSP]> {
2362    let Inst{31-27} = 0b11111;
2363    let Inst{26-23} = 0b0110;
2364    let Inst{22-20} = 0b011;
2365    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2366    let Inst{7-6} = 0b00;
2367    let Inst{5-4} = 0b00;
2368  }
2369
2370  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2371              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2372              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2373                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
2374          Requires<[IsThumb2, HasThumb2DSP]> {
2375    let Inst{31-27} = 0b11111;
2376    let Inst{26-23} = 0b0110;
2377    let Inst{22-20} = 0b011;
2378    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2379    let Inst{7-6} = 0b00;
2380    let Inst{5-4} = 0b01;
2381  }
2382}
2383
2384
2385multiclass T2I_smla<string opc, PatFrag opnode> {
2386  def BB : T2FourReg<
2387        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2388              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2389              [(set rGPR:$Rd, (add rGPR:$Ra,
2390                               (opnode (sext_inreg rGPR:$Rn, i16),
2391                                       (sext_inreg rGPR:$Rm, i16))))]>,
2392          Requires<[IsThumb2, HasThumb2DSP]> {
2393    let Inst{31-27} = 0b11111;
2394    let Inst{26-23} = 0b0110;
2395    let Inst{22-20} = 0b001;
2396    let Inst{7-6} = 0b00;
2397    let Inst{5-4} = 0b00;
2398  }
2399
2400  def BT : T2FourReg<
2401       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2402             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2403             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2404                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2405          Requires<[IsThumb2, HasThumb2DSP]> {
2406    let Inst{31-27} = 0b11111;
2407    let Inst{26-23} = 0b0110;
2408    let Inst{22-20} = 0b001;
2409    let Inst{7-6} = 0b00;
2410    let Inst{5-4} = 0b01;
2411  }
2412
2413  def TB : T2FourReg<
2414        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2415              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2416              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2417                                               (sext_inreg rGPR:$Rm, i16))))]>,
2418          Requires<[IsThumb2, HasThumb2DSP]> {
2419    let Inst{31-27} = 0b11111;
2420    let Inst{26-23} = 0b0110;
2421    let Inst{22-20} = 0b001;
2422    let Inst{7-6} = 0b00;
2423    let Inst{5-4} = 0b10;
2424  }
2425
2426  def TT : T2FourReg<
2427        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2428              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2429             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2430                                                 (sra rGPR:$Rm, (i32 16)))))]>,
2431          Requires<[IsThumb2, HasThumb2DSP]> {
2432    let Inst{31-27} = 0b11111;
2433    let Inst{26-23} = 0b0110;
2434    let Inst{22-20} = 0b001;
2435    let Inst{7-6} = 0b00;
2436    let Inst{5-4} = 0b11;
2437  }
2438
2439  def WB : T2FourReg<
2440        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2441              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2442              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2443                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
2444          Requires<[IsThumb2, HasThumb2DSP]> {
2445    let Inst{31-27} = 0b11111;
2446    let Inst{26-23} = 0b0110;
2447    let Inst{22-20} = 0b011;
2448    let Inst{7-6} = 0b00;
2449    let Inst{5-4} = 0b00;
2450  }
2451
2452  def WT : T2FourReg<
2453        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2454              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2455              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2456                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
2457          Requires<[IsThumb2, HasThumb2DSP]> {
2458    let Inst{31-27} = 0b11111;
2459    let Inst{26-23} = 0b0110;
2460    let Inst{22-20} = 0b011;
2461    let Inst{7-6} = 0b00;
2462    let Inst{5-4} = 0b01;
2463  }
2464}
2465
2466defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2467defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2468
2469// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2470def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2471         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2472           [/* For disassembly only; pattern left blank */]>,
2473          Requires<[IsThumb2, HasThumb2DSP]>;
2474def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2475         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2476           [/* For disassembly only; pattern left blank */]>,
2477          Requires<[IsThumb2, HasThumb2DSP]>;
2478def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2479         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2480           [/* For disassembly only; pattern left blank */]>,
2481          Requires<[IsThumb2, HasThumb2DSP]>;
2482def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2483         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2484           [/* For disassembly only; pattern left blank */]>,
2485          Requires<[IsThumb2, HasThumb2DSP]>;
2486
2487// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2488// These are for disassembly only.
2489
2490def t2SMUAD: T2ThreeReg_mac<
2491            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2492            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
2493          Requires<[IsThumb2, HasThumb2DSP]> {
2494  let Inst{15-12} = 0b1111;
2495}
2496def t2SMUADX:T2ThreeReg_mac<
2497            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2498            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
2499          Requires<[IsThumb2, HasThumb2DSP]> {
2500  let Inst{15-12} = 0b1111;
2501}
2502def t2SMUSD: T2ThreeReg_mac<
2503            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2504            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
2505          Requires<[IsThumb2, HasThumb2DSP]> {
2506  let Inst{15-12} = 0b1111;
2507}
2508def t2SMUSDX:T2ThreeReg_mac<
2509            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2510            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
2511          Requires<[IsThumb2, HasThumb2DSP]> {
2512  let Inst{15-12} = 0b1111;
2513}
2514def t2SMLAD   : T2ThreeReg_mac<
2515            0, 0b010, 0b0000, (outs rGPR:$Rd),
2516            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2517            "\t$Rd, $Rn, $Rm, $Ra", []>,
2518          Requires<[IsThumb2, HasThumb2DSP]>;
2519def t2SMLADX  : T2FourReg_mac<
2520            0, 0b010, 0b0001, (outs rGPR:$Rd),
2521            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2522            "\t$Rd, $Rn, $Rm, $Ra", []>,
2523          Requires<[IsThumb2, HasThumb2DSP]>;
2524def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2525            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2526            "\t$Rd, $Rn, $Rm, $Ra", []>,
2527          Requires<[IsThumb2, HasThumb2DSP]>;
2528def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2529            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2530            "\t$Rd, $Rn, $Rm, $Ra", []>,
2531          Requires<[IsThumb2, HasThumb2DSP]>;
2532def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2533                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2534                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2535          Requires<[IsThumb2, HasThumb2DSP]>;
2536def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2537                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2538                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2539          Requires<[IsThumb2, HasThumb2DSP]>;
2540def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2541                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2542                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2543          Requires<[IsThumb2, HasThumb2DSP]>;
2544def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2545                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2546                        "\t$Ra, $Rd, $Rm, $Rn", []>,
2547          Requires<[IsThumb2, HasThumb2DSP]>;
2548
2549//===----------------------------------------------------------------------===//
2550//  Division Instructions.
2551//  Signed and unsigned division on v7-M
2552//
2553def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2554                 "sdiv", "\t$Rd, $Rn, $Rm",
2555                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2556                 Requires<[HasDivide, IsThumb2]> {
2557  let Inst{31-27} = 0b11111;
2558  let Inst{26-21} = 0b011100;
2559  let Inst{20} = 0b1;
2560  let Inst{15-12} = 0b1111;
2561  let Inst{7-4} = 0b1111;
2562}
2563
2564def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2565                 "udiv", "\t$Rd, $Rn, $Rm",
2566                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2567                 Requires<[HasDivide, IsThumb2]> {
2568  let Inst{31-27} = 0b11111;
2569  let Inst{26-21} = 0b011101;
2570  let Inst{20} = 0b1;
2571  let Inst{15-12} = 0b1111;
2572  let Inst{7-4} = 0b1111;
2573}
2574
2575//===----------------------------------------------------------------------===//
2576//  Misc. Arithmetic Instructions.
2577//
2578
2579class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2580      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2581  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2582  let Inst{31-27} = 0b11111;
2583  let Inst{26-22} = 0b01010;
2584  let Inst{21-20} = op1;
2585  let Inst{15-12} = 0b1111;
2586  let Inst{7-6} = 0b10;
2587  let Inst{5-4} = op2;
2588  let Rn{3-0} = Rm;
2589}
2590
2591def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2592                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2593
2594def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2595                      "rbit", "\t$Rd, $Rm",
2596                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2597
2598def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2599                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2600
2601def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2602                       "rev16", ".w\t$Rd, $Rm",
2603                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2604
2605def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2606                       "revsh", ".w\t$Rd, $Rm",
2607                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2608
2609def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2610                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2611            (t2REVSH rGPR:$Rm)>;
2612
2613def t2PKHBT : T2ThreeReg<
2614            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2615                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm, lsl $sh",
2616                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2617                                      (and (shl rGPR:$Rm, pkh_lsl_amt:$sh),
2618                                           0xFFFF0000)))]>,
2619                  Requires<[HasT2ExtractPack, IsThumb2]> {
2620  let Inst{31-27} = 0b11101;
2621  let Inst{26-25} = 0b01;
2622  let Inst{24-20} = 0b01100;
2623  let Inst{5} = 0; // BT form
2624  let Inst{4} = 0;
2625
2626  bits<5> sh;
2627  let Inst{14-12} = sh{4-2};
2628  let Inst{7-6}   = sh{1-0};
2629}
2630
2631// Alternate cases for PKHBT where identities eliminate some nodes.
2632def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2633            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2634            Requires<[HasT2ExtractPack, IsThumb2]>;
2635def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2636            (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2637            Requires<[HasT2ExtractPack, IsThumb2]>;
2638
2639// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2640// will match the pattern below.
2641def t2PKHTB : T2ThreeReg<
2642                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$sh),
2643                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm, asr $sh",
2644                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2645                                       (and (sra rGPR:$Rm, pkh_asr_amt:$sh),
2646                                            0xFFFF)))]>,
2647                  Requires<[HasT2ExtractPack, IsThumb2]> {
2648  let Inst{31-27} = 0b11101;
2649  let Inst{26-25} = 0b01;
2650  let Inst{24-20} = 0b01100;
2651  let Inst{5} = 1; // TB form
2652  let Inst{4} = 0;
2653
2654  bits<5> sh;
2655  let Inst{14-12} = sh{4-2};
2656  let Inst{7-6}   = sh{1-0};
2657}
2658
2659// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2660// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2661def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2662            (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2663            Requires<[HasT2ExtractPack, IsThumb2]>;
2664def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2665                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2666            (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>,
2667            Requires<[HasT2ExtractPack, IsThumb2]>;
2668
2669//===----------------------------------------------------------------------===//
2670//  Comparison Instructions...
2671//
2672defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2673                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2674                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2675
2676def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_imm:$imm),
2677            (t2CMPri  GPR:$lhs, t2_so_imm:$imm)>;
2678def : T2Pat<(ARMcmpZ  GPR:$lhs, rGPR:$rhs),
2679            (t2CMPrr  GPR:$lhs, rGPR:$rhs)>;
2680def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_reg:$rhs),
2681            (t2CMPrs  GPR:$lhs, t2_so_reg:$rhs)>;
2682
2683//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2684//       Compare-to-zero still works out, just not the relationals
2685//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2686//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2687defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2688                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2689                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2690
2691//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2692//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2693
2694def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
2695            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2696
2697defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2698                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2699                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2700defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2701                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2702                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2703
2704// Conditional moves
2705// FIXME: should be able to write a pattern for ARMcmov, but can't use
2706// a two-value operand where a dag node expects two operands. :(
2707let neverHasSideEffects = 1 in {
2708def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
2709                            (ins rGPR:$false, rGPR:$Rm, pred:$p),
2710                            4, IIC_iCMOVr,
2711   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2712                RegConstraint<"$false = $Rd">;
2713
2714let isMoveImm = 1 in
2715def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
2716                            (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
2717                   4, IIC_iCMOVi,
2718[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2719                   RegConstraint<"$false = $Rd">;
2720
2721// FIXME: Pseudo-ize these. For now, just mark codegen only.
2722let isCodeGenOnly = 1 in {
2723let isMoveImm = 1 in
2724def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm),
2725                      IIC_iCMOVi,
2726                      "movw", "\t$Rd, $imm", []>,
2727                      RegConstraint<"$false = $Rd"> {
2728  let Inst{31-27} = 0b11110;
2729  let Inst{25} = 1;
2730  let Inst{24-21} = 0b0010;
2731  let Inst{20} = 0; // The S bit.
2732  let Inst{15} = 0;
2733
2734  bits<4> Rd;
2735  bits<16> imm;
2736
2737  let Inst{11-8}  = Rd;
2738  let Inst{19-16} = imm{15-12};
2739  let Inst{26}    = imm{11};
2740  let Inst{14-12} = imm{10-8};
2741  let Inst{7-0}   = imm{7-0};
2742}
2743
2744let isMoveImm = 1 in
2745def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2746                               (ins rGPR:$false, i32imm:$src, pred:$p),
2747                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2748
2749let isMoveImm = 1 in
2750def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2751                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2752[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2753                   imm:$cc, CCR:$ccr))*/]>,
2754                   RegConstraint<"$false = $Rd"> {
2755  let Inst{31-27} = 0b11110;
2756  let Inst{25} = 0;
2757  let Inst{24-21} = 0b0011;
2758  let Inst{20} = 0; // The S bit.
2759  let Inst{19-16} = 0b1111; // Rn
2760  let Inst{15} = 0;
2761}
2762
2763class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2764                   string opc, string asm, list<dag> pattern>
2765  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2766  let Inst{31-27} = 0b11101;
2767  let Inst{26-25} = 0b01;
2768  let Inst{24-21} = 0b0010;
2769  let Inst{20} = 0; // The S bit.
2770  let Inst{19-16} = 0b1111; // Rn
2771  let Inst{5-4} = opcod; // Shift type.
2772}
2773def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2774                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2775                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2776                 RegConstraint<"$false = $Rd">;
2777def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2778                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2779                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2780                 RegConstraint<"$false = $Rd">;
2781def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2782                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2783                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2784                 RegConstraint<"$false = $Rd">;
2785def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2786                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2787                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2788                 RegConstraint<"$false = $Rd">;
2789} // isCodeGenOnly = 1
2790} // neverHasSideEffects
2791
2792//===----------------------------------------------------------------------===//
2793// Atomic operations intrinsics
2794//
2795
2796// memory barriers protect the atomic sequences
2797let hasSideEffects = 1 in {
2798def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2799                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2800                  Requires<[IsThumb, HasDB]> {
2801  bits<4> opt;
2802  let Inst{31-4} = 0xf3bf8f5;
2803  let Inst{3-0} = opt;
2804}
2805}
2806
2807def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2808                  "dsb", "\t$opt",
2809                  [/* For disassembly only; pattern left blank */]>,
2810                  Requires<[IsThumb, HasDB]> {
2811  bits<4> opt;
2812  let Inst{31-4} = 0xf3bf8f4;
2813  let Inst{3-0} = opt;
2814}
2815
2816// ISB has only full system option -- for disassembly only
2817def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2818                  [/* For disassembly only; pattern left blank */]>,
2819                  Requires<[IsThumb2, HasV7]> {
2820  let Inst{31-4} = 0xf3bf8f6;
2821  let Inst{3-0} = 0b1111;
2822}
2823
2824class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2825                InstrItinClass itin, string opc, string asm, string cstr,
2826                list<dag> pattern, bits<4> rt2 = 0b1111>
2827  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2828  let Inst{31-27} = 0b11101;
2829  let Inst{26-20} = 0b0001101;
2830  let Inst{11-8} = rt2;
2831  let Inst{7-6} = 0b01;
2832  let Inst{5-4} = opcod;
2833  let Inst{3-0} = 0b1111;
2834
2835  bits<4> addr;
2836  bits<4> Rt;
2837  let Inst{19-16} = addr;
2838  let Inst{15-12} = Rt;
2839}
2840class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz,
2841                InstrItinClass itin, string opc, string asm, string cstr,
2842                list<dag> pattern, bits<4> rt2 = 0b1111>
2843  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2844  let Inst{31-27} = 0b11101;
2845  let Inst{26-20} = 0b0001100;
2846  let Inst{11-8} = rt2;
2847  let Inst{7-6} = 0b01;
2848  let Inst{5-4} = opcod;
2849
2850  bits<4> Rd;
2851  bits<4> addr;
2852  bits<4> Rt;
2853  let Inst{3-0}  = Rd;
2854  let Inst{19-16} = addr;
2855  let Inst{15-12} = Rt;
2856}
2857
2858let mayLoad = 1 in {
2859def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2860                         AddrModeNone, 4, NoItinerary,
2861                         "ldrexb", "\t$Rt, $addr", "", []>;
2862def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2863                         AddrModeNone, 4, NoItinerary,
2864                         "ldrexh", "\t$Rt, $addr", "", []>;
2865def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2866                       AddrModeNone, 4, NoItinerary,
2867                       "ldrex", "\t$Rt, $addr", "", []> {
2868  let Inst{31-27} = 0b11101;
2869  let Inst{26-20} = 0b0000101;
2870  let Inst{11-8} = 0b1111;
2871  let Inst{7-0} = 0b00000000; // imm8 = 0
2872
2873  bits<4> Rt;
2874  bits<4> addr;
2875  let Inst{19-16} = addr;
2876  let Inst{15-12} = Rt;
2877}
2878let hasExtraDefRegAllocReq = 1 in
2879def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2880                         (ins t2addrmode_reg:$addr),
2881                         AddrModeNone, 4, NoItinerary,
2882                         "ldrexd", "\t$Rt, $Rt2, $addr", "",
2883                         [], {?, ?, ?, ?}> {
2884  bits<4> Rt2;
2885  let Inst{11-8} = Rt2;
2886}
2887}
2888
2889let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2890def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2891                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2892                         AddrModeNone, 4, NoItinerary,
2893                         "strexb", "\t$Rd, $Rt, $addr", "", []>;
2894def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2895                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2896                         AddrModeNone, 4, NoItinerary,
2897                         "strexh", "\t$Rd, $Rt, $addr", "", []>;
2898def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2899                  AddrModeNone, 4, NoItinerary,
2900                  "strex", "\t$Rd, $Rt, $addr", "",
2901                  []> {
2902  let Inst{31-27} = 0b11101;
2903  let Inst{26-20} = 0b0000100;
2904  let Inst{7-0} = 0b00000000; // imm8 = 0
2905
2906  bits<4> Rd;
2907  bits<4> addr;
2908  bits<4> Rt;
2909  let Inst{11-8}  = Rd;
2910  let Inst{19-16} = addr;
2911  let Inst{15-12} = Rt;
2912}
2913}
2914
2915let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2916def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2917                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2918                         AddrModeNone, 4, NoItinerary,
2919                         "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2920                         {?, ?, ?, ?}> {
2921  bits<4> Rt2;
2922  let Inst{11-8} = Rt2;
2923}
2924
2925// Clear-Exclusive is for disassembly only.
2926def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2927                   [/* For disassembly only; pattern left blank */]>,
2928            Requires<[IsThumb2, HasV7]>  {
2929  let Inst{31-16} = 0xf3bf;
2930  let Inst{15-14} = 0b10;
2931  let Inst{13} = 0;
2932  let Inst{12} = 0;
2933  let Inst{11-8} = 0b1111;
2934  let Inst{7-4} = 0b0010;
2935  let Inst{3-0} = 0b1111;
2936}
2937
2938//===----------------------------------------------------------------------===//
2939// SJLJ Exception handling intrinsics
2940//   eh_sjlj_setjmp() is an instruction sequence to store the return
2941//   address and save #0 in R0 for the non-longjmp case.
2942//   Since by its nature we may be coming from some other function to get
2943//   here, and we're using the stack frame for the containing function to
2944//   save/restore registers, we can't keep anything live in regs across
2945//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2946//   when we get here from a longjmp(). We force everything out of registers
2947//   except for our own input by listing the relevant registers in Defs. By
2948//   doing so, we also cause the prologue/epilogue code to actively preserve
2949//   all of the callee-saved resgisters, which is exactly what we want.
2950//   $val is a scratch register for our use.
2951let Defs =
2952  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
2953    QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2954  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2955  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2956                               AddrModeNone, 0, NoItinerary, "", "",
2957                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2958                             Requires<[IsThumb2, HasVFP2]>;
2959}
2960
2961let Defs =
2962  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
2963  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2964  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2965                               AddrModeNone, 0, NoItinerary, "", "",
2966                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2967                                  Requires<[IsThumb2, NoVFP]>;
2968}
2969
2970
2971//===----------------------------------------------------------------------===//
2972// Control-Flow Instructions
2973//
2974
2975// FIXME: remove when we have a way to marking a MI with these properties.
2976// FIXME: Should pc be an implicit operand like PICADD, etc?
2977let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2978    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2979def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2980                                                   reglist:$regs, variable_ops),
2981                              4, IIC_iLoad_mBr, [],
2982            (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2983                         RegConstraint<"$Rn = $wb">;
2984
2985let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2986let isPredicable = 1 in
2987def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2988                 "b.w\t$target",
2989                 [(br bb:$target)]> {
2990  let Inst{31-27} = 0b11110;
2991  let Inst{15-14} = 0b10;
2992  let Inst{12} = 1;
2993
2994  bits<20> target;
2995  let Inst{26} = target{19};
2996  let Inst{11} = target{18};
2997  let Inst{13} = target{17};
2998  let Inst{21-16} = target{16-11};
2999  let Inst{10-0} = target{10-0};
3000}
3001
3002let isNotDuplicable = 1, isIndirectBranch = 1 in {
3003def t2BR_JT : t2PseudoInst<(outs),
3004          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3005           0, IIC_Br,
3006          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3007
3008// FIXME: Add a non-pc based case that can be predicated.
3009def t2TBB_JT : t2PseudoInst<(outs),
3010        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3011         0, IIC_Br, []>;
3012
3013def t2TBH_JT : t2PseudoInst<(outs),
3014        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3015         0, IIC_Br, []>;
3016
3017def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3018                    "tbb", "\t[$Rn, $Rm]", []> {
3019  bits<4> Rn;
3020  bits<4> Rm;
3021  let Inst{31-20} = 0b111010001101;
3022  let Inst{19-16} = Rn;
3023  let Inst{15-5} = 0b11110000000;
3024  let Inst{4} = 0; // B form
3025  let Inst{3-0} = Rm;
3026}
3027
3028def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3029                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3030  bits<4> Rn;
3031  bits<4> Rm;
3032  let Inst{31-20} = 0b111010001101;
3033  let Inst{19-16} = Rn;
3034  let Inst{15-5} = 0b11110000000;
3035  let Inst{4} = 1; // H form
3036  let Inst{3-0} = Rm;
3037}
3038} // isNotDuplicable, isIndirectBranch
3039
3040} // isBranch, isTerminator, isBarrier
3041
3042// FIXME: should be able to write a pattern for ARMBrcond, but can't use
3043// a two-value operand where a dag node expects two operands. :(
3044let isBranch = 1, isTerminator = 1 in
3045def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3046                "b", ".w\t$target",
3047                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3048  let Inst{31-27} = 0b11110;
3049  let Inst{15-14} = 0b10;
3050  let Inst{12} = 0;
3051
3052  bits<4> p;
3053  let Inst{25-22} = p;
3054
3055  bits<21> target;
3056  let Inst{26} = target{20};
3057  let Inst{11} = target{19};
3058  let Inst{13} = target{18};
3059  let Inst{21-16} = target{17-12};
3060  let Inst{10-0} = target{11-1};
3061}
3062
3063// Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so
3064// it goes here.
3065let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
3066  // Darwin version.
3067  let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
3068      Uses = [SP] in
3069  def tTAILJMPd: tPseudoExpand<(outs), (ins uncondbrtarget:$dst, variable_ops),
3070                   4, IIC_Br, [],
3071                   (t2B uncondbrtarget:$dst)>,
3072                 Requires<[IsThumb2, IsDarwin]>;
3073}
3074
3075// IT block
3076let Defs = [ITSTATE] in
3077def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3078                    AddrModeNone, 2,  IIC_iALUx,
3079                    "it$mask\t$cc", "", []> {
3080  // 16-bit instruction.
3081  let Inst{31-16} = 0x0000;
3082  let Inst{15-8} = 0b10111111;
3083
3084  bits<4> cc;
3085  bits<4> mask;
3086  let Inst{7-4} = cc;
3087  let Inst{3-0} = mask;
3088}
3089
3090// Branch and Exchange Jazelle -- for disassembly only
3091// Rm = Inst{19-16}
3092def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3093              [/* For disassembly only; pattern left blank */]> {
3094  let Inst{31-27} = 0b11110;
3095  let Inst{26} = 0;
3096  let Inst{25-20} = 0b111100;
3097  let Inst{15-14} = 0b10;
3098  let Inst{12} = 0;
3099
3100  bits<4> func;
3101  let Inst{19-16} = func;
3102}
3103
3104// Change Processor State is a system instruction -- for disassembly and
3105// parsing only.
3106// FIXME: Since the asm parser has currently no clean way to handle optional
3107// operands, create 3 versions of the same instruction. Once there's a clean
3108// framework to represent optional operands, change this behavior.
3109class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3110            !strconcat("cps", asm_op),
3111            [/* For disassembly only; pattern left blank */]> {
3112  bits<2> imod;
3113  bits<3> iflags;
3114  bits<5> mode;
3115  bit M;
3116
3117  let Inst{31-27} = 0b11110;
3118  let Inst{26}    = 0;
3119  let Inst{25-20} = 0b111010;
3120  let Inst{19-16} = 0b1111;
3121  let Inst{15-14} = 0b10;
3122  let Inst{12}    = 0;
3123  let Inst{10-9}  = imod;
3124  let Inst{8}     = M;
3125  let Inst{7-5}   = iflags;
3126  let Inst{4-0}   = mode;
3127}
3128
3129let M = 1 in
3130  def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3131                      "$imod.w\t$iflags, $mode">;
3132let mode = 0, M = 0 in
3133  def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3134                      "$imod.w\t$iflags">;
3135let imod = 0, iflags = 0, M = 1 in
3136  def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3137
3138// A6.3.4 Branches and miscellaneous control
3139// Table A6-14 Change Processor State, and hint instructions
3140// Helper class for disassembly only.
3141class T2I_hint<bits<8> op7_0, string opc, string asm>
3142  : T2I<(outs), (ins), NoItinerary, opc, asm,
3143        [/* For disassembly only; pattern left blank */]> {
3144  let Inst{31-20} = 0xf3a;
3145  let Inst{19-16} = 0b1111;
3146  let Inst{15-14} = 0b10;
3147  let Inst{12} = 0;
3148  let Inst{10-8} = 0b000;
3149  let Inst{7-0} = op7_0;
3150}
3151
3152def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3153def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3154def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3155def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3156def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3157
3158def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
3159  let Inst{31-20} = 0xf3a;
3160  let Inst{15-14} = 0b10;
3161  let Inst{12} = 0;
3162  let Inst{10-8} = 0b000;
3163  let Inst{7-4} = 0b1111;
3164
3165  bits<4> opt;
3166  let Inst{3-0} = opt;
3167}
3168
3169// Secure Monitor Call is a system instruction -- for disassembly only
3170// Option = Inst{19-16}
3171def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
3172                [/* For disassembly only; pattern left blank */]> {
3173  let Inst{31-27} = 0b11110;
3174  let Inst{26-20} = 0b1111111;
3175  let Inst{15-12} = 0b1000;
3176
3177  bits<4> opt;
3178  let Inst{19-16} = opt;
3179}
3180
3181class T2SRS<bits<12> op31_20,
3182           dag oops, dag iops, InstrItinClass itin,
3183          string opc, string asm, list<dag> pattern>
3184  : T2I<oops, iops, itin, opc, asm, pattern> {
3185  let Inst{31-20} = op31_20{11-0};
3186
3187  bits<5> mode;
3188  let Inst{4-0} = mode{4-0};
3189}
3190
3191// Store Return State is a system instruction -- for disassembly only
3192def t2SRSDBW : T2SRS<0b111010000010,
3193                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3194                   [/* For disassembly only; pattern left blank */]>;
3195def t2SRSDB  : T2SRS<0b111010000000,
3196                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3197                   [/* For disassembly only; pattern left blank */]>;
3198def t2SRSIAW : T2SRS<0b111010011010,
3199                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3200                   [/* For disassembly only; pattern left blank */]>;
3201def t2SRSIA  : T2SRS<0b111010011000,
3202                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3203                   [/* For disassembly only; pattern left blank */]>;
3204
3205// Return From Exception is a system instruction -- for disassembly only
3206
3207class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3208          string opc, string asm, list<dag> pattern>
3209  : T2I<oops, iops, itin, opc, asm, pattern> {
3210  let Inst{31-20} = op31_20{11-0};
3211
3212  bits<4> Rn;
3213  let Inst{19-16} = Rn;
3214  let Inst{15-0} = 0xc000;
3215}
3216
3217def t2RFEDBW : T2RFE<0b111010000011,
3218                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3219                   [/* For disassembly only; pattern left blank */]>;
3220def t2RFEDB  : T2RFE<0b111010000001,
3221                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3222                   [/* For disassembly only; pattern left blank */]>;
3223def t2RFEIAW : T2RFE<0b111010011011,
3224                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3225                   [/* For disassembly only; pattern left blank */]>;
3226def t2RFEIA  : T2RFE<0b111010011001,
3227                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3228                   [/* For disassembly only; pattern left blank */]>;
3229
3230//===----------------------------------------------------------------------===//
3231// Non-Instruction Patterns
3232//
3233
3234// 32-bit immediate using movw + movt.
3235// This is a single pseudo instruction to make it re-materializable.
3236// FIXME: Remove this when we can do generalized remat.
3237let isReMaterializable = 1, isMoveImm = 1 in
3238def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3239                            [(set rGPR:$dst, (i32 imm:$src))]>,
3240                            Requires<[IsThumb, HasV6T2]>;
3241
3242// Pseudo instruction that combines movw + movt + add pc (if pic).
3243// It also makes it possible to rematerialize the instructions.
3244// FIXME: Remove this when we can do generalized remat and when machine licm
3245// can properly the instructions.
3246let isReMaterializable = 1 in {
3247def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3248                                IIC_iMOVix2addpc,
3249                          [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3250                          Requires<[IsThumb2, UseMovt]>;
3251
3252def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3253                              IIC_iMOVix2,
3254                          [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3255                          Requires<[IsThumb2, UseMovt]>;
3256}
3257
3258// ConstantPool, GlobalAddress, and JumpTable
3259def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3260           Requires<[IsThumb2, DontUseMovt]>;
3261def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3262def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3263           Requires<[IsThumb2, UseMovt]>;
3264
3265def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3266            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3267
3268// Pseudo instruction that combines ldr from constpool and add pc. This should
3269// be expanded into two instructions late to allow if-conversion and
3270// scheduling.
3271let canFoldAsLoad = 1, isReMaterializable = 1 in
3272def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3273                   IIC_iLoadiALU,
3274              [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3275                                           imm:$cp))]>,
3276               Requires<[IsThumb2]>;
3277
3278//===----------------------------------------------------------------------===//
3279// Move between special register and ARM core register -- for disassembly only
3280//
3281
3282class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3283          dag oops, dag iops, InstrItinClass itin,
3284          string opc, string asm, list<dag> pattern>
3285  : T2I<oops, iops, itin, opc, asm, pattern> {
3286  let Inst{31-20} = op31_20{11-0};
3287  let Inst{15-14} = op15_14{1-0};
3288  let Inst{12} = op12{0};
3289}
3290
3291class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3292          dag oops, dag iops, InstrItinClass itin,
3293          string opc, string asm, list<dag> pattern>
3294  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3295  bits<4> Rd;
3296  let Inst{11-8} = Rd;
3297  let Inst{19-16} = 0b1111;
3298}
3299
3300def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3301                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3302                [/* For disassembly only; pattern left blank */]>;
3303def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3304                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3305                   [/* For disassembly only; pattern left blank */]>;
3306
3307// Move from ARM core register to Special Register
3308//
3309// No need to have both system and application versions, the encodings are the
3310// same and the assembly parser has no way to distinguish between them. The mask
3311// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3312// the mask with the fields to be accessed in the special register.
3313def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3314                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3315                         NoItinerary, "msr", "\t$mask, $Rn",
3316                         [/* For disassembly only; pattern left blank */]> {
3317  bits<5> mask;
3318  bits<4> Rn;
3319  let Inst{19-16} = Rn;
3320  let Inst{20}    = mask{4}; // R Bit
3321  let Inst{13}    = 0b0;
3322  let Inst{11-8}  = mask{3-0};
3323}
3324
3325//===----------------------------------------------------------------------===//
3326// Move between coprocessor and ARM core register
3327//
3328
3329class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops,
3330                  list<dag> pattern>
3331  : T2Cop<Op, oops, iops,
3332          !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3333          pattern> {
3334  let Inst{27-24} = 0b1110;
3335  let Inst{20} = direction;
3336  let Inst{4} = 1;
3337
3338  bits<4> Rt;
3339  bits<4> cop;
3340  bits<3> opc1;
3341  bits<3> opc2;
3342  bits<4> CRm;
3343  bits<4> CRn;
3344
3345  let Inst{15-12} = Rt;
3346  let Inst{11-8}  = cop;
3347  let Inst{23-21} = opc1;
3348  let Inst{7-5}   = opc2;
3349  let Inst{3-0}   = CRm;
3350  let Inst{19-16} = CRn;
3351}
3352
3353class t2MovRRCopro<bits<4> Op, string opc, bit direction,
3354                   list<dag> pattern = []>
3355  : T2Cop<Op, (outs),
3356          (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3357          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3358  let Inst{27-24} = 0b1100;
3359  let Inst{23-21} = 0b010;
3360  let Inst{20} = direction;
3361
3362  bits<4> Rt;
3363  bits<4> Rt2;
3364  bits<4> cop;
3365  bits<4> opc1;
3366  bits<4> CRm;
3367
3368  let Inst{15-12} = Rt;
3369  let Inst{19-16} = Rt2;
3370  let Inst{11-8}  = cop;
3371  let Inst{7-4}   = opc1;
3372  let Inst{3-0}   = CRm;
3373}
3374
3375/* from ARM core register to coprocessor */
3376def t2MCR : t2MovRCopro<0b1110, "mcr", 0,
3377           (outs),
3378           (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3379                c_imm:$CRm, imm0_7:$opc2),
3380           [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3381                         imm:$CRm, imm:$opc2)]>;
3382def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0,
3383             (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3384                          c_imm:$CRm, imm0_7:$opc2),
3385             [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3386                            imm:$CRm, imm:$opc2)]>;
3387
3388/* from coprocessor to ARM core register */
3389def t2MRC : t2MovRCopro<0b1110, "mrc", 1,
3390             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3391                                  c_imm:$CRm, imm0_7:$opc2), []>;
3392
3393def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1,
3394             (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3395                                  c_imm:$CRm, imm0_7:$opc2), []>;
3396
3397def : T2v6Pat<(int_arm_mrc  imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3398              (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3399
3400def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3401              (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3402
3403
3404/* from ARM core register to coprocessor */
3405def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0,
3406                        [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3407                                       imm:$CRm)]>;
3408def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0,
3409                           [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3410                                           GPR:$Rt2, imm:$CRm)]>;
3411/* from coprocessor to ARM core register */
3412def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>;
3413
3414def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>;
3415
3416//===----------------------------------------------------------------------===//
3417// Other Coprocessor Instructions.
3418//
3419
3420def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3421                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3422                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3423                 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3424                               imm:$CRm, imm:$opc2)]> {
3425  let Inst{27-24} = 0b1110;
3426
3427  bits<4> opc1;
3428  bits<4> CRn;
3429  bits<4> CRd;
3430  bits<4> cop;
3431  bits<3> opc2;
3432  bits<4> CRm;
3433
3434  let Inst{3-0}   = CRm;
3435  let Inst{4}     = 0;
3436  let Inst{7-5}   = opc2;
3437  let Inst{11-8}  = cop;
3438  let Inst{15-12} = CRd;
3439  let Inst{19-16} = CRn;
3440  let Inst{23-20} = opc1;
3441}
3442
3443def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1,
3444                   c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
3445                   "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3446                   [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3447                                  imm:$CRm, imm:$opc2)]> {
3448  let Inst{27-24} = 0b1110;
3449
3450  bits<4> opc1;
3451  bits<4> CRn;
3452  bits<4> CRd;
3453  bits<4> cop;
3454  bits<3> opc2;
3455  bits<4> CRm;
3456
3457  let Inst{3-0}   = CRm;
3458  let Inst{4}     = 0;
3459  let Inst{7-5}   = opc2;
3460  let Inst{11-8}  = cop;
3461  let Inst{15-12} = CRd;
3462  let Inst{19-16} = CRn;
3463  let Inst{23-20} = opc1;
3464}
3465