ARMInstrThumb2.td revision 7721e7f279c4c01b29583011eaff48250ec6cdd9 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred : Operand<i32> {
16  let PrintMethod = "printMandatoryPredicateOperand";
17}
18
19// IT block condition mask
20def it_mask : Operand<i32> {
21  let PrintMethod = "printThumbITMask";
22}
23
24// Shifted operands. No register controlled shifts for Thumb2.
25// Note: We do not support rrx shifted operands yet.
26def t2_so_reg : Operand<i32>,    // reg imm
27                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
28                               [shl,srl,sra,rotr]> {
29  let EncoderMethod = "getT2SORegOpValue";
30  let PrintMethod = "printT2SOOperand";
31  let MIOperandInfo = (ops rGPR, i32imm);
32}
33
34// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
37}]>;
38
39// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
42}]>;
43
44// t2_so_imm - Match a 32-bit immediate operand, which is an
45// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46// immediate splatted into multiple bytes of the word. t2_so_imm values are
47// represented in the imm field in the same 12-bit form that they are encoded
48// into t2_so_imm instructions: the 8-bit immediate is the least significant
49// bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
50def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> {
51  let EncoderMethod = "getT2SOImmOpValue";
52}
53
54// t2_so_imm_not - Match an immediate that is a complement
55// of a t2_so_imm.
56def t2_so_imm_not : Operand<i32>,
57                    PatLeaf<(imm), [{
58  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
59}], t2_so_imm_not_XFORM>;
60
61// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
62def t2_so_imm_neg : Operand<i32>,
63                    PatLeaf<(imm), [{
64  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
65}], t2_so_imm_neg_XFORM>;
66
67// Break t2_so_imm's up into two pieces.  This handles immediates with up to 16
68// bits set in them.  This uses t2_so_imm2part to match and t2_so_imm2part_[12]
69// to get the first/second pieces.
70def t2_so_imm2part : Operand<i32>,
71                  PatLeaf<(imm), [{
72      return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
73    }]> {
74}
75
76def t2_so_imm2part_1 : SDNodeXForm<imm, [{
77  unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
78  return CurDAG->getTargetConstant(V, MVT::i32);
79}]>;
80
81def t2_so_imm2part_2 : SDNodeXForm<imm, [{
82  unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
83  return CurDAG->getTargetConstant(V, MVT::i32);
84}]>;
85
86def t2_so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
87      return ARM_AM::isT2SOImmTwoPartVal(-(int)N->getZExtValue());
88    }]> {
89}
90
91def t2_so_neg_imm2part_1 : SDNodeXForm<imm, [{
92  unsigned V = ARM_AM::getT2SOImmTwoPartFirst(-(int)N->getZExtValue());
93  return CurDAG->getTargetConstant(V, MVT::i32);
94}]>;
95
96def t2_so_neg_imm2part_2 : SDNodeXForm<imm, [{
97  unsigned V = ARM_AM::getT2SOImmTwoPartSecond(-(int)N->getZExtValue());
98  return CurDAG->getTargetConstant(V, MVT::i32);
99}]>;
100
101/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
102def imm1_31 : PatLeaf<(i32 imm), [{
103  return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
104}]>;
105
106/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
107def imm0_4095 : Operand<i32>,
108                PatLeaf<(i32 imm), [{
109  return (uint32_t)N->getZExtValue() < 4096;
110}]>;
111
112def imm0_4095_neg : PatLeaf<(i32 imm), [{
113 return (uint32_t)(-N->getZExtValue()) < 4096;
114}], imm_neg_XFORM>;
115
116def imm0_255_neg : PatLeaf<(i32 imm), [{
117  return (uint32_t)(-N->getZExtValue()) < 255;
118}], imm_neg_XFORM>;
119
120def imm0_255_not : PatLeaf<(i32 imm), [{
121  return (uint32_t)(~N->getZExtValue()) < 255;
122}], imm_comp_XFORM>;
123
124// Define Thumb2 specific addressing modes.
125
126// t2addrmode_imm12  := reg + imm12
127def t2addrmode_imm12 : Operand<i32>,
128                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
129  let PrintMethod = "printAddrModeImm12Operand";
130  string EncoderMethod = "getAddrModeImm12OpValue";
131  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
132}
133
134// t2addrmode_imm8  := reg +/- imm8
135def t2addrmode_imm8 : Operand<i32>,
136                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
137  let PrintMethod = "printT2AddrModeImm8Operand";
138  string EncoderMethod = "getT2AddrModeImm8OpValue";
139  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
140}
141
142def t2am_imm8_offset : Operand<i32>,
143                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
144                                      [], [SDNPWantRoot]> {
145  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
146  string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
147}
148
149// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
150def t2addrmode_imm8s4 : Operand<i32> {
151  let PrintMethod = "printT2AddrModeImm8s4Operand";
152  string EncoderMethod = "getT2AddrModeImm8s4OpValue";
153  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
154}
155
156def t2am_imm8s4_offset : Operand<i32> {
157  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
158}
159
160// t2addrmode_so_reg  := reg + (reg << imm2)
161def t2addrmode_so_reg : Operand<i32>,
162                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
163  let PrintMethod = "printT2AddrModeSoRegOperand";
164  string EncoderMethod = "getT2AddrModeSORegOpValue";
165  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
166}
167
168
169//===----------------------------------------------------------------------===//
170// Multiclass helpers...
171//
172
173
174class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
175           string opc, string asm, list<dag> pattern>
176  : T2I<oops, iops, itin, opc, asm, pattern> {
177  bits<4> Rd;
178  bits<12> imm;
179
180  let Inst{11-8}  = Rd{3-0};
181  let Inst{26}    = imm{11};
182  let Inst{14-12} = imm{10-8};
183  let Inst{7-0}   = imm{7-0};
184}
185
186
187class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
188           string opc, string asm, list<dag> pattern>
189  : T2sI<oops, iops, itin, opc, asm, pattern> {
190  bits<4> Rd;
191  bits<4> Rn;
192  bits<12> imm;
193
194  let Inst{11-8}  = Rd{3-0};
195  let Inst{26}    = imm{11};
196  let Inst{14-12} = imm{10-8};
197  let Inst{7-0}   = imm{7-0};
198}
199
200class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
201           string opc, string asm, list<dag> pattern>
202  : T2I<oops, iops, itin, opc, asm, pattern> {
203  bits<4> Rn;
204  bits<12> imm;
205
206  let Inst{19-16}  = Rn{3-0};
207  let Inst{26}    = imm{11};
208  let Inst{14-12} = imm{10-8};
209  let Inst{7-0}   = imm{7-0};
210}
211
212
213class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
214           string opc, string asm, list<dag> pattern>
215  : T2I<oops, iops, itin, opc, asm, pattern> {
216  bits<4> Rd;
217  bits<12> ShiftedRm;
218
219  let Inst{11-8}  = Rd{3-0};
220  let Inst{3-0}   = ShiftedRm{3-0};
221  let Inst{5-4}   = ShiftedRm{6-5};
222  let Inst{14-12} = ShiftedRm{11-9};
223  let Inst{7-6}   = ShiftedRm{8-7};
224}
225
226class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
227           string opc, string asm, list<dag> pattern>
228  : T2I<oops, iops, itin, opc, asm, pattern> {
229  bits<4> Rd;
230  bits<12> ShiftedRm;
231
232  let Inst{11-8}  = Rd{3-0};
233  let Inst{3-0}   = ShiftedRm{3-0};
234  let Inst{5-4}   = ShiftedRm{6-5};
235  let Inst{14-12} = ShiftedRm{11-9};
236  let Inst{7-6}   = ShiftedRm{8-7};
237}
238
239class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
240           string opc, string asm, list<dag> pattern>
241  : T2I<oops, iops, itin, opc, asm, pattern> {
242  bits<4> Rn;
243  bits<12> ShiftedRm;
244
245  let Inst{19-16} = Rn{3-0};
246  let Inst{3-0}   = ShiftedRm{3-0};
247  let Inst{5-4}   = ShiftedRm{6-5};
248  let Inst{14-12} = ShiftedRm{11-9};
249  let Inst{7-6}   = ShiftedRm{8-7};
250}
251
252class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
253           string opc, string asm, list<dag> pattern>
254  : T2I<oops, iops, itin, opc, asm, pattern> {
255  bits<4> Rd;
256  bits<4> Rm;
257
258  let Inst{11-8}  = Rd{3-0};
259  let Inst{3-0}   = Rm{3-0};
260}
261
262class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
263           string opc, string asm, list<dag> pattern>
264  : T2sI<oops, iops, itin, opc, asm, pattern> {
265  bits<4> Rd;
266  bits<4> Rm;
267
268  let Inst{11-8}  = Rd{3-0};
269  let Inst{3-0}   = Rm{3-0};
270}
271
272class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
273           string opc, string asm, list<dag> pattern>
274  : T2I<oops, iops, itin, opc, asm, pattern> {
275  bits<4> Rn;
276  bits<4> Rm;
277
278  let Inst{19-16} = Rn{3-0};
279  let Inst{3-0}   = Rm{3-0};
280}
281
282
283class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
284           string opc, string asm, list<dag> pattern>
285  : T2I<oops, iops, itin, opc, asm, pattern> {
286  bits<4> Rd;
287  bits<4> Rm;
288
289  let Inst{11-8}  = Rd{3-0};
290  let Inst{3-0}   = Rm{3-0};
291}
292
293class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
294           string opc, string asm, list<dag> pattern>
295  : T2sI<oops, iops, itin, opc, asm, pattern> {
296  bits<4> Rd;
297  bits<4> Rn;
298  bits<12> imm;
299
300  let Inst{11-8}  = Rd{3-0};
301  let Inst{19-16} = Rn{3-0};
302  let Inst{26}    = imm{11};
303  let Inst{14-12} = imm{10-8};
304  let Inst{7-0}   = imm{7-0};
305}
306
307class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
308           string opc, string asm, list<dag> pattern>
309  : T2I<oops, iops, itin, opc, asm, pattern> {
310  bits<4> Rd;
311  bits<4> Rm;
312  bits<5> imm;
313
314  let Inst{11-8}  = Rd{3-0};
315  let Inst{3-0}   = Rm{3-0};
316  let Inst{14-12} = imm{4-2};
317  let Inst{7-6}   = imm{1-0};
318}
319
320class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
321           string opc, string asm, list<dag> pattern>
322  : T2sI<oops, iops, itin, opc, asm, pattern> {
323  bits<4> Rd;
324  bits<4> Rm;
325  bits<5> imm;
326
327  let Inst{11-8}  = Rd{3-0};
328  let Inst{3-0}   = Rm{3-0};
329  let Inst{14-12} = imm{4-2};
330  let Inst{7-6}   = imm{1-0};
331}
332
333class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
334           string opc, string asm, list<dag> pattern>
335  : T2I<oops, iops, itin, opc, asm, pattern> {
336  bits<4> Rd;
337  bits<4> Rn;
338  bits<4> Rm;
339
340  let Inst{11-8}  = Rd{3-0};
341  let Inst{19-16} = Rn{3-0};
342  let Inst{3-0}   = Rm{3-0};
343}
344
345class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
346           string opc, string asm, list<dag> pattern>
347  : T2sI<oops, iops, itin, opc, asm, pattern> {
348  bits<4> Rd;
349  bits<4> Rn;
350  bits<4> Rm;
351
352  let Inst{11-8}  = Rd{3-0};
353  let Inst{19-16} = Rn{3-0};
354  let Inst{3-0}   = Rm{3-0};
355}
356
357class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
358           string opc, string asm, list<dag> pattern>
359  : T2I<oops, iops, itin, opc, asm, pattern> {
360  bits<4> Rd;
361  bits<4> Rn;
362  bits<12> ShiftedRm;
363
364  let Inst{11-8}  = Rd{3-0};
365  let Inst{19-16} = Rn{3-0};
366  let Inst{3-0}   = ShiftedRm{3-0};
367  let Inst{5-4}   = ShiftedRm{6-5};
368  let Inst{14-12} = ShiftedRm{11-9};
369  let Inst{7-6}   = ShiftedRm{8-7};
370}
371
372class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
373           string opc, string asm, list<dag> pattern>
374  : T2sI<oops, iops, itin, opc, asm, pattern> {
375  bits<4> Rd;
376  bits<4> Rn;
377  bits<12> ShiftedRm;
378
379  let Inst{11-8}  = Rd{3-0};
380  let Inst{19-16} = Rn{3-0};
381  let Inst{3-0}   = ShiftedRm{3-0};
382  let Inst{5-4}   = ShiftedRm{6-5};
383  let Inst{14-12} = ShiftedRm{11-9};
384  let Inst{7-6}   = ShiftedRm{8-7};
385}
386
387class T2FourReg<dag oops, dag iops, InstrItinClass itin,
388           string opc, string asm, list<dag> pattern>
389  : T2I<oops, iops, itin, opc, asm, pattern> {
390  bits<4> Rd;
391  bits<4> Rn;
392  bits<4> Rm;
393  bits<4> Ra;
394
395  let Inst{11-8}  = Rd{3-0};
396  let Inst{19-16} = Rn{3-0};
397  let Inst{3-0}   = Rm{3-0};
398  let Inst{15-12} = Ra{3-0};
399}
400
401
402/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
403/// unary operation that produces a value. These are predicable and can be
404/// changed to modify CPSR.
405multiclass T2I_un_irs<bits<4> opcod, string opc,
406                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
407                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
408   // shifted imm
409   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
410                opc, "\t$Rd, $imm",
411                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
412     let isAsCheapAsAMove = Cheap;
413     let isReMaterializable = ReMat;
414     let Inst{31-27} = 0b11110;
415     let Inst{25} = 0;
416     let Inst{24-21} = opcod;
417     let Inst{20} = ?; // The S bit.
418     let Inst{19-16} = 0b1111; // Rn
419     let Inst{15} = 0;
420   }
421   // register
422   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
423                opc, ".w\t$Rd, $Rm",
424                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
425     let Inst{31-27} = 0b11101;
426     let Inst{26-25} = 0b01;
427     let Inst{24-21} = opcod;
428     let Inst{20} = ?; // The S bit.
429     let Inst{19-16} = 0b1111; // Rn
430     let Inst{14-12} = 0b000; // imm3
431     let Inst{7-6} = 0b00; // imm2
432     let Inst{5-4} = 0b00; // type
433   }
434   // shifted register
435   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
436                opc, ".w\t$Rd, $ShiftedRm",
437                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
438     let Inst{31-27} = 0b11101;
439     let Inst{26-25} = 0b01;
440     let Inst{24-21} = opcod;
441     let Inst{20} = ?; // The S bit.
442     let Inst{19-16} = 0b1111; // Rn
443   }
444}
445
446/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
447/// binary operation that produces a value. These are predicable and can be
448/// changed to modify CPSR.
449multiclass T2I_bin_irs<bits<4> opcod, string opc,
450                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
451                       PatFrag opnode, bit Commutable = 0, string wide = ""> {
452   // shifted imm
453   def ri : T2sTwoRegImm<
454                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
455                 opc, "\t$Rd, $Rn, $imm",
456                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
457     let Inst{31-27} = 0b11110;
458     let Inst{25} = 0;
459     let Inst{24-21} = opcod;
460     let Inst{20} = ?; // The S bit.
461     let Inst{15} = 0;
462   }
463   // register
464   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
465                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
466                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
467     let isCommutable = Commutable;
468     let Inst{31-27} = 0b11101;
469     let Inst{26-25} = 0b01;
470     let Inst{24-21} = opcod;
471     let Inst{20} = ?; // The S bit.
472     let Inst{14-12} = 0b000; // imm3
473     let Inst{7-6} = 0b00; // imm2
474     let Inst{5-4} = 0b00; // type
475   }
476   // shifted register
477   def rs : T2sTwoRegShiftedReg<
478                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
479                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
480                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
481     let Inst{31-27} = 0b11101;
482     let Inst{26-25} = 0b01;
483     let Inst{24-21} = opcod;
484     let Inst{20} = ?; // The S bit.
485   }
486}
487
488/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
489//  the ".w" prefix to indicate that they are wide.
490multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
491                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
492                         PatFrag opnode, bit Commutable = 0> :
493    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w">;
494
495/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
496/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
497/// it is equivalent to the T2I_bin_irs counterpart.
498multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
499   // shifted imm
500   def ri : T2sTwoRegImm<
501                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
502                 opc, ".w\t$Rd, $Rn, $imm",
503                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
504     let Inst{31-27} = 0b11110;
505     let Inst{25} = 0;
506     let Inst{24-21} = opcod;
507     let Inst{20} = ?; // The S bit.
508     let Inst{15} = 0;
509   }
510   // register
511   def rr : T2sThreeReg<
512                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
513                 opc, "\t$Rd, $Rn, $Rm",
514                 [/* For disassembly only; pattern left blank */]> {
515     let Inst{31-27} = 0b11101;
516     let Inst{26-25} = 0b01;
517     let Inst{24-21} = opcod;
518     let Inst{20} = ?; // The S bit.
519     let Inst{14-12} = 0b000; // imm3
520     let Inst{7-6} = 0b00; // imm2
521     let Inst{5-4} = 0b00; // type
522   }
523   // shifted register
524   def rs : T2sTwoRegShiftedReg<
525                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
526                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
527                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
528     let Inst{31-27} = 0b11101;
529     let Inst{26-25} = 0b01;
530     let Inst{24-21} = opcod;
531     let Inst{20} = ?; // The S bit.
532   }
533}
534
535/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
536/// instruction modifies the CPSR register.
537let Defs = [CPSR] in {
538multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
539                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
540                         PatFrag opnode, bit Commutable = 0> {
541   // shifted imm
542   def ri : T2TwoRegImm<
543                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
544                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
545                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
546     let Inst{31-27} = 0b11110;
547     let Inst{25} = 0;
548     let Inst{24-21} = opcod;
549     let Inst{20} = 1; // The S bit.
550     let Inst{15} = 0;
551   }
552   // register
553   def rr : T2ThreeReg<
554                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
555                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
556                [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
557     let isCommutable = Commutable;
558     let Inst{31-27} = 0b11101;
559     let Inst{26-25} = 0b01;
560     let Inst{24-21} = opcod;
561     let Inst{20} = 1; // The S bit.
562     let Inst{14-12} = 0b000; // imm3
563     let Inst{7-6} = 0b00; // imm2
564     let Inst{5-4} = 0b00; // type
565   }
566   // shifted register
567   def rs : T2TwoRegShiftedReg<
568                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
569                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
570                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
571     let Inst{31-27} = 0b11101;
572     let Inst{26-25} = 0b01;
573     let Inst{24-21} = opcod;
574     let Inst{20} = 1; // The S bit.
575   }
576}
577}
578
579/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
580/// patterns for a binary operation that produces a value.
581multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
582                          bit Commutable = 0> {
583   // shifted imm
584   // The register-immediate version is re-materializable. This is useful
585   // in particular for taking the address of a local.
586   let isReMaterializable = 1 in {
587   def ri : T2sTwoRegImm<
588                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
589                 opc, ".w\t$Rd, $Rn, $imm",
590                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
591     let Inst{31-27} = 0b11110;
592     let Inst{25} = 0;
593     let Inst{24} = 1;
594     let Inst{23-21} = op23_21;
595     let Inst{20} = 0; // The S bit.
596     let Inst{15} = 0;
597   }
598   }
599   // 12-bit imm
600   def ri12 : T2TwoRegImm<
601                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
602                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
603                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
604     let Inst{31-27} = 0b11110;
605     let Inst{25} = 1;
606     let Inst{24} = 0;
607     let Inst{23-21} = op23_21;
608     let Inst{20} = 0; // The S bit.
609     let Inst{15} = 0;
610   }
611   // register
612   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
613                 opc, ".w\t$Rd, $Rn, $Rm",
614                 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
615     let isCommutable = Commutable;
616     let Inst{31-27} = 0b11101;
617     let Inst{26-25} = 0b01;
618     let Inst{24} = 1;
619     let Inst{23-21} = op23_21;
620     let Inst{20} = 0; // The S bit.
621     let Inst{14-12} = 0b000; // imm3
622     let Inst{7-6} = 0b00; // imm2
623     let Inst{5-4} = 0b00; // type
624   }
625   // shifted register
626   def rs : T2sTwoRegShiftedReg<
627                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
628                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
629                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
630     let Inst{31-27} = 0b11101;
631     let Inst{26-25} = 0b01;
632     let Inst{24} = 1;
633     let Inst{23-21} = op23_21;
634     let Inst{20} = 0; // The S bit.
635   }
636}
637
638/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
639/// for a binary operation that produces a value and use the carry
640/// bit. It's not predicable.
641let Uses = [CPSR] in {
642multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
643                             bit Commutable = 0> {
644   // shifted imm
645   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
646                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
647                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
648                 Requires<[IsThumb2]> {
649     let Inst{31-27} = 0b11110;
650     let Inst{25} = 0;
651     let Inst{24-21} = opcod;
652     let Inst{20} = 0; // The S bit.
653     let Inst{15} = 0;
654   }
655   // register
656   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
657                 opc, ".w\t$Rd, $Rn, $Rm",
658                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
659                 Requires<[IsThumb2]> {
660     let isCommutable = Commutable;
661     let Inst{31-27} = 0b11101;
662     let Inst{26-25} = 0b01;
663     let Inst{24-21} = opcod;
664     let Inst{20} = 0; // The S bit.
665     let Inst{14-12} = 0b000; // imm3
666     let Inst{7-6} = 0b00; // imm2
667     let Inst{5-4} = 0b00; // type
668   }
669   // shifted register
670   def rs : T2sTwoRegShiftedReg<
671                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
672                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
673                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
674                 Requires<[IsThumb2]> {
675     let Inst{31-27} = 0b11101;
676     let Inst{26-25} = 0b01;
677     let Inst{24-21} = opcod;
678     let Inst{20} = 0; // The S bit.
679   }
680}
681
682// Carry setting variants
683let Defs = [CPSR] in {
684multiclass T2I_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
685                               bit Commutable = 0> {
686   // shifted imm
687   def ri : T2sTwoRegImm<
688                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
689                 opc, "\t$Rd, $Rn, $imm",
690                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
691                 Requires<[IsThumb2]> {
692     let Inst{31-27} = 0b11110;
693     let Inst{25} = 0;
694     let Inst{24-21} = opcod;
695     let Inst{20} = 1; // The S bit.
696     let Inst{15} = 0;
697   }
698   // register
699   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
700                 opc, ".w\t$Rd, $Rn, $Rm",
701                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
702                 Requires<[IsThumb2]> {
703     let isCommutable = Commutable;
704     let Inst{31-27} = 0b11101;
705     let Inst{26-25} = 0b01;
706     let Inst{24-21} = opcod;
707     let Inst{20} = 1; // The S bit.
708     let Inst{14-12} = 0b000; // imm3
709     let Inst{7-6} = 0b00; // imm2
710     let Inst{5-4} = 0b00; // type
711   }
712   // shifted register
713   def rs : T2sTwoRegShiftedReg<
714                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
715                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
716                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
717                 Requires<[IsThumb2]> {
718     let Inst{31-27} = 0b11101;
719     let Inst{26-25} = 0b01;
720     let Inst{24-21} = opcod;
721     let Inst{20} = 1; // The S bit.
722   }
723}
724}
725}
726
727/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
728/// version is not needed since this is only for codegen.
729let Defs = [CPSR] in {
730multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
731   // shifted imm
732   def ri : T2TwoRegImm<
733                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
734                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
735                [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
736     let Inst{31-27} = 0b11110;
737     let Inst{25} = 0;
738     let Inst{24-21} = opcod;
739     let Inst{20} = 1; // The S bit.
740     let Inst{15} = 0;
741   }
742   // shifted register
743   def rs : T2TwoRegShiftedReg<
744                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
745                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
746                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
747     let Inst{31-27} = 0b11101;
748     let Inst{26-25} = 0b01;
749     let Inst{24-21} = opcod;
750     let Inst{20} = 1; // The S bit.
751   }
752}
753}
754
755/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
756//  rotate operation that produces a value.
757multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
758   // 5-bit imm
759   def ri : T2sTwoRegShiftImm<
760                 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
761                 opc, ".w\t$Rd, $Rm, $imm",
762                 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
763     let Inst{31-27} = 0b11101;
764     let Inst{26-21} = 0b010010;
765     let Inst{19-16} = 0b1111; // Rn
766     let Inst{5-4} = opcod;
767   }
768   // register
769   def rr : T2sThreeReg<
770                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
771                 opc, ".w\t$Rd, $Rn, $Rm",
772                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
773     let Inst{31-27} = 0b11111;
774     let Inst{26-23} = 0b0100;
775     let Inst{22-21} = opcod;
776     let Inst{15-12} = 0b1111;
777     let Inst{7-4} = 0b0000;
778   }
779}
780
781/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
782/// patterns. Similar to T2I_bin_irs except the instruction does not produce
783/// a explicit result, only implicitly set CPSR.
784let isCompare = 1, Defs = [CPSR] in {
785multiclass T2I_cmp_irs<bits<4> opcod, string opc,
786                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
787                       PatFrag opnode> {
788   // shifted imm
789   def ri : T2OneRegCmpImm<
790                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
791                opc, ".w\t$Rn, $imm",
792                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
793     let Inst{31-27} = 0b11110;
794     let Inst{25} = 0;
795     let Inst{24-21} = opcod;
796     let Inst{20} = 1; // The S bit.
797     let Inst{15} = 0;
798     let Inst{11-8} = 0b1111; // Rd
799   }
800   // register
801   def rr : T2TwoRegCmp<
802                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
803                opc, ".w\t$lhs, $rhs",
804                [(opnode GPR:$lhs, rGPR:$rhs)]> {
805     let Inst{31-27} = 0b11101;
806     let Inst{26-25} = 0b01;
807     let Inst{24-21} = opcod;
808     let Inst{20} = 1; // The S bit.
809     let Inst{14-12} = 0b000; // imm3
810     let Inst{11-8} = 0b1111; // Rd
811     let Inst{7-6} = 0b00; // imm2
812     let Inst{5-4} = 0b00; // type
813   }
814   // shifted register
815   def rs : T2OneRegCmpShiftedReg<
816                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
817                opc, ".w\t$Rn, $ShiftedRm",
818                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
819     let Inst{31-27} = 0b11101;
820     let Inst{26-25} = 0b01;
821     let Inst{24-21} = opcod;
822     let Inst{20} = 1; // The S bit.
823     let Inst{11-8} = 0b1111; // Rd
824   }
825}
826}
827
828/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
829multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
830                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
831  def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
832                   opc, ".w\t$Rt, $addr",
833                   [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
834    let Inst{31-27} = 0b11111;
835    let Inst{26-25} = 0b00;
836    let Inst{24} = signed;
837    let Inst{23} = 1;
838    let Inst{22-21} = opcod;
839    let Inst{20} = 1; // load
840
841    bits<4> Rt;
842    let Inst{15-12} = Rt{3-0};
843
844    bits<17> addr;
845    let Inst{19-16} = addr{16-13}; // Rn
846    let Inst{23}    = addr{12};    // U
847    let Inst{11-0}  = addr{11-0};  // imm
848  }
849  def i8  : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
850                   opc, "\t$Rt, $addr",
851                   [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
852    let Inst{31-27} = 0b11111;
853    let Inst{26-25} = 0b00;
854    let Inst{24} = signed;
855    let Inst{23} = 0;
856    let Inst{22-21} = opcod;
857    let Inst{20} = 1; // load
858    let Inst{11} = 1;
859    // Offset: index==TRUE, wback==FALSE
860    let Inst{10} = 1; // The P bit.
861    let Inst{8} = 0; // The W bit.
862
863    bits<4> Rt;
864    let Inst{15-12} = Rt{3-0};
865
866    bits<13> addr;
867    let Inst{19-16} = addr{12-9}; // Rn
868    let Inst{9}     = addr{8};    // U
869    let Inst{7-0}   = addr{7-0};  // imm
870  }
871  def s   : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
872                   opc, ".w\t$Rt, $addr",
873                   [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
874    let Inst{31-27} = 0b11111;
875    let Inst{26-25} = 0b00;
876    let Inst{24} = signed;
877    let Inst{23} = 0;
878    let Inst{22-21} = opcod;
879    let Inst{20} = 1; // load
880    let Inst{11-6} = 0b000000;
881
882    bits<4> Rt;
883    let Inst{15-12} = Rt{3-0};
884
885    bits<10> addr;
886    let Inst{19-16} = addr{9-6}; // Rn
887    let Inst{3-0}   = addr{5-2}; // Rm
888    let Inst{5-4}   = addr{1-0}; // imm
889  }
890
891  // FIXME: Is the pci variant actually needed?
892  def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii,
893                   opc, ".w\t$Rt, $addr",
894                   [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
895    let isReMaterializable = 1;
896    let Inst{31-27} = 0b11111;
897    let Inst{26-25} = 0b00;
898    let Inst{24} = signed;
899    let Inst{23} = ?; // add = (U == '1')
900    let Inst{22-21} = opcod;
901    let Inst{20} = 1; // load
902    let Inst{19-16} = 0b1111; // Rn
903
904    bits<4> Rt;
905    bits<12> addr;
906    let Inst{15-12} = Rt{3-0};
907    let Inst{11-0}  = addr{11-0};
908  }
909}
910
911/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
912multiclass T2I_st<bits<2> opcod, string opc,
913                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
914  def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
915                   opc, ".w\t$Rt, $addr",
916                   [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
917    let Inst{31-27} = 0b11111;
918    let Inst{26-23} = 0b0001;
919    let Inst{22-21} = opcod;
920    let Inst{20} = 0; // !load
921
922    bits<4> Rt;
923    let Inst{15-12} = Rt{3-0};
924
925    bits<17> addr;
926    let Inst{19-16} = addr{16-13}; // Rn
927    let Inst{23}    = addr{12};    // U
928    let Inst{11-0}  = addr{11-0};  // imm
929  }
930  def i8  : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
931                   opc, "\t$Rt, $addr",
932                   [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
933    let Inst{31-27} = 0b11111;
934    let Inst{26-23} = 0b0000;
935    let Inst{22-21} = opcod;
936    let Inst{20} = 0; // !load
937    let Inst{11} = 1;
938    // Offset: index==TRUE, wback==FALSE
939    let Inst{10} = 1; // The P bit.
940    let Inst{8} = 0; // The W bit.
941
942    bits<4> Rt;
943    let Inst{15-12} = Rt{3-0};
944
945    bits<13> addr;
946    let Inst{19-16} = addr{12-9}; // Rn
947    let Inst{9}     = addr{8};    // U
948    let Inst{7-0}   = addr{7-0};  // imm
949  }
950  def s   : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
951                   opc, ".w\t$Rt, $addr",
952                   [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
953    let Inst{31-27} = 0b11111;
954    let Inst{26-23} = 0b0000;
955    let Inst{22-21} = opcod;
956    let Inst{20} = 0; // !load
957    let Inst{11-6} = 0b000000;
958
959    bits<4> Rt;
960    let Inst{15-12} = Rt{3-0};
961
962    bits<10> addr;
963    let Inst{19-16}   = addr{9-6}; // Rn
964    let Inst{3-0} = addr{5-2}; // Rm
965    let Inst{5-4}   = addr{1-0}; // imm
966  }
967}
968
969/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
970/// register and one whose operand is a register rotated by 8/16/24.
971multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
972  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
973                  opc, ".w\t$Rd, $Rm",
974                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
975     let Inst{31-27} = 0b11111;
976     let Inst{26-23} = 0b0100;
977     let Inst{22-20} = opcod;
978     let Inst{19-16} = 0b1111; // Rn
979     let Inst{15-12} = 0b1111;
980     let Inst{7} = 1;
981     let Inst{5-4} = 0b00; // rotate
982   }
983  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
984                  opc, ".w\t$Rd, $Rm, ror $rot",
985                 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
986     let Inst{31-27} = 0b11111;
987     let Inst{26-23} = 0b0100;
988     let Inst{22-20} = opcod;
989     let Inst{19-16} = 0b1111; // Rn
990     let Inst{15-12} = 0b1111;
991     let Inst{7} = 1;
992
993     bits<2> rot;
994     let Inst{5-4} = rot{1-0}; // rotate
995   }
996}
997
998// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
999multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1000  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1001                  opc, "\t$Rd, $Rm",
1002                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1003                 Requires<[HasT2ExtractPack, IsThumb2]> {
1004     let Inst{31-27} = 0b11111;
1005     let Inst{26-23} = 0b0100;
1006     let Inst{22-20} = opcod;
1007     let Inst{19-16} = 0b1111; // Rn
1008     let Inst{15-12} = 0b1111;
1009     let Inst{7} = 1;
1010     let Inst{5-4} = 0b00; // rotate
1011   }
1012  def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1013                  opc, "\t$dst, $Rm, ror $rot",
1014                 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1015                 Requires<[HasT2ExtractPack, IsThumb2]> {
1016     let Inst{31-27} = 0b11111;
1017     let Inst{26-23} = 0b0100;
1018     let Inst{22-20} = opcod;
1019     let Inst{19-16} = 0b1111; // Rn
1020     let Inst{15-12} = 0b1111;
1021     let Inst{7} = 1;
1022
1023     bits<2> rot;
1024     let Inst{5-4} = rot{1-0}; // rotate
1025   }
1026}
1027
1028// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1029// supported yet.
1030multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1031  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1032                  opc, "\t$Rd, $Rm", []> {
1033     let Inst{31-27} = 0b11111;
1034     let Inst{26-23} = 0b0100;
1035     let Inst{22-20} = opcod;
1036     let Inst{19-16} = 0b1111; // Rn
1037     let Inst{15-12} = 0b1111;
1038     let Inst{7} = 1;
1039     let Inst{5-4} = 0b00; // rotate
1040   }
1041  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1042                  opc, "\t$Rd, $Rm, ror $rot", []> {
1043     let Inst{31-27} = 0b11111;
1044     let Inst{26-23} = 0b0100;
1045     let Inst{22-20} = opcod;
1046     let Inst{19-16} = 0b1111; // Rn
1047     let Inst{15-12} = 0b1111;
1048     let Inst{7} = 1;
1049
1050      bits<2> rot;
1051      let Inst{5-4} = rot{1-0}; // rotate
1052   }
1053}
1054
1055/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1056/// register and one whose operand is a register rotated by 8/16/24.
1057multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1058  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1059                  opc, "\t$Rd, $Rn, $Rm",
1060                  [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1061                  Requires<[HasT2ExtractPack, IsThumb2]> {
1062     let Inst{31-27} = 0b11111;
1063     let Inst{26-23} = 0b0100;
1064     let Inst{22-20} = opcod;
1065     let Inst{15-12} = 0b1111;
1066     let Inst{7} = 1;
1067     let Inst{5-4} = 0b00; // rotate
1068   }
1069  def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1070                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1071                  [(set rGPR:$Rd, (opnode rGPR:$Rn,
1072                                          (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1073                  Requires<[HasT2ExtractPack, IsThumb2]> {
1074     let Inst{31-27} = 0b11111;
1075     let Inst{26-23} = 0b0100;
1076     let Inst{22-20} = opcod;
1077     let Inst{15-12} = 0b1111;
1078     let Inst{7} = 1;
1079
1080     bits<2> rot;
1081     let Inst{5-4} = rot{1-0}; // rotate
1082   }
1083}
1084
1085// DO variant - disassembly only, no pattern
1086
1087multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1088  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1089                  opc, "\t$Rd, $Rn, $Rm", []> {
1090     let Inst{31-27} = 0b11111;
1091     let Inst{26-23} = 0b0100;
1092     let Inst{22-20} = opcod;
1093     let Inst{15-12} = 0b1111;
1094     let Inst{7} = 1;
1095     let Inst{5-4} = 0b00; // rotate
1096   }
1097  def rr_rot : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1098                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1099     let Inst{31-27} = 0b11111;
1100     let Inst{26-23} = 0b0100;
1101     let Inst{22-20} = opcod;
1102     let Inst{15-12} = 0b1111;
1103     let Inst{7} = 1;
1104
1105     bits<2> rot;
1106     let Inst{5-4} = rot{1-0}; // rotate
1107   }
1108}
1109
1110//===----------------------------------------------------------------------===//
1111// Instructions
1112//===----------------------------------------------------------------------===//
1113
1114//===----------------------------------------------------------------------===//
1115//  Miscellaneous Instructions.
1116//
1117
1118class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1119           string asm, list<dag> pattern>
1120  : T2XI<oops, iops, itin, asm, pattern> {
1121  bits<4> Rd;
1122  bits<12> label;
1123
1124  let Inst{11-8}  = Rd{3-0};
1125  let Inst{26}    = label{11};
1126  let Inst{14-12} = label{10-8};
1127  let Inst{7-0}   = label{7-0};
1128}
1129
1130// LEApcrel - Load a pc-relative address into a register without offending the
1131// assembler.
1132let neverHasSideEffects = 1 in {
1133let isReMaterializable = 1 in
1134def t2LEApcrel : T2PCOneRegImm<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1135                      "adr${p}.w\t$Rd, #$label", []> {
1136  let Inst{31-27} = 0b11110;
1137  let Inst{25-24} = 0b10;
1138  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1139  let Inst{22} = 0;
1140  let Inst{20} = 0;
1141  let Inst{19-16} = 0b1111; // Rn
1142  let Inst{15} = 0;
1143
1144
1145}
1146} // neverHasSideEffects
1147def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
1148                        (ins i32imm:$label, nohash_imm:$id, pred:$p), IIC_iALUi,
1149                        "adr${p}.w\t$Rd, #${label}_${id}", []> {
1150  let Inst{31-27} = 0b11110;
1151  let Inst{25-24} = 0b10;
1152  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1153  let Inst{22} = 0;
1154  let Inst{20} = 0;
1155  let Inst{19-16} = 0b1111; // Rn
1156  let Inst{15} = 0;
1157}
1158
1159// ADD r, sp, {so_imm|i12}
1160def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
1161                        IIC_iALUi, "add", ".w\t$Rd, $sp, $imm", []> {
1162  let Inst{31-27} = 0b11110;
1163  let Inst{25} = 0;
1164  let Inst{24-21} = 0b1000;
1165  let Inst{20} = ?; // The S bit.
1166  let Inst{19-16} = 0b1101; // Rn = sp
1167  let Inst{15} = 0;
1168}
1169def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
1170                       IIC_iALUi, "addw", "\t$Rd, $sp, $imm", []> {
1171  let Inst{31-27} = 0b11110;
1172  let Inst{25} = 1;
1173  let Inst{24-21} = 0b0000;
1174  let Inst{20} = 0; // The S bit.
1175  let Inst{19-16} = 0b1101; // Rn = sp
1176  let Inst{15} = 0;
1177}
1178
1179// ADD r, sp, so_reg
1180def t2ADDrSPs   : T2sTwoRegShiftedReg<
1181                        (outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$ShiftedRm),
1182                        IIC_iALUsi, "add", ".w\t$Rd, $sp, $ShiftedRm", []> {
1183  let Inst{31-27} = 0b11101;
1184  let Inst{26-25} = 0b01;
1185  let Inst{24-21} = 0b1000;
1186  let Inst{20} = ?; // The S bit.
1187  let Inst{19-16} = 0b1101; // Rn = sp
1188  let Inst{15} = 0;
1189}
1190
1191// SUB r, sp, {so_imm|i12}
1192def t2SUBrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_imm:$imm),
1193                        IIC_iALUi, "sub", ".w\t$Rd, $sp, $imm", []> {
1194  let Inst{31-27} = 0b11110;
1195  let Inst{25} = 0;
1196  let Inst{24-21} = 0b1101;
1197  let Inst{20} = ?; // The S bit.
1198  let Inst{19-16} = 0b1101; // Rn = sp
1199  let Inst{15} = 0;
1200}
1201def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
1202                       IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
1203  let Inst{31-27} = 0b11110;
1204  let Inst{25} = 1;
1205  let Inst{24-21} = 0b0101;
1206  let Inst{20} = 0; // The S bit.
1207  let Inst{19-16} = 0b1101; // Rn = sp
1208  let Inst{15} = 0;
1209}
1210
1211// SUB r, sp, so_reg
1212def t2SUBrSPs   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, t2_so_reg:$imm),
1213                       IIC_iALUsi,
1214                       "sub", "\t$Rd, $sp, $imm", []> {
1215  let Inst{31-27} = 0b11101;
1216  let Inst{26-25} = 0b01;
1217  let Inst{24-21} = 0b1101;
1218  let Inst{20} = ?; // The S bit.
1219  let Inst{19-16} = 0b1101; // Rn = sp
1220  let Inst{15} = 0;
1221}
1222
1223// Signed and unsigned division on v7-M
1224def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1225                 "sdiv", "\t$Rd, $Rn, $Rm",
1226                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
1227                 Requires<[HasDivide, IsThumb2]> {
1228  let Inst{31-27} = 0b11111;
1229  let Inst{26-21} = 0b011100;
1230  let Inst{20} = 0b1;
1231  let Inst{15-12} = 0b1111;
1232  let Inst{7-4} = 0b1111;
1233}
1234
1235def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
1236                 "udiv", "\t$Rd, $Rn, $Rm",
1237                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
1238                 Requires<[HasDivide, IsThumb2]> {
1239  let Inst{31-27} = 0b11111;
1240  let Inst{26-21} = 0b011101;
1241  let Inst{20} = 0b1;
1242  let Inst{15-12} = 0b1111;
1243  let Inst{7-4} = 0b1111;
1244}
1245
1246//===----------------------------------------------------------------------===//
1247//  Load / store Instructions.
1248//
1249
1250// Load
1251let canFoldAsLoad = 1, isReMaterializable = 1  in
1252defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1253                      UnOpFrag<(load node:$Src)>>;
1254
1255// Loads with zero extension
1256defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1257                      UnOpFrag<(zextloadi16 node:$Src)>>;
1258defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1259                      UnOpFrag<(zextloadi8  node:$Src)>>;
1260
1261// Loads with sign extension
1262defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1263                      UnOpFrag<(sextloadi16 node:$Src)>>;
1264defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1265                      UnOpFrag<(sextloadi8  node:$Src)>>;
1266
1267let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1268// Load doubleword
1269def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1270                        (ins t2addrmode_imm8s4:$addr),
1271                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1272} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1273
1274// zextload i1 -> zextload i8
1275def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1276            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1277def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1278            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1279def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1280            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1281def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1282            (t2LDRBpci  tconstpool:$addr)>;
1283
1284// extload -> zextload
1285// FIXME: Reduce the number of patterns by legalizing extload to zextload
1286// earlier?
1287def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1288            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1289def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1290            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1291def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1292            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1293def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1294            (t2LDRBpci  tconstpool:$addr)>;
1295
1296def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1297            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1298def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1299            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1300def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1301            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1302def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1303            (t2LDRBpci  tconstpool:$addr)>;
1304
1305def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1306            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1307def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1308            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1309def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1310            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1311def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1312            (t2LDRHpci  tconstpool:$addr)>;
1313
1314// FIXME: The destination register of the loads and stores can't be PC, but
1315//        can be SP. We need another regclass (similar to rGPR) to represent
1316//        that. Not a pressing issue since these are selected manually,
1317//        not via pattern.
1318
1319// Indexed loads
1320
1321class T2Iidxld<bit signed, bits<2> opcod, bit pre,
1322                 dag oops, dag iops,
1323                 AddrMode am, IndexMode im, InstrItinClass itin,
1324                 string opc, string asm, string cstr, list<dag> pattern>
1325  : T2Iidxldst<signed, opcod, 1, pre, oops,
1326               iops, am,im,itin, opc, asm, cstr, pattern>;
1327class T2Iidxst<bit signed, bits<2> opcod, bit pre,
1328                 dag oops, dag iops,
1329                 AddrMode am, IndexMode im, InstrItinClass itin,
1330                 string opc, string asm, string cstr, list<dag> pattern>
1331  : T2Iidxldst<signed, opcod, 0, pre, oops,
1332               iops, am,im,itin, opc, asm, cstr, pattern>;
1333
1334let mayLoad = 1, neverHasSideEffects = 1 in {
1335def t2LDR_PRE  : T2Iidxld<0, 0b10, 1, (outs GPR:$Rt, GPR:$Rn),
1336                            (ins t2addrmode_imm8:$addr),
1337                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1338                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1339                            []>;
1340
1341def t2LDR_POST : T2Iidxld<0, 0b10, 0, (outs GPR:$Rt, GPR:$Rn),
1342                            (ins GPR:$base, t2am_imm8_offset:$offset),
1343                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1344                          "ldr", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1345                            []>;
1346
1347def t2LDRB_PRE : T2Iidxld<0, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1348                            (ins t2addrmode_imm8:$addr),
1349                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1350                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1351                            []>;
1352def t2LDRB_POST : T2Iidxld<0, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1353                            (ins GPR:$base, t2am_imm8_offset:$offset),
1354                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1355                         "ldrb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1356                            []>;
1357
1358def t2LDRH_PRE : T2Iidxld<0, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1359                            (ins t2addrmode_imm8:$addr),
1360                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1361                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1362                            []>;
1363def t2LDRH_POST : T2Iidxld<0, 0b01, 0, (outs GPR:$Rt, GPR:$Rn),
1364                            (ins GPR:$base, t2am_imm8_offset:$offset),
1365                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1366                         "ldrh", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1367                            []>;
1368
1369def t2LDRSB_PRE : T2Iidxld<1, 0b00, 1, (outs GPR:$Rt, GPR:$Rn),
1370                            (ins t2addrmode_imm8:$addr),
1371                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1372                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1373                            []>;
1374def t2LDRSB_POST : T2Iidxld<1, 0b00, 0, (outs GPR:$Rt, GPR:$Rn),
1375                            (ins GPR:$base, t2am_imm8_offset:$offset),
1376                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1377                        "ldrsb", "\t$Rt, [$Rn], $offset", "$base = $Rn",
1378                            []>;
1379
1380def t2LDRSH_PRE : T2Iidxld<1, 0b01, 1, (outs GPR:$Rt, GPR:$Rn),
1381                            (ins t2addrmode_imm8:$addr),
1382                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1383                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1384                            []>;
1385def t2LDRSH_POST : T2Iidxld<1, 0b01, 0, (outs GPR:$dst, GPR:$Rn),
1386                            (ins GPR:$base, t2am_imm8_offset:$offset),
1387                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1388                        "ldrsh", "\t$dst, [$Rn], $offset", "$base = $Rn",
1389                            []>;
1390} // mayLoad = 1, neverHasSideEffects = 1
1391
1392// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1393// for disassembly only.
1394// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1395class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1396  : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1397          "\t$Rt, $addr", []> {
1398  let Inst{31-27} = 0b11111;
1399  let Inst{26-25} = 0b00;
1400  let Inst{24} = signed;
1401  let Inst{23} = 0;
1402  let Inst{22-21} = type;
1403  let Inst{20} = 1; // load
1404  let Inst{11} = 1;
1405  let Inst{10-8} = 0b110; // PUW.
1406
1407  bits<4> Rt;
1408  bits<13> addr;
1409  let Inst{15-12} = Rt{3-0};
1410  let Inst{19-16} = addr{12-9};
1411  let Inst{7-0}   = addr{7-0};
1412}
1413
1414def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1415def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1416def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1417def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1418def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1419
1420// Store
1421defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1422                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1423defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1424                   BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1425defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1426                   BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1427
1428// Store doubleword
1429let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1430def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1431                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1432               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1433
1434// Indexed stores
1435def t2STR_PRE  : T2Iidxst<0, 0b10, 1, (outs GPR:$base_wb),
1436                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1437                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1438                         "str", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1439             [(set GPR:$base_wb,
1440                   (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1441
1442def t2STR_POST : T2Iidxst<0, 0b10, 0, (outs GPR:$base_wb),
1443                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1444                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1445                          "str", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1446             [(set GPR:$base_wb,
1447                  (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1448
1449def t2STRH_PRE  : T2Iidxst<0, 0b01, 1, (outs GPR:$base_wb),
1450                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1451                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1452                        "strh", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1453        [(set GPR:$base_wb,
1454              (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1455
1456def t2STRH_POST : T2Iidxst<0, 0b01, 0, (outs GPR:$base_wb),
1457                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1458                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1459                         "strh", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1460       [(set GPR:$base_wb,
1461             (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1462
1463def t2STRB_PRE  : T2Iidxst<0, 0b00, 1, (outs GPR:$base_wb),
1464                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1465                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1466                        "strb", "\t$Rt, [$Rn, $addr]!", "$Rn = $base_wb",
1467         [(set GPR:$base_wb,
1468               (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1469
1470def t2STRB_POST : T2Iidxst<0, 0b00, 0, (outs GPR:$base_wb),
1471                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1472                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1473                         "strb", "\t$Rt, [$Rn], $addr", "$Rn = $base_wb",
1474        [(set GPR:$base_wb,
1475              (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1476
1477// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1478// only.
1479// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1480class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1481  : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1482          "\t$Rt, $addr", []> {
1483  let Inst{31-27} = 0b11111;
1484  let Inst{26-25} = 0b00;
1485  let Inst{24} = 0; // not signed
1486  let Inst{23} = 0;
1487  let Inst{22-21} = type;
1488  let Inst{20} = 0; // store
1489  let Inst{11} = 1;
1490  let Inst{10-8} = 0b110; // PUW
1491
1492  bits<4> Rt;
1493  bits<13> addr;
1494  let Inst{15-12} = Rt{3-0};
1495  let Inst{19-16} = addr{12-9};
1496  let Inst{7-0}   = addr{7-0};
1497}
1498
1499def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1500def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1501def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1502
1503// ldrd / strd pre / post variants
1504// For disassembly only.
1505
1506def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1507                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1508                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1509
1510def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs GPR:$Rt, GPR:$Rt2),
1511                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1512                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1513
1514def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs),
1515                 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1516                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1517
1518def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1519                 (ins GPR:$Rt, GPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1520                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1521
1522// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1523// data/instruction access.  These are for disassembly only.
1524// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1525// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1526multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1527
1528  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1529                "\t$addr",
1530              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1531    let Inst{31-25} = 0b1111100;
1532    let Inst{24} = instr;
1533    let Inst{22} = 0;
1534    let Inst{21} = write;
1535    let Inst{20} = 1;
1536    let Inst{15-12} = 0b1111;
1537
1538    bits<17> addr;
1539    let Inst{19-16} = addr{16-13}; // Rn
1540    let Inst{23}    = addr{12};    // U
1541    let Inst{11-0}  = addr{11-0};  // imm12
1542  }
1543
1544  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1545                "\t$addr",
1546               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1547    let Inst{31-25} = 0b1111100;
1548    let Inst{24} = instr;
1549    let Inst{23} = 0; // U = 0
1550    let Inst{22} = 0;
1551    let Inst{21} = write;
1552    let Inst{20} = 1;
1553    let Inst{15-12} = 0b1111;
1554    let Inst{11-8} = 0b1100;
1555
1556    bits<13> addr;
1557    let Inst{19-16} = addr{12-9}; // Rn
1558    let Inst{7-0}   = addr{7-0};  // imm8
1559  }
1560
1561  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1562               "\t$addr",
1563             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1564    let Inst{31-25} = 0b1111100;
1565    let Inst{24} = instr;
1566    let Inst{23} = 0; // add = TRUE for T1
1567    let Inst{22} = 0;
1568    let Inst{21} = write;
1569    let Inst{20} = 1;
1570    let Inst{15-12} = 0b1111;
1571    let Inst{11-6} = 0000000;
1572
1573    bits<10> addr;
1574    let Inst{19-16} = addr{9-6}; // Rn
1575    let Inst{3-0}   = addr{5-2}; // Rm
1576    let Inst{5-4}   = addr{1-0}; // imm2
1577  }
1578}
1579
1580defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1581defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1582defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1583
1584//===----------------------------------------------------------------------===//
1585//  Load / store multiple Instructions.
1586//
1587
1588multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1589                            InstrItinClass itin_upd, bit L_bit> {
1590  def IA :
1591    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1592         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1593    bits<4>  Rn;
1594    bits<16> regs;
1595
1596    let Inst{31-27} = 0b11101;
1597    let Inst{26-25} = 0b00;
1598    let Inst{24-23} = 0b01;     // Increment After
1599    let Inst{22}    = 0;
1600    let Inst{21}    = 0;        // No writeback
1601    let Inst{20}    = L_bit;
1602    let Inst{19-16} = Rn;
1603    let Inst{15-0}  = regs;
1604  }
1605  def IA_UPD :
1606    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1607          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1608    bits<4>  Rn;
1609    bits<16> regs;
1610
1611    let Inst{31-27} = 0b11101;
1612    let Inst{26-25} = 0b00;
1613    let Inst{24-23} = 0b01;     // Increment After
1614    let Inst{22}    = 0;
1615    let Inst{21}    = 1;        // Writeback
1616    let Inst{20}    = L_bit;
1617    let Inst{19-16} = Rn;
1618    let Inst{15-0}  = regs;
1619  }
1620  def DB :
1621    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1622         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1623    bits<4>  Rn;
1624    bits<16> regs;
1625
1626    let Inst{31-27} = 0b11101;
1627    let Inst{26-25} = 0b00;
1628    let Inst{24-23} = 0b10;     // Decrement Before
1629    let Inst{22}    = 0;
1630    let Inst{21}    = 0;        // No writeback
1631    let Inst{20}    = L_bit;
1632    let Inst{19-16} = Rn;
1633    let Inst{15-0}  = regs;
1634  }
1635  def DB_UPD :
1636    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1637          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1638    bits<4>  Rn;
1639    bits<16> regs;
1640
1641    let Inst{31-27} = 0b11101;
1642    let Inst{26-25} = 0b00;
1643    let Inst{24-23} = 0b10;     // Decrement Before
1644    let Inst{22}    = 0;
1645    let Inst{21}    = 1;        // Writeback
1646    let Inst{20}    = L_bit;
1647    let Inst{19-16} = Rn;
1648    let Inst{15-0}  = regs;
1649  }
1650}
1651
1652let neverHasSideEffects = 1 in {
1653
1654let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1655defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1656
1657let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1658defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1659
1660} // neverHasSideEffects
1661
1662
1663//===----------------------------------------------------------------------===//
1664//  Move Instructions.
1665//
1666
1667let neverHasSideEffects = 1 in
1668def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1669                   "mov", ".w\t$Rd, $Rm", []> {
1670  let Inst{31-27} = 0b11101;
1671  let Inst{26-25} = 0b01;
1672  let Inst{24-21} = 0b0010;
1673  let Inst{20} = ?; // The S bit.
1674  let Inst{19-16} = 0b1111; // Rn
1675  let Inst{14-12} = 0b000;
1676  let Inst{7-4} = 0b0000;
1677}
1678
1679// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1680let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1681    AddedComplexity = 1 in
1682def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1683                   "mov", ".w\t$Rd, $imm",
1684                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1685  let Inst{31-27} = 0b11110;
1686  let Inst{25} = 0;
1687  let Inst{24-21} = 0b0010;
1688  let Inst{20} = ?; // The S bit.
1689  let Inst{19-16} = 0b1111; // Rn
1690  let Inst{15} = 0;
1691}
1692
1693let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1694def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi,
1695                   "movw", "\t$Rd, $imm",
1696                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1697  let Inst{31-27} = 0b11110;
1698  let Inst{25} = 1;
1699  let Inst{24-21} = 0b0010;
1700  let Inst{20} = 0; // The S bit.
1701  let Inst{15} = 0;
1702
1703  bits<4> Rd;
1704  bits<16> imm;
1705
1706  let Inst{11-8}  = Rd{3-0};
1707  let Inst{19-16} = imm{15-12};
1708  let Inst{26}    = imm{11};
1709  let Inst{14-12} = imm{10-8};
1710  let Inst{7-0}   = imm{7-0};
1711}
1712
1713let Constraints = "$src = $Rd" in
1714def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi,
1715                    "movt", "\t$Rd, $imm",
1716                    [(set rGPR:$Rd,
1717                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1718  let Inst{31-27} = 0b11110;
1719  let Inst{25} = 1;
1720  let Inst{24-21} = 0b0110;
1721  let Inst{20} = 0; // The S bit.
1722  let Inst{15} = 0;
1723
1724  bits<4> Rd;
1725  bits<16> imm;
1726
1727  let Inst{11-8}  = Rd{3-0};
1728  let Inst{19-16} = imm{15-12};
1729  let Inst{26}    = imm{11};
1730  let Inst{14-12} = imm{10-8};
1731  let Inst{7-0}   = imm{7-0};
1732}
1733
1734def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1735
1736//===----------------------------------------------------------------------===//
1737//  Extend Instructions.
1738//
1739
1740// Sign extenders
1741
1742defm t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1743                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1744defm t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1745                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1746defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1747
1748defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1749                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1750defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1751                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1752defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1753
1754// TODO: SXT(A){B|H}16 - done for disassembly only
1755
1756// Zero extenders
1757
1758let AddedComplexity = 16 in {
1759defm t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1760                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1761defm t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1762                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1763defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1764                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1765
1766// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1767//        The transformation should probably be done as a combiner action
1768//        instead so we can include a check for masking back in the upper
1769//        eight bits of the source into the lower eight bits of the result.
1770//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1771//            (t2UXTB16r_rot rGPR:$Src, 24)>,
1772//          Requires<[HasT2ExtractPack, IsThumb2]>;
1773def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1774            (t2UXTB16r_rot rGPR:$Src, 8)>,
1775        Requires<[HasT2ExtractPack, IsThumb2]>;
1776
1777defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1778                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1779defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1780                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1781defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1782}
1783
1784//===----------------------------------------------------------------------===//
1785//  Arithmetic Instructions.
1786//
1787
1788defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1789                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1790defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1791                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1792
1793// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1794defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1795                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1796                             BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1797defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1798                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1799                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1800
1801defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1802                          BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1803defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1804                          BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1805defm t2ADCS : T2I_adde_sube_s_irs<0b1010, "adc",
1806                          BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
1807defm t2SBCS : T2I_adde_sube_s_irs<0b1011, "sbc",
1808                          BinOpFrag<(sube_live_carry node:$LHS, node:$RHS)>>;
1809
1810// RSB
1811defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1812                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1813defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1814                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1815
1816// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1817// The assume-no-carry-in form uses the negation of the input since add/sub
1818// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1819// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1820// details.
1821// The AddedComplexity preferences the first variant over the others since
1822// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1823let AddedComplexity = 1 in
1824def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1825            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1826def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1827            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1828def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1829            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1830let AddedComplexity = 1 in
1831def : T2Pat<(addc       rGPR:$src, imm0_255_neg:$imm),
1832            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1833def : T2Pat<(addc       rGPR:$src, t2_so_imm_neg:$imm),
1834            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1835// The with-carry-in form matches bitwise not instead of the negation.
1836// Effectively, the inverse interpretation of the carry flag already accounts
1837// for part of the negation.
1838let AddedComplexity = 1 in
1839def : T2Pat<(adde       rGPR:$src, imm0_255_not:$imm),
1840            (t2SBCSri   rGPR:$src, imm0_255_not:$imm)>;
1841def : T2Pat<(adde       rGPR:$src, t2_so_imm_not:$imm),
1842            (t2SBCSri   rGPR:$src, t2_so_imm_not:$imm)>;
1843
1844// Select Bytes -- for disassembly only
1845
1846def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1847                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1848  let Inst{31-27} = 0b11111;
1849  let Inst{26-24} = 0b010;
1850  let Inst{23} = 0b1;
1851  let Inst{22-20} = 0b010;
1852  let Inst{15-12} = 0b1111;
1853  let Inst{7} = 0b1;
1854  let Inst{6-4} = 0b000;
1855}
1856
1857// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1858// And Miscellaneous operations -- for disassembly only
1859class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1860              list<dag> pat = [/* For disassembly only; pattern left blank */]>
1861  : T2I<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, opc,
1862        "\t$Rd, $Rn, $Rm", pat> {
1863  let Inst{31-27} = 0b11111;
1864  let Inst{26-23} = 0b0101;
1865  let Inst{22-20} = op22_20;
1866  let Inst{15-12} = 0b1111;
1867  let Inst{7-4} = op7_4;
1868
1869  bits<4> Rd;
1870  bits<4> Rn;
1871  bits<4> Rm;
1872
1873  let Inst{11-8}  = Rd{3-0};
1874  let Inst{19-16} = Rn{3-0};
1875  let Inst{3-0}   = Rm{3-0};
1876}
1877
1878// Saturating add/subtract -- for disassembly only
1879
1880def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1881                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))]>;
1882def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1883def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1884def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1885def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd">;
1886def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub">;
1887def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1888def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1889                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))]>;
1890def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1891def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1892def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1893def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1894def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1895def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1896def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1897def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1898
1899// Signed/Unsigned add/subtract -- for disassembly only
1900
1901def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1902def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1903def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1904def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1905def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1906def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1907def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1908def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1909def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1910def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1911def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1912def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1913
1914// Signed/Unsigned halving add/subtract -- for disassembly only
1915
1916def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1917def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1918def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1919def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1920def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1921def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1922def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1923def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1924def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1925def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1926def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1927def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1928
1929// Helper class for disassembly only
1930// A6.3.16 & A6.3.17
1931// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1932class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1933  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1934  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1935  let Inst{31-27} = 0b11111;
1936  let Inst{26-24} = 0b011;
1937  let Inst{23}    = long;
1938  let Inst{22-20} = op22_20;
1939  let Inst{7-4}   = op7_4;
1940}
1941
1942class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1943  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1944  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1945  let Inst{31-27} = 0b11111;
1946  let Inst{26-24} = 0b011;
1947  let Inst{23}    = long;
1948  let Inst{22-20} = op22_20;
1949  let Inst{7-4}   = op7_4;
1950}
1951
1952// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1953
1954def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1955                                           (ins rGPR:$Rn, rGPR:$Rm),
1956                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1957  let Inst{15-12} = 0b1111;
1958}
1959def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1960                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1961                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1962
1963// Signed/Unsigned saturate -- for disassembly only
1964
1965class T2SatI<dag oops, dag iops, InstrItinClass itin,
1966           string opc, string asm, list<dag> pattern>
1967  : T2I<oops, iops, itin, opc, asm, pattern> {
1968  bits<4> Rd;
1969  bits<4> Rn;
1970  bits<5> sat_imm;
1971  bits<7> sh;
1972
1973  let Inst{11-8}  = Rd{3-0};
1974  let Inst{19-16} = Rn{3-0};
1975  let Inst{4-0}   = sat_imm{4-0};
1976  let Inst{21}    = sh{6};
1977  let Inst{14-12} = sh{4-2};
1978  let Inst{7-6}   = sh{1-0};
1979}
1980
1981def t2SSAT: T2SatI<
1982                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1983                NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1984                [/* For disassembly only; pattern left blank */]> {
1985  let Inst{31-27} = 0b11110;
1986  let Inst{25-22} = 0b1100;
1987  let Inst{20} = 0;
1988  let Inst{15} = 0;
1989}
1990
1991def t2SSAT16: T2SatI<
1992                   (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
1993                   "ssat16", "\t$Rd, $sat_imm, $Rn",
1994                   [/* For disassembly only; pattern left blank */]> {
1995  let Inst{31-27} = 0b11110;
1996  let Inst{25-22} = 0b1100;
1997  let Inst{20} = 0;
1998  let Inst{15} = 0;
1999  let Inst{21} = 1;        // sh = '1'
2000  let Inst{14-12} = 0b000; // imm3 = '000'
2001  let Inst{7-6} = 0b00;    // imm2 = '00'
2002}
2003
2004def t2USAT: T2SatI<
2005                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
2006                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
2007                [/* For disassembly only; pattern left blank */]> {
2008  let Inst{31-27} = 0b11110;
2009  let Inst{25-22} = 0b1110;
2010  let Inst{20} = 0;
2011  let Inst{15} = 0;
2012}
2013
2014def t2USAT16: T2SatI<
2015                    (outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
2016                   "usat16", "\t$dst, $sat_imm, $Rn",
2017                   [/* For disassembly only; pattern left blank */]> {
2018  let Inst{31-27} = 0b11110;
2019  let Inst{25-22} = 0b1110;
2020  let Inst{20} = 0;
2021  let Inst{15} = 0;
2022  let Inst{21} = 1;        // sh = '1'
2023  let Inst{14-12} = 0b000; // imm3 = '000'
2024  let Inst{7-6} = 0b00;    // imm2 = '00'
2025}
2026
2027def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
2028def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
2029
2030//===----------------------------------------------------------------------===//
2031//  Shift and rotate Instructions.
2032//
2033
2034defm t2LSL  : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
2035defm t2LSR  : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl  node:$LHS, node:$RHS)>>;
2036defm t2ASR  : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
2037defm t2ROR  : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
2038
2039let Uses = [CPSR] in {
2040def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2041                   "rrx", "\t$Rd, $Rm",
2042                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
2043  let Inst{31-27} = 0b11101;
2044  let Inst{26-25} = 0b01;
2045  let Inst{24-21} = 0b0010;
2046  let Inst{20} = ?; // The S bit.
2047  let Inst{19-16} = 0b1111; // Rn
2048  let Inst{14-12} = 0b000;
2049  let Inst{7-4} = 0b0011;
2050}
2051}
2052
2053let Defs = [CPSR] in {
2054def t2MOVsrl_flag : T2TwoRegShiftImm<
2055                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2056                        "lsrs", ".w\t$Rd, $Rm, #1",
2057                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2058  let Inst{31-27} = 0b11101;
2059  let Inst{26-25} = 0b01;
2060  let Inst{24-21} = 0b0010;
2061  let Inst{20} = 1; // The S bit.
2062  let Inst{19-16} = 0b1111; // Rn
2063  let Inst{5-4} = 0b01; // Shift type.
2064  // Shift amount = Inst{14-12:7-6} = 1.
2065  let Inst{14-12} = 0b000;
2066  let Inst{7-6} = 0b01;
2067}
2068def t2MOVsra_flag : T2TwoRegShiftImm<
2069                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2070                        "asrs", ".w\t$Rd, $Rm, #1",
2071                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2072  let Inst{31-27} = 0b11101;
2073  let Inst{26-25} = 0b01;
2074  let Inst{24-21} = 0b0010;
2075  let Inst{20} = 1; // The S bit.
2076  let Inst{19-16} = 0b1111; // Rn
2077  let Inst{5-4} = 0b10; // Shift type.
2078  // Shift amount = Inst{14-12:7-6} = 1.
2079  let Inst{14-12} = 0b000;
2080  let Inst{7-6} = 0b01;
2081}
2082}
2083
2084//===----------------------------------------------------------------------===//
2085//  Bitwise Instructions.
2086//
2087
2088defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2089                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2090                            BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2091defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
2092                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2093                            BinOpFrag<(or  node:$LHS, node:$RHS)>, 1>;
2094defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
2095                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2096                            BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2097
2098defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
2099                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2100                            BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2101
2102class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2103              string opc, string asm, list<dag> pattern>
2104    : T2I<oops, iops, itin, opc, asm, pattern> {
2105  bits<4> Rd;
2106  bits<5> msb;
2107  bits<5> lsb;
2108
2109  let Inst{11-8}  = Rd{3-0};
2110  let Inst{4-0}   = msb{4-0};
2111  let Inst{14-12} = lsb{4-2};
2112  let Inst{7-6}   = lsb{1-0};
2113}
2114
2115class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2116              string opc, string asm, list<dag> pattern>
2117    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2118  bits<4> Rn;
2119
2120  let Inst{19-16} = Rn{3-0};
2121}
2122
2123let Constraints = "$src = $Rd" in
2124def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2125                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2126                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2127  let Inst{31-27} = 0b11110;
2128  let Inst{25} = 1;
2129  let Inst{24-20} = 0b10110;
2130  let Inst{19-16} = 0b1111; // Rn
2131  let Inst{15} = 0;
2132
2133  bits<10> imm;
2134  let msb{4-0} = imm{9-5};
2135  let lsb{4-0} = imm{4-0};
2136}
2137
2138def t2SBFX: T2TwoRegBitFI<
2139                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2140                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2141  let Inst{31-27} = 0b11110;
2142  let Inst{25} = 1;
2143  let Inst{24-20} = 0b10100;
2144  let Inst{15} = 0;
2145}
2146
2147def t2UBFX: T2TwoRegBitFI<
2148                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2149                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2150  let Inst{31-27} = 0b11110;
2151  let Inst{25} = 1;
2152  let Inst{24-20} = 0b11100;
2153  let Inst{15} = 0;
2154}
2155
2156// A8.6.18  BFI - Bitfield insert (Encoding T1)
2157let Constraints = "$src = $Rd" in
2158def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2159                (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2160                IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2161                [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2162                                 bf_inv_mask_imm:$imm))]> {
2163  let Inst{31-27} = 0b11110;
2164  let Inst{25} = 1;
2165  let Inst{24-20} = 0b10110;
2166  let Inst{15} = 0;
2167
2168  bits<10> imm;
2169  let msb{4-0} = imm{9-5};
2170  let lsb{4-0} = imm{4-0};
2171}
2172
2173defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2174                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2175                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>, 0, "">;
2176
2177// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2178let AddedComplexity = 1 in
2179defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2180                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2181                          UnOpFrag<(not node:$Src)>, 1, 1>;
2182
2183
2184let AddedComplexity = 1 in
2185def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2186            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2187
2188// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2189def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2190            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2191            Requires<[IsThumb2]>;
2192
2193def : T2Pat<(t2_so_imm_not:$src),
2194            (t2MVNi t2_so_imm_not:$src)>;
2195
2196//===----------------------------------------------------------------------===//
2197//  Multiply Instructions.
2198//
2199let isCommutable = 1 in
2200def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2201                "mul", "\t$Rd, $Rn, $Rm",
2202                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2203  let Inst{31-27} = 0b11111;
2204  let Inst{26-23} = 0b0110;
2205  let Inst{22-20} = 0b000;
2206  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2207  let Inst{7-4} = 0b0000; // Multiply
2208}
2209
2210def t2MLA: T2FourReg<
2211                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2212                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2213                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2214  let Inst{31-27} = 0b11111;
2215  let Inst{26-23} = 0b0110;
2216  let Inst{22-20} = 0b000;
2217  let Inst{7-4} = 0b0000; // Multiply
2218}
2219
2220def t2MLS: T2FourReg<
2221                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2222                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2223                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2224  let Inst{31-27} = 0b11111;
2225  let Inst{26-23} = 0b0110;
2226  let Inst{22-20} = 0b000;
2227  let Inst{7-4} = 0b0001; // Multiply and Subtract
2228}
2229
2230// Extra precision multiplies with low / high results
2231let neverHasSideEffects = 1 in {
2232let isCommutable = 1 in {
2233def t2SMULL : T2FourReg<
2234                  (outs rGPR:$Rd, rGPR:$Ra),
2235                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2236                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []> {
2237  let Inst{31-27} = 0b11111;
2238  let Inst{26-23} = 0b0111;
2239  let Inst{22-20} = 0b000;
2240  let Inst{7-4} = 0b0000;
2241}
2242
2243def t2UMULL : T2FourReg<
2244                  (outs rGPR:$Rd, rGPR:$Ra),
2245                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2246                   "umull", "\t$Rd, $Ra, $Rn, $Rm", []> {
2247  let Inst{31-27} = 0b11111;
2248  let Inst{26-23} = 0b0111;
2249  let Inst{22-20} = 0b010;
2250  let Inst{7-4} = 0b0000;
2251}
2252} // isCommutable
2253
2254// Multiply + accumulate
2255def t2SMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2256                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2257                  "smlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2258  let Inst{31-27} = 0b11111;
2259  let Inst{26-23} = 0b0111;
2260  let Inst{22-20} = 0b100;
2261  let Inst{7-4} = 0b0000;
2262}
2263
2264def t2UMLAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2265                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2266                  "umlal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2267  let Inst{31-27} = 0b11111;
2268  let Inst{26-23} = 0b0111;
2269  let Inst{22-20} = 0b110;
2270  let Inst{7-4} = 0b0000;
2271}
2272
2273def t2UMAAL : T2FourReg<(outs rGPR:$Ra, rGPR:$Rd),
2274                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2275                  "umaal", "\t$Ra, $Rd, $Rn, $Rm", []>{
2276  let Inst{31-27} = 0b11111;
2277  let Inst{26-23} = 0b0111;
2278  let Inst{22-20} = 0b110;
2279  let Inst{7-4} = 0b0110;
2280}
2281} // neverHasSideEffects
2282
2283// Rounding variants of the below included for disassembly only
2284
2285// Most significant word multiply
2286def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2287                  "smmul", "\t$Rd, $Rn, $Rm",
2288                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2289  let Inst{31-27} = 0b11111;
2290  let Inst{26-23} = 0b0110;
2291  let Inst{22-20} = 0b101;
2292  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2293  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2294}
2295
2296def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2297                  "smmulr", "\t$Rd, $Rn, $Rm", []> {
2298  let Inst{31-27} = 0b11111;
2299  let Inst{26-23} = 0b0110;
2300  let Inst{22-20} = 0b101;
2301  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2302  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2303}
2304
2305def t2SMMLA : T2FourReg<
2306        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2307                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2308                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2309  let Inst{31-27} = 0b11111;
2310  let Inst{26-23} = 0b0110;
2311  let Inst{22-20} = 0b101;
2312  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2313}
2314
2315def t2SMMLAR: T2FourReg<
2316        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2317                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2318  let Inst{31-27} = 0b11111;
2319  let Inst{26-23} = 0b0110;
2320  let Inst{22-20} = 0b101;
2321  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2322}
2323
2324def t2SMMLS: T2FourReg<
2325        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2326                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2327                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2328  let Inst{31-27} = 0b11111;
2329  let Inst{26-23} = 0b0110;
2330  let Inst{22-20} = 0b110;
2331  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2332}
2333
2334def t2SMMLSR:T2FourReg<
2335        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2336                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2337  let Inst{31-27} = 0b11111;
2338  let Inst{26-23} = 0b0110;
2339  let Inst{22-20} = 0b110;
2340  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2341}
2342
2343multiclass T2I_smul<string opc, PatFrag opnode> {
2344  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2345              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2346              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2347                                      (sext_inreg rGPR:$Rm, i16)))]> {
2348    let Inst{31-27} = 0b11111;
2349    let Inst{26-23} = 0b0110;
2350    let Inst{22-20} = 0b001;
2351    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2352    let Inst{7-6} = 0b00;
2353    let Inst{5-4} = 0b00;
2354  }
2355
2356  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2357              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2358              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2359                                      (sra rGPR:$Rm, (i32 16))))]> {
2360    let Inst{31-27} = 0b11111;
2361    let Inst{26-23} = 0b0110;
2362    let Inst{22-20} = 0b001;
2363    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2364    let Inst{7-6} = 0b00;
2365    let Inst{5-4} = 0b01;
2366  }
2367
2368  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2369              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2370              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2371                                      (sext_inreg rGPR:$Rm, i16)))]> {
2372    let Inst{31-27} = 0b11111;
2373    let Inst{26-23} = 0b0110;
2374    let Inst{22-20} = 0b001;
2375    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2376    let Inst{7-6} = 0b00;
2377    let Inst{5-4} = 0b10;
2378  }
2379
2380  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2381              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2382              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2383                                      (sra rGPR:$Rm, (i32 16))))]> {
2384    let Inst{31-27} = 0b11111;
2385    let Inst{26-23} = 0b0110;
2386    let Inst{22-20} = 0b001;
2387    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2388    let Inst{7-6} = 0b00;
2389    let Inst{5-4} = 0b11;
2390  }
2391
2392  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2393              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2394              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2395                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2396    let Inst{31-27} = 0b11111;
2397    let Inst{26-23} = 0b0110;
2398    let Inst{22-20} = 0b011;
2399    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2400    let Inst{7-6} = 0b00;
2401    let Inst{5-4} = 0b00;
2402  }
2403
2404  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2405              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2406              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2407                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2408    let Inst{31-27} = 0b11111;
2409    let Inst{26-23} = 0b0110;
2410    let Inst{22-20} = 0b011;
2411    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2412    let Inst{7-6} = 0b00;
2413    let Inst{5-4} = 0b01;
2414  }
2415}
2416
2417
2418multiclass T2I_smla<string opc, PatFrag opnode> {
2419  def BB : T2FourReg<
2420        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2421              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2422              [(set rGPR:$Rd, (add rGPR:$Ra,
2423                               (opnode (sext_inreg rGPR:$Rn, i16),
2424                                       (sext_inreg rGPR:$Rm, i16))))]> {
2425    let Inst{31-27} = 0b11111;
2426    let Inst{26-23} = 0b0110;
2427    let Inst{22-20} = 0b001;
2428    let Inst{7-6} = 0b00;
2429    let Inst{5-4} = 0b00;
2430  }
2431
2432  def BT : T2FourReg<
2433       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2434             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2435             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2436                                                 (sra rGPR:$Rm, (i32 16)))))]> {
2437    let Inst{31-27} = 0b11111;
2438    let Inst{26-23} = 0b0110;
2439    let Inst{22-20} = 0b001;
2440    let Inst{7-6} = 0b00;
2441    let Inst{5-4} = 0b01;
2442  }
2443
2444  def TB : T2FourReg<
2445        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2446              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2447              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2448                                               (sext_inreg rGPR:$Rm, i16))))]> {
2449    let Inst{31-27} = 0b11111;
2450    let Inst{26-23} = 0b0110;
2451    let Inst{22-20} = 0b001;
2452    let Inst{7-6} = 0b00;
2453    let Inst{5-4} = 0b10;
2454  }
2455
2456  def TT : T2FourReg<
2457        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2458              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2459             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2460                                                 (sra rGPR:$Rm, (i32 16)))))]> {
2461    let Inst{31-27} = 0b11111;
2462    let Inst{26-23} = 0b0110;
2463    let Inst{22-20} = 0b001;
2464    let Inst{7-6} = 0b00;
2465    let Inst{5-4} = 0b11;
2466  }
2467
2468  def WB : T2FourReg<
2469        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2470              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2471              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2472                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2473    let Inst{31-27} = 0b11111;
2474    let Inst{26-23} = 0b0110;
2475    let Inst{22-20} = 0b011;
2476    let Inst{7-6} = 0b00;
2477    let Inst{5-4} = 0b00;
2478  }
2479
2480  def WT : T2FourReg<
2481        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2482              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2483              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2484                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2485    let Inst{31-27} = 0b11111;
2486    let Inst{26-23} = 0b0110;
2487    let Inst{22-20} = 0b011;
2488    let Inst{7-6} = 0b00;
2489    let Inst{5-4} = 0b01;
2490  }
2491}
2492
2493defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2494defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2495
2496// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2497def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2498         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2499           [/* For disassembly only; pattern left blank */]>;
2500def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2501         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2502           [/* For disassembly only; pattern left blank */]>;
2503def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2504         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2505           [/* For disassembly only; pattern left blank */]>;
2506def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2507         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2508           [/* For disassembly only; pattern left blank */]>;
2509
2510// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2511// These are for disassembly only.
2512
2513def t2SMUAD: T2ThreeReg_mac<
2514            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2515            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2516  let Inst{15-12} = 0b1111;
2517}
2518def t2SMUADX:T2ThreeReg_mac<
2519            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2520            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2521  let Inst{15-12} = 0b1111;
2522}
2523def t2SMUSD: T2ThreeReg_mac<
2524            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2525            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2526  let Inst{15-12} = 0b1111;
2527}
2528def t2SMUSDX:T2ThreeReg_mac<
2529            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2530            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2531  let Inst{15-12} = 0b1111;
2532}
2533def t2SMLAD   : T2ThreeReg_mac<
2534            0, 0b010, 0b0000, (outs rGPR:$Rd),
2535            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2536            "\t$Rd, $Rn, $Rm, $Ra", []>;
2537def t2SMLADX  : T2FourReg_mac<
2538            0, 0b010, 0b0001, (outs rGPR:$Rd),
2539            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2540            "\t$Rd, $Rn, $Rm, $Ra", []>;
2541def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2542            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2543            "\t$Rd, $Rn, $Rm, $Ra", []>;
2544def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2545            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2546            "\t$Rd, $Rn, $Rm, $Ra", []>;
2547def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2548                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2549                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2550def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2551                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2552                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2553def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2554                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2555                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2556def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2557                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2558                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2559
2560//===----------------------------------------------------------------------===//
2561//  Misc. Arithmetic Instructions.
2562//
2563
2564class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2565      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2566  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2567  let Inst{31-27} = 0b11111;
2568  let Inst{26-22} = 0b01010;
2569  let Inst{21-20} = op1;
2570  let Inst{15-12} = 0b1111;
2571  let Inst{7-6} = 0b10;
2572  let Inst{5-4} = op2;
2573  let Rn{3-0} = Rm{3-0};
2574}
2575
2576def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2577                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2578
2579def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2580                      "rbit", "\t$Rd, $Rm",
2581                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2582
2583def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2584                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2585
2586def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2587                       "rev16", ".w\t$Rd, $Rm",
2588                [(set rGPR:$Rd,
2589                    (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
2590                        (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
2591                            (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
2592                               (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
2593
2594def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2595                       "revsh", ".w\t$Rd, $Rm",
2596                 [(set rGPR:$Rd,
2597                    (sext_inreg
2598                      (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
2599                          (shl rGPR:$Rm, (i32 8))), i16))]>;
2600
2601def t2PKHBT : T2ThreeReg<
2602            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2603                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2604                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2605                                      (and (shl rGPR:$Rm, lsl_amt:$sh),
2606                                           0xFFFF0000)))]>,
2607                  Requires<[HasT2ExtractPack, IsThumb2]> {
2608  let Inst{31-27} = 0b11101;
2609  let Inst{26-25} = 0b01;
2610  let Inst{24-20} = 0b01100;
2611  let Inst{5} = 0; // BT form
2612  let Inst{4} = 0;
2613
2614  bits<8> sh;
2615  let Inst{14-12} = sh{7-5};
2616  let Inst{7-6}   = sh{4-3};
2617}
2618
2619// Alternate cases for PKHBT where identities eliminate some nodes.
2620def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2621            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2622            Requires<[HasT2ExtractPack, IsThumb2]>;
2623def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2624            (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2625            Requires<[HasT2ExtractPack, IsThumb2]>;
2626
2627// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2628// will match the pattern below.
2629def t2PKHTB : T2ThreeReg<
2630                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2631                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2632                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2633                                       (and (sra rGPR:$Rm, asr_amt:$sh),
2634                                            0xFFFF)))]>,
2635                  Requires<[HasT2ExtractPack, IsThumb2]> {
2636  let Inst{31-27} = 0b11101;
2637  let Inst{26-25} = 0b01;
2638  let Inst{24-20} = 0b01100;
2639  let Inst{5} = 1; // TB form
2640  let Inst{4} = 0;
2641
2642  bits<8> sh;
2643  let Inst{14-12} = sh{7-5};
2644  let Inst{7-6}   = sh{4-3};
2645}
2646
2647// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2648// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2649def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2650            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2651            Requires<[HasT2ExtractPack, IsThumb2]>;
2652def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2653                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2654            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2655            Requires<[HasT2ExtractPack, IsThumb2]>;
2656
2657//===----------------------------------------------------------------------===//
2658//  Comparison Instructions...
2659//
2660defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2661                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2662                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2663defm t2CMPz : T2I_cmp_irs<0b1101, "cmp",
2664                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2665                          BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2666
2667//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2668//       Compare-to-zero still works out, just not the relationals
2669//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2670//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2671defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2672                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2673                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2674
2675//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2676//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2677
2678def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
2679            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2680
2681defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2682                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2683                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2684defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2685                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2686                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2687
2688// Conditional moves
2689// FIXME: should be able to write a pattern for ARMcmov, but can't use
2690// a two-value operand where a dag node expects two operands. :(
2691let neverHasSideEffects = 1 in {
2692def t2MOVCCr : T2TwoReg<
2693                   (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2694                   "mov", ".w\t$Rd, $Rm",
2695   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2696                RegConstraint<"$false = $Rd"> {
2697  let Inst{31-27} = 0b11101;
2698  let Inst{26-25} = 0b01;
2699  let Inst{24-21} = 0b0010;
2700  let Inst{20} = 0; // The S bit.
2701  let Inst{19-16} = 0b1111; // Rn
2702  let Inst{14-12} = 0b000;
2703  let Inst{7-4} = 0b0000;
2704}
2705
2706let isMoveImm = 1 in
2707def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2708                   IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2709[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2710                   RegConstraint<"$false = $Rd"> {
2711  let Inst{31-27} = 0b11110;
2712  let Inst{25} = 0;
2713  let Inst{24-21} = 0b0010;
2714  let Inst{20} = 0; // The S bit.
2715  let Inst{19-16} = 0b1111; // Rn
2716  let Inst{15} = 0;
2717}
2718
2719let isMoveImm = 1 in
2720def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm),
2721                      IIC_iCMOVi,
2722                      "movw", "\t$Rd, $imm", []>,
2723                      RegConstraint<"$false = $Rd"> {
2724  let Inst{31-27} = 0b11110;
2725  let Inst{25} = 1;
2726  let Inst{24-21} = 0b0010;
2727  let Inst{20} = 0; // The S bit.
2728  let Inst{15} = 0;
2729
2730  bits<4> Rd;
2731  bits<16> imm;
2732
2733  let Inst{11-8}  = Rd{3-0};
2734  let Inst{19-16} = imm{15-12};
2735  let Inst{26}    = imm{11};
2736  let Inst{14-12} = imm{10-8};
2737  let Inst{7-0}   = imm{7-0};
2738}
2739
2740let isMoveImm = 1 in
2741def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2742                               (ins rGPR:$false, i32imm:$src, pred:$p),
2743                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2744
2745let isMoveImm = 1 in
2746def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2747                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2748[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2749                   imm:$cc, CCR:$ccr))*/]>,
2750                   RegConstraint<"$false = $Rd"> {
2751  let Inst{31-27} = 0b11110;
2752  let Inst{25} = 0;
2753  let Inst{24-21} = 0b0011;
2754  let Inst{20} = 0; // The S bit.
2755  let Inst{19-16} = 0b1111; // Rn
2756  let Inst{15} = 0;
2757}
2758
2759class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2760                   string opc, string asm, list<dag> pattern>
2761  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2762  let Inst{31-27} = 0b11101;
2763  let Inst{26-25} = 0b01;
2764  let Inst{24-21} = 0b0010;
2765  let Inst{20} = 0; // The S bit.
2766  let Inst{19-16} = 0b1111; // Rn
2767  let Inst{5-4} = opcod; // Shift type.
2768}
2769def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2770                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2771                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2772                 RegConstraint<"$false = $Rd">;
2773def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2774                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2775                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2776                 RegConstraint<"$false = $Rd">;
2777def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2778                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2779                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2780                 RegConstraint<"$false = $Rd">;
2781def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2782                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2783                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2784                 RegConstraint<"$false = $Rd">;
2785} // neverHasSideEffects
2786
2787//===----------------------------------------------------------------------===//
2788// Atomic operations intrinsics
2789//
2790
2791// memory barriers protect the atomic sequences
2792let hasSideEffects = 1 in {
2793def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2794                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2795                  Requires<[IsThumb, HasDB]> {
2796  bits<4> opt;
2797  let Inst{31-4} = 0xf3bf8f5;
2798  let Inst{3-0} = opt;
2799}
2800}
2801
2802def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2803                  "dsb", "\t$opt",
2804                  [/* For disassembly only; pattern left blank */]>,
2805                  Requires<[IsThumb, HasDB]> {
2806  bits<4> opt;
2807  let Inst{31-4} = 0xf3bf8f4;
2808  let Inst{3-0} = opt;
2809}
2810
2811// ISB has only full system option -- for disassembly only
2812def t2ISB : T2I<(outs), (ins), NoItinerary, "isb", "",
2813                  [/* For disassembly only; pattern left blank */]>,
2814                  Requires<[IsThumb2, HasV7]> {
2815  let Inst{31-4} = 0xf3bf8f6;
2816  let Inst{3-0} = 0b1111;
2817}
2818
2819class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2820                InstrItinClass itin, string opc, string asm, string cstr,
2821                list<dag> pattern, bits<4> rt2 = 0b1111>
2822  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2823  let Inst{31-27} = 0b11101;
2824  let Inst{26-20} = 0b0001101;
2825  let Inst{11-8} = rt2;
2826  let Inst{7-6} = 0b01;
2827  let Inst{5-4} = opcod;
2828  let Inst{3-0} = 0b1111;
2829
2830  bits<4> Rn;
2831  bits<4> Rt;
2832  let Inst{19-16} = Rn{3-0};
2833  let Inst{15-12} = Rt{3-0};
2834}
2835class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2836                InstrItinClass itin, string opc, string asm, string cstr,
2837                list<dag> pattern, bits<4> rt2 = 0b1111>
2838  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2839  let Inst{31-27} = 0b11101;
2840  let Inst{26-20} = 0b0001100;
2841  let Inst{11-8} = rt2;
2842  let Inst{7-6} = 0b01;
2843  let Inst{5-4} = opcod;
2844
2845  bits<4> Rd;
2846  bits<4> Rn;
2847  bits<4> Rt;
2848  let Inst{11-8}  = Rd{3-0};
2849  let Inst{19-16} = Rn{3-0};
2850  let Inst{15-12} = Rt{3-0};
2851}
2852
2853let mayLoad = 1 in {
2854def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2855                         Size4Bytes, NoItinerary, "ldrexb", "\t$Rt, [$Rn]",
2856                         "", []>;
2857def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2858                         Size4Bytes, NoItinerary, "ldrexh", "\t$Rt, [$Rn]",
2859                         "", []>;
2860def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins rGPR:$Rn), AddrModeNone,
2861                       Size4Bytes, NoItinerary,
2862                       "ldrex", "\t$Rt, [$Rn]", "",
2863                      []> {
2864  let Inst{31-27} = 0b11101;
2865  let Inst{26-20} = 0b0000101;
2866  let Inst{11-8} = 0b1111;
2867  let Inst{7-0} = 0b00000000; // imm8 = 0
2868}
2869def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), (ins rGPR:$Rn),
2870                         AddrModeNone, Size4Bytes, NoItinerary,
2871                         "ldrexd", "\t$Rt, $Rt2, [$Rn]", "",
2872                         [], {?, ?, ?, ?}> {
2873  bits<4> Rt2;
2874  let Inst{11-8} = Rt2{3-0};
2875}
2876}
2877
2878let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2879def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2880                         AddrModeNone, Size4Bytes, NoItinerary,
2881                         "strexb", "\t$Rd, $Rt, [$Rn]", "", []>;
2882def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2883                         AddrModeNone, Size4Bytes, NoItinerary,
2884                         "strexh", "\t$Rd, $Rt, [$Rn]", "", []>;
2885def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, rGPR:$Rn),
2886                       AddrModeNone, Size4Bytes, NoItinerary,
2887                       "strex", "\t$Rd, $Rt, [$Rn]", "",
2888                      []> {
2889  let Inst{31-27} = 0b11101;
2890  let Inst{26-20} = 0b0000100;
2891  let Inst{7-0} = 0b00000000; // imm8 = 0
2892}
2893def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2894                         (ins rGPR:$Rt, rGPR:$Rt2, rGPR:$Rn),
2895                         AddrModeNone, Size4Bytes, NoItinerary,
2896                         "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]", "", [],
2897                         {?, ?, ?, ?}> {
2898  bits<4> Rt2;
2899  let Inst{11-8} = Rt2{3-0};
2900}
2901}
2902
2903// Clear-Exclusive is for disassembly only.
2904def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "",
2905                  [/* For disassembly only; pattern left blank */]>,
2906            Requires<[IsARM, HasV7]>  {
2907  let Inst{31-20} = 0xf3b;
2908  let Inst{15-14} = 0b10;
2909  let Inst{12} = 0;
2910  let Inst{7-4} = 0b0010;
2911}
2912
2913//===----------------------------------------------------------------------===//
2914// TLS Instructions
2915//
2916
2917// __aeabi_read_tp preserves the registers r1-r3.
2918let isCall = 1,
2919  Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
2920  def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
2921                     "bl\t__aeabi_read_tp",
2922                     [(set R0, ARMthread_pointer)]> {
2923    let Inst{31-27} = 0b11110;
2924    let Inst{15-14} = 0b11;
2925    let Inst{12} = 1;
2926  }
2927}
2928
2929//===----------------------------------------------------------------------===//
2930// SJLJ Exception handling intrinsics
2931//   eh_sjlj_setjmp() is an instruction sequence to store the return
2932//   address and save #0 in R0 for the non-longjmp case.
2933//   Since by its nature we may be coming from some other function to get
2934//   here, and we're using the stack frame for the containing function to
2935//   save/restore registers, we can't keep anything live in regs across
2936//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2937//   when we get here from a longjmp(). We force everthing out of registers
2938//   except for our own input by listing the relevant registers in Defs. By
2939//   doing so, we also cause the prologue/epilogue code to actively preserve
2940//   all of the callee-saved resgisters, which is exactly what we want.
2941//   $val is a scratch register for our use.
2942let Defs =
2943  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR,  D0,
2944    D1,  D2,  D3,  D4,  D5,  D6,  D7,  D8,  D9,  D10, D11, D12, D13, D14, D15,
2945    D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
2946    D31 ], hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2947  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2948                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2949                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2950                             Requires<[IsThumb2, HasVFP2]>;
2951}
2952
2953let Defs =
2954  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR ],
2955  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2956  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2957                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2958                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2959                                  Requires<[IsThumb2, NoVFP]>;
2960}
2961
2962
2963//===----------------------------------------------------------------------===//
2964// Control-Flow Instructions
2965//
2966
2967// FIXME: remove when we have a way to marking a MI with these properties.
2968// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
2969// operand list.
2970// FIXME: Should pc be an implicit operand like PICADD, etc?
2971let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2972    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2973def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2974                                        reglist:$regs, variable_ops),
2975                        IIC_iLoad_mBr,
2976                        "ldmia${p}.w\t$Rn!, $regs",
2977                        "$Rn = $wb", []> {
2978  bits<4>  Rn;
2979  bits<16> regs;
2980
2981  let Inst{31-27} = 0b11101;
2982  let Inst{26-25} = 0b00;
2983  let Inst{24-23} = 0b01;     // Increment After
2984  let Inst{22}    = 0;
2985  let Inst{21}    = 1;        // Writeback
2986  let Inst{20}    = 1;
2987  let Inst{19-16} = Rn;
2988  let Inst{15-0}  = regs;
2989}
2990
2991let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2992let isPredicable = 1 in
2993def t2B   : T2XI<(outs), (ins brtarget:$target), IIC_Br,
2994                 "b.w\t$target",
2995                 [(br bb:$target)]> {
2996  let Inst{31-27} = 0b11110;
2997  let Inst{15-14} = 0b10;
2998  let Inst{12} = 1;
2999
3000  bits<20> target;
3001  let Inst{26} = target{19};
3002  let Inst{11} = target{18};
3003  let Inst{13} = target{17};
3004  let Inst{21-16} = target{16-11};
3005  let Inst{10-0} = target{10-0};
3006}
3007
3008let isNotDuplicable = 1, isIndirectBranch = 1 in {
3009def t2BR_JT : tPseudoInst<(outs),
3010          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
3011           SizeSpecial, IIC_Br,
3012          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
3013
3014// FIXME: Add a non-pc based case that can be predicated.
3015def t2TBB_JT : tPseudoInst<(outs),
3016        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3017         SizeSpecial, IIC_Br, []>;
3018
3019def t2TBH_JT : tPseudoInst<(outs),
3020        (ins GPR:$index, i32imm:$jt, i32imm:$id),
3021         SizeSpecial, IIC_Br, []>;
3022
3023def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3024                    "tbb", "\t[$Rn, $Rm]", []> {
3025  bits<4> Rn;
3026  bits<4> Rm;
3027  let Inst{27-20} = 0b10001101;
3028  let Inst{19-16} = Rn;
3029  let Inst{15-5} = 0b11110000000;
3030  let Inst{4} = 0; // B form
3031  let Inst{3-0} = Rm;
3032}
3033
3034def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3035                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3036  bits<4> Rn;
3037  bits<4> Rm;
3038  let Inst{27-20} = 0b10001101;
3039  let Inst{19-16} = Rn;
3040  let Inst{15-5} = 0b11110000000;
3041  let Inst{4} = 1; // H form
3042  let Inst{3-0} = Rm;
3043}
3044} // isNotDuplicable, isIndirectBranch
3045
3046} // isBranch, isTerminator, isBarrier
3047
3048// FIXME: should be able to write a pattern for ARMBrcond, but can't use
3049// a two-value operand where a dag node expects two operands. :(
3050let isBranch = 1, isTerminator = 1 in
3051def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3052                "b", ".w\t$target",
3053                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3054  let Inst{31-27} = 0b11110;
3055  let Inst{15-14} = 0b10;
3056  let Inst{12} = 0;
3057
3058  bits<20> target;
3059  let Inst{26} = target{19};
3060  let Inst{11} = target{18};
3061  let Inst{13} = target{17};
3062  let Inst{21-16} = target{16-11};
3063  let Inst{10-0} = target{10-0};
3064}
3065
3066
3067// IT block
3068let Defs = [ITSTATE] in
3069def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3070                    AddrModeNone, Size2Bytes,  IIC_iALUx,
3071                    "it$mask\t$cc", "", []> {
3072  // 16-bit instruction.
3073  let Inst{31-16} = 0x0000;
3074  let Inst{15-8} = 0b10111111;
3075
3076  bits<4> cc;
3077  bits<4> mask;
3078  let Inst{7-4} = cc{3-0};
3079  let Inst{3-0} = mask{3-0};
3080}
3081
3082// Branch and Exchange Jazelle -- for disassembly only
3083// Rm = Inst{19-16}
3084def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3085              [/* For disassembly only; pattern left blank */]> {
3086  let Inst{31-27} = 0b11110;
3087  let Inst{26} = 0;
3088  let Inst{25-20} = 0b111100;
3089  let Inst{15-14} = 0b10;
3090  let Inst{12} = 0;
3091
3092  bits<4> func;
3093  let Inst{19-16} = func{3-0};
3094}
3095
3096// Change Processor State is a system instruction -- for disassembly only.
3097// The singleton $opt operand contains the following information:
3098// opt{4-0} = mode from Inst{4-0}
3099// opt{5} = changemode from Inst{17}
3100// opt{8-6} = AIF from Inst{8-6}
3101// opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
3102def t2CPS : T2XI<(outs),(ins cps_opt:$opt), NoItinerary, "cps$opt",
3103                 [/* For disassembly only; pattern left blank */]> {
3104  let Inst{31-27} = 0b11110;
3105  let Inst{26} = 0;
3106  let Inst{25-20} = 0b111010;
3107  let Inst{15-14} = 0b10;
3108  let Inst{12} = 0;
3109
3110  bits<11> opt;
3111
3112  // mode number
3113  let Inst{4-0} = opt{4-0};
3114
3115  // M flag
3116  let Inst{8} = opt{5};
3117
3118  // F flag
3119  let Inst{5} = opt{6};
3120
3121  // I flag
3122  let Inst{6} = opt{7};
3123
3124  // A flag
3125  let Inst{7} = opt{8};
3126
3127  // imod flag
3128  let Inst{10-9} = opt{10-9};
3129}
3130
3131// A6.3.4 Branches and miscellaneous control
3132// Table A6-14 Change Processor State, and hint instructions
3133// Helper class for disassembly only.
3134class T2I_hint<bits<8> op7_0, string opc, string asm>
3135  : T2I<(outs), (ins), NoItinerary, opc, asm,
3136        [/* For disassembly only; pattern left blank */]> {
3137  let Inst{31-20} = 0xf3a;
3138  let Inst{15-14} = 0b10;
3139  let Inst{12} = 0;
3140  let Inst{10-8} = 0b000;
3141  let Inst{7-0} = op7_0;
3142}
3143
3144def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3145def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3146def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3147def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3148def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3149
3150def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3151                [/* For disassembly only; pattern left blank */]> {
3152  let Inst{31-20} = 0xf3a;
3153  let Inst{15-14} = 0b10;
3154  let Inst{12} = 0;
3155  let Inst{10-8} = 0b000;
3156  let Inst{7-4} = 0b1111;
3157
3158  bits<4> opt;
3159  let Inst{3-0} = opt{3-0};
3160}
3161
3162// Secure Monitor Call is a system instruction -- for disassembly only
3163// Option = Inst{19-16}
3164def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3165                [/* For disassembly only; pattern left blank */]> {
3166  let Inst{31-27} = 0b11110;
3167  let Inst{26-20} = 0b1111111;
3168  let Inst{15-12} = 0b1000;
3169
3170  bits<4> opt;
3171  let Inst{19-16} = opt{3-0};
3172}
3173
3174class T2SRS<bits<12> op31_20,
3175           dag oops, dag iops, InstrItinClass itin,
3176          string opc, string asm, list<dag> pattern>
3177  : T2I<oops, iops, itin, opc, asm, pattern> {
3178  let Inst{31-20} = op31_20{11-0};
3179
3180  bits<5> mode;
3181  let Inst{4-0} = mode{4-0};
3182}
3183
3184// Store Return State is a system instruction -- for disassembly only
3185def t2SRSDBW : T2SRS<0b111010000010,
3186                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3187                   [/* For disassembly only; pattern left blank */]>;
3188def t2SRSDB  : T2SRS<0b111010000000,
3189                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3190                   [/* For disassembly only; pattern left blank */]>;
3191def t2SRSIAW : T2SRS<0b111010011010,
3192                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3193                   [/* For disassembly only; pattern left blank */]>;
3194def t2SRSIA  : T2SRS<0b111010011000,
3195                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3196                   [/* For disassembly only; pattern left blank */]>;
3197
3198// Return From Exception is a system instruction -- for disassembly only
3199
3200class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3201          string opc, string asm, list<dag> pattern>
3202  : T2I<oops, iops, itin, opc, asm, pattern> {
3203  let Inst{31-20} = op31_20{11-0};
3204
3205  bits<4> Rn;
3206  let Inst{19-16} = Rn{3-0};
3207}
3208
3209def t2RFEDBW : T2RFE<0b111010000011,
3210                   (outs), (ins rGPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3211                   [/* For disassembly only; pattern left blank */]>;
3212def t2RFEDB  : T2RFE<0b111010000001,
3213                   (outs), (ins rGPR:$Rn), NoItinerary, "rfeab", "\t$Rn",
3214                   [/* For disassembly only; pattern left blank */]>;
3215def t2RFEIAW : T2RFE<0b111010011011,
3216                   (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3217                   [/* For disassembly only; pattern left blank */]>;
3218def t2RFEIA  : T2RFE<0b111010011001,
3219                   (outs), (ins rGPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3220                   [/* For disassembly only; pattern left blank */]>;
3221
3222//===----------------------------------------------------------------------===//
3223// Non-Instruction Patterns
3224//
3225
3226// 32-bit immediate using movw + movt.
3227// This is a single pseudo instruction to make it re-materializable.
3228// FIXME: Remove this when we can do generalized remat.
3229let isReMaterializable = 1, isMoveImm = 1 in
3230def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3231                            [(set rGPR:$dst, (i32 imm:$src))]>,
3232                            Requires<[IsThumb, HasV6T2]>;
3233
3234// ConstantPool, GlobalAddress, and JumpTable
3235def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3236           Requires<[IsThumb2, DontUseMovt]>;
3237def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3238def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3239           Requires<[IsThumb2, UseMovt]>;
3240
3241def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3242            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3243
3244// Pseudo instruction that combines ldr from constpool and add pc. This should
3245// be expanded into two instructions late to allow if-conversion and
3246// scheduling.
3247let canFoldAsLoad = 1, isReMaterializable = 1 in
3248def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3249                   IIC_iLoadiALU,
3250               [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3251                                           imm:$cp))]>,
3252               Requires<[IsThumb2]>;
3253
3254//===----------------------------------------------------------------------===//
3255// Move between special register and ARM core register -- for disassembly only
3256//
3257
3258class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3259          dag oops, dag iops, InstrItinClass itin,
3260          string opc, string asm, list<dag> pattern>
3261  : T2I<oops, iops, itin, opc, asm, pattern> {
3262  let Inst{31-20} = op31_20{11-0};
3263  let Inst{15-14} = op15_14{1-0};
3264  let Inst{12} = op12{0};
3265}
3266
3267class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3268          dag oops, dag iops, InstrItinClass itin,
3269          string opc, string asm, list<dag> pattern>
3270  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3271  bits<4> Rd;
3272  let Inst{11-8} = Rd{3-0};
3273}
3274
3275def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3276                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3277                [/* For disassembly only; pattern left blank */]>;
3278def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3279                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3280                   [/* For disassembly only; pattern left blank */]>;
3281
3282class T2MSR<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3283            dag oops, dag iops, InstrItinClass itin,
3284          string opc, string asm, list<dag> pattern>
3285  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3286  bits<4> Rn;
3287  bits<4> mask;
3288  let Inst{19-16} = Rn{3-0};
3289  let Inst{11-8} = mask{3-0};
3290}
3291
3292def t2MSR : T2MSR<0b111100111000, 0b10, 0,
3293                (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3294                "\tcpsr$mask, $Rn",
3295                [/* For disassembly only; pattern left blank */]>;
3296def t2MSRsys : T2MSR<0b111100111001, 0b10, 0,
3297                   (outs), (ins rGPR:$Rn, msr_mask:$mask), NoItinerary, "msr",
3298                   "\tspsr$mask, $Rn",
3299                   [/* For disassembly only; pattern left blank */]>;
3300