ARMInstrThumb2.td revision ff97eb0cf4394090570feaa327d1237ba4b935e2 
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb2 instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14// IT block predicate field
15def it_pred : Operand<i32> {
16  let PrintMethod = "printMandatoryPredicateOperand";
17}
18
19// IT block condition mask
20def it_mask : Operand<i32> {
21  let PrintMethod = "printThumbITMask";
22}
23
24// Shifted operands. No register controlled shifts for Thumb2.
25// Note: We do not support rrx shifted operands yet.
26def t2_so_reg : Operand<i32>,    // reg imm
27                ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
28                               [shl,srl,sra,rotr]> {
29  let EncoderMethod = "getT2SORegOpValue";
30  let PrintMethod = "printT2SOOperand";
31  let MIOperandInfo = (ops rGPR, i32imm);
32}
33
34// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
35def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
36  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
37}]>;
38
39// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
40def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
41  return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
42}]>;
43
44// t2_so_imm - Match a 32-bit immediate operand, which is an
45// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
46// immediate splatted into multiple bytes of the word.
47def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; }
48def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{
49    return ARM_AM::getT2SOImmVal(Imm) != -1;
50  }]> {
51  let ParserMatchClass = t2_so_imm_asmoperand;
52  let EncoderMethod = "getT2SOImmOpValue";
53}
54
55// t2_so_imm_not - Match an immediate that is a complement
56// of a t2_so_imm.
57def t2_so_imm_not : Operand<i32>,
58                    PatLeaf<(imm), [{
59  return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
60}], t2_so_imm_not_XFORM>;
61
62// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
63def t2_so_imm_neg : Operand<i32>,
64                    PatLeaf<(imm), [{
65  return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1;
66}], t2_so_imm_neg_XFORM>;
67
68/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
69def imm1_31 : ImmLeaf<i32, [{
70  return (int32_t)Imm >= 1 && (int32_t)Imm < 32;
71}]>;
72
73/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
74def imm0_4095 : Operand<i32>,
75                ImmLeaf<i32, [{
76  return Imm >= 0 && Imm < 4096;
77}]>;
78
79def imm0_4095_neg : PatLeaf<(i32 imm), [{
80 return (uint32_t)(-N->getZExtValue()) < 4096;
81}], imm_neg_XFORM>;
82
83def imm0_255_neg : PatLeaf<(i32 imm), [{
84  return (uint32_t)(-N->getZExtValue()) < 255;
85}], imm_neg_XFORM>;
86
87def imm0_255_not : PatLeaf<(i32 imm), [{
88  return (uint32_t)(~N->getZExtValue()) < 255;
89}], imm_comp_XFORM>;
90
91def lo5AllOne : PatLeaf<(i32 imm), [{
92  // Returns true if all low 5-bits are 1.
93  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
94}]>;
95
96// Define Thumb2 specific addressing modes.
97
98// t2addrmode_imm12  := reg + imm12
99def t2addrmode_imm12 : Operand<i32>,
100                       ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
101  let PrintMethod = "printAddrModeImm12Operand";
102  let EncoderMethod = "getAddrModeImm12OpValue";
103  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
104  let ParserMatchClass = MemMode5AsmOperand;
105}
106
107// t2ldrlabel  := imm12
108def t2ldrlabel : Operand<i32> {
109  let EncoderMethod = "getAddrModeImm12OpValue";
110}
111
112
113// ADR instruction labels.
114def t2adrlabel : Operand<i32> {
115  let EncoderMethod = "getT2AdrLabelOpValue";
116}
117
118
119// t2addrmode_imm8  := reg +/- imm8
120def t2addrmode_imm8 : Operand<i32>,
121                      ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
122  let PrintMethod = "printT2AddrModeImm8Operand";
123  let EncoderMethod = "getT2AddrModeImm8OpValue";
124  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
125  let ParserMatchClass = MemMode5AsmOperand;
126}
127
128def t2am_imm8_offset : Operand<i32>,
129                       ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset",
130                                      [], [SDNPWantRoot]> {
131  let PrintMethod = "printT2AddrModeImm8OffsetOperand";
132  let EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
133  let ParserMatchClass = MemMode5AsmOperand;
134}
135
136// t2addrmode_imm8s4  := reg +/- (imm8 << 2)
137def t2addrmode_imm8s4 : Operand<i32> {
138  let PrintMethod = "printT2AddrModeImm8s4Operand";
139  let EncoderMethod = "getT2AddrModeImm8s4OpValue";
140  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141  let ParserMatchClass = MemMode5AsmOperand;
142}
143
144def t2am_imm8s4_offset : Operand<i32> {
145  let PrintMethod = "printT2AddrModeImm8s4OffsetOperand";
146}
147
148// t2addrmode_so_reg  := reg + (reg << imm2)
149def t2addrmode_so_reg : Operand<i32>,
150                        ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
151  let PrintMethod = "printT2AddrModeSoRegOperand";
152  let EncoderMethod = "getT2AddrModeSORegOpValue";
153  let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm);
154  let ParserMatchClass = MemMode5AsmOperand;
155}
156
157// t2addrmode_reg := reg
158// Used by load/store exclusive instructions. Useful to enable right assembly
159// parsing and printing. Not used for any codegen matching.
160//
161def t2addrmode_reg : Operand<i32> {
162  let PrintMethod = "printAddrMode7Operand";
163  let MIOperandInfo = (ops GPR);
164  let ParserMatchClass = MemMode7AsmOperand;
165}
166
167//===----------------------------------------------------------------------===//
168// Multiclass helpers...
169//
170
171
172class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
173           string opc, string asm, list<dag> pattern>
174  : T2I<oops, iops, itin, opc, asm, pattern> {
175  bits<4> Rd;
176  bits<12> imm;
177
178  let Inst{11-8}  = Rd;
179  let Inst{26}    = imm{11};
180  let Inst{14-12} = imm{10-8};
181  let Inst{7-0}   = imm{7-0};
182}
183
184
185class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
186           string opc, string asm, list<dag> pattern>
187  : T2sI<oops, iops, itin, opc, asm, pattern> {
188  bits<4> Rd;
189  bits<4> Rn;
190  bits<12> imm;
191
192  let Inst{11-8}  = Rd;
193  let Inst{26}    = imm{11};
194  let Inst{14-12} = imm{10-8};
195  let Inst{7-0}   = imm{7-0};
196}
197
198class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
199           string opc, string asm, list<dag> pattern>
200  : T2I<oops, iops, itin, opc, asm, pattern> {
201  bits<4> Rn;
202  bits<12> imm;
203
204  let Inst{19-16}  = Rn;
205  let Inst{26}    = imm{11};
206  let Inst{14-12} = imm{10-8};
207  let Inst{7-0}   = imm{7-0};
208}
209
210
211class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
212           string opc, string asm, list<dag> pattern>
213  : T2I<oops, iops, itin, opc, asm, pattern> {
214  bits<4> Rd;
215  bits<12> ShiftedRm;
216
217  let Inst{11-8}  = Rd;
218  let Inst{3-0}   = ShiftedRm{3-0};
219  let Inst{5-4}   = ShiftedRm{6-5};
220  let Inst{14-12} = ShiftedRm{11-9};
221  let Inst{7-6}   = ShiftedRm{8-7};
222}
223
224class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
225           string opc, string asm, list<dag> pattern>
226  : T2sI<oops, iops, itin, opc, asm, pattern> {
227  bits<4> Rd;
228  bits<12> ShiftedRm;
229
230  let Inst{11-8}  = Rd;
231  let Inst{3-0}   = ShiftedRm{3-0};
232  let Inst{5-4}   = ShiftedRm{6-5};
233  let Inst{14-12} = ShiftedRm{11-9};
234  let Inst{7-6}   = ShiftedRm{8-7};
235}
236
237class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin,
238           string opc, string asm, list<dag> pattern>
239  : T2I<oops, iops, itin, opc, asm, pattern> {
240  bits<4> Rn;
241  bits<12> ShiftedRm;
242
243  let Inst{19-16} = Rn;
244  let Inst{3-0}   = ShiftedRm{3-0};
245  let Inst{5-4}   = ShiftedRm{6-5};
246  let Inst{14-12} = ShiftedRm{11-9};
247  let Inst{7-6}   = ShiftedRm{8-7};
248}
249
250class T2TwoReg<dag oops, dag iops, InstrItinClass itin,
251           string opc, string asm, list<dag> pattern>
252  : T2I<oops, iops, itin, opc, asm, pattern> {
253  bits<4> Rd;
254  bits<4> Rm;
255
256  let Inst{11-8}  = Rd;
257  let Inst{3-0}   = Rm;
258}
259
260class T2sTwoReg<dag oops, dag iops, InstrItinClass itin,
261           string opc, string asm, list<dag> pattern>
262  : T2sI<oops, iops, itin, opc, asm, pattern> {
263  bits<4> Rd;
264  bits<4> Rm;
265
266  let Inst{11-8}  = Rd;
267  let Inst{3-0}   = Rm;
268}
269
270class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin,
271           string opc, string asm, list<dag> pattern>
272  : T2I<oops, iops, itin, opc, asm, pattern> {
273  bits<4> Rn;
274  bits<4> Rm;
275
276  let Inst{19-16} = Rn;
277  let Inst{3-0}   = Rm;
278}
279
280
281class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin,
282           string opc, string asm, list<dag> pattern>
283  : T2I<oops, iops, itin, opc, asm, pattern> {
284  bits<4> Rd;
285  bits<4> Rn;
286  bits<12> imm;
287
288  let Inst{11-8}  = Rd;
289  let Inst{19-16} = Rn;
290  let Inst{26}    = imm{11};
291  let Inst{14-12} = imm{10-8};
292  let Inst{7-0}   = imm{7-0};
293}
294
295class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin,
296           string opc, string asm, list<dag> pattern>
297  : T2sI<oops, iops, itin, opc, asm, pattern> {
298  bits<4> Rd;
299  bits<4> Rn;
300  bits<12> imm;
301
302  let Inst{11-8}  = Rd;
303  let Inst{19-16} = Rn;
304  let Inst{26}    = imm{11};
305  let Inst{14-12} = imm{10-8};
306  let Inst{7-0}   = imm{7-0};
307}
308
309class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
310           string opc, string asm, list<dag> pattern>
311  : T2I<oops, iops, itin, opc, asm, pattern> {
312  bits<4> Rd;
313  bits<4> Rm;
314  bits<5> imm;
315
316  let Inst{11-8}  = Rd;
317  let Inst{3-0}   = Rm;
318  let Inst{14-12} = imm{4-2};
319  let Inst{7-6}   = imm{1-0};
320}
321
322class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin,
323           string opc, string asm, list<dag> pattern>
324  : T2sI<oops, iops, itin, opc, asm, pattern> {
325  bits<4> Rd;
326  bits<4> Rm;
327  bits<5> imm;
328
329  let Inst{11-8}  = Rd;
330  let Inst{3-0}   = Rm;
331  let Inst{14-12} = imm{4-2};
332  let Inst{7-6}   = imm{1-0};
333}
334
335class T2ThreeReg<dag oops, dag iops, InstrItinClass itin,
336           string opc, string asm, list<dag> pattern>
337  : T2I<oops, iops, itin, opc, asm, pattern> {
338  bits<4> Rd;
339  bits<4> Rn;
340  bits<4> Rm;
341
342  let Inst{11-8}  = Rd;
343  let Inst{19-16} = Rn;
344  let Inst{3-0}   = Rm;
345}
346
347class T2sThreeReg<dag oops, dag iops, InstrItinClass itin,
348           string opc, string asm, list<dag> pattern>
349  : T2sI<oops, iops, itin, opc, asm, pattern> {
350  bits<4> Rd;
351  bits<4> Rn;
352  bits<4> Rm;
353
354  let Inst{11-8}  = Rd;
355  let Inst{19-16} = Rn;
356  let Inst{3-0}   = Rm;
357}
358
359class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
360           string opc, string asm, list<dag> pattern>
361  : T2I<oops, iops, itin, opc, asm, pattern> {
362  bits<4> Rd;
363  bits<4> Rn;
364  bits<12> ShiftedRm;
365
366  let Inst{11-8}  = Rd;
367  let Inst{19-16} = Rn;
368  let Inst{3-0}   = ShiftedRm{3-0};
369  let Inst{5-4}   = ShiftedRm{6-5};
370  let Inst{14-12} = ShiftedRm{11-9};
371  let Inst{7-6}   = ShiftedRm{8-7};
372}
373
374class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
375           string opc, string asm, list<dag> pattern>
376  : T2sI<oops, iops, itin, opc, asm, pattern> {
377  bits<4> Rd;
378  bits<4> Rn;
379  bits<12> ShiftedRm;
380
381  let Inst{11-8}  = Rd;
382  let Inst{19-16} = Rn;
383  let Inst{3-0}   = ShiftedRm{3-0};
384  let Inst{5-4}   = ShiftedRm{6-5};
385  let Inst{14-12} = ShiftedRm{11-9};
386  let Inst{7-6}   = ShiftedRm{8-7};
387}
388
389class T2FourReg<dag oops, dag iops, InstrItinClass itin,
390           string opc, string asm, list<dag> pattern>
391  : T2I<oops, iops, itin, opc, asm, pattern> {
392  bits<4> Rd;
393  bits<4> Rn;
394  bits<4> Rm;
395  bits<4> Ra;
396
397  let Inst{19-16} = Rn;
398  let Inst{15-12} = Ra;
399  let Inst{11-8}  = Rd;
400  let Inst{3-0}   = Rm;
401}
402
403class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
404                dag oops, dag iops, InstrItinClass itin,
405                string opc, string asm, list<dag> pattern>
406  : T2I<oops, iops, itin, opc, asm, pattern> {
407  bits<4> RdLo;
408  bits<4> RdHi;
409  bits<4> Rn;
410  bits<4> Rm;
411
412  let Inst{31-23} = 0b111110111;
413  let Inst{22-20} = opc22_20;
414  let Inst{19-16} = Rn;
415  let Inst{15-12} = RdLo;
416  let Inst{11-8}  = RdHi;
417  let Inst{7-4}   = opc7_4;
418  let Inst{3-0}   = Rm;
419}
420
421
422/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
423/// unary operation that produces a value. These are predicable and can be
424/// changed to modify CPSR.
425multiclass T2I_un_irs<bits<4> opcod, string opc,
426                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
427                      PatFrag opnode, bit Cheap = 0, bit ReMat = 0> {
428   // shifted imm
429   def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
430                opc, "\t$Rd, $imm",
431                [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> {
432     let isAsCheapAsAMove = Cheap;
433     let isReMaterializable = ReMat;
434     let Inst{31-27} = 0b11110;
435     let Inst{25} = 0;
436     let Inst{24-21} = opcod;
437     let Inst{19-16} = 0b1111; // Rn
438     let Inst{15} = 0;
439   }
440   // register
441   def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
442                opc, ".w\t$Rd, $Rm",
443                [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
444     let Inst{31-27} = 0b11101;
445     let Inst{26-25} = 0b01;
446     let Inst{24-21} = opcod;
447     let Inst{19-16} = 0b1111; // Rn
448     let Inst{14-12} = 0b000; // imm3
449     let Inst{7-6} = 0b00; // imm2
450     let Inst{5-4} = 0b00; // type
451   }
452   // shifted register
453   def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
454                opc, ".w\t$Rd, $ShiftedRm",
455                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> {
456     let Inst{31-27} = 0b11101;
457     let Inst{26-25} = 0b01;
458     let Inst{24-21} = opcod;
459     let Inst{19-16} = 0b1111; // Rn
460   }
461}
462
463/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
464/// binary operation that produces a value. These are predicable and can be
465/// changed to modify CPSR.
466multiclass T2I_bin_irs<bits<4> opcod, string opc,
467                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
468                       PatFrag opnode, string baseOpc, bit Commutable = 0,
469                       string wide = ""> {
470   // shifted imm
471   def ri : T2sTwoRegImm<
472                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
473                 opc, "\t$Rd, $Rn, $imm",
474                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> {
475     let Inst{31-27} = 0b11110;
476     let Inst{25} = 0;
477     let Inst{24-21} = opcod;
478     let Inst{15} = 0;
479   }
480   // register
481   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
482                 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
483                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
484     let isCommutable = Commutable;
485     let Inst{31-27} = 0b11101;
486     let Inst{26-25} = 0b01;
487     let Inst{24-21} = opcod;
488     let Inst{14-12} = 0b000; // imm3
489     let Inst{7-6} = 0b00; // imm2
490     let Inst{5-4} = 0b00; // type
491   }
492   // shifted register
493   def rs : T2sTwoRegShiftedReg<
494                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
495                 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
496                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> {
497     let Inst{31-27} = 0b11101;
498     let Inst{26-25} = 0b01;
499     let Inst{24-21} = opcod;
500   }
501  // Assembly aliases for optional destination operand when it's the same
502  // as the source operand.
503  def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
504     (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn,
505                                                    t2_so_imm:$imm, pred:$p,
506                                                    cc_out:$s)>,
507     Requires<[IsThumb2]>;
508  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"),
509     (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn,
510                                                    rGPR:$Rm, pred:$p,
511                                                    cc_out:$s)>,
512     Requires<[IsThumb2]>;
513  def : InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"),
514     (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn,
515                                                    t2_so_reg:$shift, pred:$p,
516                                                    cc_out:$s)>,
517     Requires<[IsThumb2]>;
518}
519
520/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
521//  the ".w" suffix to indicate that they are wide.
522multiclass T2I_bin_w_irs<bits<4> opcod, string opc,
523                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
524                         PatFrag opnode, string baseOpc, bit Commutable = 0> :
525    T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w">;
526
527/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
528/// reversed.  The 'rr' form is only defined for the disassembler; for codegen
529/// it is equivalent to the T2I_bin_irs counterpart.
530multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> {
531   // shifted imm
532   def ri : T2sTwoRegImm<
533                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
534                 opc, ".w\t$Rd, $Rn, $imm",
535                 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
536     let Inst{31-27} = 0b11110;
537     let Inst{25} = 0;
538     let Inst{24-21} = opcod;
539     let Inst{15} = 0;
540   }
541   // register
542   def rr : T2sThreeReg<
543                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
544                 opc, "\t$Rd, $Rn, $Rm",
545                 [/* For disassembly only; pattern left blank */]> {
546     let Inst{31-27} = 0b11101;
547     let Inst{26-25} = 0b01;
548     let Inst{24-21} = opcod;
549     let Inst{14-12} = 0b000; // imm3
550     let Inst{7-6} = 0b00; // imm2
551     let Inst{5-4} = 0b00; // type
552   }
553   // shifted register
554   def rs : T2sTwoRegShiftedReg<
555                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
556                 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
557                 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
558     let Inst{31-27} = 0b11101;
559     let Inst{26-25} = 0b01;
560     let Inst{24-21} = opcod;
561   }
562}
563
564/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
565/// instruction modifies the CPSR register.
566let isCodeGenOnly = 1, Defs = [CPSR] in {
567multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
568                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
569                         PatFrag opnode, bit Commutable = 0> {
570   // shifted imm
571   def ri : T2TwoRegImm<
572                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii,
573                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
574                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
575     let Inst{31-27} = 0b11110;
576     let Inst{25} = 0;
577     let Inst{24-21} = opcod;
578     let Inst{20} = 1; // The S bit.
579     let Inst{15} = 0;
580   }
581   // register
582   def rr : T2ThreeReg<
583                (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir,
584                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $Rm",
585                [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
586     let isCommutable = Commutable;
587     let Inst{31-27} = 0b11101;
588     let Inst{26-25} = 0b01;
589     let Inst{24-21} = opcod;
590     let Inst{20} = 1; // The S bit.
591     let Inst{14-12} = 0b000; // imm3
592     let Inst{7-6} = 0b00; // imm2
593     let Inst{5-4} = 0b00; // type
594   }
595   // shifted register
596   def rs : T2TwoRegShiftedReg<
597                (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
598                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $ShiftedRm",
599                [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
600     let Inst{31-27} = 0b11101;
601     let Inst{26-25} = 0b01;
602     let Inst{24-21} = opcod;
603     let Inst{20} = 1; // The S bit.
604   }
605}
606}
607
608/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
609/// patterns for a binary operation that produces a value.
610multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode,
611                          bit Commutable = 0> {
612   // shifted imm
613   // The register-immediate version is re-materializable. This is useful
614   // in particular for taking the address of a local.
615   let isReMaterializable = 1 in {
616   def ri : T2sTwoRegImm<
617                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
618                 opc, ".w\t$Rd, $Rn, $imm",
619                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_imm:$imm))]> {
620     let Inst{31-27} = 0b11110;
621     let Inst{25} = 0;
622     let Inst{24} = 1;
623     let Inst{23-21} = op23_21;
624     let Inst{15} = 0;
625   }
626   }
627   // 12-bit imm
628   def ri12 : T2I<
629                  (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
630                  !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
631                  [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> {
632     bits<4> Rd;
633     bits<4> Rn;
634     bits<12> imm;
635     let Inst{31-27} = 0b11110;
636     let Inst{26} = imm{11};
637     let Inst{25-24} = 0b10;
638     let Inst{23-21} = op23_21;
639     let Inst{20} = 0; // The S bit.
640     let Inst{19-16} = Rn;
641     let Inst{15} = 0;
642     let Inst{14-12} = imm{10-8};
643     let Inst{11-8} = Rd;
644     let Inst{7-0} = imm{7-0};
645   }
646   // register
647   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), IIC_iALUr,
648                 opc, ".w\t$Rd, $Rn, $Rm",
649                 [(set rGPR:$Rd, (opnode GPR:$Rn, rGPR:$Rm))]> {
650     let isCommutable = Commutable;
651     let Inst{31-27} = 0b11101;
652     let Inst{26-25} = 0b01;
653     let Inst{24} = 1;
654     let Inst{23-21} = op23_21;
655     let Inst{14-12} = 0b000; // imm3
656     let Inst{7-6} = 0b00; // imm2
657     let Inst{5-4} = 0b00; // type
658   }
659   // shifted register
660   def rs : T2sTwoRegShiftedReg<
661                 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm),
662                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
663                 [(set rGPR:$Rd, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]> {
664     let Inst{31-27} = 0b11101;
665     let Inst{26-25} = 0b01;
666     let Inst{24} = 1;
667     let Inst{23-21} = op23_21;
668   }
669}
670
671/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns
672/// for a binary operation that produces a value and use the carry
673/// bit. It's not predicable.
674let Uses = [CPSR] in {
675multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
676                             bit Commutable = 0> {
677   // shifted imm
678   def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
679                 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
680                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
681                 Requires<[IsThumb2]> {
682     let Inst{31-27} = 0b11110;
683     let Inst{25} = 0;
684     let Inst{24-21} = opcod;
685     let Inst{15} = 0;
686   }
687   // register
688   def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
689                 opc, ".w\t$Rd, $Rn, $Rm",
690                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
691                 Requires<[IsThumb2]> {
692     let isCommutable = Commutable;
693     let Inst{31-27} = 0b11101;
694     let Inst{26-25} = 0b01;
695     let Inst{24-21} = opcod;
696     let Inst{14-12} = 0b000; // imm3
697     let Inst{7-6} = 0b00; // imm2
698     let Inst{5-4} = 0b00; // type
699   }
700   // shifted register
701   def rs : T2sTwoRegShiftedReg<
702                 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
703                 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
704                 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
705                 Requires<[IsThumb2]> {
706     let Inst{31-27} = 0b11101;
707     let Inst{26-25} = 0b01;
708     let Inst{24-21} = opcod;
709   }
710}
711}
712
713// Carry setting variants
714// NOTE: CPSR def omitted because it will be handled by the custom inserter.
715let usesCustomInserter = 1 in {
716multiclass T2I_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
717   // shifted imm
718   def ri : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
719                Size4Bytes, IIC_iALUi,
720                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>;
721   // register
722   def rr : t2PseudoInst<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
723                Size4Bytes, IIC_iALUr,
724                [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
725     let isCommutable = Commutable;
726   }
727   // shifted register
728   def rs : t2PseudoInst<
729                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
730                Size4Bytes, IIC_iALUsi,
731                [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>;
732}
733}
734
735/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
736/// version is not needed since this is only for codegen.
737let isCodeGenOnly = 1, Defs = [CPSR] in {
738multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
739   // shifted imm
740   def ri : T2TwoRegImm<
741                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
742                !strconcat(opc, "s"), ".w\t$Rd, $Rn, $imm",
743                [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> {
744     let Inst{31-27} = 0b11110;
745     let Inst{25} = 0;
746     let Inst{24-21} = opcod;
747     let Inst{20} = 1; // The S bit.
748     let Inst{15} = 0;
749   }
750   // shifted register
751   def rs : T2TwoRegShiftedReg<
752                (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
753                IIC_iALUsi, !strconcat(opc, "s"), "\t$Rd, $Rn, $ShiftedRm",
754                [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> {
755     let Inst{31-27} = 0b11101;
756     let Inst{26-25} = 0b01;
757     let Inst{24-21} = opcod;
758     let Inst{20} = 1; // The S bit.
759   }
760}
761}
762
763/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
764//  rotate operation that produces a value.
765multiclass T2I_sh_ir<bits<2> opcod, string opc, PatFrag opnode> {
766   // 5-bit imm
767   def ri : T2sTwoRegShiftImm<
768                 (outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$imm), IIC_iMOVsi,
769                 opc, ".w\t$Rd, $Rm, $imm",
770                 [(set rGPR:$Rd, (opnode rGPR:$Rm, imm1_31:$imm))]> {
771     let Inst{31-27} = 0b11101;
772     let Inst{26-21} = 0b010010;
773     let Inst{19-16} = 0b1111; // Rn
774     let Inst{5-4} = opcod;
775   }
776   // register
777   def rr : T2sThreeReg<
778                 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
779                 opc, ".w\t$Rd, $Rn, $Rm",
780                 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> {
781     let Inst{31-27} = 0b11111;
782     let Inst{26-23} = 0b0100;
783     let Inst{22-21} = opcod;
784     let Inst{15-12} = 0b1111;
785     let Inst{7-4} = 0b0000;
786   }
787}
788
789/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
790/// patterns. Similar to T2I_bin_irs except the instruction does not produce
791/// a explicit result, only implicitly set CPSR.
792let isCompare = 1, Defs = [CPSR] in {
793multiclass T2I_cmp_irs<bits<4> opcod, string opc,
794                     InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
795                       PatFrag opnode> {
796   // shifted imm
797   def ri : T2OneRegCmpImm<
798                (outs), (ins GPR:$Rn, t2_so_imm:$imm), iii,
799                opc, ".w\t$Rn, $imm",
800                [(opnode GPR:$Rn, t2_so_imm:$imm)]> {
801     let Inst{31-27} = 0b11110;
802     let Inst{25} = 0;
803     let Inst{24-21} = opcod;
804     let Inst{20} = 1; // The S bit.
805     let Inst{15} = 0;
806     let Inst{11-8} = 0b1111; // Rd
807   }
808   // register
809   def rr : T2TwoRegCmp<
810                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
811                opc, ".w\t$lhs, $rhs",
812                [(opnode GPR:$lhs, rGPR:$rhs)]> {
813     let Inst{31-27} = 0b11101;
814     let Inst{26-25} = 0b01;
815     let Inst{24-21} = opcod;
816     let Inst{20} = 1; // The S bit.
817     let Inst{14-12} = 0b000; // imm3
818     let Inst{11-8} = 0b1111; // Rd
819     let Inst{7-6} = 0b00; // imm2
820     let Inst{5-4} = 0b00; // type
821   }
822   // shifted register
823   def rs : T2OneRegCmpShiftedReg<
824                (outs), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis,
825                opc, ".w\t$Rn, $ShiftedRm",
826                [(opnode GPR:$Rn, t2_so_reg:$ShiftedRm)]> {
827     let Inst{31-27} = 0b11101;
828     let Inst{26-25} = 0b01;
829     let Inst{24-21} = opcod;
830     let Inst{20} = 1; // The S bit.
831     let Inst{11-8} = 0b1111; // Rd
832   }
833}
834}
835
836/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
837multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
838                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
839  def i12 : T2Ii12<(outs GPR:$Rt), (ins t2addrmode_imm12:$addr), iii,
840                   opc, ".w\t$Rt, $addr",
841                   [(set GPR:$Rt, (opnode t2addrmode_imm12:$addr))]> {
842    let Inst{31-27} = 0b11111;
843    let Inst{26-25} = 0b00;
844    let Inst{24} = signed;
845    let Inst{23} = 1;
846    let Inst{22-21} = opcod;
847    let Inst{20} = 1; // load
848
849    bits<4> Rt;
850    let Inst{15-12} = Rt;
851
852    bits<17> addr;
853    let addr{12}    = 1;           // add = TRUE
854    let Inst{19-16} = addr{16-13}; // Rn
855    let Inst{23}    = addr{12};    // U
856    let Inst{11-0}  = addr{11-0};  // imm
857  }
858  def i8  : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
859                   opc, "\t$Rt, $addr",
860                   [(set GPR:$Rt, (opnode t2addrmode_imm8:$addr))]> {
861    let Inst{31-27} = 0b11111;
862    let Inst{26-25} = 0b00;
863    let Inst{24} = signed;
864    let Inst{23} = 0;
865    let Inst{22-21} = opcod;
866    let Inst{20} = 1; // load
867    let Inst{11} = 1;
868    // Offset: index==TRUE, wback==FALSE
869    let Inst{10} = 1; // The P bit.
870    let Inst{8} = 0; // The W bit.
871
872    bits<4> Rt;
873    let Inst{15-12} = Rt;
874
875    bits<13> addr;
876    let Inst{19-16} = addr{12-9}; // Rn
877    let Inst{9}     = addr{8};    // U
878    let Inst{7-0}   = addr{7-0};  // imm
879  }
880  def s   : T2Iso <(outs GPR:$Rt), (ins t2addrmode_so_reg:$addr), iis,
881                   opc, ".w\t$Rt, $addr",
882                   [(set GPR:$Rt, (opnode t2addrmode_so_reg:$addr))]> {
883    let Inst{31-27} = 0b11111;
884    let Inst{26-25} = 0b00;
885    let Inst{24} = signed;
886    let Inst{23} = 0;
887    let Inst{22-21} = opcod;
888    let Inst{20} = 1; // load
889    let Inst{11-6} = 0b000000;
890
891    bits<4> Rt;
892    let Inst{15-12} = Rt;
893
894    bits<10> addr;
895    let Inst{19-16} = addr{9-6}; // Rn
896    let Inst{3-0}   = addr{5-2}; // Rm
897    let Inst{5-4}   = addr{1-0}; // imm
898  }
899
900  // FIXME: Is the pci variant actually needed?
901  def pci : T2Ipc <(outs GPR:$Rt), (ins t2ldrlabel:$addr), iii,
902                   opc, ".w\t$Rt, $addr",
903                   [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
904    let isReMaterializable = 1;
905    let Inst{31-27} = 0b11111;
906    let Inst{26-25} = 0b00;
907    let Inst{24} = signed;
908    let Inst{23} = ?; // add = (U == '1')
909    let Inst{22-21} = opcod;
910    let Inst{20} = 1; // load
911    let Inst{19-16} = 0b1111; // Rn
912    bits<4> Rt;
913    bits<12> addr;
914    let Inst{15-12} = Rt{3-0};
915    let Inst{11-0}  = addr{11-0};
916  }
917}
918
919/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
920multiclass T2I_st<bits<2> opcod, string opc,
921                  InstrItinClass iii, InstrItinClass iis, PatFrag opnode> {
922  def i12 : T2Ii12<(outs), (ins GPR:$Rt, t2addrmode_imm12:$addr), iii,
923                   opc, ".w\t$Rt, $addr",
924                   [(opnode GPR:$Rt, t2addrmode_imm12:$addr)]> {
925    let Inst{31-27} = 0b11111;
926    let Inst{26-23} = 0b0001;
927    let Inst{22-21} = opcod;
928    let Inst{20} = 0; // !load
929
930    bits<4> Rt;
931    let Inst{15-12} = Rt;
932
933    bits<17> addr;
934    let addr{12}    = 1;           // add = TRUE
935    let Inst{19-16} = addr{16-13}; // Rn
936    let Inst{23}    = addr{12};    // U
937    let Inst{11-0}  = addr{11-0};  // imm
938  }
939  def i8  : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
940                   opc, "\t$Rt, $addr",
941                   [(opnode GPR:$Rt, t2addrmode_imm8:$addr)]> {
942    let Inst{31-27} = 0b11111;
943    let Inst{26-23} = 0b0000;
944    let Inst{22-21} = opcod;
945    let Inst{20} = 0; // !load
946    let Inst{11} = 1;
947    // Offset: index==TRUE, wback==FALSE
948    let Inst{10} = 1; // The P bit.
949    let Inst{8} = 0; // The W bit.
950
951    bits<4> Rt;
952    let Inst{15-12} = Rt;
953
954    bits<13> addr;
955    let Inst{19-16} = addr{12-9}; // Rn
956    let Inst{9}     = addr{8};    // U
957    let Inst{7-0}   = addr{7-0};  // imm
958  }
959  def s   : T2Iso <(outs), (ins GPR:$Rt, t2addrmode_so_reg:$addr), iis,
960                   opc, ".w\t$Rt, $addr",
961                   [(opnode GPR:$Rt, t2addrmode_so_reg:$addr)]> {
962    let Inst{31-27} = 0b11111;
963    let Inst{26-23} = 0b0000;
964    let Inst{22-21} = opcod;
965    let Inst{20} = 0; // !load
966    let Inst{11-6} = 0b000000;
967
968    bits<4> Rt;
969    let Inst{15-12} = Rt;
970
971    bits<10> addr;
972    let Inst{19-16}   = addr{9-6}; // Rn
973    let Inst{3-0} = addr{5-2}; // Rm
974    let Inst{5-4}   = addr{1-0}; // imm
975  }
976}
977
978/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a
979/// register and one whose operand is a register rotated by 8/16/24.
980multiclass T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> {
981  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
982                  opc, ".w\t$Rd, $Rm",
983                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> {
984     let Inst{31-27} = 0b11111;
985     let Inst{26-23} = 0b0100;
986     let Inst{22-20} = opcod;
987     let Inst{19-16} = 0b1111; // Rn
988     let Inst{15-12} = 0b1111;
989     let Inst{7} = 1;
990     let Inst{5-4} = 0b00; // rotate
991   }
992  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr,
993                  opc, ".w\t$Rd, $Rm, ror $rot",
994                 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]> {
995     let Inst{31-27} = 0b11111;
996     let Inst{26-23} = 0b0100;
997     let Inst{22-20} = opcod;
998     let Inst{19-16} = 0b1111; // Rn
999     let Inst{15-12} = 0b1111;
1000     let Inst{7} = 1;
1001
1002     bits<2> rot;
1003     let Inst{5-4} = rot{1-0}; // rotate
1004   }
1005}
1006
1007// UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
1008multiclass T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> {
1009  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1010                  opc, "\t$Rd, $Rm",
1011                 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>,
1012                 Requires<[HasT2ExtractPack, IsThumb2]> {
1013     let Inst{31-27} = 0b11111;
1014     let Inst{26-23} = 0b0100;
1015     let Inst{22-20} = opcod;
1016     let Inst{19-16} = 0b1111; // Rn
1017     let Inst{15-12} = 0b1111;
1018     let Inst{7} = 1;
1019     let Inst{5-4} = 0b00; // rotate
1020   }
1021  def r_rot : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
1022                  IIC_iEXTr, opc, "\t$dst, $Rm, ror $rot",
1023                 [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1024                 Requires<[HasT2ExtractPack, IsThumb2]> {
1025     let Inst{31-27} = 0b11111;
1026     let Inst{26-23} = 0b0100;
1027     let Inst{22-20} = opcod;
1028     let Inst{19-16} = 0b1111; // Rn
1029     let Inst{15-12} = 0b1111;
1030     let Inst{7} = 1;
1031
1032     bits<2> rot;
1033     let Inst{5-4} = rot{1-0}; // rotate
1034   }
1035}
1036
1037// SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern
1038// supported yet.
1039multiclass T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> {
1040  def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
1041                  opc, "\t$Rd, $Rm", []> {
1042     let Inst{31-27} = 0b11111;
1043     let Inst{26-23} = 0b0100;
1044     let Inst{22-20} = opcod;
1045     let Inst{19-16} = 0b1111; // Rn
1046     let Inst{15-12} = 0b1111;
1047     let Inst{7} = 1;
1048     let Inst{5-4} = 0b00; // rotate
1049   }
1050  def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
1051                  opc, "\t$Rd, $Rm, ror $rot", []> {
1052     let Inst{31-27} = 0b11111;
1053     let Inst{26-23} = 0b0100;
1054     let Inst{22-20} = opcod;
1055     let Inst{19-16} = 0b1111; // Rn
1056     let Inst{15-12} = 0b1111;
1057     let Inst{7} = 1;
1058
1059      bits<2> rot;
1060      let Inst{5-4} = rot{1-0}; // rotate
1061   }
1062}
1063
1064/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a
1065/// register and one whose operand is a register rotated by 8/16/24.
1066multiclass T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> {
1067  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1068                  opc, "\t$Rd, $Rn, $Rm",
1069                  [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1070                  Requires<[HasT2ExtractPack, IsThumb2]> {
1071     let Inst{31-27} = 0b11111;
1072     let Inst{26-23} = 0b0100;
1073     let Inst{22-20} = opcod;
1074     let Inst{15-12} = 0b1111;
1075     let Inst{7} = 1;
1076     let Inst{5-4} = 0b00; // rotate
1077   }
1078  def rr_rot : T2ThreeReg<(outs rGPR:$Rd),
1079                  (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot),
1080                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
1081                  [(set rGPR:$Rd, (opnode rGPR:$Rn,
1082                                          (rotr rGPR:$Rm, rot_imm:$rot)))]>,
1083                  Requires<[HasT2ExtractPack, IsThumb2]> {
1084     let Inst{31-27} = 0b11111;
1085     let Inst{26-23} = 0b0100;
1086     let Inst{22-20} = opcod;
1087     let Inst{15-12} = 0b1111;
1088     let Inst{7} = 1;
1089
1090     bits<2> rot;
1091     let Inst{5-4} = rot{1-0}; // rotate
1092   }
1093}
1094
1095// DO variant - disassembly only, no pattern
1096
1097multiclass T2I_exta_rrot_DO<bits<3> opcod, string opc> {
1098  def rr     : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iEXTAr,
1099                  opc, "\t$Rd, $Rn, $Rm", []> {
1100     let Inst{31-27} = 0b11111;
1101     let Inst{26-23} = 0b0100;
1102     let Inst{22-20} = opcod;
1103     let Inst{15-12} = 0b1111;
1104     let Inst{7} = 1;
1105     let Inst{5-4} = 0b00; // rotate
1106   }
1107  def rr_rot :T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, i32imm:$rot),
1108                  IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm, ror $rot", []> {
1109     let Inst{31-27} = 0b11111;
1110     let Inst{26-23} = 0b0100;
1111     let Inst{22-20} = opcod;
1112     let Inst{15-12} = 0b1111;
1113     let Inst{7} = 1;
1114
1115     bits<2> rot;
1116     let Inst{5-4} = rot{1-0}; // rotate
1117   }
1118}
1119
1120//===----------------------------------------------------------------------===//
1121// Instructions
1122//===----------------------------------------------------------------------===//
1123
1124//===----------------------------------------------------------------------===//
1125//  Miscellaneous Instructions.
1126//
1127
1128class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin,
1129           string asm, list<dag> pattern>
1130  : T2XI<oops, iops, itin, asm, pattern> {
1131  bits<4> Rd;
1132  bits<12> label;
1133
1134  let Inst{11-8}  = Rd;
1135  let Inst{26}    = label{11};
1136  let Inst{14-12} = label{10-8};
1137  let Inst{7-0}   = label{7-0};
1138}
1139
1140// LEApcrel - Load a pc-relative address into a register without offending the
1141// assembler.
1142def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1143              (ins t2adrlabel:$addr, pred:$p),
1144              IIC_iALUi, "adr{$p}.w\t$Rd, #$addr", []> {
1145  let Inst{31-27} = 0b11110;
1146  let Inst{25-24} = 0b10;
1147  // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE)
1148  let Inst{22} = 0;
1149  let Inst{20} = 0;
1150  let Inst{19-16} = 0b1111; // Rn
1151  let Inst{15} = 0;
1152
1153  bits<4> Rd;
1154  bits<13> addr;
1155  let Inst{11-8} = Rd;
1156  let Inst{23}    = addr{12};
1157  let Inst{21}    = addr{12};
1158  let Inst{26}    = addr{11};
1159  let Inst{14-12} = addr{10-8};
1160  let Inst{7-0}   = addr{7-0};
1161}
1162
1163let neverHasSideEffects = 1, isReMaterializable = 1 in
1164def t2LEApcrel   : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1165                                Size4Bytes, IIC_iALUi, []>;
1166def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
1167                                (ins i32imm:$label, nohash_imm:$id, pred:$p),
1168                                Size4Bytes, IIC_iALUi,
1169                                []>;
1170
1171
1172//===----------------------------------------------------------------------===//
1173//  Load / store Instructions.
1174//
1175
1176// Load
1177let canFoldAsLoad = 1, isReMaterializable = 1  in
1178defm t2LDR   : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si,
1179                      UnOpFrag<(load node:$Src)>>;
1180
1181// Loads with zero extension
1182defm t2LDRH  : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1183                      UnOpFrag<(zextloadi16 node:$Src)>>;
1184defm t2LDRB  : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1185                      UnOpFrag<(zextloadi8  node:$Src)>>;
1186
1187// Loads with sign extension
1188defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1189                      UnOpFrag<(sextloadi16 node:$Src)>>;
1190defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1191                      UnOpFrag<(sextloadi8  node:$Src)>>;
1192
1193let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1194// Load doubleword
1195def t2LDRDi8  : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1196                        (ins t2addrmode_imm8s4:$addr),
1197                        IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", []>;
1198} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1199
1200// zextload i1 -> zextload i8
1201def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
1202            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1203def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
1204            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1205def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
1206            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1207def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
1208            (t2LDRBpci  tconstpool:$addr)>;
1209
1210// extload -> zextload
1211// FIXME: Reduce the number of patterns by legalizing extload to zextload
1212// earlier?
1213def : T2Pat<(extloadi1  t2addrmode_imm12:$addr),
1214            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1215def : T2Pat<(extloadi1  t2addrmode_imm8:$addr),
1216            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1217def : T2Pat<(extloadi1  t2addrmode_so_reg:$addr),
1218            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1219def : T2Pat<(extloadi1  (ARMWrapper tconstpool:$addr)),
1220            (t2LDRBpci  tconstpool:$addr)>;
1221
1222def : T2Pat<(extloadi8  t2addrmode_imm12:$addr),
1223            (t2LDRBi12  t2addrmode_imm12:$addr)>;
1224def : T2Pat<(extloadi8  t2addrmode_imm8:$addr),
1225            (t2LDRBi8   t2addrmode_imm8:$addr)>;
1226def : T2Pat<(extloadi8  t2addrmode_so_reg:$addr),
1227            (t2LDRBs    t2addrmode_so_reg:$addr)>;
1228def : T2Pat<(extloadi8  (ARMWrapper tconstpool:$addr)),
1229            (t2LDRBpci  tconstpool:$addr)>;
1230
1231def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
1232            (t2LDRHi12  t2addrmode_imm12:$addr)>;
1233def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
1234            (t2LDRHi8   t2addrmode_imm8:$addr)>;
1235def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
1236            (t2LDRHs    t2addrmode_so_reg:$addr)>;
1237def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
1238            (t2LDRHpci  tconstpool:$addr)>;
1239
1240// FIXME: The destination register of the loads and stores can't be PC, but
1241//        can be SP. We need another regclass (similar to rGPR) to represent
1242//        that. Not a pressing issue since these are selected manually,
1243//        not via pattern.
1244
1245// Indexed loads
1246
1247let mayLoad = 1, neverHasSideEffects = 1 in {
1248def t2LDR_PRE  : T2Iidxldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1249                            (ins t2addrmode_imm8:$addr),
1250                            AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
1251                            "ldr", "\t$Rt, $addr!", "$addr.base = $Rn",
1252                            []>;
1253
1254def t2LDR_POST : T2Iidxldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1255                            (ins GPR:$base, t2am_imm8_offset:$addr),
1256                            AddrModeT2_i8, IndexModePost, IIC_iLoad_iu,
1257                          "ldr", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1258                            []>;
1259
1260def t2LDRB_PRE : T2Iidxldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1261                            (ins t2addrmode_imm8:$addr),
1262                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1263                            "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn",
1264                            []>;
1265def t2LDRB_POST : T2Iidxldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1266                            (ins GPR:$base, t2am_imm8_offset:$addr),
1267                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1268                         "ldrb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1269                            []>;
1270
1271def t2LDRH_PRE : T2Iidxldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1272                            (ins t2addrmode_imm8:$addr),
1273                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1274                            "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn",
1275                            []>;
1276def t2LDRH_POST : T2Iidxldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1277                            (ins GPR:$base, t2am_imm8_offset:$addr),
1278                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1279                         "ldrh", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1280                            []>;
1281
1282def t2LDRSB_PRE : T2Iidxldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1283                            (ins t2addrmode_imm8:$addr),
1284                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1285                            "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn",
1286                            []>;
1287def t2LDRSB_POST : T2Iidxldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn),
1288                            (ins GPR:$base, t2am_imm8_offset:$addr),
1289                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1290                        "ldrsb", "\t$Rt, [$Rn], $addr", "$base = $Rn",
1291                            []>;
1292
1293def t2LDRSH_PRE : T2Iidxldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn),
1294                            (ins t2addrmode_imm8:$addr),
1295                            AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
1296                            "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn",
1297                            []>;
1298def t2LDRSH_POST : T2Iidxldst<1, 0b01, 1, 0, (outs GPR:$dst, GPR:$Rn),
1299                            (ins GPR:$base, t2am_imm8_offset:$addr),
1300                            AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
1301                        "ldrsh", "\t$dst, [$Rn], $addr", "$base = $Rn",
1302                            []>;
1303} // mayLoad = 1, neverHasSideEffects = 1
1304
1305// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110) and are
1306// for disassembly only.
1307// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
1308class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
1309  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1310          "\t$Rt, $addr", []> {
1311  let Inst{31-27} = 0b11111;
1312  let Inst{26-25} = 0b00;
1313  let Inst{24} = signed;
1314  let Inst{23} = 0;
1315  let Inst{22-21} = type;
1316  let Inst{20} = 1; // load
1317  let Inst{11} = 1;
1318  let Inst{10-8} = 0b110; // PUW.
1319
1320  bits<4> Rt;
1321  bits<13> addr;
1322  let Inst{15-12} = Rt;
1323  let Inst{19-16} = addr{12-9};
1324  let Inst{7-0}   = addr{7-0};
1325}
1326
1327def t2LDRT   : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>;
1328def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1329def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1330def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1331def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1332
1333// Store
1334defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si,
1335                   BinOpFrag<(store node:$LHS, node:$RHS)>>;
1336defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1337                   BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1338defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1339                   BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
1340
1341// Store doubleword
1342let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1343def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs),
1344                       (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr),
1345               IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>;
1346
1347// Indexed stores
1348def t2STR_PRE  : T2Iidxldst<0, 0b10, 0, 1, (outs GPR:$base_wb),
1349                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1350                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1351                         "str", "\t$Rt, [$Rn, $addr]!",
1352                         "$Rn = $base_wb,@earlyclobber $base_wb",
1353             [(set GPR:$base_wb,
1354                   (pre_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1355
1356def t2STR_POST : T2Iidxldst<0, 0b10, 0, 0, (outs GPR:$base_wb),
1357                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1358                            AddrModeT2_i8, IndexModePost, IIC_iStore_iu,
1359                          "str", "\t$Rt, [$Rn], $addr",
1360                          "$Rn = $base_wb,@earlyclobber $base_wb",
1361             [(set GPR:$base_wb,
1362                  (post_store GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1363
1364def t2STRH_PRE  : T2Iidxldst<0, 0b01, 0, 1, (outs GPR:$base_wb),
1365                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1366                            AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
1367                        "strh", "\t$Rt, [$Rn, $addr]!",
1368                        "$Rn = $base_wb,@earlyclobber $base_wb",
1369        [(set GPR:$base_wb,
1370              (pre_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1371
1372def t2STRH_POST : T2Iidxldst<0, 0b01, 0, 0, (outs GPR:$base_wb),
1373                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1374                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1375                         "strh", "\t$Rt, [$Rn], $addr",
1376                         "$Rn = $base_wb,@earlyclobber $base_wb",
1377       [(set GPR:$base_wb,
1378             (post_truncsti16 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1379
1380def t2STRB_PRE  : T2Iidxldst<0, 0b00, 0, 1, (outs GPR:$base_wb),
1381                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1382                            AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
1383                        "strb", "\t$Rt, [$Rn, $addr]!",
1384                        "$Rn = $base_wb,@earlyclobber $base_wb",
1385         [(set GPR:$base_wb,
1386               (pre_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1387
1388def t2STRB_POST : T2Iidxldst<0, 0b00, 0, 0, (outs GPR:$base_wb),
1389                            (ins GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr),
1390                            AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu,
1391                         "strb", "\t$Rt, [$Rn], $addr",
1392                         "$Rn = $base_wb,@earlyclobber $base_wb",
1393        [(set GPR:$base_wb,
1394              (post_truncsti8 GPR:$Rt, GPR:$Rn, t2am_imm8_offset:$addr))]>;
1395
1396// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1397// only.
1398// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
1399class T2IstT<bits<2> type, string opc, InstrItinClass ii>
1400  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
1401          "\t$Rt, $addr", []> {
1402  let Inst{31-27} = 0b11111;
1403  let Inst{26-25} = 0b00;
1404  let Inst{24} = 0; // not signed
1405  let Inst{23} = 0;
1406  let Inst{22-21} = type;
1407  let Inst{20} = 0; // store
1408  let Inst{11} = 1;
1409  let Inst{10-8} = 0b110; // PUW
1410
1411  bits<4> Rt;
1412  bits<13> addr;
1413  let Inst{15-12} = Rt;
1414  let Inst{19-16} = addr{12-9};
1415  let Inst{7-0}   = addr{7-0};
1416}
1417
1418def t2STRT   : T2IstT<0b10, "strt", IIC_iStore_i>;
1419def t2STRBT  : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1420def t2STRHT  : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1421
1422// ldrd / strd pre / post variants
1423// For disassembly only.
1424
1425def t2LDRD_PRE  : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1426                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1427                 "ldrd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1428
1429def t2LDRD_POST : T2Ii8s4<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1430                 (ins GPR:$base, t2am_imm8s4_offset:$imm), IIC_iLoad_d_ru,
1431                 "ldrd", "\t$Rt, $Rt2, [$base], $imm", []>;
1432
1433def t2STRD_PRE  : T2Ii8s4<1, 1, 0, (outs),
1434                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1435                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base, $imm]!", []>;
1436
1437def t2STRD_POST : T2Ii8s4<0, 1, 0, (outs),
1438                 (ins rGPR:$Rt, rGPR:$Rt2, GPR:$base, t2am_imm8s4_offset:$imm),
1439                 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, [$base], $imm", []>;
1440
1441// T2Ipl (Preload Data/Instruction) signals the memory system of possible future
1442// data/instruction access.  These are for disassembly only.
1443// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1444// (prefetch 1) -> (preload 2),  (prefetch 2) -> (preload 1).
1445multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
1446
1447  def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc,
1448                "\t$addr",
1449              [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
1450    let Inst{31-25} = 0b1111100;
1451    let Inst{24} = instr;
1452    let Inst{22} = 0;
1453    let Inst{21} = write;
1454    let Inst{20} = 1;
1455    let Inst{15-12} = 0b1111;
1456
1457    bits<17> addr;
1458    let addr{12}    = 1;           // add = TRUE
1459    let Inst{19-16} = addr{16-13}; // Rn
1460    let Inst{23}    = addr{12};    // U
1461    let Inst{11-0}  = addr{11-0};  // imm12
1462  }
1463
1464  def i8 : T2Ii8<(outs), (ins t2addrmode_imm8:$addr), IIC_Preload, opc,
1465                "\t$addr",
1466               [(ARMPreload t2addrmode_imm8:$addr, (i32 write), (i32 instr))]> {
1467    let Inst{31-25} = 0b1111100;
1468    let Inst{24} = instr;
1469    let Inst{23} = 0; // U = 0
1470    let Inst{22} = 0;
1471    let Inst{21} = write;
1472    let Inst{20} = 1;
1473    let Inst{15-12} = 0b1111;
1474    let Inst{11-8} = 0b1100;
1475
1476    bits<13> addr;
1477    let Inst{19-16} = addr{12-9}; // Rn
1478    let Inst{7-0}   = addr{7-0};  // imm8
1479  }
1480
1481  def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc,
1482               "\t$addr",
1483             [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> {
1484    let Inst{31-25} = 0b1111100;
1485    let Inst{24} = instr;
1486    let Inst{23} = 0; // add = TRUE for T1
1487    let Inst{22} = 0;
1488    let Inst{21} = write;
1489    let Inst{20} = 1;
1490    let Inst{15-12} = 0b1111;
1491    let Inst{11-6} = 0000000;
1492
1493    bits<10> addr;
1494    let Inst{19-16} = addr{9-6}; // Rn
1495    let Inst{3-0}   = addr{5-2}; // Rm
1496    let Inst{5-4}   = addr{1-0}; // imm2
1497  }
1498}
1499
1500defm t2PLD  : T2Ipl<0, 0, "pld">,  Requires<[IsThumb2]>;
1501defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
1502defm t2PLI  : T2Ipl<0, 1, "pli">,  Requires<[IsThumb2,HasV7]>;
1503
1504//===----------------------------------------------------------------------===//
1505//  Load / store multiple Instructions.
1506//
1507
1508multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
1509                            InstrItinClass itin_upd, bit L_bit> {
1510  def IA :
1511    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1512         itin, !strconcat(asm, "ia${p}.w\t$Rn, $regs"), []> {
1513    bits<4>  Rn;
1514    bits<16> regs;
1515
1516    let Inst{31-27} = 0b11101;
1517    let Inst{26-25} = 0b00;
1518    let Inst{24-23} = 0b01;     // Increment After
1519    let Inst{22}    = 0;
1520    let Inst{21}    = 0;        // No writeback
1521    let Inst{20}    = L_bit;
1522    let Inst{19-16} = Rn;
1523    let Inst{15-0}  = regs;
1524  }
1525  def IA_UPD :
1526    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1527          itin_upd, !strconcat(asm, "ia${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
1528    bits<4>  Rn;
1529    bits<16> regs;
1530
1531    let Inst{31-27} = 0b11101;
1532    let Inst{26-25} = 0b00;
1533    let Inst{24-23} = 0b01;     // Increment After
1534    let Inst{22}    = 0;
1535    let Inst{21}    = 1;        // Writeback
1536    let Inst{20}    = L_bit;
1537    let Inst{19-16} = Rn;
1538    let Inst{15-0}  = regs;
1539  }
1540  def DB :
1541    T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1542         itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
1543    bits<4>  Rn;
1544    bits<16> regs;
1545
1546    let Inst{31-27} = 0b11101;
1547    let Inst{26-25} = 0b00;
1548    let Inst{24-23} = 0b10;     // Decrement Before
1549    let Inst{22}    = 0;
1550    let Inst{21}    = 0;        // No writeback
1551    let Inst{20}    = L_bit;
1552    let Inst{19-16} = Rn;
1553    let Inst{15-0}  = regs;
1554  }
1555  def DB_UPD :
1556    T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1557          itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
1558    bits<4>  Rn;
1559    bits<16> regs;
1560
1561    let Inst{31-27} = 0b11101;
1562    let Inst{26-25} = 0b00;
1563    let Inst{24-23} = 0b10;     // Decrement Before
1564    let Inst{22}    = 0;
1565    let Inst{21}    = 1;        // Writeback
1566    let Inst{20}    = L_bit;
1567    let Inst{19-16} = Rn;
1568    let Inst{15-0}  = regs;
1569  }
1570}
1571
1572let neverHasSideEffects = 1 in {
1573
1574let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1575defm t2LDM : thumb2_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>;
1576
1577let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1578defm t2STM : thumb2_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>;
1579
1580} // neverHasSideEffects
1581
1582
1583//===----------------------------------------------------------------------===//
1584//  Move Instructions.
1585//
1586
1587let neverHasSideEffects = 1 in
1588def t2MOVr : T2sTwoReg<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1589                   "mov", ".w\t$Rd, $Rm", []> {
1590  let Inst{31-27} = 0b11101;
1591  let Inst{26-25} = 0b01;
1592  let Inst{24-21} = 0b0010;
1593  let Inst{19-16} = 0b1111; // Rn
1594  let Inst{14-12} = 0b000;
1595  let Inst{7-4} = 0b0000;
1596}
1597
1598// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16.
1599let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
1600    AddedComplexity = 1 in
1601def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
1602                   "mov", ".w\t$Rd, $imm",
1603                   [(set rGPR:$Rd, t2_so_imm:$imm)]> {
1604  let Inst{31-27} = 0b11110;
1605  let Inst{25} = 0;
1606  let Inst{24-21} = 0b0010;
1607  let Inst{19-16} = 0b1111; // Rn
1608  let Inst{15} = 0;
1609}
1610
1611def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
1612                                                 pred:$p, cc_out:$s)>,
1613                Requires<[IsThumb2]>;
1614
1615let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1616def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi,
1617                   "movw", "\t$Rd, $imm",
1618                   [(set rGPR:$Rd, imm0_65535:$imm)]> {
1619  let Inst{31-27} = 0b11110;
1620  let Inst{25} = 1;
1621  let Inst{24-21} = 0b0010;
1622  let Inst{20} = 0; // The S bit.
1623  let Inst{15} = 0;
1624
1625  bits<4> Rd;
1626  bits<16> imm;
1627
1628  let Inst{11-8}  = Rd;
1629  let Inst{19-16} = imm{15-12};
1630  let Inst{26}    = imm{11};
1631  let Inst{14-12} = imm{10-8};
1632  let Inst{7-0}   = imm{7-0};
1633}
1634
1635def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1636                                (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1637
1638let Constraints = "$src = $Rd" in {
1639def t2MOVTi16 : T2I<(outs rGPR:$Rd),
1640                    (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi,
1641                    "movt", "\t$Rd, $imm",
1642                    [(set rGPR:$Rd,
1643                          (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> {
1644  let Inst{31-27} = 0b11110;
1645  let Inst{25} = 1;
1646  let Inst{24-21} = 0b0110;
1647  let Inst{20} = 0; // The S bit.
1648  let Inst{15} = 0;
1649
1650  bits<4> Rd;
1651  bits<16> imm;
1652
1653  let Inst{11-8}  = Rd;
1654  let Inst{19-16} = imm{15-12};
1655  let Inst{26}    = imm{11};
1656  let Inst{14-12} = imm{10-8};
1657  let Inst{7-0}   = imm{7-0};
1658}
1659
1660def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
1661                     (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1662} // Constraints
1663
1664def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
1665
1666//===----------------------------------------------------------------------===//
1667//  Extend Instructions.
1668//
1669
1670// Sign extenders
1671
1672defm t2SXTB  : T2I_ext_rrot<0b100, "sxtb",
1673                              UnOpFrag<(sext_inreg node:$Src, i8)>>;
1674defm t2SXTH  : T2I_ext_rrot<0b000, "sxth",
1675                              UnOpFrag<(sext_inreg node:$Src, i16)>>;
1676defm t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">;
1677
1678defm t2SXTAB : T2I_exta_rrot<0b100, "sxtab",
1679                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1680defm t2SXTAH : T2I_exta_rrot<0b000, "sxtah",
1681                        BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1682defm t2SXTAB16 : T2I_exta_rrot_DO<0b010, "sxtab16">;
1683
1684// TODO: SXT(A){B|H}16 - done for disassembly only
1685
1686// Zero extenders
1687
1688let AddedComplexity = 16 in {
1689defm t2UXTB   : T2I_ext_rrot<0b101, "uxtb",
1690                               UnOpFrag<(and node:$Src, 0x000000FF)>>;
1691defm t2UXTH   : T2I_ext_rrot<0b001, "uxth",
1692                               UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
1693defm t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16",
1694                               UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
1695
1696// FIXME: This pattern incorrectly assumes the shl operator is a rotate.
1697//        The transformation should probably be done as a combiner action
1698//        instead so we can include a check for masking back in the upper
1699//        eight bits of the source into the lower eight bits of the result.
1700//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF),
1701//            (t2UXTB16r_rot rGPR:$Src, 24)>,
1702//          Requires<[HasT2ExtractPack, IsThumb2]>;
1703def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF),
1704            (t2UXTB16r_rot rGPR:$Src, 8)>,
1705        Requires<[HasT2ExtractPack, IsThumb2]>;
1706
1707defm t2UXTAB : T2I_exta_rrot<0b101, "uxtab",
1708                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1709defm t2UXTAH : T2I_exta_rrot<0b001, "uxtah",
1710                           BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1711defm t2UXTAB16 : T2I_exta_rrot_DO<0b011, "uxtab16">;
1712}
1713
1714//===----------------------------------------------------------------------===//
1715//  Arithmetic Instructions.
1716//
1717
1718defm t2ADD  : T2I_bin_ii12rs<0b000, "add",
1719                             BinOpFrag<(add  node:$LHS, node:$RHS)>, 1>;
1720defm t2SUB  : T2I_bin_ii12rs<0b101, "sub",
1721                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1722
1723// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
1724defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
1725                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1726                             BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
1727defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
1728                             IIC_iALUi, IIC_iALUr, IIC_iALUsi,
1729                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1730
1731defm t2ADC  : T2I_adde_sube_irs<0b1010, "adc",
1732                          BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
1733defm t2SBC  : T2I_adde_sube_irs<0b1011, "sbc",
1734                          BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
1735defm t2ADCS : T2I_adde_sube_s_irs<BinOpFrag<(adde_live_carry node:$LHS,
1736                                                             node:$RHS)>, 1>;
1737defm t2SBCS : T2I_adde_sube_s_irs<BinOpFrag<(sube_live_carry node:$LHS,
1738                                                             node:$RHS)>>;
1739
1740// RSB
1741defm t2RSB  : T2I_rbin_irs  <0b1110, "rsb",
1742                             BinOpFrag<(sub  node:$LHS, node:$RHS)>>;
1743defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
1744                             BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1745
1746// (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
1747// The assume-no-carry-in form uses the negation of the input since add/sub
1748// assume opposite meanings of the carry flag (i.e., carry == !borrow).
1749// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
1750// details.
1751// The AddedComplexity preferences the first variant over the others since
1752// it can be shrunk to a 16-bit wide encoding, while the others cannot.
1753let AddedComplexity = 1 in
1754def : T2Pat<(add        GPR:$src, imm0_255_neg:$imm),
1755            (t2SUBri    GPR:$src, imm0_255_neg:$imm)>;
1756def : T2Pat<(add        GPR:$src, t2_so_imm_neg:$imm),
1757            (t2SUBri    GPR:$src, t2_so_imm_neg:$imm)>;
1758def : T2Pat<(add        GPR:$src, imm0_4095_neg:$imm),
1759            (t2SUBri12  GPR:$src, imm0_4095_neg:$imm)>;
1760let AddedComplexity = 1 in
1761def : T2Pat<(addc       rGPR:$src, imm0_255_neg:$imm),
1762            (t2SUBSri   rGPR:$src, imm0_255_neg:$imm)>;
1763def : T2Pat<(addc       rGPR:$src, t2_so_imm_neg:$imm),
1764            (t2SUBSri   rGPR:$src, t2_so_imm_neg:$imm)>;
1765// The with-carry-in form matches bitwise not instead of the negation.
1766// Effectively, the inverse interpretation of the carry flag already accounts
1767// for part of the negation.
1768let AddedComplexity = 1 in
1769def : T2Pat<(adde_dead_carry       rGPR:$src, imm0_255_not:$imm),
1770            (t2SBCri    rGPR:$src, imm0_255_not:$imm)>;
1771def : T2Pat<(adde_dead_carry       rGPR:$src, t2_so_imm_not:$imm),
1772            (t2SBCri    rGPR:$src, t2_so_imm_not:$imm)>;
1773let AddedComplexity = 1 in
1774def : T2Pat<(adde_live_carry       rGPR:$src, imm0_255_not:$imm),
1775            (t2SBCSri   rGPR:$src, imm0_255_not:$imm)>;
1776def : T2Pat<(adde_live_carry       rGPR:$src, t2_so_imm_not:$imm),
1777            (t2SBCSri   rGPR:$src, t2_so_imm_not:$imm)>;
1778
1779// Select Bytes -- for disassembly only
1780
1781def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1782                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
1783  let Inst{31-27} = 0b11111;
1784  let Inst{26-24} = 0b010;
1785  let Inst{23} = 0b1;
1786  let Inst{22-20} = 0b010;
1787  let Inst{15-12} = 0b1111;
1788  let Inst{7} = 0b1;
1789  let Inst{6-4} = 0b000;
1790}
1791
1792// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned)
1793// And Miscellaneous operations -- for disassembly only
1794class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc,
1795              list<dag> pat = [/* For disassembly only; pattern left blank */],
1796              dag iops = (ins rGPR:$Rn, rGPR:$Rm),
1797              string asm = "\t$Rd, $Rn, $Rm">
1798  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> {
1799  let Inst{31-27} = 0b11111;
1800  let Inst{26-23} = 0b0101;
1801  let Inst{22-20} = op22_20;
1802  let Inst{15-12} = 0b1111;
1803  let Inst{7-4} = op7_4;
1804
1805  bits<4> Rd;
1806  bits<4> Rn;
1807  bits<4> Rm;
1808
1809  let Inst{11-8}  = Rd;
1810  let Inst{19-16} = Rn;
1811  let Inst{3-0}   = Rm;
1812}
1813
1814// Saturating add/subtract -- for disassembly only
1815
1816def t2QADD    : T2I_pam<0b000, 0b1000, "qadd",
1817                        [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))],
1818                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1819def t2QADD16  : T2I_pam<0b001, 0b0001, "qadd16">;
1820def t2QADD8   : T2I_pam<0b000, 0b0001, "qadd8">;
1821def t2QASX    : T2I_pam<0b010, 0b0001, "qasx">;
1822def t2QDADD   : T2I_pam<0b000, 0b1001, "qdadd", [],
1823                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1824def t2QDSUB   : T2I_pam<0b000, 0b1011, "qdsub", [],
1825                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1826def t2QSAX    : T2I_pam<0b110, 0b0001, "qsax">;
1827def t2QSUB    : T2I_pam<0b000, 0b1010, "qsub",
1828                        [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))],
1829                        (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
1830def t2QSUB16  : T2I_pam<0b101, 0b0001, "qsub16">;
1831def t2QSUB8   : T2I_pam<0b100, 0b0001, "qsub8">;
1832def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;
1833def t2UQADD8  : T2I_pam<0b000, 0b0101, "uqadd8">;
1834def t2UQASX   : T2I_pam<0b010, 0b0101, "uqasx">;
1835def t2UQSAX   : T2I_pam<0b110, 0b0101, "uqsax">;
1836def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
1837def t2UQSUB8  : T2I_pam<0b100, 0b0101, "uqsub8">;
1838
1839// Signed/Unsigned add/subtract -- for disassembly only
1840
1841def t2SASX    : T2I_pam<0b010, 0b0000, "sasx">;
1842def t2SADD16  : T2I_pam<0b001, 0b0000, "sadd16">;
1843def t2SADD8   : T2I_pam<0b000, 0b0000, "sadd8">;
1844def t2SSAX    : T2I_pam<0b110, 0b0000, "ssax">;
1845def t2SSUB16  : T2I_pam<0b101, 0b0000, "ssub16">;
1846def t2SSUB8   : T2I_pam<0b100, 0b0000, "ssub8">;
1847def t2UASX    : T2I_pam<0b010, 0b0100, "uasx">;
1848def t2UADD16  : T2I_pam<0b001, 0b0100, "uadd16">;
1849def t2UADD8   : T2I_pam<0b000, 0b0100, "uadd8">;
1850def t2USAX    : T2I_pam<0b110, 0b0100, "usax">;
1851def t2USUB16  : T2I_pam<0b101, 0b0100, "usub16">;
1852def t2USUB8   : T2I_pam<0b100, 0b0100, "usub8">;
1853
1854// Signed/Unsigned halving add/subtract -- for disassembly only
1855
1856def t2SHASX   : T2I_pam<0b010, 0b0010, "shasx">;
1857def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">;
1858def t2SHADD8  : T2I_pam<0b000, 0b0010, "shadd8">;
1859def t2SHSAX   : T2I_pam<0b110, 0b0010, "shsax">;
1860def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">;
1861def t2SHSUB8  : T2I_pam<0b100, 0b0010, "shsub8">;
1862def t2UHASX   : T2I_pam<0b010, 0b0110, "uhasx">;
1863def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">;
1864def t2UHADD8  : T2I_pam<0b000, 0b0110, "uhadd8">;
1865def t2UHSAX   : T2I_pam<0b110, 0b0110, "uhsax">;
1866def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">;
1867def t2UHSUB8  : T2I_pam<0b100, 0b0110, "uhsub8">;
1868
1869// Helper class for disassembly only
1870// A6.3.16 & A6.3.17
1871// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions.
1872class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1873  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1874  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
1875  let Inst{31-27} = 0b11111;
1876  let Inst{26-24} = 0b011;
1877  let Inst{23}    = long;
1878  let Inst{22-20} = op22_20;
1879  let Inst{7-4}   = op7_4;
1880}
1881
1882class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops,
1883  dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
1884  : T2FourReg<oops, iops, itin, opc, asm, pattern> {
1885  let Inst{31-27} = 0b11111;
1886  let Inst{26-24} = 0b011;
1887  let Inst{23}    = long;
1888  let Inst{22-20} = op22_20;
1889  let Inst{7-4}   = op7_4;
1890}
1891
1892// Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
1893
1894def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1895                                           (ins rGPR:$Rn, rGPR:$Rm),
1896                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
1897  let Inst{15-12} = 0b1111;
1898}
1899def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
1900                       (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
1901                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
1902
1903// Signed/Unsigned saturate -- for disassembly only
1904
1905class T2SatI<dag oops, dag iops, InstrItinClass itin,
1906           string opc, string asm, list<dag> pattern>
1907  : T2I<oops, iops, itin, opc, asm, pattern> {
1908  bits<4> Rd;
1909  bits<4> Rn;
1910  bits<5> sat_imm;
1911  bits<7> sh;
1912
1913  let Inst{11-8}  = Rd;
1914  let Inst{19-16} = Rn;
1915  let Inst{4-0}   = sat_imm{4-0};
1916  let Inst{21}    = sh{6};
1917  let Inst{14-12} = sh{4-2};
1918  let Inst{7-6}   = sh{1-0};
1919}
1920
1921def t2SSAT: T2SatI<
1922              (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1923              NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
1924              [/* For disassembly only; pattern left blank */]> {
1925  let Inst{31-27} = 0b11110;
1926  let Inst{25-22} = 0b1100;
1927  let Inst{20} = 0;
1928  let Inst{15} = 0;
1929}
1930
1931def t2SSAT16: T2SatI<
1932                (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
1933                "ssat16", "\t$Rd, $sat_imm, $Rn",
1934                [/* For disassembly only; pattern left blank */]> {
1935  let Inst{31-27} = 0b11110;
1936  let Inst{25-22} = 0b1100;
1937  let Inst{20} = 0;
1938  let Inst{15} = 0;
1939  let Inst{21} = 1;        // sh = '1'
1940  let Inst{14-12} = 0b000; // imm3 = '000'
1941  let Inst{7-6} = 0b00;    // imm2 = '00'
1942}
1943
1944def t2USAT: T2SatI<
1945                (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
1946                NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh",
1947                [/* For disassembly only; pattern left blank */]> {
1948  let Inst{31-27} = 0b11110;
1949  let Inst{25-22} = 0b1110;
1950  let Inst{20} = 0;
1951  let Inst{15} = 0;
1952}
1953
1954def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
1955                     NoItinerary,
1956                     "usat16", "\t$dst, $sat_imm, $Rn",
1957                     [/* For disassembly only; pattern left blank */]> {
1958  let Inst{31-27} = 0b11110;
1959  let Inst{25-22} = 0b1110;
1960  let Inst{20} = 0;
1961  let Inst{15} = 0;
1962  let Inst{21} = 1;        // sh = '1'
1963  let Inst{14-12} = 0b000; // imm3 = '000'
1964  let Inst{7-6} = 0b00;    // imm2 = '00'
1965}
1966
1967def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>;
1968def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>;
1969
1970//===----------------------------------------------------------------------===//
1971//  Shift and rotate Instructions.
1972//
1973
1974defm t2LSL  : T2I_sh_ir<0b00, "lsl", BinOpFrag<(shl  node:$LHS, node:$RHS)>>;
1975defm t2LSR  : T2I_sh_ir<0b01, "lsr", BinOpFrag<(srl  node:$LHS, node:$RHS)>>;
1976defm t2ASR  : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
1977defm t2ROR  : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
1978
1979// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
1980def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
1981          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
1982
1983let Uses = [CPSR] in {
1984def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1985                   "rrx", "\t$Rd, $Rm",
1986                   [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> {
1987  let Inst{31-27} = 0b11101;
1988  let Inst{26-25} = 0b01;
1989  let Inst{24-21} = 0b0010;
1990  let Inst{19-16} = 0b1111; // Rn
1991  let Inst{14-12} = 0b000;
1992  let Inst{7-4} = 0b0011;
1993}
1994}
1995
1996let isCodeGenOnly = 1, Defs = [CPSR] in {
1997def t2MOVsrl_flag : T2TwoRegShiftImm<
1998                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
1999                        "lsrs", ".w\t$Rd, $Rm, #1",
2000                        [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> {
2001  let Inst{31-27} = 0b11101;
2002  let Inst{26-25} = 0b01;
2003  let Inst{24-21} = 0b0010;
2004  let Inst{20} = 1; // The S bit.
2005  let Inst{19-16} = 0b1111; // Rn
2006  let Inst{5-4} = 0b01; // Shift type.
2007  // Shift amount = Inst{14-12:7-6} = 1.
2008  let Inst{14-12} = 0b000;
2009  let Inst{7-6} = 0b01;
2010}
2011def t2MOVsra_flag : T2TwoRegShiftImm<
2012                        (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2013                        "asrs", ".w\t$Rd, $Rm, #1",
2014                        [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> {
2015  let Inst{31-27} = 0b11101;
2016  let Inst{26-25} = 0b01;
2017  let Inst{24-21} = 0b0010;
2018  let Inst{20} = 1; // The S bit.
2019  let Inst{19-16} = 0b1111; // Rn
2020  let Inst{5-4} = 0b10; // Shift type.
2021  // Shift amount = Inst{14-12:7-6} = 1.
2022  let Inst{14-12} = 0b000;
2023  let Inst{7-6} = 0b01;
2024}
2025}
2026
2027//===----------------------------------------------------------------------===//
2028//  Bitwise Instructions.
2029//
2030
2031defm t2AND  : T2I_bin_w_irs<0b0000, "and",
2032                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2033                            BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>;
2034defm t2ORR  : T2I_bin_w_irs<0b0010, "orr",
2035                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2036                            BinOpFrag<(or  node:$LHS, node:$RHS)>, "t2ORR", 1>;
2037defm t2EOR  : T2I_bin_w_irs<0b0100, "eor",
2038                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2039                            BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>;
2040
2041defm t2BIC  : T2I_bin_w_irs<0b0001, "bic",
2042                            IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2043                            BinOpFrag<(and node:$LHS, (not node:$RHS))>,
2044                            "t2BIC">;
2045
2046class T2BitFI<dag oops, dag iops, InstrItinClass itin,
2047              string opc, string asm, list<dag> pattern>
2048    : T2I<oops, iops, itin, opc, asm, pattern> {
2049  bits<4> Rd;
2050  bits<5> msb;
2051  bits<5> lsb;
2052
2053  let Inst{11-8}  = Rd;
2054  let Inst{4-0}   = msb{4-0};
2055  let Inst{14-12} = lsb{4-2};
2056  let Inst{7-6}   = lsb{1-0};
2057}
2058
2059class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin,
2060              string opc, string asm, list<dag> pattern>
2061    : T2BitFI<oops, iops, itin, opc, asm, pattern> {
2062  bits<4> Rn;
2063
2064  let Inst{19-16} = Rn;
2065}
2066
2067let Constraints = "$src = $Rd" in
2068def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2069                IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2070                [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> {
2071  let Inst{31-27} = 0b11110;
2072  let Inst{26} = 0; // should be 0.
2073  let Inst{25} = 1;
2074  let Inst{24-20} = 0b10110;
2075  let Inst{19-16} = 0b1111; // Rn
2076  let Inst{15} = 0;
2077  let Inst{5} = 0; // should be 0.
2078
2079  bits<10> imm;
2080  let msb{4-0} = imm{9-5};
2081  let lsb{4-0} = imm{4-0};
2082}
2083
2084def t2SBFX: T2TwoRegBitFI<
2085                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2086                 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2087  let Inst{31-27} = 0b11110;
2088  let Inst{25} = 1;
2089  let Inst{24-20} = 0b10100;
2090  let Inst{15} = 0;
2091}
2092
2093def t2UBFX: T2TwoRegBitFI<
2094                (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
2095                 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
2096  let Inst{31-27} = 0b11110;
2097  let Inst{25} = 1;
2098  let Inst{24-20} = 0b11100;
2099  let Inst{15} = 0;
2100}
2101
2102// A8.6.18  BFI - Bitfield insert (Encoding T1)
2103let Constraints = "$src = $Rd" in {
2104  def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2105                  (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm),
2106                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2107                  [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2108                                   bf_inv_mask_imm:$imm))]> {
2109    let Inst{31-27} = 0b11110;
2110    let Inst{26} = 0; // should be 0.
2111    let Inst{25} = 1;
2112    let Inst{24-20} = 0b10110;
2113    let Inst{15} = 0;
2114    let Inst{5} = 0; // should be 0.
2115
2116    bits<10> imm;
2117    let msb{4-0} = imm{9-5};
2118    let lsb{4-0} = imm{4-0};
2119  }
2120
2121  // GNU as only supports this form of bfi (w/ 4 arguments)
2122  let isAsmParserOnly = 1 in
2123  def t2BFI4p : T2TwoRegBitFI<(outs rGPR:$Rd),
2124                  (ins rGPR:$src, rGPR:$Rn, lsb_pos_imm:$lsbit,
2125                       width_imm:$width),
2126                  IIC_iBITi, "bfi", "\t$Rd, $Rn, $lsbit, $width",
2127                  []> {
2128    let Inst{31-27} = 0b11110;
2129    let Inst{26} = 0; // should be 0.
2130    let Inst{25} = 1;
2131    let Inst{24-20} = 0b10110;
2132    let Inst{15} = 0;
2133    let Inst{5} = 0; // should be 0.
2134
2135    bits<5> lsbit;
2136    bits<5> width;
2137    let msb{4-0} = width; // Custom encoder => lsb+width-1
2138    let lsb{4-0} = lsbit;
2139  }
2140}
2141
2142defm t2ORN  : T2I_bin_irs<0b0011, "orn",
2143                          IIC_iBITi, IIC_iBITr, IIC_iBITsi,
2144                          BinOpFrag<(or  node:$LHS, (not node:$RHS))>,
2145                          "t2ORN", 0, "">;
2146
2147// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
2148let AddedComplexity = 1 in
2149defm t2MVN  : T2I_un_irs <0b0011, "mvn",
2150                          IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi,
2151                          UnOpFrag<(not node:$Src)>, 1, 1>;
2152
2153
2154let AddedComplexity = 1 in
2155def : T2Pat<(and     rGPR:$src, t2_so_imm_not:$imm),
2156            (t2BICri rGPR:$src, t2_so_imm_not:$imm)>;
2157
2158// FIXME: Disable this pattern on Darwin to workaround an assembler bug.
2159def : T2Pat<(or      rGPR:$src, t2_so_imm_not:$imm),
2160            (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>,
2161            Requires<[IsThumb2]>;
2162
2163def : T2Pat<(t2_so_imm_not:$src),
2164            (t2MVNi t2_so_imm_not:$src)>;
2165
2166//===----------------------------------------------------------------------===//
2167//  Multiply Instructions.
2168//
2169let isCommutable = 1 in
2170def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2171                "mul", "\t$Rd, $Rn, $Rm",
2172                [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> {
2173  let Inst{31-27} = 0b11111;
2174  let Inst{26-23} = 0b0110;
2175  let Inst{22-20} = 0b000;
2176  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2177  let Inst{7-4} = 0b0000; // Multiply
2178}
2179
2180def t2MLA: T2FourReg<
2181                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2182                "mla", "\t$Rd, $Rn, $Rm, $Ra",
2183                [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> {
2184  let Inst{31-27} = 0b11111;
2185  let Inst{26-23} = 0b0110;
2186  let Inst{22-20} = 0b000;
2187  let Inst{7-4} = 0b0000; // Multiply
2188}
2189
2190def t2MLS: T2FourReg<
2191                (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2192                "mls", "\t$Rd, $Rn, $Rm, $Ra",
2193                [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> {
2194  let Inst{31-27} = 0b11111;
2195  let Inst{26-23} = 0b0110;
2196  let Inst{22-20} = 0b000;
2197  let Inst{7-4} = 0b0001; // Multiply and Subtract
2198}
2199
2200// Extra precision multiplies with low / high results
2201let neverHasSideEffects = 1 in {
2202let isCommutable = 1 in {
2203def t2SMULL : T2MulLong<0b000, 0b0000,
2204                  (outs rGPR:$Rd, rGPR:$Ra),
2205                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2206                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
2207
2208def t2UMULL : T2MulLong<0b010, 0b0000,
2209                  (outs rGPR:$RdLo, rGPR:$RdHi),
2210                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
2211                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2212} // isCommutable
2213
2214// Multiply + accumulate
2215def t2SMLAL : T2MulLong<0b100, 0b0000,
2216                  (outs rGPR:$RdLo, rGPR:$RdHi),
2217                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2218                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2219
2220def t2UMLAL : T2MulLong<0b110, 0b0000,
2221                  (outs rGPR:$RdLo, rGPR:$RdHi),
2222                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2223                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2224
2225def t2UMAAL : T2MulLong<0b110, 0b0110,
2226                  (outs rGPR:$RdLo, rGPR:$RdHi),
2227                  (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
2228                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2229} // neverHasSideEffects
2230
2231// Rounding variants of the below included for disassembly only
2232
2233// Most significant word multiply
2234def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2235                  "smmul", "\t$Rd, $Rn, $Rm",
2236                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
2237  let Inst{31-27} = 0b11111;
2238  let Inst{26-23} = 0b0110;
2239  let Inst{22-20} = 0b101;
2240  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2241  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2242}
2243
2244def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2245                  "smmulr", "\t$Rd, $Rn, $Rm", []> {
2246  let Inst{31-27} = 0b11111;
2247  let Inst{26-23} = 0b0110;
2248  let Inst{22-20} = 0b101;
2249  let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2250  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2251}
2252
2253def t2SMMLA : T2FourReg<
2254        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2255                "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2256                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
2257  let Inst{31-27} = 0b11111;
2258  let Inst{26-23} = 0b0110;
2259  let Inst{22-20} = 0b101;
2260  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2261}
2262
2263def t2SMMLAR: T2FourReg<
2264        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2265                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
2266  let Inst{31-27} = 0b11111;
2267  let Inst{26-23} = 0b0110;
2268  let Inst{22-20} = 0b101;
2269  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2270}
2271
2272def t2SMMLS: T2FourReg<
2273        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2274                "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2275                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
2276  let Inst{31-27} = 0b11111;
2277  let Inst{26-23} = 0b0110;
2278  let Inst{22-20} = 0b110;
2279  let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
2280}
2281
2282def t2SMMLSR:T2FourReg<
2283        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2284                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
2285  let Inst{31-27} = 0b11111;
2286  let Inst{26-23} = 0b0110;
2287  let Inst{22-20} = 0b110;
2288  let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
2289}
2290
2291multiclass T2I_smul<string opc, PatFrag opnode> {
2292  def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2293              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2294              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2295                                      (sext_inreg rGPR:$Rm, i16)))]> {
2296    let Inst{31-27} = 0b11111;
2297    let Inst{26-23} = 0b0110;
2298    let Inst{22-20} = 0b001;
2299    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2300    let Inst{7-6} = 0b00;
2301    let Inst{5-4} = 0b00;
2302  }
2303
2304  def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2305              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2306              [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
2307                                      (sra rGPR:$Rm, (i32 16))))]> {
2308    let Inst{31-27} = 0b11111;
2309    let Inst{26-23} = 0b0110;
2310    let Inst{22-20} = 0b001;
2311    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2312    let Inst{7-6} = 0b00;
2313    let Inst{5-4} = 0b01;
2314  }
2315
2316  def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2317              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2318              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2319                                      (sext_inreg rGPR:$Rm, i16)))]> {
2320    let Inst{31-27} = 0b11111;
2321    let Inst{26-23} = 0b0110;
2322    let Inst{22-20} = 0b001;
2323    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2324    let Inst{7-6} = 0b00;
2325    let Inst{5-4} = 0b10;
2326  }
2327
2328  def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2329              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2330              [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
2331                                      (sra rGPR:$Rm, (i32 16))))]> {
2332    let Inst{31-27} = 0b11111;
2333    let Inst{26-23} = 0b0110;
2334    let Inst{22-20} = 0b001;
2335    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2336    let Inst{7-6} = 0b00;
2337    let Inst{5-4} = 0b11;
2338  }
2339
2340  def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2341              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2342              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2343                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
2344    let Inst{31-27} = 0b11111;
2345    let Inst{26-23} = 0b0110;
2346    let Inst{22-20} = 0b011;
2347    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2348    let Inst{7-6} = 0b00;
2349    let Inst{5-4} = 0b00;
2350  }
2351
2352  def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
2353              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2354              [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
2355                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
2356    let Inst{31-27} = 0b11111;
2357    let Inst{26-23} = 0b0110;
2358    let Inst{22-20} = 0b011;
2359    let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
2360    let Inst{7-6} = 0b00;
2361    let Inst{5-4} = 0b01;
2362  }
2363}
2364
2365
2366multiclass T2I_smla<string opc, PatFrag opnode> {
2367  def BB : T2FourReg<
2368        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2369              !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2370              [(set rGPR:$Rd, (add rGPR:$Ra,
2371                               (opnode (sext_inreg rGPR:$Rn, i16),
2372                                       (sext_inreg rGPR:$Rm, i16))))]> {
2373    let Inst{31-27} = 0b11111;
2374    let Inst{26-23} = 0b0110;
2375    let Inst{22-20} = 0b001;
2376    let Inst{7-6} = 0b00;
2377    let Inst{5-4} = 0b00;
2378  }
2379
2380  def BT : T2FourReg<
2381       (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2382             !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2383             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
2384                                                 (sra rGPR:$Rm, (i32 16)))))]> {
2385    let Inst{31-27} = 0b11111;
2386    let Inst{26-23} = 0b0110;
2387    let Inst{22-20} = 0b001;
2388    let Inst{7-6} = 0b00;
2389    let Inst{5-4} = 0b01;
2390  }
2391
2392  def TB : T2FourReg<
2393        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2394              !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2395              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2396                                               (sext_inreg rGPR:$Rm, i16))))]> {
2397    let Inst{31-27} = 0b11111;
2398    let Inst{26-23} = 0b0110;
2399    let Inst{22-20} = 0b001;
2400    let Inst{7-6} = 0b00;
2401    let Inst{5-4} = 0b10;
2402  }
2403
2404  def TT : T2FourReg<
2405        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2406              !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2407             [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
2408                                                 (sra rGPR:$Rm, (i32 16)))))]> {
2409    let Inst{31-27} = 0b11111;
2410    let Inst{26-23} = 0b0110;
2411    let Inst{22-20} = 0b001;
2412    let Inst{7-6} = 0b00;
2413    let Inst{5-4} = 0b11;
2414  }
2415
2416  def WB : T2FourReg<
2417        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2418              !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2419              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2420                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
2421    let Inst{31-27} = 0b11111;
2422    let Inst{26-23} = 0b0110;
2423    let Inst{22-20} = 0b011;
2424    let Inst{7-6} = 0b00;
2425    let Inst{5-4} = 0b00;
2426  }
2427
2428  def WT : T2FourReg<
2429        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
2430              !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2431              [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
2432                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
2433    let Inst{31-27} = 0b11111;
2434    let Inst{26-23} = 0b0110;
2435    let Inst{22-20} = 0b011;
2436    let Inst{7-6} = 0b00;
2437    let Inst{5-4} = 0b01;
2438  }
2439}
2440
2441defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2442defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2443
2444// Halfword multiple accumulate long: SMLAL<x><y> -- for disassembly only
2445def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
2446         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
2447           [/* For disassembly only; pattern left blank */]>;
2448def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
2449         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
2450           [/* For disassembly only; pattern left blank */]>;
2451def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
2452         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
2453           [/* For disassembly only; pattern left blank */]>;
2454def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
2455         (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
2456           [/* For disassembly only; pattern left blank */]>;
2457
2458// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
2459// These are for disassembly only.
2460
2461def t2SMUAD: T2ThreeReg_mac<
2462            0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2463            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
2464  let Inst{15-12} = 0b1111;
2465}
2466def t2SMUADX:T2ThreeReg_mac<
2467            0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2468            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
2469  let Inst{15-12} = 0b1111;
2470}
2471def t2SMUSD: T2ThreeReg_mac<
2472            0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2473            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
2474  let Inst{15-12} = 0b1111;
2475}
2476def t2SMUSDX:T2ThreeReg_mac<
2477            0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
2478            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
2479  let Inst{15-12} = 0b1111;
2480}
2481def t2SMLAD   : T2ThreeReg_mac<
2482            0, 0b010, 0b0000, (outs rGPR:$Rd),
2483            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
2484            "\t$Rd, $Rn, $Rm, $Ra", []>;
2485def t2SMLADX  : T2FourReg_mac<
2486            0, 0b010, 0b0001, (outs rGPR:$Rd),
2487            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
2488            "\t$Rd, $Rn, $Rm, $Ra", []>;
2489def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
2490            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
2491            "\t$Rd, $Rn, $Rm, $Ra", []>;
2492def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
2493            (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
2494            "\t$Rd, $Rn, $Rm, $Ra", []>;
2495def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2496                        (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
2497                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2498def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2499                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
2500                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2501def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
2502                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
2503                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2504def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
2505                        (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
2506                        "\t$Ra, $Rd, $Rm, $Rn", []>;
2507
2508//===----------------------------------------------------------------------===//
2509//  Division Instructions.
2510//  Signed and unsigned division on v7-M
2511//
2512def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2513                 "sdiv", "\t$Rd, $Rn, $Rm",
2514                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
2515                 Requires<[HasDivide, IsThumb2]> {
2516  let Inst{31-27} = 0b11111;
2517  let Inst{26-21} = 0b011100;
2518  let Inst{20} = 0b1;
2519  let Inst{15-12} = 0b1111;
2520  let Inst{7-4} = 0b1111;
2521}
2522
2523def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
2524                 "udiv", "\t$Rd, $Rn, $Rm",
2525                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
2526                 Requires<[HasDivide, IsThumb2]> {
2527  let Inst{31-27} = 0b11111;
2528  let Inst{26-21} = 0b011101;
2529  let Inst{20} = 0b1;
2530  let Inst{15-12} = 0b1111;
2531  let Inst{7-4} = 0b1111;
2532}
2533
2534//===----------------------------------------------------------------------===//
2535//  Misc. Arithmetic Instructions.
2536//
2537
2538class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
2539      InstrItinClass itin, string opc, string asm, list<dag> pattern>
2540  : T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
2541  let Inst{31-27} = 0b11111;
2542  let Inst{26-22} = 0b01010;
2543  let Inst{21-20} = op1;
2544  let Inst{15-12} = 0b1111;
2545  let Inst{7-6} = 0b10;
2546  let Inst{5-4} = op2;
2547  let Rn{3-0} = Rm;
2548}
2549
2550def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2551                    "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
2552
2553def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2554                      "rbit", "\t$Rd, $Rm",
2555                      [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
2556
2557def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2558                 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
2559
2560def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2561                       "rev16", ".w\t$Rd, $Rm",
2562                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
2563
2564def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2565                       "revsh", ".w\t$Rd, $Rm",
2566                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
2567
2568def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
2569                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
2570            (t2REVSH rGPR:$Rm)>;
2571
2572def t2PKHBT : T2ThreeReg<
2573            (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2574                  IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2575                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
2576                                      (and (shl rGPR:$Rm, lsl_amt:$sh),
2577                                           0xFFFF0000)))]>,
2578                  Requires<[HasT2ExtractPack, IsThumb2]> {
2579  let Inst{31-27} = 0b11101;
2580  let Inst{26-25} = 0b01;
2581  let Inst{24-20} = 0b01100;
2582  let Inst{5} = 0; // BT form
2583  let Inst{4} = 0;
2584
2585  bits<8> sh;
2586  let Inst{14-12} = sh{7-5};
2587  let Inst{7-6}   = sh{4-3};
2588}
2589
2590// Alternate cases for PKHBT where identities eliminate some nodes.
2591def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
2592            (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
2593            Requires<[HasT2ExtractPack, IsThumb2]>;
2594def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2595            (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
2596            Requires<[HasT2ExtractPack, IsThumb2]>;
2597
2598// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2599// will match the pattern below.
2600def t2PKHTB : T2ThreeReg<
2601                  (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
2602                  IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2603                  [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
2604                                       (and (sra rGPR:$Rm, asr_amt:$sh),
2605                                            0xFFFF)))]>,
2606                  Requires<[HasT2ExtractPack, IsThumb2]> {
2607  let Inst{31-27} = 0b11101;
2608  let Inst{26-25} = 0b01;
2609  let Inst{24-20} = 0b01100;
2610  let Inst{5} = 1; // TB form
2611  let Inst{4} = 0;
2612
2613  bits<8> sh;
2614  let Inst{14-12} = sh{7-5};
2615  let Inst{7-6}   = sh{4-3};
2616}
2617
2618// Alternate cases for PKHTB where identities eliminate some nodes.  Note that
2619// a shift amount of 0 is *not legal* here, it is PKHBT instead.
2620def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2621            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
2622            Requires<[HasT2ExtractPack, IsThumb2]>;
2623def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2624                (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2625            (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
2626            Requires<[HasT2ExtractPack, IsThumb2]>;
2627
2628//===----------------------------------------------------------------------===//
2629//  Comparison Instructions...
2630//
2631defm t2CMP  : T2I_cmp_irs<0b1101, "cmp",
2632                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2633                          BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2634
2635def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_imm:$imm),
2636            (t2CMPri  GPR:$lhs, t2_so_imm:$imm)>;
2637def : T2Pat<(ARMcmpZ  GPR:$lhs, rGPR:$rhs),
2638            (t2CMPrr  GPR:$lhs, rGPR:$rhs)>;
2639def : T2Pat<(ARMcmpZ  GPR:$lhs, t2_so_reg:$rhs),
2640            (t2CMPrs  GPR:$lhs, t2_so_reg:$rhs)>;
2641
2642//FIXME: Disable CMN, as CCodes are backwards from compare expectations
2643//       Compare-to-zero still works out, just not the relationals
2644//defm t2CMN  : T2I_cmp_irs<0b1000, "cmn",
2645//                          BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2646defm t2CMNz : T2I_cmp_irs<0b1000, "cmn",
2647                          IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi,
2648                          BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2649
2650//def : T2Pat<(ARMcmp  GPR:$src, t2_so_imm_neg:$imm),
2651//            (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
2652
2653def : T2Pat<(ARMcmpZ  GPR:$src, t2_so_imm_neg:$imm),
2654            (t2CMNzri GPR:$src, t2_so_imm_neg:$imm)>;
2655
2656defm t2TST  : T2I_cmp_irs<0b0000, "tst",
2657                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2658                         BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>;
2659defm t2TEQ  : T2I_cmp_irs<0b0100, "teq",
2660                          IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi,
2661                         BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>;
2662
2663// Conditional moves
2664// FIXME: should be able to write a pattern for ARMcmov, but can't use
2665// a two-value operand where a dag node expects two operands. :(
2666let neverHasSideEffects = 1 in {
2667def t2MOVCCr : T2TwoReg<
2668                   (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
2669                   "mov", ".w\t$Rd, $Rm",
2670   [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2671                RegConstraint<"$false = $Rd"> {
2672  let Inst{31-27} = 0b11101;
2673  let Inst{26-25} = 0b01;
2674  let Inst{24-21} = 0b0010;
2675  let Inst{20} = 0; // The S bit.
2676  let Inst{19-16} = 0b1111; // Rn
2677  let Inst{14-12} = 0b000;
2678  let Inst{7-4} = 0b0000;
2679}
2680
2681// FIXME: Pseudo-ize these. For now, just mark codegen only.
2682let isCodeGenOnly = 1 in {
2683let isMoveImm = 1 in
2684def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2685                   IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
2686[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
2687                   RegConstraint<"$false = $Rd"> {
2688  let Inst{31-27} = 0b11110;
2689  let Inst{25} = 0;
2690  let Inst{24-21} = 0b0010;
2691  let Inst{20} = 0; // The S bit.
2692  let Inst{19-16} = 0b1111; // Rn
2693  let Inst{15} = 0;
2694}
2695
2696let isMoveImm = 1 in
2697def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
2698                      IIC_iCMOVi,
2699                      "movw", "\t$Rd, $imm", []>,
2700                      RegConstraint<"$false = $Rd"> {
2701  let Inst{31-27} = 0b11110;
2702  let Inst{25} = 1;
2703  let Inst{24-21} = 0b0010;
2704  let Inst{20} = 0; // The S bit.
2705  let Inst{15} = 0;
2706
2707  bits<4> Rd;
2708  bits<16> imm;
2709
2710  let Inst{11-8}  = Rd;
2711  let Inst{19-16} = imm{15-12};
2712  let Inst{26}    = imm{11};
2713  let Inst{14-12} = imm{10-8};
2714  let Inst{7-0}   = imm{7-0};
2715}
2716
2717let isMoveImm = 1 in
2718def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst),
2719                               (ins rGPR:$false, i32imm:$src, pred:$p),
2720                    IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">;
2721
2722let isMoveImm = 1 in
2723def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
2724                   IIC_iCMOVi, "mvn", ".w\t$Rd, $imm",
2725[/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm,
2726                   imm:$cc, CCR:$ccr))*/]>,
2727                   RegConstraint<"$false = $Rd"> {
2728  let Inst{31-27} = 0b11110;
2729  let Inst{25} = 0;
2730  let Inst{24-21} = 0b0011;
2731  let Inst{20} = 0; // The S bit.
2732  let Inst{19-16} = 0b1111; // Rn
2733  let Inst{15} = 0;
2734}
2735
2736class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
2737                   string opc, string asm, list<dag> pattern>
2738  : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> {
2739  let Inst{31-27} = 0b11101;
2740  let Inst{26-25} = 0b01;
2741  let Inst{24-21} = 0b0010;
2742  let Inst{20} = 0; // The S bit.
2743  let Inst{19-16} = 0b1111; // Rn
2744  let Inst{5-4} = opcod; // Shift type.
2745}
2746def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd),
2747                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2748                             IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>,
2749                 RegConstraint<"$false = $Rd">;
2750def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd),
2751                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2752                             IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>,
2753                 RegConstraint<"$false = $Rd">;
2754def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd),
2755                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2756                             IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>,
2757                 RegConstraint<"$false = $Rd">;
2758def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd),
2759                             (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
2760                             IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
2761                 RegConstraint<"$false = $Rd">;
2762} // neverHasSideEffects
2763} // isCodeGenOnly = 1
2764
2765//===----------------------------------------------------------------------===//
2766// Atomic operations intrinsics
2767//
2768
2769// memory barriers protect the atomic sequences
2770let hasSideEffects = 1 in {
2771def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2772                  "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
2773                  Requires<[IsThumb, HasDB]> {
2774  bits<4> opt;
2775  let Inst{31-4} = 0xf3bf8f5;
2776  let Inst{3-0} = opt;
2777}
2778}
2779
2780def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary,
2781                  "dsb", "\t$opt",
2782                  [/* For disassembly only; pattern left blank */]>,
2783                  Requires<[IsThumb, HasDB]> {
2784  bits<4> opt;
2785  let Inst{31-4} = 0xf3bf8f4;
2786  let Inst{3-0} = opt;
2787}
2788
2789// ISB has only full system option -- for disassembly only
2790def t2ISB : AInoP<(outs), (ins), ThumbFrm, NoItinerary, "isb", "",
2791                  [/* For disassembly only; pattern left blank */]>,
2792                  Requires<[IsThumb2, HasV7]> {
2793  let Inst{31-4} = 0xf3bf8f6;
2794  let Inst{3-0} = 0b1111;
2795}
2796
2797class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2798                InstrItinClass itin, string opc, string asm, string cstr,
2799                list<dag> pattern, bits<4> rt2 = 0b1111>
2800  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2801  let Inst{31-27} = 0b11101;
2802  let Inst{26-20} = 0b0001101;
2803  let Inst{11-8} = rt2;
2804  let Inst{7-6} = 0b01;
2805  let Inst{5-4} = opcod;
2806  let Inst{3-0} = 0b1111;
2807
2808  bits<4> addr;
2809  bits<4> Rt;
2810  let Inst{19-16} = addr;
2811  let Inst{15-12} = Rt;
2812}
2813class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
2814                InstrItinClass itin, string opc, string asm, string cstr,
2815                list<dag> pattern, bits<4> rt2 = 0b1111>
2816  : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> {
2817  let Inst{31-27} = 0b11101;
2818  let Inst{26-20} = 0b0001100;
2819  let Inst{11-8} = rt2;
2820  let Inst{7-6} = 0b01;
2821  let Inst{5-4} = opcod;
2822
2823  bits<4> Rd;
2824  bits<4> addr;
2825  bits<4> Rt;
2826  let Inst{3-0}  = Rd;
2827  let Inst{19-16} = addr;
2828  let Inst{15-12} = Rt;
2829}
2830
2831let mayLoad = 1 in {
2832def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2833                         AddrModeNone, Size4Bytes, NoItinerary,
2834                         "ldrexb", "\t$Rt, $addr", "", []>;
2835def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2836                         AddrModeNone, Size4Bytes, NoItinerary,
2837                         "ldrexh", "\t$Rt, $addr", "", []>;
2838def t2LDREX  : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_reg:$addr),
2839                       AddrModeNone, Size4Bytes, NoItinerary,
2840                       "ldrex", "\t$Rt, $addr", "", []> {
2841  let Inst{31-27} = 0b11101;
2842  let Inst{26-20} = 0b0000101;
2843  let Inst{11-8} = 0b1111;
2844  let Inst{7-0} = 0b00000000; // imm8 = 0
2845
2846  bits<4> Rt;
2847  bits<4> addr;
2848  let Inst{19-16} = addr;
2849  let Inst{15-12} = Rt;
2850}
2851let hasExtraDefRegAllocReq = 1 in
2852def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2),
2853                         (ins t2addrmode_reg:$addr),
2854                         AddrModeNone, Size4Bytes, NoItinerary,
2855                         "ldrexd", "\t$Rt, $Rt2, $addr", "",
2856                         [], {?, ?, ?, ?}> {
2857  bits<4> Rt2;
2858  let Inst{11-8} = Rt2;
2859}
2860}
2861
2862let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
2863def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd),
2864                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2865                         AddrModeNone, Size4Bytes, NoItinerary,
2866                         "strexb", "\t$Rd, $Rt, $addr", "", []>;
2867def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd),
2868                         (ins rGPR:$Rt, t2addrmode_reg:$addr),
2869                         AddrModeNone, Size4Bytes, NoItinerary,
2870                         "strexh", "\t$Rd, $Rt, $addr", "", []>;
2871def t2STREX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, t2addrmode_reg:$addr),
2872                  AddrModeNone, Size4Bytes, NoItinerary,
2873                  "strex", "\t$Rd, $Rt, $addr", "",
2874                  []> {
2875  let Inst{31-27} = 0b11101;
2876  let Inst{26-20} = 0b0000100;
2877  let Inst{7-0} = 0b00000000; // imm8 = 0
2878
2879  bits<4> Rd;
2880  bits<4> addr;
2881  bits<4> Rt;
2882  let Inst{11-8}  = Rd;
2883  let Inst{19-16} = addr;
2884  let Inst{15-12} = Rt;
2885}
2886}
2887
2888let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
2889def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
2890                         (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_reg:$addr),
2891                         AddrModeNone, Size4Bytes, NoItinerary,
2892                         "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
2893                         {?, ?, ?, ?}> {
2894  bits<4> Rt2;
2895  let Inst{11-8} = Rt2;
2896}
2897
2898// Clear-Exclusive is for disassembly only.
2899def t2CLREX : T2XI<(outs), (ins), NoItinerary, "clrex",
2900                   [/* For disassembly only; pattern left blank */]>,
2901            Requires<[IsThumb2, HasV7]>  {
2902  let Inst{31-16} = 0xf3bf;
2903  let Inst{15-14} = 0b10;
2904  let Inst{13} = 0;
2905  let Inst{12} = 0;
2906  let Inst{11-8} = 0b1111;
2907  let Inst{7-4} = 0b0010;
2908  let Inst{3-0} = 0b1111;
2909}
2910
2911//===----------------------------------------------------------------------===//
2912// SJLJ Exception handling intrinsics
2913//   eh_sjlj_setjmp() is an instruction sequence to store the return
2914//   address and save #0 in R0 for the non-longjmp case.
2915//   Since by its nature we may be coming from some other function to get
2916//   here, and we're using the stack frame for the containing function to
2917//   save/restore registers, we can't keep anything live in regs across
2918//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
2919//   when we get here from a longjmp(). We force everything out of registers
2920//   except for our own input by listing the relevant registers in Defs. By
2921//   doing so, we also cause the prologue/epilogue code to actively preserve
2922//   all of the callee-saved resgisters, which is exactly what we want.
2923//   $val is a scratch register for our use.
2924let Defs =
2925  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR,
2926    QQQQ0, QQQQ1, QQQQ2, QQQQ3 ],
2927  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2928  def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2929                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2930                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2931                             Requires<[IsThumb2, HasVFP2]>;
2932}
2933
2934let Defs =
2935  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10, R11, R12, LR, CPSR ],
2936  hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in {
2937  def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val),
2938                               AddrModeNone, SizeSpecial, NoItinerary, "", "",
2939                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>,
2940                                  Requires<[IsThumb2, NoVFP]>;
2941}
2942
2943
2944//===----------------------------------------------------------------------===//
2945// Control-Flow Instructions
2946//
2947
2948// FIXME: remove when we have a way to marking a MI with these properties.
2949// FIXME: Should pc be an implicit operand like PICADD, etc?
2950let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2951    hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2952def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2953                                                   reglist:$regs, variable_ops),
2954                              Size4Bytes, IIC_iLoad_mBr, []>,
2955                         RegConstraint<"$Rn = $wb">;
2956
2957let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
2958let isPredicable = 1 in
2959def t2B   : T2XI<(outs), (ins uncondbrtarget:$target), IIC_Br,
2960                 "b.w\t$target",
2961                 [(br bb:$target)]> {
2962  let Inst{31-27} = 0b11110;
2963  let Inst{15-14} = 0b10;
2964  let Inst{12} = 1;
2965
2966  bits<20> target;
2967  let Inst{26} = target{19};
2968  let Inst{11} = target{18};
2969  let Inst{13} = target{17};
2970  let Inst{21-16} = target{16-11};
2971  let Inst{10-0} = target{10-0};
2972}
2973
2974let isNotDuplicable = 1, isIndirectBranch = 1 in {
2975def t2BR_JT : t2PseudoInst<(outs),
2976          (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id),
2977           SizeSpecial, IIC_Br,
2978          [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
2979
2980// FIXME: Add a non-pc based case that can be predicated.
2981def t2TBB_JT : t2PseudoInst<(outs),
2982        (ins GPR:$index, i32imm:$jt, i32imm:$id),
2983         SizeSpecial, IIC_Br, []>;
2984
2985def t2TBH_JT : t2PseudoInst<(outs),
2986        (ins GPR:$index, i32imm:$jt, i32imm:$id),
2987         SizeSpecial, IIC_Br, []>;
2988
2989def t2TBB : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
2990                    "tbb", "\t[$Rn, $Rm]", []> {
2991  bits<4> Rn;
2992  bits<4> Rm;
2993  let Inst{31-20} = 0b111010001101;
2994  let Inst{19-16} = Rn;
2995  let Inst{15-5} = 0b11110000000;
2996  let Inst{4} = 0; // B form
2997  let Inst{3-0} = Rm;
2998}
2999
3000def t2TBH : T2I<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_Br,
3001                   "tbh", "\t[$Rn, $Rm, lsl #1]", []> {
3002  bits<4> Rn;
3003  bits<4> Rm;
3004  let Inst{31-20} = 0b111010001101;
3005  let Inst{19-16} = Rn;
3006  let Inst{15-5} = 0b11110000000;
3007  let Inst{4} = 1; // H form
3008  let Inst{3-0} = Rm;
3009}
3010} // isNotDuplicable, isIndirectBranch
3011
3012} // isBranch, isTerminator, isBarrier
3013
3014// FIXME: should be able to write a pattern for ARMBrcond, but can't use
3015// a two-value operand where a dag node expects two operands. :(
3016let isBranch = 1, isTerminator = 1 in
3017def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
3018                "b", ".w\t$target",
3019                [/*(ARMbrcond bb:$target, imm:$cc)*/]> {
3020  let Inst{31-27} = 0b11110;
3021  let Inst{15-14} = 0b10;
3022  let Inst{12} = 0;
3023
3024  bits<4> p;
3025  let Inst{25-22} = p;
3026
3027  bits<21> target;
3028  let Inst{26} = target{20};
3029  let Inst{11} = target{19};
3030  let Inst{13} = target{18};
3031  let Inst{21-16} = target{17-12};
3032  let Inst{10-0} = target{11-1};
3033}
3034
3035
3036// IT block
3037let Defs = [ITSTATE] in
3038def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
3039                    AddrModeNone, Size2Bytes,  IIC_iALUx,
3040                    "it$mask\t$cc", "", []> {
3041  // 16-bit instruction.
3042  let Inst{31-16} = 0x0000;
3043  let Inst{15-8} = 0b10111111;
3044
3045  bits<4> cc;
3046  bits<4> mask;
3047  let Inst{7-4} = cc;
3048  let Inst{3-0} = mask;
3049}
3050
3051// Branch and Exchange Jazelle -- for disassembly only
3052// Rm = Inst{19-16}
3053def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func",
3054              [/* For disassembly only; pattern left blank */]> {
3055  let Inst{31-27} = 0b11110;
3056  let Inst{26} = 0;
3057  let Inst{25-20} = 0b111100;
3058  let Inst{15-14} = 0b10;
3059  let Inst{12} = 0;
3060
3061  bits<4> func;
3062  let Inst{19-16} = func;
3063}
3064
3065// Change Processor State is a system instruction -- for disassembly and
3066// parsing only.
3067// FIXME: Since the asm parser has currently no clean way to handle optional
3068// operands, create 3 versions of the same instruction. Once there's a clean
3069// framework to represent optional operands, change this behavior.
3070class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
3071            !strconcat("cps", asm_op),
3072            [/* For disassembly only; pattern left blank */]> {
3073  bits<2> imod;
3074  bits<3> iflags;
3075  bits<5> mode;
3076  bit M;
3077
3078  let Inst{31-27} = 0b11110;
3079  let Inst{26}    = 0;
3080  let Inst{25-20} = 0b111010;
3081  let Inst{19-16} = 0b1111;
3082  let Inst{15-14} = 0b10;
3083  let Inst{12}    = 0;
3084  let Inst{10-9}  = imod;
3085  let Inst{8}     = M;
3086  let Inst{7-5}   = iflags;
3087  let Inst{4-0}   = mode;
3088}
3089
3090let M = 1 in
3091  def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3092                      "$imod.w\t$iflags, $mode">;
3093let mode = 0, M = 0 in
3094  def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags),
3095                      "$imod.w\t$iflags">;
3096let imod = 0, iflags = 0, M = 1 in
3097  def t2CPS1p : t2CPS<(ins i32imm:$mode), "\t$mode">;
3098
3099// A6.3.4 Branches and miscellaneous control
3100// Table A6-14 Change Processor State, and hint instructions
3101// Helper class for disassembly only.
3102class T2I_hint<bits<8> op7_0, string opc, string asm>
3103  : T2I<(outs), (ins), NoItinerary, opc, asm,
3104        [/* For disassembly only; pattern left blank */]> {
3105  let Inst{31-20} = 0xf3a;
3106  let Inst{19-16} = 0b1111;
3107  let Inst{15-14} = 0b10;
3108  let Inst{12} = 0;
3109  let Inst{10-8} = 0b000;
3110  let Inst{7-0} = op7_0;
3111}
3112
3113def t2NOP   : T2I_hint<0b00000000, "nop",   ".w">;
3114def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3115def t2WFE   : T2I_hint<0b00000010, "wfe",   ".w">;
3116def t2WFI   : T2I_hint<0b00000011, "wfi",   ".w">;
3117def t2SEV   : T2I_hint<0b00000100, "sev",   ".w">;
3118
3119def t2DBG : T2I<(outs),(ins i32imm:$opt), NoItinerary, "dbg", "\t$opt",
3120                [/* For disassembly only; pattern left blank */]> {
3121  let Inst{31-20} = 0xf3a;
3122  let Inst{15-14} = 0b10;
3123  let Inst{12} = 0;
3124  let Inst{10-8} = 0b000;
3125  let Inst{7-4} = 0b1111;
3126
3127  bits<4> opt;
3128  let Inst{3-0} = opt;
3129}
3130
3131// Secure Monitor Call is a system instruction -- for disassembly only
3132// Option = Inst{19-16}
3133def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
3134                [/* For disassembly only; pattern left blank */]> {
3135  let Inst{31-27} = 0b11110;
3136  let Inst{26-20} = 0b1111111;
3137  let Inst{15-12} = 0b1000;
3138
3139  bits<4> opt;
3140  let Inst{19-16} = opt;
3141}
3142
3143class T2SRS<bits<12> op31_20,
3144           dag oops, dag iops, InstrItinClass itin,
3145          string opc, string asm, list<dag> pattern>
3146  : T2I<oops, iops, itin, opc, asm, pattern> {
3147  let Inst{31-20} = op31_20{11-0};
3148
3149  bits<5> mode;
3150  let Inst{4-0} = mode{4-0};
3151}
3152
3153// Store Return State is a system instruction -- for disassembly only
3154def t2SRSDBW : T2SRS<0b111010000010,
3155                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp!, $mode",
3156                   [/* For disassembly only; pattern left blank */]>;
3157def t2SRSDB  : T2SRS<0b111010000000,
3158                   (outs),(ins i32imm:$mode),NoItinerary,"srsdb","\tsp, $mode",
3159                   [/* For disassembly only; pattern left blank */]>;
3160def t2SRSIAW : T2SRS<0b111010011010,
3161                   (outs),(ins i32imm:$mode),NoItinerary,"srsia","\tsp!, $mode",
3162                   [/* For disassembly only; pattern left blank */]>;
3163def t2SRSIA  : T2SRS<0b111010011000,
3164                   (outs), (ins i32imm:$mode),NoItinerary,"srsia","\tsp, $mode",
3165                   [/* For disassembly only; pattern left blank */]>;
3166
3167// Return From Exception is a system instruction -- for disassembly only
3168
3169class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin,
3170          string opc, string asm, list<dag> pattern>
3171  : T2I<oops, iops, itin, opc, asm, pattern> {
3172  let Inst{31-20} = op31_20{11-0};
3173
3174  bits<4> Rn;
3175  let Inst{19-16} = Rn;
3176  let Inst{15-0} = 0xc000;
3177}
3178
3179def t2RFEDBW : T2RFE<0b111010000011,
3180                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!",
3181                   [/* For disassembly only; pattern left blank */]>;
3182def t2RFEDB  : T2RFE<0b111010000001,
3183                   (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn",
3184                   [/* For disassembly only; pattern left blank */]>;
3185def t2RFEIAW : T2RFE<0b111010011011,
3186                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!",
3187                   [/* For disassembly only; pattern left blank */]>;
3188def t2RFEIA  : T2RFE<0b111010011001,
3189                   (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn",
3190                   [/* For disassembly only; pattern left blank */]>;
3191
3192//===----------------------------------------------------------------------===//
3193// Non-Instruction Patterns
3194//
3195
3196// 32-bit immediate using movw + movt.
3197// This is a single pseudo instruction to make it re-materializable.
3198// FIXME: Remove this when we can do generalized remat.
3199let isReMaterializable = 1, isMoveImm = 1 in
3200def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3201                            [(set rGPR:$dst, (i32 imm:$src))]>,
3202                            Requires<[IsThumb, HasV6T2]>;
3203
3204// Pseudo instruction that combines movw + movt + add pc (if pic).
3205// It also makes it possible to rematerialize the instructions.
3206// FIXME: Remove this when we can do generalized remat and when machine licm
3207// can properly the instructions.
3208let isReMaterializable = 1 in {
3209def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3210                                IIC_iMOVix2addpc,
3211                          [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3212                          Requires<[IsThumb2, UseMovt]>;
3213
3214def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
3215                              IIC_iMOVix2,
3216                          [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3217                          Requires<[IsThumb2, UseMovt]>;
3218}
3219
3220// ConstantPool, GlobalAddress, and JumpTable
3221def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>,
3222           Requires<[IsThumb2, DontUseMovt]>;
3223def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
3224def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
3225           Requires<[IsThumb2, UseMovt]>;
3226
3227def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3228            (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
3229
3230// Pseudo instruction that combines ldr from constpool and add pc. This should
3231// be expanded into two instructions late to allow if-conversion and
3232// scheduling.
3233let canFoldAsLoad = 1, isReMaterializable = 1 in
3234def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
3235                   IIC_iLoadiALU,
3236              [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
3237                                           imm:$cp))]>,
3238               Requires<[IsThumb2]>;
3239
3240//===----------------------------------------------------------------------===//
3241// Move between special register and ARM core register -- for disassembly only
3242//
3243
3244class T2SpecialReg<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3245          dag oops, dag iops, InstrItinClass itin,
3246          string opc, string asm, list<dag> pattern>
3247  : T2I<oops, iops, itin, opc, asm, pattern> {
3248  let Inst{31-20} = op31_20{11-0};
3249  let Inst{15-14} = op15_14{1-0};
3250  let Inst{12} = op12{0};
3251}
3252
3253class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
3254          dag oops, dag iops, InstrItinClass itin,
3255          string opc, string asm, list<dag> pattern>
3256  : T2SpecialReg<op31_20, op15_14, op12, oops, iops, itin, opc, asm, pattern> {
3257  bits<4> Rd;
3258  let Inst{11-8} = Rd;
3259  let Inst{19-16} = 0b1111;
3260}
3261
3262def t2MRS : T2MRS<0b111100111110, 0b10, 0,
3263                (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3264                [/* For disassembly only; pattern left blank */]>;
3265def t2MRSsys : T2MRS<0b111100111111, 0b10, 0,
3266                   (outs rGPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
3267                   [/* For disassembly only; pattern left blank */]>;
3268
3269// Move from ARM core register to Special Register
3270//
3271// No need to have both system and application versions, the encodings are the
3272// same and the assembly parser has no way to distinguish between them. The mask
3273// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3274// the mask with the fields to be accessed in the special register.
3275def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
3276                         0 /* op12 */, (outs), (ins msr_mask:$mask, rGPR:$Rn),
3277                         NoItinerary, "msr", "\t$mask, $Rn",
3278                         [/* For disassembly only; pattern left blank */]> {
3279  bits<5> mask;
3280  bits<4> Rn;
3281  let Inst{19-16} = Rn;
3282  let Inst{20}    = mask{4}; // R Bit
3283  let Inst{13}    = 0b0;
3284  let Inst{11-8}  = mask{3-0};
3285}
3286
3287//===----------------------------------------------------------------------===//
3288// Move between coprocessor and ARM core register -- for disassembly only
3289//
3290
3291class t2MovRCopro<string opc, bit direction, dag oops, dag iops,
3292                  list<dag> pattern>
3293  : T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3294          pattern> {
3295  let Inst{27-24} = 0b1110;
3296  let Inst{20} = direction;
3297  let Inst{4} = 1;
3298
3299  bits<4> Rt;
3300  bits<4> cop;
3301  bits<3> opc1;
3302  bits<3> opc2;
3303  bits<4> CRm;
3304  bits<4> CRn;
3305
3306  let Inst{15-12} = Rt;
3307  let Inst{11-8}  = cop;
3308  let Inst{23-21} = opc1;
3309  let Inst{7-5}   = opc2;
3310  let Inst{3-0}   = CRm;
3311  let Inst{19-16} = CRn;
3312}
3313
3314def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
3315             (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3316                          c_imm:$CRm, i32imm:$opc2),
3317             [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3318                            imm:$CRm, imm:$opc2)]>;
3319def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
3320             (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
3321                                  c_imm:$CRm, i32imm:$opc2), []>;
3322
3323def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3324                            imm:$CRm, imm:$opc2),
3325              (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3326
3327class t2MovRRCopro<string opc, bit direction,
3328                   list<dag> pattern = [/* For disassembly only */]>
3329  : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3330          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3331  let Inst{27-24} = 0b1100;
3332  let Inst{23-21} = 0b010;
3333  let Inst{20} = direction;
3334
3335  bits<4> Rt;
3336  bits<4> Rt2;
3337  bits<4> cop;
3338  bits<4> opc1;
3339  bits<4> CRm;
3340
3341  let Inst{15-12} = Rt;
3342  let Inst{19-16} = Rt2;
3343  let Inst{11-8}  = cop;
3344  let Inst{7-4}   = opc1;
3345  let Inst{3-0}   = CRm;
3346}
3347
3348def t2MCRR2 : t2MovRRCopro<"mcrr2",
3349                           0 /* from ARM core register to coprocessor */,
3350                           [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
3351                                           GPR:$Rt2, imm:$CRm)]>;
3352def t2MRRC2 : t2MovRRCopro<"mrrc2",
3353                           1 /* from coprocessor to ARM core register */>;
3354
3355//===----------------------------------------------------------------------===//
3356// Other Coprocessor Instructions.  For disassembly only.
3357//
3358
3359def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
3360                   c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3361                   "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3362                   [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3363                                  imm:$CRm, imm:$opc2)]> {
3364  let Inst{27-24} = 0b1110;
3365
3366  bits<4> opc1;
3367  bits<4> CRn;
3368  bits<4> CRd;
3369  bits<4> cop;
3370  bits<3> opc2;
3371  bits<4> CRm;
3372
3373  let Inst{3-0}   = CRm;
3374  let Inst{4}     = 0;
3375  let Inst{7-5}   = opc2;
3376  let Inst{11-8}  = cop;
3377  let Inst{15-12} = CRd;
3378  let Inst{19-16} = CRn;
3379  let Inst{23-20} = opc1;
3380}
3381