ARMInstrThumb2.td revision 81c102ba6639c807825b59df99ac41f3b14d191d
136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// 336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// The LLVM Compiler Infrastructure 436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// 536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// This file is distributed under the University of Illinois Open Source 636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// License. See LICENSE.TXT for details. 736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// 836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines//===----------------------------------------------------------------------===// 936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// 1036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// This file describes the Thumb2 instruction set. 1136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// 1236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines//===----------------------------------------------------------------------===// 1336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 1436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines// IT block predicate field 1536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesdef it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Shifted operands. No register controlled shifts for Thumb2. 25// Note: We do not support rrx shifted operands yet. 26def t2_so_reg : Operand<i32>, // reg imm 27 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 28 [shl,srl,sra,rotr]> { 29 let PrintMethod = "printT2SOOperand"; 30 let MIOperandInfo = (ops GPR, i32imm); 31} 32 33// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 34def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 35 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 36}]>; 37 38// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 39def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm - Match a 32-bit immediate operand, which is an 44// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 45// immediate splatted into multiple bytes of the word. t2_so_imm values are 46// represented in the imm field in the same 12-bit form that they are encoded 47// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 48// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 49def t2_so_imm : Operand<i32>, 50 PatLeaf<(imm), [{ 51 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 52}]>; 53 54// t2_so_imm_not - Match an immediate that is a complement 55// of a t2_so_imm. 56def t2_so_imm_not : Operand<i32>, 57 PatLeaf<(imm), [{ 58 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 59}], t2_so_imm_not_XFORM>; 60 61// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 62def t2_so_imm_neg : Operand<i32>, 63 PatLeaf<(imm), [{ 64 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 65}], t2_so_imm_neg_XFORM>; 66 67/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 68def imm1_31 : PatLeaf<(i32 imm), [{ 69 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 70}]>; 71 72/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 73def imm0_4095 : PatLeaf<(i32 imm), [{ 74 return (uint32_t)N->getZExtValue() < 4096; 75}]>; 76 77def imm0_4095_neg : PatLeaf<(i32 imm), [{ 78 return (uint32_t)(-N->getZExtValue()) < 4096; 79}], imm_neg_XFORM>; 80 81/// imm0_65535 predicate - True if the 32-bit immediate is in the range 82/// [0.65535]. 83def imm0_65535 : PatLeaf<(i32 imm), [{ 84 return (uint32_t)N->getZExtValue() < 65536; 85}]>; 86 87/// Split a 32-bit immediate into two 16 bit parts. 88def t2_lo16 : SDNodeXForm<imm, [{ 89 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, 90 MVT::i32); 91}]>; 92 93def t2_hi16 : SDNodeXForm<imm, [{ 94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 95}]>; 96 97def t2_lo16AllZero : PatLeaf<(i32 imm), [{ 98 // Returns true if all low 16-bits are 0. 99 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 100 }], t2_hi16>; 101 102 103// Define Thumb2 specific addressing modes. 104 105// t2addrmode_imm12 := reg + imm12 106def t2addrmode_imm12 : Operand<i32>, 107 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 108 let PrintMethod = "printT2AddrModeImm12Operand"; 109 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 110} 111 112// t2addrmode_imm8 := reg +/- imm8 113def t2addrmode_imm8 : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 115 let PrintMethod = "printT2AddrModeImm8Operand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119def t2am_imm8_offset : Operand<i32>, 120 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 121 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 122} 123 124// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 125def t2addrmode_imm8s4 : Operand<i32>, 126 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 127 let PrintMethod = "printT2AddrModeImm8s4Operand"; 128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 129} 130 131// t2addrmode_so_reg := reg + (reg << imm2) 132def t2addrmode_so_reg : Operand<i32>, 133 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 134 let PrintMethod = "printT2AddrModeSoRegOperand"; 135 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 136} 137 138 139//===----------------------------------------------------------------------===// 140// Multiclass helpers... 141// 142 143/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 144/// unary operation that produces a value. These are predicable and can be 145/// changed to modify CPSR. 146multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 147 // shifted imm 148 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 149 opc, " $dst, $src", 150 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 151 let isAsCheapAsAMove = Cheap; 152 let isReMaterializable = ReMat; 153 } 154 // register 155 def r : T2I<(outs GPR:$dst), (ins GPR:$src), 156 opc, " $dst, $src", 157 [(set GPR:$dst, (opnode GPR:$src))]>; 158 // shifted register 159 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), 160 opc, " $dst, $src", 161 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 162} 163 164/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 165// binary operation that produces a value. These are predicable and can be 166/// changed to modify CPSR. 167multiclass T2I_bin_irs<string opc, PatFrag opnode, bit Commutable = 0> { 168 // shifted imm 169 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 170 opc, " $dst, $lhs, $rhs", 171 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 172 // register 173 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 174 opc, " $dst, $lhs, $rhs", 175 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 176 let isCommutable = Commutable; 177 } 178 // shifted register 179 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 180 opc, " $dst, $lhs, $rhs", 181 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 182} 183 184/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 185/// reversed. It doesn't define the 'rr' form since it's handled by its 186/// T2I_bin_irs counterpart. 187multiclass T2I_rbin_is<string opc, PatFrag opnode> { 188 // shifted imm 189 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), 190 opc, " $dst, $rhs, $lhs", 191 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 192 // shifted register 193 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), 194 opc, " $dst, $rhs, $lhs", 195 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 196} 197 198/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 199/// instruction modifies the CPSR register. 200let Defs = [CPSR] in { 201multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 202 // shifted imm 203 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 204 !strconcat(opc, "s"), " $dst, $lhs, $rhs", 205 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 206 // register 207 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 208 !strconcat(opc, "s"), " $dst, $lhs, $rhs", 209 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 210 let isCommutable = Commutable; 211 } 212 // shifted register 213 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 214 !strconcat(opc, "s"), " $dst, $lhs, $rhs", 215 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 216} 217} 218 219/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 220/// patterns for a binary operation that produces a value. 221multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 222 // shifted imm 223 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 224 opc, " $dst, $lhs, $rhs", 225 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 226 // 12-bit imm 227 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 228 !strconcat(opc, "w"), " $dst, $lhs, $rhs", 229 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 230 // register 231 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 232 opc, " $dst, $lhs, $rhs", 233 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 234 let isCommutable = Commutable; 235 } 236 // shifted register 237 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 238 opc, " $dst, $lhs, $rhs", 239 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 240} 241 242/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 243/// binary operation that produces a value and use and define the carry bit. 244/// It's not predicable. 245let Uses = [CPSR] in { 246multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 247 // shifted imm 248 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 249 opc, " $dst, $lhs, $rhs", 250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 251 Requires<[IsThumb2, CarryDefIsUnused]>; 252 // register 253 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 254 opc, " $dst, $lhs, $rhs", 255 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 256 Requires<[IsThumb2, CarryDefIsUnused]> { 257 let isCommutable = Commutable; 258 } 259 // shifted register 260 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 261 opc, " $dst, $lhs, $rhs", 262 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 263 Requires<[IsThumb2, CarryDefIsUnused]>; 264 // Carry setting variants 265 // shifted imm 266 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 267 !strconcat(opc, "s $dst, $lhs, $rhs"), 268 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 269 Requires<[IsThumb2, CarryDefIsUsed]> { 270 let Defs = [CPSR]; 271 } 272 // register 273 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 274 !strconcat(opc, "s $dst, $lhs, $rhs"), 275 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 276 Requires<[IsThumb2, CarryDefIsUsed]> { 277 let Defs = [CPSR]; 278 let isCommutable = Commutable; 279 } 280 // shifted register 281 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 282 !strconcat(opc, "s $dst, $lhs, $rhs"), 283 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 284 Requires<[IsThumb2, CarryDefIsUsed]> { 285 let Defs = [CPSR]; 286 } 287} 288} 289 290/// T2I_rsc_is - Same as T2I_adde_sube_irs except the order of operands are 291/// reversed. It doesn't define the 'rr' form since it's handled by its 292/// T2I_adde_sube_irs counterpart. 293let Defs = [CPSR], Uses = [CPSR] in { 294multiclass T2I_rsc_is<string opc, PatFrag opnode> { 295 // shifted imm 296 def ri : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), 297 opc, " $dst, $rhs, $lhs", 298 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>, 299 Requires<[IsThumb2, CarryDefIsUnused]>; 300 // shifted register 301 def rs : T2sI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), 302 opc, " $dst, $rhs, $lhs", 303 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>, 304 Requires<[IsThumb2, CarryDefIsUnused]>; 305 // shifted imm 306 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), 307 !strconcat(opc, "s $dst, $rhs, $lhs"), 308 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>, 309 Requires<[IsThumb2, CarryDefIsUsed]> { 310 let Defs = [CPSR]; 311 } 312 // shifted register 313 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), 314 !strconcat(opc, "s $dst, $rhs, $lhs"), 315 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>, 316 Requires<[IsThumb2, CarryDefIsUsed]> { 317 let Defs = [CPSR]; 318 } 319} 320} 321 322/// T2I_rbin_s_is - Same as T2I_bin_s_irs except the order of operands are 323/// reversed. It doesn't define the 'rr' form since it's handled by its 324/// T2I_bin_s_irs counterpart. 325let Defs = [CPSR] in { 326multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 327 // shifted imm 328 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 329 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 330 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 331 // shifted register 332 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 333 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 334 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 335} 336} 337 338/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 339// rotate operation that produces a value. 340multiclass T2I_sh_ir<string opc, PatFrag opnode> { 341 // 5-bit imm 342 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 343 opc, " $dst, $lhs, $rhs", 344 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 345 // register 346 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 347 opc, " $dst, $lhs, $rhs", 348 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 349} 350 351/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 352/// patterns. Similar to T2I_bin_irs except the instruction does not produce 353/// a explicit result, only implicitly set CPSR. 354let Defs = [CPSR] in { 355multiclass T2I_cmp_is<string opc, PatFrag opnode> { 356 // shifted imm 357 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), 358 opc, " $lhs, $rhs", 359 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 360 // register 361 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), 362 opc, " $lhs, $rhs", 363 [(opnode GPR:$lhs, GPR:$rhs)]>; 364 // shifted register 365 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), 366 opc, " $lhs, $rhs", 367 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 368} 369} 370 371/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 372multiclass T2I_ld<string opc, PatFrag opnode> { 373 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), 374 opc, " $dst, $addr", 375 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 376 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), 377 opc, " $dst, $addr", 378 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 379 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), 380 opc, " $dst, $addr", 381 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 382 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), 383 opc, " $dst, $addr", 384 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; 385} 386 387/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 388multiclass T2I_st<string opc, PatFrag opnode> { 389 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), 390 opc, " $src, $addr", 391 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 392 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), 393 opc, " $src, $addr", 394 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 395 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), 396 opc, " $src, $addr", 397 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 398} 399 400/// T2I_picld - Defines the PIC load pattern. 401class T2I_picld<string opc, PatFrag opnode> : 402 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), 403 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr", 404 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 405 406/// T2I_picst - Defines the PIC store pattern. 407class T2I_picst<string opc, PatFrag opnode> : 408 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), 409 !strconcat("${addr:label}:\n\t", opc), " $src, $addr", 410 [(opnode GPR:$src, addrmodepc:$addr)]>; 411 412 413/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 414/// register and one whose operand is a register rotated by 8/16/24. 415multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 416 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), 417 opc, " $dst, $Src", 418 [(set GPR:$dst, (opnode GPR:$Src))]>; 419 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), 420 opc, " $dst, $Src, ror $rot", 421 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>; 422} 423 424/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 425/// register and one whose operand is a register rotated by 8/16/24. 426multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 427 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 428 opc, " $dst, $LHS, $RHS", 429 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 430 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 431 opc, " $dst, $LHS, $RHS, ror $rot", 432 [(set GPR:$dst, (opnode GPR:$LHS, 433 (rotr GPR:$RHS, rot_imm:$rot)))]>; 434} 435 436//===----------------------------------------------------------------------===// 437// Instructions 438//===----------------------------------------------------------------------===// 439 440//===----------------------------------------------------------------------===// 441// Miscellaneous Instructions. 442// 443 444let isNotDuplicable = 1 in 445def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), 446 "$cp:\n\tadd $dst, pc", 447 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; 448 449 450// LEApcrel - Load a pc-relative address into a register without offending the 451// assembler. 452def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), 453 "adr$p $dst, #$label", []>; 454 455def t2LEApcrelJT : T2XI<(outs GPR:$dst), 456 (ins i32imm:$label, i32imm:$id, pred:$p), 457 "adr$p $dst, #${label}_${id:no_hash}", []>; 458 459// ADD rd, sp, #so_imm 460def t2ADDrSPi : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), 461 "add $dst, $sp, $imm", 462 []>; 463 464// ADD rd, sp, #imm12 465def t2ADDrSPi12 : T2XI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$imm), 466 "addw $dst, $sp, $imm", 467 []>; 468 469def t2ADDrSPs : T2XI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), 470 "addw $dst, $sp, $rhs", 471 []>; 472 473 474//===----------------------------------------------------------------------===// 475// Load / store Instructions. 476// 477 478// Load 479let canFoldAsLoad = 1 in 480defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 481 482// Loads with zero extension 483defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 484defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 485 486// Loads with sign extension 487defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 488defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 489 490let mayLoad = 1 in { 491// Load doubleword 492def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), 493 "ldrd", " $dst, $addr", []>; 494def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), 495 "ldrd", " $dst, $addr", []>; 496} 497 498// zextload i1 -> zextload i8 499def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 500 (t2LDRBi12 t2addrmode_imm12:$addr)>; 501def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 502 (t2LDRBi8 t2addrmode_imm8:$addr)>; 503def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 504 (t2LDRBs t2addrmode_so_reg:$addr)>; 505def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 506 (t2LDRBpci tconstpool:$addr)>; 507 508// extload -> zextload 509// FIXME: Reduce the number of patterns by legalizing extload to zextload 510// earlier? 511def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 512 (t2LDRBi12 t2addrmode_imm12:$addr)>; 513def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 514 (t2LDRBi8 t2addrmode_imm8:$addr)>; 515def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 516 (t2LDRBs t2addrmode_so_reg:$addr)>; 517def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 518 (t2LDRBpci tconstpool:$addr)>; 519 520def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 521 (t2LDRBi12 t2addrmode_imm12:$addr)>; 522def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 523 (t2LDRBi8 t2addrmode_imm8:$addr)>; 524def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 525 (t2LDRBs t2addrmode_so_reg:$addr)>; 526def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 527 (t2LDRBpci tconstpool:$addr)>; 528 529def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 530 (t2LDRHi12 t2addrmode_imm12:$addr)>; 531def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 532 (t2LDRHi8 t2addrmode_imm8:$addr)>; 533def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 534 (t2LDRHs t2addrmode_so_reg:$addr)>; 535def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 536 (t2LDRHpci tconstpool:$addr)>; 537 538// Indexed loads 539let mayLoad = 1 in { 540def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 541 (ins t2addrmode_imm8:$addr), 542 AddrModeT2_i8, IndexModePre, 543 "ldr", " $dst, $addr!", "$addr.base = $base_wb", 544 []>; 545 546def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 547 (ins GPR:$base, t2am_imm8_offset:$offset), 548 AddrModeT2_i8, IndexModePost, 549 "ldr", " $dst, [$base], $offset", "$base = $base_wb", 550 []>; 551 552def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 553 (ins t2addrmode_imm8:$addr), 554 AddrModeT2_i8, IndexModePre, 555 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", 556 []>; 557def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 558 (ins GPR:$base, t2am_imm8_offset:$offset), 559 AddrModeT2_i8, IndexModePost, 560 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", 561 []>; 562 563def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 564 (ins t2addrmode_imm8:$addr), 565 AddrModeT2_i8, IndexModePre, 566 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", 567 []>; 568def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 569 (ins GPR:$base, t2am_imm8_offset:$offset), 570 AddrModeT2_i8, IndexModePost, 571 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", 572 []>; 573 574def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 575 (ins t2addrmode_imm8:$addr), 576 AddrModeT2_i8, IndexModePre, 577 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", 578 []>; 579def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 580 (ins GPR:$base, t2am_imm8_offset:$offset), 581 AddrModeT2_i8, IndexModePost, 582 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", 583 []>; 584 585def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 586 (ins t2addrmode_imm8:$addr), 587 AddrModeT2_i8, IndexModePre, 588 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", 589 []>; 590def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 591 (ins GPR:$base, t2am_imm8_offset:$offset), 592 AddrModeT2_i8, IndexModePost, 593 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", 594 []>; 595} 596 597// Store 598defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 599defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 600defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 601 602// Store doubleword 603let mayLoad = 1 in 604def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), 605 "strd", " $src, $addr", []>; 606 607// Indexed stores 608def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 609 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 610 AddrModeT2_i8, IndexModePre, 611 "str", " $src, [$base, $offset]!", "$base = $base_wb", 612 [(set GPR:$base_wb, 613 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 614 615def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 616 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 617 AddrModeT2_i8, IndexModePost, 618 "str", " $src, [$base], $offset", "$base = $base_wb", 619 [(set GPR:$base_wb, 620 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 621 622def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 623 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 624 AddrModeT2_i8, IndexModePre, 625 "strh", " $src, [$base, $offset]!", "$base = $base_wb", 626 [(set GPR:$base_wb, 627 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 628 629def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 630 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 631 AddrModeT2_i8, IndexModePost, 632 "strh", " $src, [$base], $offset", "$base = $base_wb", 633 [(set GPR:$base_wb, 634 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 635 636def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 637 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 638 AddrModeT2_i8, IndexModePre, 639 "strb", " $src, [$base, $offset]!", "$base = $base_wb", 640 [(set GPR:$base_wb, 641 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 642 643def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 644 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 645 AddrModeT2_i8, IndexModePost, 646 "strb", " $src, [$base], $offset", "$base = $base_wb", 647 [(set GPR:$base_wb, 648 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 649 650 651// Address computation and loads and stores in PIC mode. 652let isNotDuplicable = 1, AddedComplexity = 10 in { 653let canFoldAsLoad = 1 in 654def t2PICLDR : T2I_picld<"ldr", UnOpFrag<(load node:$Src)>>; 655 656def t2PICLDRH : T2I_picld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 657def t2PICLDRB : T2I_picld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 658def t2PICLDRSH : T2I_picld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 659def t2PICLDRSB : T2I_picld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 660 661def t2PICSTR : T2I_picst<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 662def t2PICSTRH : T2I_picst<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 663def t2PICSTRB : T2I_picst<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 664} // isNotDuplicable = 1, AddedComplexity = 10 665 666// FIXME: ldrd / strd pre / post variants 667 668//===----------------------------------------------------------------------===// 669// Load / store multiple Instructions. 670// 671 672let mayLoad = 1 in 673def t2LDM : T2XI<(outs), 674 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 675 "ldm${addr:submode}${p} $addr, $dst1", []>; 676 677let mayStore = 1 in 678def t2STM : T2XI<(outs), 679 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 680 "stm${addr:submode}${p} $addr, $src1", []>; 681 682//===----------------------------------------------------------------------===// 683// Move Instructions. 684// 685 686let neverHasSideEffects = 1 in 687def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), 688 "mov", " $dst, $src", []>; 689 690let isReMaterializable = 1, isAsCheapAsAMove = 1 in 691def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 692 "mov", " $dst, $src", 693 [(set GPR:$dst, t2_so_imm:$src)]>; 694 695let isReMaterializable = 1, isAsCheapAsAMove = 1 in 696def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), 697 "movw", " $dst, $src", 698 [(set GPR:$dst, imm0_65535:$src)]>; 699 700// FIXME: Also available in ARM mode. 701let Constraints = "$src = $dst" in 702def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), 703 "movt", " $dst, $imm", 704 [(set GPR:$dst, 705 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; 706 707//===----------------------------------------------------------------------===// 708// Extend Instructions. 709// 710 711// Sign extenders 712 713defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 714defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 715 716defm t2SXTAB : T2I_bin_rrot<"sxtab", 717 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 718defm t2SXTAH : T2I_bin_rrot<"sxtah", 719 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 720 721// TODO: SXT(A){B|H}16 722 723// Zero extenders 724 725let AddedComplexity = 16 in { 726defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 727defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 728defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 729 730def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 731 (t2UXTB16r_rot GPR:$Src, 24)>; 732def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 733 (t2UXTB16r_rot GPR:$Src, 8)>; 734 735defm t2UXTAB : T2I_bin_rrot<"uxtab", 736 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 737defm t2UXTAH : T2I_bin_rrot<"uxtah", 738 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 739} 740 741//===----------------------------------------------------------------------===// 742// Arithmetic Instructions. 743// 744 745defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 746defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 747 748// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 749defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 750defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 751 752defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 753defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 754 755// RSB, RSC 756defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 757defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 758defm t2RSC : T2I_rsc_is <"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>; 759 760// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 761def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 762 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 763def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 764 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 765 766 767//===----------------------------------------------------------------------===// 768// Shift and rotate Instructions. 769// 770 771defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 772defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 773defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 774defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 775 776def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), 777 "mov", " $dst, $src, rrx", 778 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 779 780//===----------------------------------------------------------------------===// 781// Bitwise Instructions. 782// 783 784defm t2AND : T2I_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 785defm t2ORR : T2I_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 786defm t2EOR : T2I_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 787 788defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 789 790let Constraints = "$src = $dst" in 791def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 792 "bfc", " $dst, $imm", 793 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 794 795// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 796 797defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 798 799// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 800let AddedComplexity = 1 in 801defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 802 803 804def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 805 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 806 807def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 808 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>; 809 810def : T2Pat<(t2_so_imm_not:$src), 811 (t2MVNi t2_so_imm_not:$src)>; 812 813//===----------------------------------------------------------------------===// 814// Multiply Instructions. 815// 816let isCommutable = 1 in 817def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 818 "mul", " $dst, $a, $b", 819 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 820 821def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 822 "mla", " $dst, $a, $b, $c", 823 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 824 825def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 826 "mls", " $dst, $a, $b, $c", 827 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 828 829// Extra precision multiplies with low / high results 830let neverHasSideEffects = 1 in { 831let isCommutable = 1 in { 832def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 833 "smull", " $ldst, $hdst, $a, $b", []>; 834 835def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 836 "umull", " $ldst, $hdst, $a, $b", []>; 837} 838 839// Multiply + accumulate 840def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 841 "smlal", " $ldst, $hdst, $a, $b", []>; 842 843def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 844 "umlal", " $ldst, $hdst, $a, $b", []>; 845 846def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 847 "umaal", " $ldst, $hdst, $a, $b", []>; 848} // neverHasSideEffects 849 850// Most significant word multiply 851def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 852 "smmul", " $dst, $a, $b", 853 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 854 855def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 856 "smmla", " $dst, $a, $b, $c", 857 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 858 859 860def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 861 "smmls", " $dst, $a, $b, $c", 862 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 863 864multiclass T2I_smul<string opc, PatFrag opnode> { 865 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 866 !strconcat(opc, "bb"), " $dst, $a, $b", 867 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 868 (sext_inreg GPR:$b, i16)))]>; 869 870 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 871 !strconcat(opc, "bt"), " $dst, $a, $b", 872 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 873 (sra GPR:$b, (i32 16))))]>; 874 875 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 876 !strconcat(opc, "tb"), " $dst, $a, $b", 877 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 878 (sext_inreg GPR:$b, i16)))]>; 879 880 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 881 !strconcat(opc, "tt"), " $dst, $a, $b", 882 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 883 (sra GPR:$b, (i32 16))))]>; 884 885 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 886 !strconcat(opc, "wb"), " $dst, $a, $b", 887 [(set GPR:$dst, (sra (opnode GPR:$a, 888 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 889 890 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 891 !strconcat(opc, "wt"), " $dst, $a, $b", 892 [(set GPR:$dst, (sra (opnode GPR:$a, 893 (sra GPR:$b, (i32 16))), (i32 16)))]>; 894} 895 896 897multiclass T2I_smla<string opc, PatFrag opnode> { 898 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 899 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 900 [(set GPR:$dst, (add GPR:$acc, 901 (opnode (sext_inreg GPR:$a, i16), 902 (sext_inreg GPR:$b, i16))))]>; 903 904 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 905 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 906 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 907 (sra GPR:$b, (i32 16)))))]>; 908 909 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 910 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 911 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 912 (sext_inreg GPR:$b, i16))))]>; 913 914 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 915 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 916 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 917 (sra GPR:$b, (i32 16)))))]>; 918 919 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 920 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 921 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 922 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 923 924 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 925 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 926 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 927 (sra GPR:$b, (i32 16))), (i32 16))))]>; 928} 929 930defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 931defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 932 933// TODO: Halfword multiple accumulate long: SMLAL<x><y> 934// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 935 936 937//===----------------------------------------------------------------------===// 938// Misc. Arithmetic Instructions. 939// 940 941def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), 942 "clz", " $dst, $src", 943 [(set GPR:$dst, (ctlz GPR:$src))]>; 944 945def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), 946 "rev", " $dst, $src", 947 [(set GPR:$dst, (bswap GPR:$src))]>; 948 949def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), 950 "rev16", " $dst, $src", 951 [(set GPR:$dst, 952 (or (and (srl GPR:$src, (i32 8)), 0xFF), 953 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 954 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 955 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 956 957def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), 958 "revsh", " $dst, $src", 959 [(set GPR:$dst, 960 (sext_inreg 961 (or (srl (and GPR:$src, 0xFFFF), (i32 8)), 962 (shl GPR:$src, (i32 8))), i16))]>; 963 964def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 965 "pkhbt", " $dst, $src1, $src2, LSL $shamt", 966 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 967 (and (shl GPR:$src2, (i32 imm:$shamt)), 968 0xFFFF0000)))]>; 969 970// Alternate cases for PKHBT where identities eliminate some nodes. 971def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 972 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 973def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 974 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 975 976def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 977 "pkhtb", " $dst, $src1, $src2, ASR $shamt", 978 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 979 (and (sra GPR:$src2, imm16_31:$shamt), 980 0xFFFF)))]>; 981 982// Alternate cases for PKHTB where identities eliminate some nodes. Note that 983// a shift amount of 0 is *not legal* here, it is PKHBT instead. 984def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 985 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 986def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 987 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 988 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 989 990//===----------------------------------------------------------------------===// 991// Comparison Instructions... 992// 993 994defm t2CMP : T2I_cmp_is<"cmp", 995 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 996defm t2CMPz : T2I_cmp_is<"cmp", 997 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 998 999defm t2CMN : T2I_cmp_is<"cmn", 1000 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 1001defm t2CMNz : T2I_cmp_is<"cmn", 1002 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 1003 1004def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 1005 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1006 1007def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 1008 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 1009 1010defm t2TST : T2I_cmp_is<"tst", 1011 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 1012defm t2TEQ : T2I_cmp_is<"teq", 1013 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 1014 1015// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 1016// Short range conditional branch. Looks awesome for loops. Need to figure 1017// out how to use this one. 1018 1019 1020// Conditional moves 1021// FIXME: should be able to write a pattern for ARMcmov, but can't use 1022// a two-value operand where a dag node expects two operands. :( 1023def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), 1024 "mov", " $dst, $true", 1025 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 1026 RegConstraint<"$false = $dst">; 1027 1028def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true), 1029 "mov", " $dst, $true", 1030[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 1031 RegConstraint<"$false = $dst">; 1032 1033def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 1034 "mov", " $dst, $true", 1035[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 1036 RegConstraint<"$false = $dst">; 1037 1038//===----------------------------------------------------------------------===// 1039// TLS Instructions 1040// 1041 1042// __aeabi_read_tp preserves the registers r1-r3. 1043let isCall = 1, 1044 Defs = [R0, R12, LR, CPSR] in { 1045 def t2TPsoft : T2XI<(outs), (ins), 1046 "bl __aeabi_read_tp", 1047 [(set R0, ARMthread_pointer)]>; 1048} 1049 1050//===----------------------------------------------------------------------===// 1051// Control-Flow Instructions 1052// 1053 1054// FIXME: remove when we have a way to marking a MI with these properties. 1055// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1056// operand list. 1057// FIXME: Should pc be an implicit operand like PICADD, etc? 1058let isReturn = 1, isTerminator = 1, mayLoad = 1 in 1059 def t2LDM_RET : T2XI<(outs), 1060 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 1061 "ldm${addr:submode}${p} $addr, $dst1", 1062 []>; 1063 1064// On non-Darwin platforms R9 is callee-saved. 1065let isCall = 1, 1066 Defs = [R0, R1, R2, R3, R12, LR, 1067 D0, D1, D2, D3, D4, D5, D6, D7, 1068 D16, D17, D18, D19, D20, D21, D22, D23, 1069 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in { 1070def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops), 1071 "bl ${func:call}", 1072 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; 1073 1074def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops), 1075 "blx $func", 1076 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>; 1077} 1078 1079// On Darwin R9 is call-clobbered. 1080let isCall = 1, 1081 Defs = [R0, R1, R2, R3, R9, R12, LR, 1082 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 1083def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops), 1084 "bl ${func:call}", 1085 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>; 1086 1087def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops), 1088 "blx $func", 1089 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>; 1090} 1091 1092let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1093let isPredicable = 1 in 1094def t2B : T2XI<(outs), (ins brtarget:$target), 1095 "b $target", 1096 [(br bb:$target)]>; 1097 1098let isNotDuplicable = 1, isIndirectBranch = 1 in { 1099def t2BR_JTr : T2JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), 1100 "mov pc, $target \n$jt", 1101 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; 1102 1103def t2BR_JTm : 1104 T2JTI<(outs), 1105 (ins t2addrmode_so_reg:$target, jtblock_operand:$jt, i32imm:$id), 1106 "ldr pc, $target \n$jt", 1107 [(ARMbrjt (i32 (load t2addrmode_so_reg:$target)), tjumptable:$jt, 1108 imm:$id)]>; 1109 1110def t2BR_JTadd : 1111 T2JTI<(outs), 1112 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id), 1113 "add pc, $target, $idx \n$jt", 1114 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, imm:$id)]>; 1115} // isNotDuplicate, isIndirectBranch 1116} // isBranch, isTerminator, isBarrier 1117 1118// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1119// a two-value operand where a dag node expects two operands. :( 1120let isBranch = 1, isTerminator = 1 in 1121def t2Bcc : T2I<(outs), (ins brtarget:$target), 1122 "b", " $target", 1123 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1124 1125 1126// IT block 1127def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1128 AddrModeNone, Size2Bytes, 1129 "it$mask $cc", "", []>; 1130 1131//===----------------------------------------------------------------------===// 1132// Non-Instruction Patterns 1133// 1134 1135// ConstantPool, GlobalAddress, and JumpTable 1136def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1137def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1138def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1139 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1140 1141// Large immediate handling. 1142 1143def : T2Pat<(i32 imm:$src), 1144 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>; 1145