ARMInstrThumb2.td revision 5657c01949dca6c012ac60d242d1a8d2ffdf5603
1//===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred : Operand<i32> { 16 let PrintMethod = "printPredicateOperand"; 17} 18 19// IT block condition mask 20def it_mask : Operand<i32> { 21 let PrintMethod = "printThumbITMask"; 22} 23 24// Table branch address 25def tb_addrmode : Operand<i32> { 26 let PrintMethod = "printTBAddrMode"; 27} 28 29// Shifted operands. No register controlled shifts for Thumb2. 30// Note: We do not support rrx shifted operands yet. 31def t2_so_reg : Operand<i32>, // reg imm 32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 33 [shl,srl,sra,rotr]> { 34 let PrintMethod = "printT2SOOperand"; 35 let MIOperandInfo = (ops GPR, i32imm); 36} 37 38// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 39def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 41}]>; 42 43// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 44def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 46}]>; 47 48// t2_so_imm - Match a 32-bit immediate operand, which is an 49// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 50// immediate splatted into multiple bytes of the word. t2_so_imm values are 51// represented in the imm field in the same 12-bit form that they are encoded 52// into t2_so_imm instructions: the 8-bit immediate is the least significant bits 53// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. 54def t2_so_imm : Operand<i32>, 55 PatLeaf<(imm), [{ 56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1; 57}]>; 58 59// t2_so_imm_not - Match an immediate that is a complement 60// of a t2_so_imm. 61def t2_so_imm_not : Operand<i32>, 62 PatLeaf<(imm), [{ 63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 64}], t2_so_imm_not_XFORM>; 65 66// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 67def t2_so_imm_neg : Operand<i32>, 68 PatLeaf<(imm), [{ 69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1; 70}], t2_so_imm_neg_XFORM>; 71 72/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31]. 73def imm1_31 : PatLeaf<(i32 imm), [{ 74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32; 75}]>; 76 77/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 78def imm0_4095 : PatLeaf<(i32 imm), [{ 79 return (uint32_t)N->getZExtValue() < 4096; 80}]>; 81 82def imm0_4095_neg : PatLeaf<(i32 imm), [{ 83 return (uint32_t)(-N->getZExtValue()) < 4096; 84}], imm_neg_XFORM>; 85 86/// imm0_65535 predicate - True if the 32-bit immediate is in the range 87/// [0.65535]. 88def imm0_65535 : PatLeaf<(i32 imm), [{ 89 return (uint32_t)N->getZExtValue() < 65536; 90}]>; 91 92/// Split a 32-bit immediate into two 16 bit parts. 93def t2_lo16 : SDNodeXForm<imm, [{ 94 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, 95 MVT::i32); 96}]>; 97 98def t2_hi16 : SDNodeXForm<imm, [{ 99 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); 100}]>; 101 102def t2_lo16AllZero : PatLeaf<(i32 imm), [{ 103 // Returns true if all low 16-bits are 0. 104 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 105 }], t2_hi16>; 106 107 108// Define Thumb2 specific addressing modes. 109 110// t2addrmode_imm12 := reg + imm12 111def t2addrmode_imm12 : Operand<i32>, 112 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 113 let PrintMethod = "printT2AddrModeImm12Operand"; 114 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 115} 116 117// t2addrmode_imm8 := reg - imm8 118def t2addrmode_imm8 : Operand<i32>, 119 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 120 let PrintMethod = "printT2AddrModeImm8Operand"; 121 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 122} 123 124def t2am_imm8_offset : Operand<i32>, 125 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{ 126 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 127} 128 129// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 130def t2addrmode_imm8s4 : Operand<i32>, 131 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> { 132 let PrintMethod = "printT2AddrModeImm8s4Operand"; 133 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 134} 135 136// t2addrmode_so_reg := reg + (reg << imm2) 137def t2addrmode_so_reg : Operand<i32>, 138 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 139 let PrintMethod = "printT2AddrModeSoRegOperand"; 140 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 141} 142 143 144//===----------------------------------------------------------------------===// 145// Multiclass helpers... 146// 147 148/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 149/// unary operation that produces a value. These are predicable and can be 150/// changed to modify CPSR. 151multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{ 152 // shifted imm 153 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 154 opc, " $dst, $src", 155 [(set GPR:$dst, (opnode t2_so_imm:$src))]> { 156 let isAsCheapAsAMove = Cheap; 157 let isReMaterializable = ReMat; 158 } 159 // register 160 def r : T2I<(outs GPR:$dst), (ins GPR:$src), 161 opc, ".w $dst, $src", 162 [(set GPR:$dst, (opnode GPR:$src))]>; 163 // shifted register 164 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), 165 opc, ".w $dst, $src", 166 [(set GPR:$dst, (opnode t2_so_reg:$src))]>; 167} 168 169/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 170// binary operation that produces a value. These are predicable and can be 171/// changed to modify CPSR. 172multiclass T2I_bin_irs<string opc, PatFrag opnode, 173 bit Commutable = 0, string wide =""> { 174 // shifted imm 175 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 176 opc, " $dst, $lhs, $rhs", 177 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 178 // register 179 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 180 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 181 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 182 let isCommutable = Commutable; 183 } 184 // shifted register 185 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 186 opc, !strconcat(wide, " $dst, $lhs, $rhs"), 187 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 188} 189 190/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 191// the ".w" prefix to indicate that they are wide. 192multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> : 193 T2I_bin_irs<opc, opnode, Commutable, ".w">; 194 195/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 196/// reversed. It doesn't define the 'rr' form since it's handled by its 197/// T2I_bin_irs counterpart. 198multiclass T2I_rbin_is<string opc, PatFrag opnode> { 199 // shifted imm 200 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), 201 opc, ".w $dst, $rhs, $lhs", 202 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 203 // shifted register 204 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), 205 opc, " $dst, $rhs, $lhs", 206 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 207} 208 209/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 210/// instruction modifies the CPSR register. 211let Defs = [CPSR] in { 212multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> { 213 // shifted imm 214 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 215 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 216 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 217 // register 218 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 219 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 220 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 221 let isCommutable = Commutable; 222 } 223 // shifted register 224 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 225 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs", 226 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 227} 228} 229 230/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 231/// patterns for a binary operation that produces a value. 232multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> { 233 // shifted imm 234 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 235 opc, ".w $dst, $lhs, $rhs", 236 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>; 237 // 12-bit imm 238 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 239 !strconcat(opc, "w"), " $dst, $lhs, $rhs", 240 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>; 241 // register 242 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 243 opc, ".w $dst, $lhs, $rhs", 244 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> { 245 let isCommutable = Commutable; 246 } 247 // shifted register 248 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 249 opc, ".w $dst, $lhs, $rhs", 250 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>; 251} 252 253/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 254/// binary operation that produces a value and use and define the carry bit. 255/// It's not predicable. 256let Uses = [CPSR] in { 257multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> { 258 // shifted imm 259 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 260 opc, " $dst, $lhs, $rhs", 261 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 262 Requires<[IsThumb2, CarryDefIsUnused]>; 263 // register 264 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 265 opc, ".w $dst, $lhs, $rhs", 266 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 267 Requires<[IsThumb2, CarryDefIsUnused]> { 268 let isCommutable = Commutable; 269 } 270 // shifted register 271 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 272 opc, ".w $dst, $lhs, $rhs", 273 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 274 Requires<[IsThumb2, CarryDefIsUnused]>; 275 // Carry setting variants 276 // shifted imm 277 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), 278 !strconcat(opc, "s $dst, $lhs, $rhs"), 279 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>, 280 Requires<[IsThumb2, CarryDefIsUsed]> { 281 let Defs = [CPSR]; 282 } 283 // register 284 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 285 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 286 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>, 287 Requires<[IsThumb2, CarryDefIsUsed]> { 288 let Defs = [CPSR]; 289 let isCommutable = Commutable; 290 } 291 // shifted register 292 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), 293 !strconcat(opc, "s.w $dst, $lhs, $rhs"), 294 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>, 295 Requires<[IsThumb2, CarryDefIsUsed]> { 296 let Defs = [CPSR]; 297 } 298} 299} 300 301/// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit. 302let Defs = [CPSR] in { 303multiclass T2I_rbin_s_is<string opc, PatFrag opnode> { 304 // shifted imm 305 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s), 306 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"), 307 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>; 308 // shifted register 309 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s), 310 !strconcat(opc, "${s} $dst, $rhs, $lhs"), 311 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>; 312} 313} 314 315/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 316// rotate operation that produces a value. 317multiclass T2I_sh_ir<string opc, PatFrag opnode> { 318 // 5-bit imm 319 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), 320 opc, ".w $dst, $lhs, $rhs", 321 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>; 322 // register 323 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 324 opc, ".w $dst, $lhs, $rhs", 325 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>; 326} 327 328/// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 329/// patterns. Similar to T2I_bin_irs except the instruction does not produce 330/// a explicit result, only implicitly set CPSR. 331let Defs = [CPSR] in { 332multiclass T2I_cmp_is<string opc, PatFrag opnode> { 333 // shifted imm 334 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), 335 opc, ".w $lhs, $rhs", 336 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>; 337 // register 338 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), 339 opc, ".w $lhs, $rhs", 340 [(opnode GPR:$lhs, GPR:$rhs)]>; 341 // shifted register 342 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), 343 opc, ".w $lhs, $rhs", 344 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>; 345} 346} 347 348/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 349multiclass T2I_ld<string opc, PatFrag opnode> { 350 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), 351 opc, ".w $dst, $addr", 352 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>; 353 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), 354 opc, " $dst, $addr", 355 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>; 356 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), 357 opc, ".w $dst, $addr", 358 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>; 359 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), 360 opc, ".w $dst, $addr", 361 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>; 362} 363 364/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 365multiclass T2I_st<string opc, PatFrag opnode> { 366 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), 367 opc, ".w $src, $addr", 368 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>; 369 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), 370 opc, " $src, $addr", 371 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>; 372 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), 373 opc, ".w $src, $addr", 374 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>; 375} 376 377/// T2I_picld - Defines the PIC load pattern. 378class T2I_picld<string opc, PatFrag opnode> : 379 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), 380 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr", 381 [(set GPR:$dst, (opnode addrmodepc:$addr))]>; 382 383/// T2I_picst - Defines the PIC store pattern. 384class T2I_picst<string opc, PatFrag opnode> : 385 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), 386 !strconcat("${addr:label}:\n\t", opc), " $src, $addr", 387 [(opnode GPR:$src, addrmodepc:$addr)]>; 388 389 390/// T2I_unary_rrot - A unary operation with two forms: one whose operand is a 391/// register and one whose operand is a register rotated by 8/16/24. 392multiclass T2I_unary_rrot<string opc, PatFrag opnode> { 393 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), 394 opc, ".w $dst, $Src", 395 [(set GPR:$dst, (opnode GPR:$Src))]>; 396 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), 397 opc, ".w $dst, $Src, ror $rot", 398 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>; 399} 400 401/// T2I_bin_rrot - A binary operation with two forms: one whose operand is a 402/// register and one whose operand is a register rotated by 8/16/24. 403multiclass T2I_bin_rrot<string opc, PatFrag opnode> { 404 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), 405 opc, " $dst, $LHS, $RHS", 406 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>; 407 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), 408 opc, " $dst, $LHS, $RHS, ror $rot", 409 [(set GPR:$dst, (opnode GPR:$LHS, 410 (rotr GPR:$RHS, rot_imm:$rot)))]>; 411} 412 413//===----------------------------------------------------------------------===// 414// Instructions 415//===----------------------------------------------------------------------===// 416 417//===----------------------------------------------------------------------===// 418// Miscellaneous Instructions. 419// 420 421let isNotDuplicable = 1 in 422def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), 423 "$cp:\n\tadd.w $dst, $lhs, pc", 424 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>; 425 426 427// LEApcrel - Load a pc-relative address into a register without offending the 428// assembler. 429def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), 430 "adr$p.w $dst, #$label", []>; 431 432def t2LEApcrelJT : T2XI<(outs GPR:$dst), 433 (ins i32imm:$label, i32imm:$id, pred:$p), 434 "adr$p.w $dst, #${label}_${id:no_hash}", []>; 435 436//===----------------------------------------------------------------------===// 437// Load / store Instructions. 438// 439 440// Load 441let canFoldAsLoad = 1 in 442defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>; 443 444// Loads with zero extension 445defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>; 446defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>; 447 448// Loads with sign extension 449defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>; 450defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>; 451 452let mayLoad = 1 in { 453// Load doubleword 454def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr), 455 "ldrd", " $dst, $addr", []>; 456def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), 457 "ldrd", " $dst, $addr", []>; 458} 459 460// zextload i1 -> zextload i8 461def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 462 (t2LDRBi12 t2addrmode_imm12:$addr)>; 463def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr), 464 (t2LDRBi8 t2addrmode_imm8:$addr)>; 465def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 466 (t2LDRBs t2addrmode_so_reg:$addr)>; 467def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 468 (t2LDRBpci tconstpool:$addr)>; 469 470// extload -> zextload 471// FIXME: Reduce the number of patterns by legalizing extload to zextload 472// earlier? 473def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 474 (t2LDRBi12 t2addrmode_imm12:$addr)>; 475def : T2Pat<(extloadi1 t2addrmode_imm8:$addr), 476 (t2LDRBi8 t2addrmode_imm8:$addr)>; 477def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 478 (t2LDRBs t2addrmode_so_reg:$addr)>; 479def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 480 (t2LDRBpci tconstpool:$addr)>; 481 482def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 483 (t2LDRBi12 t2addrmode_imm12:$addr)>; 484def : T2Pat<(extloadi8 t2addrmode_imm8:$addr), 485 (t2LDRBi8 t2addrmode_imm8:$addr)>; 486def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 487 (t2LDRBs t2addrmode_so_reg:$addr)>; 488def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 489 (t2LDRBpci tconstpool:$addr)>; 490 491def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 492 (t2LDRHi12 t2addrmode_imm12:$addr)>; 493def : T2Pat<(extloadi16 t2addrmode_imm8:$addr), 494 (t2LDRHi8 t2addrmode_imm8:$addr)>; 495def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 496 (t2LDRHs t2addrmode_so_reg:$addr)>; 497def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 498 (t2LDRHpci tconstpool:$addr)>; 499 500// Indexed loads 501let mayLoad = 1 in { 502def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 503 (ins t2addrmode_imm8:$addr), 504 AddrModeT2_i8, IndexModePre, 505 "ldr", " $dst, $addr!", "$addr.base = $base_wb", 506 []>; 507 508def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 509 (ins GPR:$base, t2am_imm8_offset:$offset), 510 AddrModeT2_i8, IndexModePost, 511 "ldr", " $dst, [$base], $offset", "$base = $base_wb", 512 []>; 513 514def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 515 (ins t2addrmode_imm8:$addr), 516 AddrModeT2_i8, IndexModePre, 517 "ldrb", " $dst, $addr!", "$addr.base = $base_wb", 518 []>; 519def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 520 (ins GPR:$base, t2am_imm8_offset:$offset), 521 AddrModeT2_i8, IndexModePost, 522 "ldrb", " $dst, [$base], $offset", "$base = $base_wb", 523 []>; 524 525def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 526 (ins t2addrmode_imm8:$addr), 527 AddrModeT2_i8, IndexModePre, 528 "ldrh", " $dst, $addr!", "$addr.base = $base_wb", 529 []>; 530def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 531 (ins GPR:$base, t2am_imm8_offset:$offset), 532 AddrModeT2_i8, IndexModePost, 533 "ldrh", " $dst, [$base], $offset", "$base = $base_wb", 534 []>; 535 536def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 537 (ins t2addrmode_imm8:$addr), 538 AddrModeT2_i8, IndexModePre, 539 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb", 540 []>; 541def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 542 (ins GPR:$base, t2am_imm8_offset:$offset), 543 AddrModeT2_i8, IndexModePost, 544 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb", 545 []>; 546 547def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 548 (ins t2addrmode_imm8:$addr), 549 AddrModeT2_i8, IndexModePre, 550 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb", 551 []>; 552def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb), 553 (ins GPR:$base, t2am_imm8_offset:$offset), 554 AddrModeT2_i8, IndexModePost, 555 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb", 556 []>; 557} 558 559// Store 560defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>; 561defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 562defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 563 564// Store doubleword 565let mayLoad = 1 in 566def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr), 567 "strd", " $src, $addr", []>; 568 569// Indexed stores 570def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb), 571 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 572 AddrModeT2_i8, IndexModePre, 573 "str", " $src, [$base, $offset]!", "$base = $base_wb", 574 [(set GPR:$base_wb, 575 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 576 577def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb), 578 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 579 AddrModeT2_i8, IndexModePost, 580 "str", " $src, [$base], $offset", "$base = $base_wb", 581 [(set GPR:$base_wb, 582 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 583 584def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb), 585 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 586 AddrModeT2_i8, IndexModePre, 587 "strh", " $src, [$base, $offset]!", "$base = $base_wb", 588 [(set GPR:$base_wb, 589 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 590 591def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb), 592 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 593 AddrModeT2_i8, IndexModePost, 594 "strh", " $src, [$base], $offset", "$base = $base_wb", 595 [(set GPR:$base_wb, 596 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 597 598def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb), 599 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 600 AddrModeT2_i8, IndexModePre, 601 "strb", " $src, [$base, $offset]!", "$base = $base_wb", 602 [(set GPR:$base_wb, 603 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 604 605def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb), 606 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset), 607 AddrModeT2_i8, IndexModePost, 608 "strb", " $src, [$base], $offset", "$base = $base_wb", 609 [(set GPR:$base_wb, 610 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>; 611 612 613// FIXME: ldrd / strd pre / post variants 614 615//===----------------------------------------------------------------------===// 616// Load / store multiple Instructions. 617// 618 619let mayLoad = 1 in 620def t2LDM : T2XI<(outs), 621 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 622 "ldm${addr:submode}${p}.w $addr, $dst1", []>; 623 624let mayStore = 1 in 625def t2STM : T2XI<(outs), 626 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), 627 "stm${addr:submode}${p}.w $addr, $src1", []>; 628 629//===----------------------------------------------------------------------===// 630// Move Instructions. 631// 632 633let neverHasSideEffects = 1 in 634def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), 635 "mov", ".w $dst, $src", []>; 636 637let isReMaterializable = 1, isAsCheapAsAMove = 1 in 638def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), 639 "mov", ".w $dst, $src", 640 [(set GPR:$dst, t2_so_imm:$src)]>; 641 642let isReMaterializable = 1, isAsCheapAsAMove = 1 in 643def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), 644 "movw", " $dst, $src", 645 [(set GPR:$dst, imm0_65535:$src)]>; 646 647// FIXME: Also available in ARM mode. 648let Constraints = "$src = $dst" in 649def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), 650 "movt", " $dst, $imm", 651 [(set GPR:$dst, 652 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>; 653 654//===----------------------------------------------------------------------===// 655// Extend Instructions. 656// 657 658// Sign extenders 659 660defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 661defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 662 663defm t2SXTAB : T2I_bin_rrot<"sxtab", 664 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 665defm t2SXTAH : T2I_bin_rrot<"sxtah", 666 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 667 668// TODO: SXT(A){B|H}16 669 670// Zero extenders 671 672let AddedComplexity = 16 in { 673defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 674defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 675defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 676 677def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 678 (t2UXTB16r_rot GPR:$Src, 24)>; 679def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 680 (t2UXTB16r_rot GPR:$Src, 8)>; 681 682defm t2UXTAB : T2I_bin_rrot<"uxtab", 683 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 684defm t2UXTAH : T2I_bin_rrot<"uxtah", 685 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 686} 687 688//===----------------------------------------------------------------------===// 689// Arithmetic Instructions. 690// 691 692defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 693defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 694 695// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 696defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>; 697defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 698 699defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>; 700defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>; 701 702// RSB 703defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>; 704defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>; 705 706// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 707def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 708 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 709def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 710 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 711 712 713//===----------------------------------------------------------------------===// 714// Shift and rotate Instructions. 715// 716 717defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>; 718defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>; 719defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>; 720defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>; 721 722// FIXME should be "rrx $dst,$src" once <rdar://problem/7098328> is fixed 723def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), 724 "mov", ".w $dst, $src, rrx", 725 [(set GPR:$dst, (ARMrrx GPR:$src))]>; 726 727let Defs = [CPSR] in { 728def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), 729 "lsrs.w $dst, $src, #1", 730 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>; 731def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), 732 "asrs.w $dst, $src, #1", 733 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>; 734} 735 736//===----------------------------------------------------------------------===// 737// Bitwise Instructions. 738// 739 740defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; 741defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; 742defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; 743 744defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 745 746let Constraints = "$src = $dst" in 747def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), 748 "bfc", " $dst, $imm", 749 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>; 750 751// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1) 752 753// FIXME workaround for <rdar://problem/7096522> 754//defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>; 755 756// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 757let AddedComplexity = 1 in 758defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>; 759 760 761def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm), 762 (t2BICri GPR:$src, t2_so_imm_not:$imm)>; 763 764// FIXME workaround for <rdar://problem/7096522> 765//def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm), 766// (t2ORNri GPR:$src, t2_so_imm_not:$imm)>; 767 768def : T2Pat<(t2_so_imm_not:$src), 769 (t2MVNi t2_so_imm_not:$src)>; 770 771//===----------------------------------------------------------------------===// 772// Multiply Instructions. 773// 774let isCommutable = 1 in 775def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 776 "mul", " $dst, $a, $b", 777 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>; 778 779def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 780 "mla", " $dst, $a, $b, $c", 781 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>; 782 783def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 784 "mls", " $dst, $a, $b, $c", 785 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>; 786 787// Extra precision multiplies with low / high results 788let neverHasSideEffects = 1 in { 789let isCommutable = 1 in { 790def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 791 "smull", " $ldst, $hdst, $a, $b", []>; 792 793def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 794 "umull", " $ldst, $hdst, $a, $b", []>; 795} 796 797// Multiply + accumulate 798def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 799 "smlal", " $ldst, $hdst, $a, $b", []>; 800 801def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 802 "umlal", " $ldst, $hdst, $a, $b", []>; 803 804def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), 805 "umaal", " $ldst, $hdst, $a, $b", []>; 806} // neverHasSideEffects 807 808// Most significant word multiply 809def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 810 "smmul", " $dst, $a, $b", 811 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>; 812 813def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 814 "smmla", " $dst, $a, $b, $c", 815 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>; 816 817 818def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), 819 "smmls", " $dst, $a, $b, $c", 820 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>; 821 822multiclass T2I_smul<string opc, PatFrag opnode> { 823 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 824 !strconcat(opc, "bb"), " $dst, $a, $b", 825 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 826 (sext_inreg GPR:$b, i16)))]>; 827 828 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 829 !strconcat(opc, "bt"), " $dst, $a, $b", 830 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16), 831 (sra GPR:$b, (i32 16))))]>; 832 833 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 834 !strconcat(opc, "tb"), " $dst, $a, $b", 835 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 836 (sext_inreg GPR:$b, i16)))]>; 837 838 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 839 !strconcat(opc, "tt"), " $dst, $a, $b", 840 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)), 841 (sra GPR:$b, (i32 16))))]>; 842 843 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 844 !strconcat(opc, "wb"), " $dst, $a, $b", 845 [(set GPR:$dst, (sra (opnode GPR:$a, 846 (sext_inreg GPR:$b, i16)), (i32 16)))]>; 847 848 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), 849 !strconcat(opc, "wt"), " $dst, $a, $b", 850 [(set GPR:$dst, (sra (opnode GPR:$a, 851 (sra GPR:$b, (i32 16))), (i32 16)))]>; 852} 853 854 855multiclass T2I_smla<string opc, PatFrag opnode> { 856 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 857 !strconcat(opc, "bb"), " $dst, $a, $b, $acc", 858 [(set GPR:$dst, (add GPR:$acc, 859 (opnode (sext_inreg GPR:$a, i16), 860 (sext_inreg GPR:$b, i16))))]>; 861 862 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 863 !strconcat(opc, "bt"), " $dst, $a, $b, $acc", 864 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16), 865 (sra GPR:$b, (i32 16)))))]>; 866 867 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 868 !strconcat(opc, "tb"), " $dst, $a, $b, $acc", 869 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 870 (sext_inreg GPR:$b, i16))))]>; 871 872 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 873 !strconcat(opc, "tt"), " $dst, $a, $b, $acc", 874 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)), 875 (sra GPR:$b, (i32 16)))))]>; 876 877 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 878 !strconcat(opc, "wb"), " $dst, $a, $b, $acc", 879 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 880 (sext_inreg GPR:$b, i16)), (i32 16))))]>; 881 882 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), 883 !strconcat(opc, "wt"), " $dst, $a, $b, $acc", 884 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a, 885 (sra GPR:$b, (i32 16))), (i32 16))))]>; 886} 887 888defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 889defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 890 891// TODO: Halfword multiple accumulate long: SMLAL<x><y> 892// TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 893 894 895//===----------------------------------------------------------------------===// 896// Misc. Arithmetic Instructions. 897// 898 899def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), 900 "clz", " $dst, $src", 901 [(set GPR:$dst, (ctlz GPR:$src))]>; 902 903def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), 904 "rev", ".w $dst, $src", 905 [(set GPR:$dst, (bswap GPR:$src))]>; 906 907def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), 908 "rev16", ".w $dst, $src", 909 [(set GPR:$dst, 910 (or (and (srl GPR:$src, (i32 8)), 0xFF), 911 (or (and (shl GPR:$src, (i32 8)), 0xFF00), 912 (or (and (srl GPR:$src, (i32 8)), 0xFF0000), 913 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>; 914 915def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), 916 "revsh", ".w $dst, $src", 917 [(set GPR:$dst, 918 (sext_inreg 919 (or (srl (and GPR:$src, 0xFFFF), (i32 8)), 920 (shl GPR:$src, (i32 8))), i16))]>; 921 922def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 923 "pkhbt", " $dst, $src1, $src2, LSL $shamt", 924 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), 925 (and (shl GPR:$src2, (i32 imm:$shamt)), 926 0xFFFF0000)))]>; 927 928// Alternate cases for PKHBT where identities eliminate some nodes. 929def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), 930 (t2PKHBT GPR:$src1, GPR:$src2, 0)>; 931def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), 932 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; 933 934def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), 935 "pkhtb", " $dst, $src1, $src2, ASR $shamt", 936 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), 937 (and (sra GPR:$src2, imm16_31:$shamt), 938 0xFFFF)))]>; 939 940// Alternate cases for PKHTB where identities eliminate some nodes. Note that 941// a shift amount of 0 is *not legal* here, it is PKHBT instead. 942def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), 943 (t2PKHTB GPR:$src1, GPR:$src2, 16)>; 944def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), 945 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), 946 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>; 947 948//===----------------------------------------------------------------------===// 949// Comparison Instructions... 950// 951 952defm t2CMP : T2I_cmp_is<"cmp", 953 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>; 954defm t2CMPz : T2I_cmp_is<"cmp", 955 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>; 956 957defm t2CMN : T2I_cmp_is<"cmn", 958 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 959defm t2CMNz : T2I_cmp_is<"cmn", 960 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>; 961 962def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 963 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 964 965def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm), 966 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 967 968defm t2TST : T2I_cmp_is<"tst", 969 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>; 970defm t2TEQ : T2I_cmp_is<"teq", 971 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>; 972 973// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero. 974// Short range conditional branch. Looks awesome for loops. Need to figure 975// out how to use this one. 976 977 978// Conditional moves 979// FIXME: should be able to write a pattern for ARMcmov, but can't use 980// a two-value operand where a dag node expects two operands. :( 981def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), 982 "mov", " $dst, $true", 983 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, 984 RegConstraint<"$false = $dst">; 985 986def t2MOVCCs : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_reg:$true), 987 "mov", " $dst, $true", 988[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_reg:$true, imm:$cc, CCR:$ccr))*/]>, 989 RegConstraint<"$false = $dst">; 990 991def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), 992 "mov", " $dst, $true", 993[/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>, 994 RegConstraint<"$false = $dst">; 995 996//===----------------------------------------------------------------------===// 997// TLS Instructions 998// 999 1000// __aeabi_read_tp preserves the registers r1-r3. 1001let isCall = 1, 1002 Defs = [R0, R12, LR, CPSR] in { 1003 def t2TPsoft : T2XI<(outs), (ins), 1004 "bl __aeabi_read_tp", 1005 [(set R0, ARMthread_pointer)]>; 1006} 1007 1008//===----------------------------------------------------------------------===// 1009// Control-Flow Instructions 1010// 1011 1012// FIXME: remove when we have a way to marking a MI with these properties. 1013// FIXME: $dst1 should be a def. But the extra ops must be in the end of the 1014// operand list. 1015// FIXME: Should pc be an implicit operand like PICADD, etc? 1016let isReturn = 1, isTerminator = 1, mayLoad = 1 in 1017 def t2LDM_RET : T2XI<(outs), 1018 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), 1019 "ldm${addr:submode}${p} $addr, $dst1", 1020 []>; 1021 1022// On non-Darwin platforms R9 is callee-saved. 1023let isCall = 1, 1024 Defs = [R0, R1, R2, R3, R12, LR, 1025 D0, D1, D2, D3, D4, D5, D6, D7, 1026 D16, D17, D18, D19, D20, D21, D22, D23, 1027 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in { 1028def t2BL : T2XI<(outs), (ins i32imm:$func, variable_ops), 1029 "bl ${func:call}", 1030 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>; 1031 1032def t2BLX : T2XI<(outs), (ins GPR:$func, variable_ops), 1033 "blx $func", 1034 [(ARMcall GPR:$func)]>, Requires<[IsNotDarwin]>; 1035} 1036 1037// On Darwin R9 is call-clobbered. 1038let isCall = 1, 1039 Defs = [R0, R1, R2, R3, R9, R12, LR, 1040 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { 1041def t2BLr9 : T2XI<(outs), (ins i32imm:$func, variable_ops), 1042 "bl ${func:call}", 1043 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>; 1044 1045def t2BLXr9 : T2XI<(outs), (ins GPR:$func, variable_ops), 1046 "blx $func", 1047 [(ARMcall GPR:$func)]>, Requires<[IsDarwin]>; 1048} 1049 1050let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 1051let isPredicable = 1 in 1052def t2B : T2XI<(outs), (ins brtarget:$target), 1053 "b.w $target", 1054 [(br bb:$target)]>; 1055 1056let isNotDuplicable = 1, isIndirectBranch = 1 in { 1057def t2BR_JT : 1058 T2JTI<(outs), 1059 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id), 1060 "mov pc, $target\n$jt", 1061 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 1062 1063def t2TBB : 1064 T2I<(outs), 1065 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1066 "tbb", " $index\n$jt", []>; 1067 1068def t2TBH : 1069 T2I<(outs), 1070 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id), 1071 "tbh", " $index\n$jt", []>; 1072} // isNotDuplicable, isIndirectBranch 1073 1074} // isBranch, isTerminator, isBarrier 1075 1076// FIXME: should be able to write a pattern for ARMBrcond, but can't use 1077// a two-value operand where a dag node expects two operands. :( 1078let isBranch = 1, isTerminator = 1 in 1079def t2Bcc : T2I<(outs), (ins brtarget:$target), 1080 "b", ".w $target", 1081 [/*(ARMbrcond bb:$target, imm:$cc)*/]>; 1082 1083 1084// IT block 1085def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 1086 AddrModeNone, Size2Bytes, 1087 "it$mask $cc", "", []>; 1088 1089//===----------------------------------------------------------------------===// 1090// Non-Instruction Patterns 1091// 1092 1093// ConstantPool, GlobalAddress, and JumpTable 1094def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>; 1095def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 1096def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1097 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 1098 1099// Large immediate handling. 1100 1101def : T2Pat<(i32 imm:$src), 1102 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>; 1103