1//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCDisassembler.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMBaseInfo.h"
13#include "MCTargetDesc/ARMMCExpr.h"
14#include "llvm/MC/MCContext.h"
15#include "llvm/MC/MCExpr.h"
16#include "llvm/MC/MCFixedLenDisassembler.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCInstrDesc.h"
19#include "llvm/MC/MCSubtargetInfo.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/Support/ErrorHandling.h"
22#include "llvm/Support/LEB128.h"
23#include "llvm/Support/TargetRegistry.h"
24#include "llvm/Support/raw_ostream.h"
25#include <vector>
26
27using namespace llvm;
28
29#define DEBUG_TYPE "arm-disassembler"
30
31typedef MCDisassembler::DecodeStatus DecodeStatus;
32
33namespace {
34  // Handles the condition code status of instructions in IT blocks
35  class ITStatus
36  {
37    public:
38      // Returns the condition code for instruction in IT block
39      unsigned getITCC() {
40        unsigned CC = ARMCC::AL;
41        if (instrInITBlock())
42          CC = ITStates.back();
43        return CC;
44      }
45
46      // Advances the IT block state to the next T or E
47      void advanceITState() {
48        ITStates.pop_back();
49      }
50
51      // Returns true if the current instruction is in an IT block
52      bool instrInITBlock() {
53        return !ITStates.empty();
54      }
55
56      // Returns true if current instruction is the last instruction in an IT block
57      bool instrLastInITBlock() {
58        return ITStates.size() == 1;
59      }
60
61      // Called when decoding an IT instruction. Sets the IT state for the following
62      // instructions that for the IT block. Firstcond and Mask correspond to the
63      // fields in the IT instruction encoding.
64      void setITState(char Firstcond, char Mask) {
65        // (3 - the number of trailing zeros) is the number of then / else.
66        unsigned CondBit0 = Firstcond & 1;
67        unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68        unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69        assert(NumTZ <= 3 && "Invalid IT mask!");
70        // push condition codes onto the stack the correct order for the pops
71        for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72          bool T = ((Mask >> Pos) & 1) == CondBit0;
73          if (T)
74            ITStates.push_back(CCBits);
75          else
76            ITStates.push_back(CCBits ^ 1);
77        }
78        ITStates.push_back(CCBits);
79      }
80
81    private:
82      std::vector<unsigned char> ITStates;
83  };
84}
85
86namespace {
87/// ARM disassembler for all ARM platforms.
88class ARMDisassembler : public MCDisassembler {
89public:
90  ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91    MCDisassembler(STI, Ctx) {
92  }
93
94  ~ARMDisassembler() override {}
95
96  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97                              ArrayRef<uint8_t> Bytes, uint64_t Address,
98                              raw_ostream &VStream,
99                              raw_ostream &CStream) const override;
100};
101
102/// Thumb disassembler for all Thumb platforms.
103class ThumbDisassembler : public MCDisassembler {
104public:
105  ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106    MCDisassembler(STI, Ctx) {
107  }
108
109  ~ThumbDisassembler() override {}
110
111  DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112                              ArrayRef<uint8_t> Bytes, uint64_t Address,
113                              raw_ostream &VStream,
114                              raw_ostream &CStream) const override;
115
116private:
117  mutable ITStatus ITBlock;
118  DecodeStatus AddThumbPredicate(MCInst&) const;
119  void UpdateThumbVFPPredicate(MCInst&) const;
120};
121}
122
123static bool Check(DecodeStatus &Out, DecodeStatus In) {
124  switch (In) {
125    case MCDisassembler::Success:
126      // Out stays the same.
127      return true;
128    case MCDisassembler::SoftFail:
129      Out = In;
130      return true;
131    case MCDisassembler::Fail:
132      Out = In;
133      return false;
134  }
135  llvm_unreachable("Invalid DecodeStatus!");
136}
137
138
139// Forward declare these because the autogenerated code will reference them.
140// Definitions are further down.
141static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142                                   uint64_t Address, const void *Decoder);
143static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144                                               unsigned RegNo, uint64_t Address,
145                                               const void *Decoder);
146static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147                                               unsigned RegNo, uint64_t Address,
148                                               const void *Decoder);
149static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150                                   uint64_t Address, const void *Decoder);
151static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152                                   uint64_t Address, const void *Decoder);
153static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154                                   uint64_t Address, const void *Decoder);
155static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156                                   uint64_t Address, const void *Decoder);
157static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158                                   uint64_t Address, const void *Decoder);
159static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160                                   uint64_t Address, const void *Decoder);
161static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162                                   uint64_t Address, const void *Decoder);
163static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
164                                                unsigned RegNo,
165                                                uint64_t Address,
166                                                const void *Decoder);
167static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168                                   uint64_t Address, const void *Decoder);
169static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170                                   uint64_t Address, const void *Decoder);
171static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172                               unsigned RegNo, uint64_t Address,
173                               const void *Decoder);
174
175static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176                               uint64_t Address, const void *Decoder);
177static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178                               uint64_t Address, const void *Decoder);
179static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180                               uint64_t Address, const void *Decoder);
181static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182                               uint64_t Address, const void *Decoder);
183static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184                               uint64_t Address, const void *Decoder);
185
186static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187                               uint64_t Address, const void *Decoder);
188static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189                               uint64_t Address, const void *Decoder);
190static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
191                                                  unsigned Insn,
192                                                  uint64_t Address,
193                                                  const void *Decoder);
194static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195                               uint64_t Address, const void *Decoder);
196static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197                               uint64_t Address, const void *Decoder);
198static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199                               uint64_t Address, const void *Decoder);
200static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201                               uint64_t Address, const void *Decoder);
202
203static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
204                                                  unsigned Insn,
205                                                  uint64_t Adddress,
206                                                  const void *Decoder);
207static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208                               uint64_t Address, const void *Decoder);
209static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210                               uint64_t Address, const void *Decoder);
211static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212                               uint64_t Address, const void *Decoder);
213static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214                               uint64_t Address, const void *Decoder);
215static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
216                               uint64_t Address, const void *Decoder);
217static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
218                               uint64_t Address, const void *Decoder);
219static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
220                               uint64_t Address, const void *Decoder);
221static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
222                               uint64_t Address, const void *Decoder);
223static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
224                               uint64_t Address, const void *Decoder);
225static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
226                               uint64_t Address, const void *Decoder);
227static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
228                               uint64_t Address, const void *Decoder);
229static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
230                               uint64_t Address, const void *Decoder);
231static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
232                               uint64_t Address, const void *Decoder);
233static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
234                               uint64_t Address, const void *Decoder);
235static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
236                               uint64_t Address, const void *Decoder);
237static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
238                               uint64_t Address, const void *Decoder);
239static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
240                               uint64_t Address, const void *Decoder);
241static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
242                               uint64_t Address, const void *Decoder);
243static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
244                               uint64_t Address, const void *Decoder);
245static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
246                               uint64_t Address, const void *Decoder);
247static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
248                               uint64_t Address, const void *Decoder);
249static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
250                               uint64_t Address, const void *Decoder);
251static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
252                               uint64_t Address, const void *Decoder);
253static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
254                               uint64_t Address, const void *Decoder);
255static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
256                               uint64_t Address, const void *Decoder);
257static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
258                               uint64_t Address, const void *Decoder);
259static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
260                               uint64_t Address, const void *Decoder);
261static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
262                               uint64_t Address, const void *Decoder);
263static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
264                               uint64_t Address, const void *Decoder);
265static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
266                               uint64_t Address, const void *Decoder);
267static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
268                               uint64_t Address, const void *Decoder);
269static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
270                               uint64_t Address, const void *Decoder);
271static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
272                               uint64_t Address, const void *Decoder);
273static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
274                               uint64_t Address, const void *Decoder);
275static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
276                               uint64_t Address, const void *Decoder);
277static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
278                               uint64_t Address, const void *Decoder);
279static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
280                               uint64_t Address, const void *Decoder);
281static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
282                               uint64_t Address, const void *Decoder);
283static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
284                               uint64_t Address, const void *Decoder);
285static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
286                               uint64_t Address, const void *Decoder);
287static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
288                               uint64_t Address, const void *Decoder);
289static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
290                               uint64_t Address, const void *Decoder);
291static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
292                               uint64_t Address, const void *Decoder);
293static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
294                               uint64_t Address, const void *Decoder);
295static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
296                               uint64_t Address, const void *Decoder);
297static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
298                               uint64_t Address, const void *Decoder);
299static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
300                               uint64_t Address, const void *Decoder);
301static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
302                               uint64_t Address, const void *Decoder);
303static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
304                               uint64_t Address, const void *Decoder);
305static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
306                               uint64_t Address, const void *Decoder);
307static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
308                               uint64_t Address, const void *Decoder);
309static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
310                               uint64_t Address, const void *Decoder);
311static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
312                               uint64_t Address, const void *Decoder);
313static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
314                                uint64_t Address, const void *Decoder);
315static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
316                                uint64_t Address, const void *Decoder);
317
318
319static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
320                               uint64_t Address, const void *Decoder);
321static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
322                               uint64_t Address, const void *Decoder);
323static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
324                               uint64_t Address, const void *Decoder);
325static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
326                               uint64_t Address, const void *Decoder);
327static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
328                               uint64_t Address, const void *Decoder);
329static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
330                               uint64_t Address, const void *Decoder);
331static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
332                               uint64_t Address, const void *Decoder);
333static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
334                               uint64_t Address, const void *Decoder);
335static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
336                               uint64_t Address, const void *Decoder);
337static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
338                               uint64_t Address, const void *Decoder);
339static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
340                               uint64_t Address, const void* Decoder);
341static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
342                               uint64_t Address, const void* Decoder);
343static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
344                               uint64_t Address, const void* Decoder);
345static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
346                               uint64_t Address, const void* Decoder);
347static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
348                               uint64_t Address, const void *Decoder);
349static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
350                               uint64_t Address, const void *Decoder);
351static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
352                               uint64_t Address, const void *Decoder);
353static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
354                               uint64_t Address, const void *Decoder);
355static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
356                               uint64_t Address, const void *Decoder);
357static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
358                               uint64_t Address, const void *Decoder);
359static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
360                                uint64_t Address, const void *Decoder);
361static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
362                                uint64_t Address, const void *Decoder);
363static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
364                                uint64_t Address, const void *Decoder);
365static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
366                                uint64_t Address, const void *Decoder);
367static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
368                                uint64_t Address, const void *Decoder);
369static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
370                                uint64_t Address, const void *Decoder);
371static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
372                                uint64_t Address, const void *Decoder);
373static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
374                                uint64_t Address, const void *Decoder);
375static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
376                                uint64_t Address, const void *Decoder);
377static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
378                                uint64_t Address, const void *Decoder);
379static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
380                                uint64_t Address, const void *Decoder);
381static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
382                               uint64_t Address, const void *Decoder);
383static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
384                               uint64_t Address, const void *Decoder);
385static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
386                                uint64_t Address, const void *Decoder);
387static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
388                                uint64_t Address, const void *Decoder);
389static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
390                                uint64_t Address, const void *Decoder);
391
392static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
393                                uint64_t Address, const void *Decoder);
394static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
395                                uint64_t Address, const void *Decoder);
396#include "ARMGenDisassemblerTables.inc"
397
398static MCDisassembler *createARMDisassembler(const Target &T,
399                                             const MCSubtargetInfo &STI,
400                                             MCContext &Ctx) {
401  return new ARMDisassembler(STI, Ctx);
402}
403
404static MCDisassembler *createThumbDisassembler(const Target &T,
405                                               const MCSubtargetInfo &STI,
406                                               MCContext &Ctx) {
407  return new ThumbDisassembler(STI, Ctx);
408}
409
410// Post-decoding checks
411static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
412                                            uint64_t Address, raw_ostream &OS,
413                                            raw_ostream &CS,
414                                            uint32_t Insn,
415                                            DecodeStatus Result)
416{
417  switch (MI.getOpcode()) {
418    case ARM::HVC: {
419      // HVC is undefined if condition = 0xf otherwise upredictable
420      // if condition != 0xe
421      uint32_t Cond = (Insn >> 28) & 0xF;
422      if (Cond == 0xF)
423        return MCDisassembler::Fail;
424      if (Cond != 0xE)
425        return MCDisassembler::SoftFail;
426      return Result;
427    }
428    default: return Result;
429  }
430}
431
432DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
433                                             ArrayRef<uint8_t> Bytes,
434                                             uint64_t Address, raw_ostream &OS,
435                                             raw_ostream &CS) const {
436  CommentStream = &CS;
437
438  assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
439         "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
440         "mode!");
441
442  // We want to read exactly 4 bytes of data.
443  if (Bytes.size() < 4) {
444    Size = 0;
445    return MCDisassembler::Fail;
446  }
447
448  // Encoded as a small-endian 32-bit word in the stream.
449  uint32_t Insn =
450      (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
451
452  // Calling the auto-generated decoder function.
453  DecodeStatus Result =
454      decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
455  if (Result != MCDisassembler::Fail) {
456    Size = 4;
457    return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
458  }
459
460  // VFP and NEON instructions, similarly, are shared between ARM
461  // and Thumb modes.
462  Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
463  if (Result != MCDisassembler::Fail) {
464    Size = 4;
465    return Result;
466  }
467
468  Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
469  if (Result != MCDisassembler::Fail) {
470    Size = 4;
471    return Result;
472  }
473
474  Result =
475      decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
476  if (Result != MCDisassembler::Fail) {
477    Size = 4;
478    // Add a fake predicate operand, because we share these instruction
479    // definitions with Thumb2 where these instructions are predicable.
480    if (!DecodePredicateOperand(MI, 0xE, Address, this))
481      return MCDisassembler::Fail;
482    return Result;
483  }
484
485  Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
486                             this, STI);
487  if (Result != MCDisassembler::Fail) {
488    Size = 4;
489    // Add a fake predicate operand, because we share these instruction
490    // definitions with Thumb2 where these instructions are predicable.
491    if (!DecodePredicateOperand(MI, 0xE, Address, this))
492      return MCDisassembler::Fail;
493    return Result;
494  }
495
496  Result =
497      decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
498  if (Result != MCDisassembler::Fail) {
499    Size = 4;
500    // Add a fake predicate operand, because we share these instruction
501    // definitions with Thumb2 where these instructions are predicable.
502    if (!DecodePredicateOperand(MI, 0xE, Address, this))
503      return MCDisassembler::Fail;
504    return Result;
505  }
506
507  Result =
508      decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
509  if (Result != MCDisassembler::Fail) {
510    Size = 4;
511    return Result;
512  }
513
514  Result =
515      decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
516  if (Result != MCDisassembler::Fail) {
517    Size = 4;
518    return Result;
519  }
520
521  Size = 0;
522  return MCDisassembler::Fail;
523}
524
525namespace llvm {
526extern const MCInstrDesc ARMInsts[];
527}
528
529/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
530/// immediate Value in the MCInst.  The immediate Value has had any PC
531/// adjustment made by the caller.  If the instruction is a branch instruction
532/// then isBranch is true, else false.  If the getOpInfo() function was set as
533/// part of the setupForSymbolicDisassembly() call then that function is called
534/// to get any symbolic information at the Address for this instruction.  If
535/// that returns non-zero then the symbolic information it returns is used to
536/// create an MCExpr and that is added as an operand to the MCInst.  If
537/// getOpInfo() returns zero and isBranch is true then a symbol look up for
538/// Value is done and if a symbol is found an MCExpr is created with that, else
539/// an MCExpr with Value is created.  This function returns true if it adds an
540/// operand to the MCInst and false otherwise.
541static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
542                                     bool isBranch, uint64_t InstSize,
543                                     MCInst &MI, const void *Decoder) {
544  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
545  // FIXME: Does it make sense for value to be negative?
546  return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
547                                       /* Offset */ 0, InstSize);
548}
549
550/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
551/// referenced by a load instruction with the base register that is the Pc.
552/// These can often be values in a literal pool near the Address of the
553/// instruction.  The Address of the instruction and its immediate Value are
554/// used as a possible literal pool entry.  The SymbolLookUp call back will
555/// return the name of a symbol referenced by the literal pool's entry if
556/// the referenced address is that of a symbol.  Or it will return a pointer to
557/// a literal 'C' string if the referenced address of the literal pool's entry
558/// is an address into a section with 'C' string literals.
559static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
560                                            const void *Decoder) {
561  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
562  Dis->tryAddingPcLoadReferenceComment(Value, Address);
563}
564
565// Thumb1 instructions don't have explicit S bits.  Rather, they
566// implicitly set CPSR.  Since it's not represented in the encoding, the
567// auto-generated decoder won't inject the CPSR operand.  We need to fix
568// that as a post-pass.
569static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
570  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
571  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
572  MCInst::iterator I = MI.begin();
573  for (unsigned i = 0; i < NumOps; ++i, ++I) {
574    if (I == MI.end()) break;
575    if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
576      if (i > 0 && OpInfo[i-1].isPredicate()) continue;
577      MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
578      return;
579    }
580  }
581
582  MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
583}
584
585// Most Thumb instructions don't have explicit predicates in the
586// encoding, but rather get their predicates from IT context.  We need
587// to fix up the predicate operands using this context information as a
588// post-pass.
589MCDisassembler::DecodeStatus
590ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
591  MCDisassembler::DecodeStatus S = Success;
592
593  // A few instructions actually have predicates encoded in them.  Don't
594  // try to overwrite it if we're seeing one of those.
595  switch (MI.getOpcode()) {
596    case ARM::tBcc:
597    case ARM::t2Bcc:
598    case ARM::tCBZ:
599    case ARM::tCBNZ:
600    case ARM::tCPS:
601    case ARM::t2CPS3p:
602    case ARM::t2CPS2p:
603    case ARM::t2CPS1p:
604    case ARM::tMOVSr:
605    case ARM::tSETEND:
606      // Some instructions (mostly conditional branches) are not
607      // allowed in IT blocks.
608      if (ITBlock.instrInITBlock())
609        S = SoftFail;
610      else
611        return Success;
612      break;
613    case ARM::tB:
614    case ARM::t2B:
615    case ARM::t2TBB:
616    case ARM::t2TBH:
617      // Some instructions (mostly unconditional branches) can
618      // only appears at the end of, or outside of, an IT.
619      if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
620        S = SoftFail;
621      break;
622    default:
623      break;
624  }
625
626  // If we're in an IT block, base the predicate on that.  Otherwise,
627  // assume a predicate of AL.
628  unsigned CC;
629  CC = ITBlock.getITCC();
630  if (CC == 0xF)
631    CC = ARMCC::AL;
632  if (ITBlock.instrInITBlock())
633    ITBlock.advanceITState();
634
635  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
636  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
637  MCInst::iterator I = MI.begin();
638  for (unsigned i = 0; i < NumOps; ++i, ++I) {
639    if (I == MI.end()) break;
640    if (OpInfo[i].isPredicate()) {
641      I = MI.insert(I, MCOperand::createImm(CC));
642      ++I;
643      if (CC == ARMCC::AL)
644        MI.insert(I, MCOperand::createReg(0));
645      else
646        MI.insert(I, MCOperand::createReg(ARM::CPSR));
647      return S;
648    }
649  }
650
651  I = MI.insert(I, MCOperand::createImm(CC));
652  ++I;
653  if (CC == ARMCC::AL)
654    MI.insert(I, MCOperand::createReg(0));
655  else
656    MI.insert(I, MCOperand::createReg(ARM::CPSR));
657
658  return S;
659}
660
661// Thumb VFP instructions are a special case.  Because we share their
662// encodings between ARM and Thumb modes, and they are predicable in ARM
663// mode, the auto-generated decoder will give them an (incorrect)
664// predicate operand.  We need to rewrite these operands based on the IT
665// context as a post-pass.
666void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
667  unsigned CC;
668  CC = ITBlock.getITCC();
669  if (ITBlock.instrInITBlock())
670    ITBlock.advanceITState();
671
672  const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673  MCInst::iterator I = MI.begin();
674  unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675  for (unsigned i = 0; i < NumOps; ++i, ++I) {
676    if (OpInfo[i].isPredicate() ) {
677      I->setImm(CC);
678      ++I;
679      if (CC == ARMCC::AL)
680        I->setReg(0);
681      else
682        I->setReg(ARM::CPSR);
683      return;
684    }
685  }
686}
687
688DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
689                                               ArrayRef<uint8_t> Bytes,
690                                               uint64_t Address,
691                                               raw_ostream &OS,
692                                               raw_ostream &CS) const {
693  CommentStream = &CS;
694
695  assert(STI.getFeatureBits()[ARM::ModeThumb] &&
696         "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
697
698  // We want to read exactly 2 bytes of data.
699  if (Bytes.size() < 2) {
700    Size = 0;
701    return MCDisassembler::Fail;
702  }
703
704  uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
705  DecodeStatus Result =
706      decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
707  if (Result != MCDisassembler::Fail) {
708    Size = 2;
709    Check(Result, AddThumbPredicate(MI));
710    return Result;
711  }
712
713  Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
714                             STI);
715  if (Result) {
716    Size = 2;
717    bool InITBlock = ITBlock.instrInITBlock();
718    Check(Result, AddThumbPredicate(MI));
719    AddThumb1SBit(MI, InITBlock);
720    return Result;
721  }
722
723  Result =
724      decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
725  if (Result != MCDisassembler::Fail) {
726    Size = 2;
727
728    // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
729    // the Thumb predicate.
730    if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
731      Result = MCDisassembler::SoftFail;
732
733    Check(Result, AddThumbPredicate(MI));
734
735    // If we find an IT instruction, we need to parse its condition
736    // code and mask operands so that we can apply them correctly
737    // to the subsequent instructions.
738    if (MI.getOpcode() == ARM::t2IT) {
739
740      unsigned Firstcond = MI.getOperand(0).getImm();
741      unsigned Mask = MI.getOperand(1).getImm();
742      ITBlock.setITState(Firstcond, Mask);
743    }
744
745    return Result;
746  }
747
748  // We want to read exactly 4 bytes of data.
749  if (Bytes.size() < 4) {
750    Size = 0;
751    return MCDisassembler::Fail;
752  }
753
754  uint32_t Insn32 =
755      (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
756  Result =
757      decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
758  if (Result != MCDisassembler::Fail) {
759    Size = 4;
760    bool InITBlock = ITBlock.instrInITBlock();
761    Check(Result, AddThumbPredicate(MI));
762    AddThumb1SBit(MI, InITBlock);
763    return Result;
764  }
765
766  Result =
767      decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
768  if (Result != MCDisassembler::Fail) {
769    Size = 4;
770    Check(Result, AddThumbPredicate(MI));
771    return Result;
772  }
773
774  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
775    Result =
776        decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
777    if (Result != MCDisassembler::Fail) {
778      Size = 4;
779      UpdateThumbVFPPredicate(MI);
780      return Result;
781    }
782  }
783
784  Result =
785      decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
786  if (Result != MCDisassembler::Fail) {
787    Size = 4;
788    return Result;
789  }
790
791  if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
792    Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
793                               STI);
794    if (Result != MCDisassembler::Fail) {
795      Size = 4;
796      Check(Result, AddThumbPredicate(MI));
797      return Result;
798    }
799  }
800
801  if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
802    uint32_t NEONLdStInsn = Insn32;
803    NEONLdStInsn &= 0xF0FFFFFF;
804    NEONLdStInsn |= 0x04000000;
805    Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
806                               Address, this, STI);
807    if (Result != MCDisassembler::Fail) {
808      Size = 4;
809      Check(Result, AddThumbPredicate(MI));
810      return Result;
811    }
812  }
813
814  if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
815    uint32_t NEONDataInsn = Insn32;
816    NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
817    NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
818    NEONDataInsn |= 0x12000000; // Set bits 28 and 25
819    Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
820                               Address, this, STI);
821    if (Result != MCDisassembler::Fail) {
822      Size = 4;
823      Check(Result, AddThumbPredicate(MI));
824      return Result;
825    }
826
827    uint32_t NEONCryptoInsn = Insn32;
828    NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
829    NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
830    NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
831    Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
832                               Address, this, STI);
833    if (Result != MCDisassembler::Fail) {
834      Size = 4;
835      return Result;
836    }
837
838    uint32_t NEONv8Insn = Insn32;
839    NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
840    Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
841                               this, STI);
842    if (Result != MCDisassembler::Fail) {
843      Size = 4;
844      return Result;
845    }
846  }
847
848  Size = 0;
849  return MCDisassembler::Fail;
850}
851
852
853extern "C" void LLVMInitializeARMDisassembler() {
854  TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
855                                         createARMDisassembler);
856  TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
857                                         createARMDisassembler);
858  TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
859                                         createThumbDisassembler);
860  TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
861                                         createThumbDisassembler);
862}
863
864static const uint16_t GPRDecoderTable[] = {
865  ARM::R0, ARM::R1, ARM::R2, ARM::R3,
866  ARM::R4, ARM::R5, ARM::R6, ARM::R7,
867  ARM::R8, ARM::R9, ARM::R10, ARM::R11,
868  ARM::R12, ARM::SP, ARM::LR, ARM::PC
869};
870
871static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
872                                   uint64_t Address, const void *Decoder) {
873  if (RegNo > 15)
874    return MCDisassembler::Fail;
875
876  unsigned Register = GPRDecoderTable[RegNo];
877  Inst.addOperand(MCOperand::createReg(Register));
878  return MCDisassembler::Success;
879}
880
881static DecodeStatus
882DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
883                           uint64_t Address, const void *Decoder) {
884  DecodeStatus S = MCDisassembler::Success;
885
886  if (RegNo == 15)
887    S = MCDisassembler::SoftFail;
888
889  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
890
891  return S;
892}
893
894static DecodeStatus
895DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
896                               uint64_t Address, const void *Decoder) {
897  DecodeStatus S = MCDisassembler::Success;
898
899  if (RegNo == 15)
900  {
901    Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
902    return MCDisassembler::Success;
903  }
904
905  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
906  return S;
907}
908
909static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
910                                   uint64_t Address, const void *Decoder) {
911  if (RegNo > 7)
912    return MCDisassembler::Fail;
913  return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
914}
915
916static const uint16_t GPRPairDecoderTable[] = {
917  ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
918  ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
919};
920
921static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
922                                   uint64_t Address, const void *Decoder) {
923  DecodeStatus S = MCDisassembler::Success;
924
925  if (RegNo > 13)
926    return MCDisassembler::Fail;
927
928  if ((RegNo & 1) || RegNo == 0xe)
929     S = MCDisassembler::SoftFail;
930
931  unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
932  Inst.addOperand(MCOperand::createReg(RegisterPair));
933  return S;
934}
935
936static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
937                                   uint64_t Address, const void *Decoder) {
938  unsigned Register = 0;
939  switch (RegNo) {
940    case 0:
941      Register = ARM::R0;
942      break;
943    case 1:
944      Register = ARM::R1;
945      break;
946    case 2:
947      Register = ARM::R2;
948      break;
949    case 3:
950      Register = ARM::R3;
951      break;
952    case 9:
953      Register = ARM::R9;
954      break;
955    case 12:
956      Register = ARM::R12;
957      break;
958    default:
959      return MCDisassembler::Fail;
960    }
961
962  Inst.addOperand(MCOperand::createReg(Register));
963  return MCDisassembler::Success;
964}
965
966static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
967                                   uint64_t Address, const void *Decoder) {
968  DecodeStatus S = MCDisassembler::Success;
969
970  const FeatureBitset &featureBits =
971    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
972
973  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
974    S = MCDisassembler::SoftFail;
975
976  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
977  return S;
978}
979
980static const uint16_t SPRDecoderTable[] = {
981     ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
982     ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
983     ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
984    ARM::S12, ARM::S13, ARM::S14, ARM::S15,
985    ARM::S16, ARM::S17, ARM::S18, ARM::S19,
986    ARM::S20, ARM::S21, ARM::S22, ARM::S23,
987    ARM::S24, ARM::S25, ARM::S26, ARM::S27,
988    ARM::S28, ARM::S29, ARM::S30, ARM::S31
989};
990
991static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
992                                   uint64_t Address, const void *Decoder) {
993  if (RegNo > 31)
994    return MCDisassembler::Fail;
995
996  unsigned Register = SPRDecoderTable[RegNo];
997  Inst.addOperand(MCOperand::createReg(Register));
998  return MCDisassembler::Success;
999}
1000
1001static const uint16_t DPRDecoderTable[] = {
1002     ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
1003     ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
1004     ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
1005    ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1006    ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1007    ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1008    ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1009    ARM::D28, ARM::D29, ARM::D30, ARM::D31
1010};
1011
1012static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1013                                   uint64_t Address, const void *Decoder) {
1014  const FeatureBitset &featureBits =
1015    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1016
1017  bool hasD16 = featureBits[ARM::FeatureD16];
1018
1019  if (RegNo > 31 || (hasD16 && RegNo > 15))
1020    return MCDisassembler::Fail;
1021
1022  unsigned Register = DPRDecoderTable[RegNo];
1023  Inst.addOperand(MCOperand::createReg(Register));
1024  return MCDisassembler::Success;
1025}
1026
1027static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1028                                   uint64_t Address, const void *Decoder) {
1029  if (RegNo > 7)
1030    return MCDisassembler::Fail;
1031  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1032}
1033
1034static DecodeStatus
1035DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1036                            uint64_t Address, const void *Decoder) {
1037  if (RegNo > 15)
1038    return MCDisassembler::Fail;
1039  return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1040}
1041
1042static const uint16_t QPRDecoderTable[] = {
1043     ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
1044     ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
1045     ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
1046    ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1047};
1048
1049
1050static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1051                                   uint64_t Address, const void *Decoder) {
1052  if (RegNo > 31 || (RegNo & 1) != 0)
1053    return MCDisassembler::Fail;
1054  RegNo >>= 1;
1055
1056  unsigned Register = QPRDecoderTable[RegNo];
1057  Inst.addOperand(MCOperand::createReg(Register));
1058  return MCDisassembler::Success;
1059}
1060
1061static const uint16_t DPairDecoderTable[] = {
1062  ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
1063  ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
1064  ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
1065  ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1066  ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1067  ARM::Q15
1068};
1069
1070static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1071                                   uint64_t Address, const void *Decoder) {
1072  if (RegNo > 30)
1073    return MCDisassembler::Fail;
1074
1075  unsigned Register = DPairDecoderTable[RegNo];
1076  Inst.addOperand(MCOperand::createReg(Register));
1077  return MCDisassembler::Success;
1078}
1079
1080static const uint16_t DPairSpacedDecoderTable[] = {
1081  ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
1082  ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
1083  ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
1084  ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1085  ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1086  ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1087  ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1088  ARM::D28_D30, ARM::D29_D31
1089};
1090
1091static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1092                                                   unsigned RegNo,
1093                                                   uint64_t Address,
1094                                                   const void *Decoder) {
1095  if (RegNo > 29)
1096    return MCDisassembler::Fail;
1097
1098  unsigned Register = DPairSpacedDecoderTable[RegNo];
1099  Inst.addOperand(MCOperand::createReg(Register));
1100  return MCDisassembler::Success;
1101}
1102
1103static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1104                               uint64_t Address, const void *Decoder) {
1105  if (Val == 0xF) return MCDisassembler::Fail;
1106  // AL predicate is not allowed on Thumb1 branches.
1107  if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1108    return MCDisassembler::Fail;
1109  Inst.addOperand(MCOperand::createImm(Val));
1110  if (Val == ARMCC::AL) {
1111    Inst.addOperand(MCOperand::createReg(0));
1112  } else
1113    Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1114  return MCDisassembler::Success;
1115}
1116
1117static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1118                               uint64_t Address, const void *Decoder) {
1119  if (Val)
1120    Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1121  else
1122    Inst.addOperand(MCOperand::createReg(0));
1123  return MCDisassembler::Success;
1124}
1125
1126static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1127                               uint64_t Address, const void *Decoder) {
1128  DecodeStatus S = MCDisassembler::Success;
1129
1130  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1131  unsigned type = fieldFromInstruction(Val, 5, 2);
1132  unsigned imm = fieldFromInstruction(Val, 7, 5);
1133
1134  // Register-immediate
1135  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1136    return MCDisassembler::Fail;
1137
1138  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1139  switch (type) {
1140    case 0:
1141      Shift = ARM_AM::lsl;
1142      break;
1143    case 1:
1144      Shift = ARM_AM::lsr;
1145      break;
1146    case 2:
1147      Shift = ARM_AM::asr;
1148      break;
1149    case 3:
1150      Shift = ARM_AM::ror;
1151      break;
1152  }
1153
1154  if (Shift == ARM_AM::ror && imm == 0)
1155    Shift = ARM_AM::rrx;
1156
1157  unsigned Op = Shift | (imm << 3);
1158  Inst.addOperand(MCOperand::createImm(Op));
1159
1160  return S;
1161}
1162
1163static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1164                               uint64_t Address, const void *Decoder) {
1165  DecodeStatus S = MCDisassembler::Success;
1166
1167  unsigned Rm = fieldFromInstruction(Val, 0, 4);
1168  unsigned type = fieldFromInstruction(Val, 5, 2);
1169  unsigned Rs = fieldFromInstruction(Val, 8, 4);
1170
1171  // Register-register
1172  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1173    return MCDisassembler::Fail;
1174  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1175    return MCDisassembler::Fail;
1176
1177  ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1178  switch (type) {
1179    case 0:
1180      Shift = ARM_AM::lsl;
1181      break;
1182    case 1:
1183      Shift = ARM_AM::lsr;
1184      break;
1185    case 2:
1186      Shift = ARM_AM::asr;
1187      break;
1188    case 3:
1189      Shift = ARM_AM::ror;
1190      break;
1191  }
1192
1193  Inst.addOperand(MCOperand::createImm(Shift));
1194
1195  return S;
1196}
1197
1198static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1199                                 uint64_t Address, const void *Decoder) {
1200  DecodeStatus S = MCDisassembler::Success;
1201
1202  bool NeedDisjointWriteback = false;
1203  unsigned WritebackReg = 0;
1204  switch (Inst.getOpcode()) {
1205  default:
1206    break;
1207  case ARM::LDMIA_UPD:
1208  case ARM::LDMDB_UPD:
1209  case ARM::LDMIB_UPD:
1210  case ARM::LDMDA_UPD:
1211  case ARM::t2LDMIA_UPD:
1212  case ARM::t2LDMDB_UPD:
1213  case ARM::t2STMIA_UPD:
1214  case ARM::t2STMDB_UPD:
1215    NeedDisjointWriteback = true;
1216    WritebackReg = Inst.getOperand(0).getReg();
1217    break;
1218  }
1219
1220  // Empty register lists are not allowed.
1221  if (Val == 0) return MCDisassembler::Fail;
1222  for (unsigned i = 0; i < 16; ++i) {
1223    if (Val & (1 << i)) {
1224      if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1225        return MCDisassembler::Fail;
1226      // Writeback not allowed if Rn is in the target list.
1227      if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1228        Check(S, MCDisassembler::SoftFail);
1229    }
1230  }
1231
1232  return S;
1233}
1234
1235static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1236                                 uint64_t Address, const void *Decoder) {
1237  DecodeStatus S = MCDisassembler::Success;
1238
1239  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1240  unsigned regs = fieldFromInstruction(Val, 0, 8);
1241
1242  // In case of unpredictable encoding, tweak the operands.
1243  if (regs == 0 || (Vd + regs) > 32) {
1244    regs = Vd + regs > 32 ? 32 - Vd : regs;
1245    regs = std::max( 1u, regs);
1246    S = MCDisassembler::SoftFail;
1247  }
1248
1249  if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1250    return MCDisassembler::Fail;
1251  for (unsigned i = 0; i < (regs - 1); ++i) {
1252    if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1253      return MCDisassembler::Fail;
1254  }
1255
1256  return S;
1257}
1258
1259static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1260                                 uint64_t Address, const void *Decoder) {
1261  DecodeStatus S = MCDisassembler::Success;
1262
1263  unsigned Vd = fieldFromInstruction(Val, 8, 5);
1264  unsigned regs = fieldFromInstruction(Val, 1, 7);
1265
1266  // In case of unpredictable encoding, tweak the operands.
1267  if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1268    regs = Vd + regs > 32 ? 32 - Vd : regs;
1269    regs = std::max( 1u, regs);
1270    regs = std::min(16u, regs);
1271    S = MCDisassembler::SoftFail;
1272  }
1273
1274  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1275      return MCDisassembler::Fail;
1276  for (unsigned i = 0; i < (regs - 1); ++i) {
1277    if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1278      return MCDisassembler::Fail;
1279  }
1280
1281  return S;
1282}
1283
1284static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1285                                      uint64_t Address, const void *Decoder) {
1286  // This operand encodes a mask of contiguous zeros between a specified MSB
1287  // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
1288  // the mask of all bits LSB-and-lower, and then xor them to create
1289  // the mask of that's all ones on [msb, lsb].  Finally we not it to
1290  // create the final mask.
1291  unsigned msb = fieldFromInstruction(Val, 5, 5);
1292  unsigned lsb = fieldFromInstruction(Val, 0, 5);
1293
1294  DecodeStatus S = MCDisassembler::Success;
1295  if (lsb > msb) {
1296    Check(S, MCDisassembler::SoftFail);
1297    // The check above will cause the warning for the "potentially undefined
1298    // instruction encoding" but we can't build a bad MCOperand value here
1299    // with a lsb > msb or else printing the MCInst will cause a crash.
1300    lsb = msb;
1301  }
1302
1303  uint32_t msb_mask = 0xFFFFFFFF;
1304  if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1305  uint32_t lsb_mask = (1U << lsb) - 1;
1306
1307  Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1308  return S;
1309}
1310
1311static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1312                                  uint64_t Address, const void *Decoder) {
1313  DecodeStatus S = MCDisassembler::Success;
1314
1315  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1316  unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1317  unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1318  unsigned imm = fieldFromInstruction(Insn, 0, 8);
1319  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1320  unsigned U = fieldFromInstruction(Insn, 23, 1);
1321
1322  switch (Inst.getOpcode()) {
1323    case ARM::LDC_OFFSET:
1324    case ARM::LDC_PRE:
1325    case ARM::LDC_POST:
1326    case ARM::LDC_OPTION:
1327    case ARM::LDCL_OFFSET:
1328    case ARM::LDCL_PRE:
1329    case ARM::LDCL_POST:
1330    case ARM::LDCL_OPTION:
1331    case ARM::STC_OFFSET:
1332    case ARM::STC_PRE:
1333    case ARM::STC_POST:
1334    case ARM::STC_OPTION:
1335    case ARM::STCL_OFFSET:
1336    case ARM::STCL_PRE:
1337    case ARM::STCL_POST:
1338    case ARM::STCL_OPTION:
1339    case ARM::t2LDC_OFFSET:
1340    case ARM::t2LDC_PRE:
1341    case ARM::t2LDC_POST:
1342    case ARM::t2LDC_OPTION:
1343    case ARM::t2LDCL_OFFSET:
1344    case ARM::t2LDCL_PRE:
1345    case ARM::t2LDCL_POST:
1346    case ARM::t2LDCL_OPTION:
1347    case ARM::t2STC_OFFSET:
1348    case ARM::t2STC_PRE:
1349    case ARM::t2STC_POST:
1350    case ARM::t2STC_OPTION:
1351    case ARM::t2STCL_OFFSET:
1352    case ARM::t2STCL_PRE:
1353    case ARM::t2STCL_POST:
1354    case ARM::t2STCL_OPTION:
1355      if (coproc == 0xA || coproc == 0xB)
1356        return MCDisassembler::Fail;
1357      break;
1358    default:
1359      break;
1360  }
1361
1362  const FeatureBitset &featureBits =
1363    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1364  if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1365    return MCDisassembler::Fail;
1366
1367  Inst.addOperand(MCOperand::createImm(coproc));
1368  Inst.addOperand(MCOperand::createImm(CRd));
1369  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1370    return MCDisassembler::Fail;
1371
1372  switch (Inst.getOpcode()) {
1373    case ARM::t2LDC2_OFFSET:
1374    case ARM::t2LDC2L_OFFSET:
1375    case ARM::t2LDC2_PRE:
1376    case ARM::t2LDC2L_PRE:
1377    case ARM::t2STC2_OFFSET:
1378    case ARM::t2STC2L_OFFSET:
1379    case ARM::t2STC2_PRE:
1380    case ARM::t2STC2L_PRE:
1381    case ARM::LDC2_OFFSET:
1382    case ARM::LDC2L_OFFSET:
1383    case ARM::LDC2_PRE:
1384    case ARM::LDC2L_PRE:
1385    case ARM::STC2_OFFSET:
1386    case ARM::STC2L_OFFSET:
1387    case ARM::STC2_PRE:
1388    case ARM::STC2L_PRE:
1389    case ARM::t2LDC_OFFSET:
1390    case ARM::t2LDCL_OFFSET:
1391    case ARM::t2LDC_PRE:
1392    case ARM::t2LDCL_PRE:
1393    case ARM::t2STC_OFFSET:
1394    case ARM::t2STCL_OFFSET:
1395    case ARM::t2STC_PRE:
1396    case ARM::t2STCL_PRE:
1397    case ARM::LDC_OFFSET:
1398    case ARM::LDCL_OFFSET:
1399    case ARM::LDC_PRE:
1400    case ARM::LDCL_PRE:
1401    case ARM::STC_OFFSET:
1402    case ARM::STCL_OFFSET:
1403    case ARM::STC_PRE:
1404    case ARM::STCL_PRE:
1405      imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1406      Inst.addOperand(MCOperand::createImm(imm));
1407      break;
1408    case ARM::t2LDC2_POST:
1409    case ARM::t2LDC2L_POST:
1410    case ARM::t2STC2_POST:
1411    case ARM::t2STC2L_POST:
1412    case ARM::LDC2_POST:
1413    case ARM::LDC2L_POST:
1414    case ARM::STC2_POST:
1415    case ARM::STC2L_POST:
1416    case ARM::t2LDC_POST:
1417    case ARM::t2LDCL_POST:
1418    case ARM::t2STC_POST:
1419    case ARM::t2STCL_POST:
1420    case ARM::LDC_POST:
1421    case ARM::LDCL_POST:
1422    case ARM::STC_POST:
1423    case ARM::STCL_POST:
1424      imm |= U << 8;
1425      // fall through.
1426    default:
1427      // The 'option' variant doesn't encode 'U' in the immediate since
1428      // the immediate is unsigned [0,255].
1429      Inst.addOperand(MCOperand::createImm(imm));
1430      break;
1431  }
1432
1433  switch (Inst.getOpcode()) {
1434    case ARM::LDC_OFFSET:
1435    case ARM::LDC_PRE:
1436    case ARM::LDC_POST:
1437    case ARM::LDC_OPTION:
1438    case ARM::LDCL_OFFSET:
1439    case ARM::LDCL_PRE:
1440    case ARM::LDCL_POST:
1441    case ARM::LDCL_OPTION:
1442    case ARM::STC_OFFSET:
1443    case ARM::STC_PRE:
1444    case ARM::STC_POST:
1445    case ARM::STC_OPTION:
1446    case ARM::STCL_OFFSET:
1447    case ARM::STCL_PRE:
1448    case ARM::STCL_POST:
1449    case ARM::STCL_OPTION:
1450      if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1451        return MCDisassembler::Fail;
1452      break;
1453    default:
1454      break;
1455  }
1456
1457  return S;
1458}
1459
1460static DecodeStatus
1461DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1462                              uint64_t Address, const void *Decoder) {
1463  DecodeStatus S = MCDisassembler::Success;
1464
1465  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1466  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1467  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1468  unsigned imm = fieldFromInstruction(Insn, 0, 12);
1469  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1470  unsigned reg = fieldFromInstruction(Insn, 25, 1);
1471  unsigned P = fieldFromInstruction(Insn, 24, 1);
1472  unsigned W = fieldFromInstruction(Insn, 21, 1);
1473
1474  // On stores, the writeback operand precedes Rt.
1475  switch (Inst.getOpcode()) {
1476    case ARM::STR_POST_IMM:
1477    case ARM::STR_POST_REG:
1478    case ARM::STRB_POST_IMM:
1479    case ARM::STRB_POST_REG:
1480    case ARM::STRT_POST_REG:
1481    case ARM::STRT_POST_IMM:
1482    case ARM::STRBT_POST_REG:
1483    case ARM::STRBT_POST_IMM:
1484      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1485        return MCDisassembler::Fail;
1486      break;
1487    default:
1488      break;
1489  }
1490
1491  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1492    return MCDisassembler::Fail;
1493
1494  // On loads, the writeback operand comes after Rt.
1495  switch (Inst.getOpcode()) {
1496    case ARM::LDR_POST_IMM:
1497    case ARM::LDR_POST_REG:
1498    case ARM::LDRB_POST_IMM:
1499    case ARM::LDRB_POST_REG:
1500    case ARM::LDRBT_POST_REG:
1501    case ARM::LDRBT_POST_IMM:
1502    case ARM::LDRT_POST_REG:
1503    case ARM::LDRT_POST_IMM:
1504      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1505        return MCDisassembler::Fail;
1506      break;
1507    default:
1508      break;
1509  }
1510
1511  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1512    return MCDisassembler::Fail;
1513
1514  ARM_AM::AddrOpc Op = ARM_AM::add;
1515  if (!fieldFromInstruction(Insn, 23, 1))
1516    Op = ARM_AM::sub;
1517
1518  bool writeback = (P == 0) || (W == 1);
1519  unsigned idx_mode = 0;
1520  if (P && writeback)
1521    idx_mode = ARMII::IndexModePre;
1522  else if (!P && writeback)
1523    idx_mode = ARMII::IndexModePost;
1524
1525  if (writeback && (Rn == 15 || Rn == Rt))
1526    S = MCDisassembler::SoftFail; // UNPREDICTABLE
1527
1528  if (reg) {
1529    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1530      return MCDisassembler::Fail;
1531    ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1532    switch( fieldFromInstruction(Insn, 5, 2)) {
1533      case 0:
1534        Opc = ARM_AM::lsl;
1535        break;
1536      case 1:
1537        Opc = ARM_AM::lsr;
1538        break;
1539      case 2:
1540        Opc = ARM_AM::asr;
1541        break;
1542      case 3:
1543        Opc = ARM_AM::ror;
1544        break;
1545      default:
1546        return MCDisassembler::Fail;
1547    }
1548    unsigned amt = fieldFromInstruction(Insn, 7, 5);
1549    if (Opc == ARM_AM::ror && amt == 0)
1550      Opc = ARM_AM::rrx;
1551    unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1552
1553    Inst.addOperand(MCOperand::createImm(imm));
1554  } else {
1555    Inst.addOperand(MCOperand::createReg(0));
1556    unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1557    Inst.addOperand(MCOperand::createImm(tmp));
1558  }
1559
1560  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1561    return MCDisassembler::Fail;
1562
1563  return S;
1564}
1565
1566static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1567                                  uint64_t Address, const void *Decoder) {
1568  DecodeStatus S = MCDisassembler::Success;
1569
1570  unsigned Rn = fieldFromInstruction(Val, 13, 4);
1571  unsigned Rm = fieldFromInstruction(Val,  0, 4);
1572  unsigned type = fieldFromInstruction(Val, 5, 2);
1573  unsigned imm = fieldFromInstruction(Val, 7, 5);
1574  unsigned U = fieldFromInstruction(Val, 12, 1);
1575
1576  ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1577  switch (type) {
1578    case 0:
1579      ShOp = ARM_AM::lsl;
1580      break;
1581    case 1:
1582      ShOp = ARM_AM::lsr;
1583      break;
1584    case 2:
1585      ShOp = ARM_AM::asr;
1586      break;
1587    case 3:
1588      ShOp = ARM_AM::ror;
1589      break;
1590  }
1591
1592  if (ShOp == ARM_AM::ror && imm == 0)
1593    ShOp = ARM_AM::rrx;
1594
1595  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1596    return MCDisassembler::Fail;
1597  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1598    return MCDisassembler::Fail;
1599  unsigned shift;
1600  if (U)
1601    shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1602  else
1603    shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1604  Inst.addOperand(MCOperand::createImm(shift));
1605
1606  return S;
1607}
1608
1609static DecodeStatus
1610DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1611                           uint64_t Address, const void *Decoder) {
1612  DecodeStatus S = MCDisassembler::Success;
1613
1614  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1615  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1616  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1617  unsigned type = fieldFromInstruction(Insn, 22, 1);
1618  unsigned imm = fieldFromInstruction(Insn, 8, 4);
1619  unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1620  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1621  unsigned W = fieldFromInstruction(Insn, 21, 1);
1622  unsigned P = fieldFromInstruction(Insn, 24, 1);
1623  unsigned Rt2 = Rt + 1;
1624
1625  bool writeback = (W == 1) | (P == 0);
1626
1627  // For {LD,ST}RD, Rt must be even, else undefined.
1628  switch (Inst.getOpcode()) {
1629    case ARM::STRD:
1630    case ARM::STRD_PRE:
1631    case ARM::STRD_POST:
1632    case ARM::LDRD:
1633    case ARM::LDRD_PRE:
1634    case ARM::LDRD_POST:
1635      if (Rt & 0x1) S = MCDisassembler::SoftFail;
1636      break;
1637    default:
1638      break;
1639  }
1640  switch (Inst.getOpcode()) {
1641    case ARM::STRD:
1642    case ARM::STRD_PRE:
1643    case ARM::STRD_POST:
1644      if (P == 0 && W == 1)
1645        S = MCDisassembler::SoftFail;
1646
1647      if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1648        S = MCDisassembler::SoftFail;
1649      if (type && Rm == 15)
1650        S = MCDisassembler::SoftFail;
1651      if (Rt2 == 15)
1652        S = MCDisassembler::SoftFail;
1653      if (!type && fieldFromInstruction(Insn, 8, 4))
1654        S = MCDisassembler::SoftFail;
1655      break;
1656    case ARM::STRH:
1657    case ARM::STRH_PRE:
1658    case ARM::STRH_POST:
1659      if (Rt == 15)
1660        S = MCDisassembler::SoftFail;
1661      if (writeback && (Rn == 15 || Rn == Rt))
1662        S = MCDisassembler::SoftFail;
1663      if (!type && Rm == 15)
1664        S = MCDisassembler::SoftFail;
1665      break;
1666    case ARM::LDRD:
1667    case ARM::LDRD_PRE:
1668    case ARM::LDRD_POST:
1669      if (type && Rn == 15){
1670        if (Rt2 == 15)
1671          S = MCDisassembler::SoftFail;
1672        break;
1673      }
1674      if (P == 0 && W == 1)
1675        S = MCDisassembler::SoftFail;
1676      if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1677        S = MCDisassembler::SoftFail;
1678      if (!type && writeback && Rn == 15)
1679        S = MCDisassembler::SoftFail;
1680      if (writeback && (Rn == Rt || Rn == Rt2))
1681        S = MCDisassembler::SoftFail;
1682      break;
1683    case ARM::LDRH:
1684    case ARM::LDRH_PRE:
1685    case ARM::LDRH_POST:
1686      if (type && Rn == 15){
1687        if (Rt == 15)
1688          S = MCDisassembler::SoftFail;
1689        break;
1690      }
1691      if (Rt == 15)
1692        S = MCDisassembler::SoftFail;
1693      if (!type && Rm == 15)
1694        S = MCDisassembler::SoftFail;
1695      if (!type && writeback && (Rn == 15 || Rn == Rt))
1696        S = MCDisassembler::SoftFail;
1697      break;
1698    case ARM::LDRSH:
1699    case ARM::LDRSH_PRE:
1700    case ARM::LDRSH_POST:
1701    case ARM::LDRSB:
1702    case ARM::LDRSB_PRE:
1703    case ARM::LDRSB_POST:
1704      if (type && Rn == 15){
1705        if (Rt == 15)
1706          S = MCDisassembler::SoftFail;
1707        break;
1708      }
1709      if (type && (Rt == 15 || (writeback && Rn == Rt)))
1710        S = MCDisassembler::SoftFail;
1711      if (!type && (Rt == 15 || Rm == 15))
1712        S = MCDisassembler::SoftFail;
1713      if (!type && writeback && (Rn == 15 || Rn == Rt))
1714        S = MCDisassembler::SoftFail;
1715      break;
1716    default:
1717      break;
1718  }
1719
1720  if (writeback) { // Writeback
1721    if (P)
1722      U |= ARMII::IndexModePre << 9;
1723    else
1724      U |= ARMII::IndexModePost << 9;
1725
1726    // On stores, the writeback operand precedes Rt.
1727    switch (Inst.getOpcode()) {
1728    case ARM::STRD:
1729    case ARM::STRD_PRE:
1730    case ARM::STRD_POST:
1731    case ARM::STRH:
1732    case ARM::STRH_PRE:
1733    case ARM::STRH_POST:
1734      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1735        return MCDisassembler::Fail;
1736      break;
1737    default:
1738      break;
1739    }
1740  }
1741
1742  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1743    return MCDisassembler::Fail;
1744  switch (Inst.getOpcode()) {
1745    case ARM::STRD:
1746    case ARM::STRD_PRE:
1747    case ARM::STRD_POST:
1748    case ARM::LDRD:
1749    case ARM::LDRD_PRE:
1750    case ARM::LDRD_POST:
1751      if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1752        return MCDisassembler::Fail;
1753      break;
1754    default:
1755      break;
1756  }
1757
1758  if (writeback) {
1759    // On loads, the writeback operand comes after Rt.
1760    switch (Inst.getOpcode()) {
1761    case ARM::LDRD:
1762    case ARM::LDRD_PRE:
1763    case ARM::LDRD_POST:
1764    case ARM::LDRH:
1765    case ARM::LDRH_PRE:
1766    case ARM::LDRH_POST:
1767    case ARM::LDRSH:
1768    case ARM::LDRSH_PRE:
1769    case ARM::LDRSH_POST:
1770    case ARM::LDRSB:
1771    case ARM::LDRSB_PRE:
1772    case ARM::LDRSB_POST:
1773    case ARM::LDRHTr:
1774    case ARM::LDRSBTr:
1775      if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1776        return MCDisassembler::Fail;
1777      break;
1778    default:
1779      break;
1780    }
1781  }
1782
1783  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784    return MCDisassembler::Fail;
1785
1786  if (type) {
1787    Inst.addOperand(MCOperand::createReg(0));
1788    Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1789  } else {
1790    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1791    return MCDisassembler::Fail;
1792    Inst.addOperand(MCOperand::createImm(U));
1793  }
1794
1795  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1796    return MCDisassembler::Fail;
1797
1798  return S;
1799}
1800
1801static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1802                                 uint64_t Address, const void *Decoder) {
1803  DecodeStatus S = MCDisassembler::Success;
1804
1805  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1806  unsigned mode = fieldFromInstruction(Insn, 23, 2);
1807
1808  switch (mode) {
1809    case 0:
1810      mode = ARM_AM::da;
1811      break;
1812    case 1:
1813      mode = ARM_AM::ia;
1814      break;
1815    case 2:
1816      mode = ARM_AM::db;
1817      break;
1818    case 3:
1819      mode = ARM_AM::ib;
1820      break;
1821  }
1822
1823  Inst.addOperand(MCOperand::createImm(mode));
1824  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1825    return MCDisassembler::Fail;
1826
1827  return S;
1828}
1829
1830static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1831                               uint64_t Address, const void *Decoder) {
1832  DecodeStatus S = MCDisassembler::Success;
1833
1834  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1835  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1836  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1837  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1838
1839  if (pred == 0xF)
1840    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1841
1842  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1843    return MCDisassembler::Fail;
1844  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1845    return MCDisassembler::Fail;
1846  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1847    return MCDisassembler::Fail;
1848  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1849    return MCDisassembler::Fail;
1850  return S;
1851}
1852
1853static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1854                                  unsigned Insn,
1855                                  uint64_t Address, const void *Decoder) {
1856  DecodeStatus S = MCDisassembler::Success;
1857
1858  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1859  unsigned pred = fieldFromInstruction(Insn, 28, 4);
1860  unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1861
1862  if (pred == 0xF) {
1863    // Ambiguous with RFE and SRS
1864    switch (Inst.getOpcode()) {
1865      case ARM::LDMDA:
1866        Inst.setOpcode(ARM::RFEDA);
1867        break;
1868      case ARM::LDMDA_UPD:
1869        Inst.setOpcode(ARM::RFEDA_UPD);
1870        break;
1871      case ARM::LDMDB:
1872        Inst.setOpcode(ARM::RFEDB);
1873        break;
1874      case ARM::LDMDB_UPD:
1875        Inst.setOpcode(ARM::RFEDB_UPD);
1876        break;
1877      case ARM::LDMIA:
1878        Inst.setOpcode(ARM::RFEIA);
1879        break;
1880      case ARM::LDMIA_UPD:
1881        Inst.setOpcode(ARM::RFEIA_UPD);
1882        break;
1883      case ARM::LDMIB:
1884        Inst.setOpcode(ARM::RFEIB);
1885        break;
1886      case ARM::LDMIB_UPD:
1887        Inst.setOpcode(ARM::RFEIB_UPD);
1888        break;
1889      case ARM::STMDA:
1890        Inst.setOpcode(ARM::SRSDA);
1891        break;
1892      case ARM::STMDA_UPD:
1893        Inst.setOpcode(ARM::SRSDA_UPD);
1894        break;
1895      case ARM::STMDB:
1896        Inst.setOpcode(ARM::SRSDB);
1897        break;
1898      case ARM::STMDB_UPD:
1899        Inst.setOpcode(ARM::SRSDB_UPD);
1900        break;
1901      case ARM::STMIA:
1902        Inst.setOpcode(ARM::SRSIA);
1903        break;
1904      case ARM::STMIA_UPD:
1905        Inst.setOpcode(ARM::SRSIA_UPD);
1906        break;
1907      case ARM::STMIB:
1908        Inst.setOpcode(ARM::SRSIB);
1909        break;
1910      case ARM::STMIB_UPD:
1911        Inst.setOpcode(ARM::SRSIB_UPD);
1912        break;
1913      default:
1914        return MCDisassembler::Fail;
1915    }
1916
1917    // For stores (which become SRS's, the only operand is the mode.
1918    if (fieldFromInstruction(Insn, 20, 1) == 0) {
1919      // Check SRS encoding constraints
1920      if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1921            fieldFromInstruction(Insn, 20, 1) == 0))
1922        return MCDisassembler::Fail;
1923
1924      Inst.addOperand(
1925          MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1926      return S;
1927    }
1928
1929    return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1930  }
1931
1932  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1933    return MCDisassembler::Fail;
1934  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1935    return MCDisassembler::Fail; // Tied
1936  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1937    return MCDisassembler::Fail;
1938  if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1939    return MCDisassembler::Fail;
1940
1941  return S;
1942}
1943
1944static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1945                                 uint64_t Address, const void *Decoder) {
1946  unsigned imod = fieldFromInstruction(Insn, 18, 2);
1947  unsigned M = fieldFromInstruction(Insn, 17, 1);
1948  unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1949  unsigned mode = fieldFromInstruction(Insn, 0, 5);
1950
1951  DecodeStatus S = MCDisassembler::Success;
1952
1953  // This decoder is called from multiple location that do not check
1954  // the full encoding is valid before they do.
1955  if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1956      fieldFromInstruction(Insn, 16, 1) != 0 ||
1957      fieldFromInstruction(Insn, 20, 8) != 0x10)
1958    return MCDisassembler::Fail;
1959
1960  // imod == '01' --> UNPREDICTABLE
1961  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1962  // return failure here.  The '01' imod value is unprintable, so there's
1963  // nothing useful we could do even if we returned UNPREDICTABLE.
1964
1965  if (imod == 1) return MCDisassembler::Fail;
1966
1967  if (imod && M) {
1968    Inst.setOpcode(ARM::CPS3p);
1969    Inst.addOperand(MCOperand::createImm(imod));
1970    Inst.addOperand(MCOperand::createImm(iflags));
1971    Inst.addOperand(MCOperand::createImm(mode));
1972  } else if (imod && !M) {
1973    Inst.setOpcode(ARM::CPS2p);
1974    Inst.addOperand(MCOperand::createImm(imod));
1975    Inst.addOperand(MCOperand::createImm(iflags));
1976    if (mode) S = MCDisassembler::SoftFail;
1977  } else if (!imod && M) {
1978    Inst.setOpcode(ARM::CPS1p);
1979    Inst.addOperand(MCOperand::createImm(mode));
1980    if (iflags) S = MCDisassembler::SoftFail;
1981  } else {
1982    // imod == '00' && M == '0' --> UNPREDICTABLE
1983    Inst.setOpcode(ARM::CPS1p);
1984    Inst.addOperand(MCOperand::createImm(mode));
1985    S = MCDisassembler::SoftFail;
1986  }
1987
1988  return S;
1989}
1990
1991static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1992                                 uint64_t Address, const void *Decoder) {
1993  unsigned imod = fieldFromInstruction(Insn, 9, 2);
1994  unsigned M = fieldFromInstruction(Insn, 8, 1);
1995  unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1996  unsigned mode = fieldFromInstruction(Insn, 0, 5);
1997
1998  DecodeStatus S = MCDisassembler::Success;
1999
2000  // imod == '01' --> UNPREDICTABLE
2001  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2002  // return failure here.  The '01' imod value is unprintable, so there's
2003  // nothing useful we could do even if we returned UNPREDICTABLE.
2004
2005  if (imod == 1) return MCDisassembler::Fail;
2006
2007  if (imod && M) {
2008    Inst.setOpcode(ARM::t2CPS3p);
2009    Inst.addOperand(MCOperand::createImm(imod));
2010    Inst.addOperand(MCOperand::createImm(iflags));
2011    Inst.addOperand(MCOperand::createImm(mode));
2012  } else if (imod && !M) {
2013    Inst.setOpcode(ARM::t2CPS2p);
2014    Inst.addOperand(MCOperand::createImm(imod));
2015    Inst.addOperand(MCOperand::createImm(iflags));
2016    if (mode) S = MCDisassembler::SoftFail;
2017  } else if (!imod && M) {
2018    Inst.setOpcode(ARM::t2CPS1p);
2019    Inst.addOperand(MCOperand::createImm(mode));
2020    if (iflags) S = MCDisassembler::SoftFail;
2021  } else {
2022    // imod == '00' && M == '0' --> this is a HINT instruction
2023    int imm = fieldFromInstruction(Insn, 0, 8);
2024    // HINT are defined only for immediate in [0..4]
2025    if(imm > 4) return MCDisassembler::Fail;
2026    Inst.setOpcode(ARM::t2HINT);
2027    Inst.addOperand(MCOperand::createImm(imm));
2028  }
2029
2030  return S;
2031}
2032
2033static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2034                                 uint64_t Address, const void *Decoder) {
2035  DecodeStatus S = MCDisassembler::Success;
2036
2037  unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2038  unsigned imm = 0;
2039
2040  imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2041  imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2042  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2043  imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2044
2045  if (Inst.getOpcode() == ARM::t2MOVTi16)
2046    if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2047      return MCDisassembler::Fail;
2048  if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2049    return MCDisassembler::Fail;
2050
2051  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2052    Inst.addOperand(MCOperand::createImm(imm));
2053
2054  return S;
2055}
2056
2057static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2058                                 uint64_t Address, const void *Decoder) {
2059  DecodeStatus S = MCDisassembler::Success;
2060
2061  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2062  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2063  unsigned imm = 0;
2064
2065  imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2066  imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2067
2068  if (Inst.getOpcode() == ARM::MOVTi16)
2069    if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2070      return MCDisassembler::Fail;
2071
2072  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2073    return MCDisassembler::Fail;
2074
2075  if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2076    Inst.addOperand(MCOperand::createImm(imm));
2077
2078  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2079    return MCDisassembler::Fail;
2080
2081  return S;
2082}
2083
2084static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2085                                 uint64_t Address, const void *Decoder) {
2086  DecodeStatus S = MCDisassembler::Success;
2087
2088  unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2089  unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2090  unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2091  unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2092  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2093
2094  if (pred == 0xF)
2095    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2096
2097  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2098    return MCDisassembler::Fail;
2099  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2100    return MCDisassembler::Fail;
2101  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2102    return MCDisassembler::Fail;
2103  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2104    return MCDisassembler::Fail;
2105
2106  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2107    return MCDisassembler::Fail;
2108
2109  return S;
2110}
2111
2112static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2113                                  uint64_t Address, const void *Decoder) {
2114  DecodeStatus S = MCDisassembler::Success;
2115
2116  unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2117  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2118  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2119
2120  if (Pred == 0xF)
2121    return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2122
2123  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2124    return MCDisassembler::Fail;
2125  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2126    return MCDisassembler::Fail;
2127  if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2128    return MCDisassembler::Fail;
2129
2130  return S;
2131}
2132
2133static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2134                                  uint64_t Address, const void *Decoder) {
2135  DecodeStatus S = MCDisassembler::Success;
2136
2137  unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2138
2139  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2140  const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2141
2142  if (!FeatureBits[ARM::HasV8_1aOps] ||
2143      !FeatureBits[ARM::HasV8Ops])
2144    return MCDisassembler::Fail;
2145
2146  // Decoder can be called from DecodeTST, which does not check the full
2147  // encoding is valid.
2148  if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2149      fieldFromInstruction(Insn, 4,4) != 0)
2150    return MCDisassembler::Fail;
2151  if (fieldFromInstruction(Insn, 10,10) != 0 ||
2152      fieldFromInstruction(Insn, 0,4) != 0)
2153    S = MCDisassembler::SoftFail;
2154
2155  Inst.setOpcode(ARM::SETPAN);
2156  Inst.addOperand(MCOperand::createImm(Imm));
2157
2158  return S;
2159}
2160
2161static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2162                           uint64_t Address, const void *Decoder) {
2163  DecodeStatus S = MCDisassembler::Success;
2164
2165  unsigned add = fieldFromInstruction(Val, 12, 1);
2166  unsigned imm = fieldFromInstruction(Val, 0, 12);
2167  unsigned Rn = fieldFromInstruction(Val, 13, 4);
2168
2169  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2170    return MCDisassembler::Fail;
2171
2172  if (!add) imm *= -1;
2173  if (imm == 0 && !add) imm = INT32_MIN;
2174  Inst.addOperand(MCOperand::createImm(imm));
2175  if (Rn == 15)
2176    tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2177
2178  return S;
2179}
2180
2181static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2182                                   uint64_t Address, const void *Decoder) {
2183  DecodeStatus S = MCDisassembler::Success;
2184
2185  unsigned Rn = fieldFromInstruction(Val, 9, 4);
2186  unsigned U = fieldFromInstruction(Val, 8, 1);
2187  unsigned imm = fieldFromInstruction(Val, 0, 8);
2188
2189  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2190    return MCDisassembler::Fail;
2191
2192  if (U)
2193    Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2194  else
2195    Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2196
2197  return S;
2198}
2199
2200static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2201                                   uint64_t Address, const void *Decoder) {
2202  return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2203}
2204
2205static DecodeStatus
2206DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2207                     uint64_t Address, const void *Decoder) {
2208  DecodeStatus Status = MCDisassembler::Success;
2209
2210  // Note the J1 and J2 values are from the encoded instruction.  So here
2211  // change them to I1 and I2 values via as documented:
2212  // I1 = NOT(J1 EOR S);
2213  // I2 = NOT(J2 EOR S);
2214  // and build the imm32 with one trailing zero as documented:
2215  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2216  unsigned S = fieldFromInstruction(Insn, 26, 1);
2217  unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2218  unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2219  unsigned I1 = !(J1 ^ S);
2220  unsigned I2 = !(J2 ^ S);
2221  unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2222  unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2223  unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2224  int imm32 = SignExtend32<25>(tmp << 1);
2225  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2226                                true, 4, Inst, Decoder))
2227    Inst.addOperand(MCOperand::createImm(imm32));
2228
2229  return Status;
2230}
2231
2232static DecodeStatus
2233DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2234                           uint64_t Address, const void *Decoder) {
2235  DecodeStatus S = MCDisassembler::Success;
2236
2237  unsigned pred = fieldFromInstruction(Insn, 28, 4);
2238  unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2239
2240  if (pred == 0xF) {
2241    Inst.setOpcode(ARM::BLXi);
2242    imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2243    if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2244                                  true, 4, Inst, Decoder))
2245    Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2246    return S;
2247  }
2248
2249  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2250                                true, 4, Inst, Decoder))
2251    Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2252  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2253    return MCDisassembler::Fail;
2254
2255  return S;
2256}
2257
2258
2259static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2260                                   uint64_t Address, const void *Decoder) {
2261  DecodeStatus S = MCDisassembler::Success;
2262
2263  unsigned Rm = fieldFromInstruction(Val, 0, 4);
2264  unsigned align = fieldFromInstruction(Val, 4, 2);
2265
2266  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2267    return MCDisassembler::Fail;
2268  if (!align)
2269    Inst.addOperand(MCOperand::createImm(0));
2270  else
2271    Inst.addOperand(MCOperand::createImm(4 << align));
2272
2273  return S;
2274}
2275
2276static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2277                                   uint64_t Address, const void *Decoder) {
2278  DecodeStatus S = MCDisassembler::Success;
2279
2280  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2281  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2282  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2283  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2284  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2285  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2286
2287  // First output register
2288  switch (Inst.getOpcode()) {
2289  case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2290  case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2291  case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2292  case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2293  case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2294  case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2295  case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2296  case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2297  case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2298    if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2299      return MCDisassembler::Fail;
2300    break;
2301  case ARM::VLD2b16:
2302  case ARM::VLD2b32:
2303  case ARM::VLD2b8:
2304  case ARM::VLD2b16wb_fixed:
2305  case ARM::VLD2b16wb_register:
2306  case ARM::VLD2b32wb_fixed:
2307  case ARM::VLD2b32wb_register:
2308  case ARM::VLD2b8wb_fixed:
2309  case ARM::VLD2b8wb_register:
2310    if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2311      return MCDisassembler::Fail;
2312    break;
2313  default:
2314    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2315      return MCDisassembler::Fail;
2316  }
2317
2318  // Second output register
2319  switch (Inst.getOpcode()) {
2320    case ARM::VLD3d8:
2321    case ARM::VLD3d16:
2322    case ARM::VLD3d32:
2323    case ARM::VLD3d8_UPD:
2324    case ARM::VLD3d16_UPD:
2325    case ARM::VLD3d32_UPD:
2326    case ARM::VLD4d8:
2327    case ARM::VLD4d16:
2328    case ARM::VLD4d32:
2329    case ARM::VLD4d8_UPD:
2330    case ARM::VLD4d16_UPD:
2331    case ARM::VLD4d32_UPD:
2332      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2333        return MCDisassembler::Fail;
2334      break;
2335    case ARM::VLD3q8:
2336    case ARM::VLD3q16:
2337    case ARM::VLD3q32:
2338    case ARM::VLD3q8_UPD:
2339    case ARM::VLD3q16_UPD:
2340    case ARM::VLD3q32_UPD:
2341    case ARM::VLD4q8:
2342    case ARM::VLD4q16:
2343    case ARM::VLD4q32:
2344    case ARM::VLD4q8_UPD:
2345    case ARM::VLD4q16_UPD:
2346    case ARM::VLD4q32_UPD:
2347      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2348        return MCDisassembler::Fail;
2349    default:
2350      break;
2351  }
2352
2353  // Third output register
2354  switch(Inst.getOpcode()) {
2355    case ARM::VLD3d8:
2356    case ARM::VLD3d16:
2357    case ARM::VLD3d32:
2358    case ARM::VLD3d8_UPD:
2359    case ARM::VLD3d16_UPD:
2360    case ARM::VLD3d32_UPD:
2361    case ARM::VLD4d8:
2362    case ARM::VLD4d16:
2363    case ARM::VLD4d32:
2364    case ARM::VLD4d8_UPD:
2365    case ARM::VLD4d16_UPD:
2366    case ARM::VLD4d32_UPD:
2367      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2368        return MCDisassembler::Fail;
2369      break;
2370    case ARM::VLD3q8:
2371    case ARM::VLD3q16:
2372    case ARM::VLD3q32:
2373    case ARM::VLD3q8_UPD:
2374    case ARM::VLD3q16_UPD:
2375    case ARM::VLD3q32_UPD:
2376    case ARM::VLD4q8:
2377    case ARM::VLD4q16:
2378    case ARM::VLD4q32:
2379    case ARM::VLD4q8_UPD:
2380    case ARM::VLD4q16_UPD:
2381    case ARM::VLD4q32_UPD:
2382      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2383        return MCDisassembler::Fail;
2384      break;
2385    default:
2386      break;
2387  }
2388
2389  // Fourth output register
2390  switch (Inst.getOpcode()) {
2391    case ARM::VLD4d8:
2392    case ARM::VLD4d16:
2393    case ARM::VLD4d32:
2394    case ARM::VLD4d8_UPD:
2395    case ARM::VLD4d16_UPD:
2396    case ARM::VLD4d32_UPD:
2397      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2398        return MCDisassembler::Fail;
2399      break;
2400    case ARM::VLD4q8:
2401    case ARM::VLD4q16:
2402    case ARM::VLD4q32:
2403    case ARM::VLD4q8_UPD:
2404    case ARM::VLD4q16_UPD:
2405    case ARM::VLD4q32_UPD:
2406      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2407        return MCDisassembler::Fail;
2408      break;
2409    default:
2410      break;
2411  }
2412
2413  // Writeback operand
2414  switch (Inst.getOpcode()) {
2415    case ARM::VLD1d8wb_fixed:
2416    case ARM::VLD1d16wb_fixed:
2417    case ARM::VLD1d32wb_fixed:
2418    case ARM::VLD1d64wb_fixed:
2419    case ARM::VLD1d8wb_register:
2420    case ARM::VLD1d16wb_register:
2421    case ARM::VLD1d32wb_register:
2422    case ARM::VLD1d64wb_register:
2423    case ARM::VLD1q8wb_fixed:
2424    case ARM::VLD1q16wb_fixed:
2425    case ARM::VLD1q32wb_fixed:
2426    case ARM::VLD1q64wb_fixed:
2427    case ARM::VLD1q8wb_register:
2428    case ARM::VLD1q16wb_register:
2429    case ARM::VLD1q32wb_register:
2430    case ARM::VLD1q64wb_register:
2431    case ARM::VLD1d8Twb_fixed:
2432    case ARM::VLD1d8Twb_register:
2433    case ARM::VLD1d16Twb_fixed:
2434    case ARM::VLD1d16Twb_register:
2435    case ARM::VLD1d32Twb_fixed:
2436    case ARM::VLD1d32Twb_register:
2437    case ARM::VLD1d64Twb_fixed:
2438    case ARM::VLD1d64Twb_register:
2439    case ARM::VLD1d8Qwb_fixed:
2440    case ARM::VLD1d8Qwb_register:
2441    case ARM::VLD1d16Qwb_fixed:
2442    case ARM::VLD1d16Qwb_register:
2443    case ARM::VLD1d32Qwb_fixed:
2444    case ARM::VLD1d32Qwb_register:
2445    case ARM::VLD1d64Qwb_fixed:
2446    case ARM::VLD1d64Qwb_register:
2447    case ARM::VLD2d8wb_fixed:
2448    case ARM::VLD2d16wb_fixed:
2449    case ARM::VLD2d32wb_fixed:
2450    case ARM::VLD2q8wb_fixed:
2451    case ARM::VLD2q16wb_fixed:
2452    case ARM::VLD2q32wb_fixed:
2453    case ARM::VLD2d8wb_register:
2454    case ARM::VLD2d16wb_register:
2455    case ARM::VLD2d32wb_register:
2456    case ARM::VLD2q8wb_register:
2457    case ARM::VLD2q16wb_register:
2458    case ARM::VLD2q32wb_register:
2459    case ARM::VLD2b8wb_fixed:
2460    case ARM::VLD2b16wb_fixed:
2461    case ARM::VLD2b32wb_fixed:
2462    case ARM::VLD2b8wb_register:
2463    case ARM::VLD2b16wb_register:
2464    case ARM::VLD2b32wb_register:
2465      Inst.addOperand(MCOperand::createImm(0));
2466      break;
2467    case ARM::VLD3d8_UPD:
2468    case ARM::VLD3d16_UPD:
2469    case ARM::VLD3d32_UPD:
2470    case ARM::VLD3q8_UPD:
2471    case ARM::VLD3q16_UPD:
2472    case ARM::VLD3q32_UPD:
2473    case ARM::VLD4d8_UPD:
2474    case ARM::VLD4d16_UPD:
2475    case ARM::VLD4d32_UPD:
2476    case ARM::VLD4q8_UPD:
2477    case ARM::VLD4q16_UPD:
2478    case ARM::VLD4q32_UPD:
2479      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2480        return MCDisassembler::Fail;
2481      break;
2482    default:
2483      break;
2484  }
2485
2486  // AddrMode6 Base (register+alignment)
2487  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2488    return MCDisassembler::Fail;
2489
2490  // AddrMode6 Offset (register)
2491  switch (Inst.getOpcode()) {
2492  default:
2493    // The below have been updated to have explicit am6offset split
2494    // between fixed and register offset. For those instructions not
2495    // yet updated, we need to add an additional reg0 operand for the
2496    // fixed variant.
2497    //
2498    // The fixed offset encodes as Rm == 0xd, so we check for that.
2499    if (Rm == 0xd) {
2500      Inst.addOperand(MCOperand::createReg(0));
2501      break;
2502    }
2503    // Fall through to handle the register offset variant.
2504  case ARM::VLD1d8wb_fixed:
2505  case ARM::VLD1d16wb_fixed:
2506  case ARM::VLD1d32wb_fixed:
2507  case ARM::VLD1d64wb_fixed:
2508  case ARM::VLD1d8Twb_fixed:
2509  case ARM::VLD1d16Twb_fixed:
2510  case ARM::VLD1d32Twb_fixed:
2511  case ARM::VLD1d64Twb_fixed:
2512  case ARM::VLD1d8Qwb_fixed:
2513  case ARM::VLD1d16Qwb_fixed:
2514  case ARM::VLD1d32Qwb_fixed:
2515  case ARM::VLD1d64Qwb_fixed:
2516  case ARM::VLD1d8wb_register:
2517  case ARM::VLD1d16wb_register:
2518  case ARM::VLD1d32wb_register:
2519  case ARM::VLD1d64wb_register:
2520  case ARM::VLD1q8wb_fixed:
2521  case ARM::VLD1q16wb_fixed:
2522  case ARM::VLD1q32wb_fixed:
2523  case ARM::VLD1q64wb_fixed:
2524  case ARM::VLD1q8wb_register:
2525  case ARM::VLD1q16wb_register:
2526  case ARM::VLD1q32wb_register:
2527  case ARM::VLD1q64wb_register:
2528    // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2529    // variant encodes Rm == 0xf. Anything else is a register offset post-
2530    // increment and we need to add the register operand to the instruction.
2531    if (Rm != 0xD && Rm != 0xF &&
2532        !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2533      return MCDisassembler::Fail;
2534    break;
2535  case ARM::VLD2d8wb_fixed:
2536  case ARM::VLD2d16wb_fixed:
2537  case ARM::VLD2d32wb_fixed:
2538  case ARM::VLD2b8wb_fixed:
2539  case ARM::VLD2b16wb_fixed:
2540  case ARM::VLD2b32wb_fixed:
2541  case ARM::VLD2q8wb_fixed:
2542  case ARM::VLD2q16wb_fixed:
2543  case ARM::VLD2q32wb_fixed:
2544    break;
2545  }
2546
2547  return S;
2548}
2549
2550static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2551                                   uint64_t Address, const void *Decoder) {
2552  unsigned type = fieldFromInstruction(Insn, 8, 4);
2553  unsigned align = fieldFromInstruction(Insn, 4, 2);
2554  if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2555  if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2556  if (type == 10 && align == 3) return MCDisassembler::Fail;
2557
2558  unsigned load = fieldFromInstruction(Insn, 21, 1);
2559  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2560              : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2561}
2562
2563static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2564                                   uint64_t Address, const void *Decoder) {
2565  unsigned size = fieldFromInstruction(Insn, 6, 2);
2566  if (size == 3) return MCDisassembler::Fail;
2567
2568  unsigned type = fieldFromInstruction(Insn, 8, 4);
2569  unsigned align = fieldFromInstruction(Insn, 4, 2);
2570  if (type == 8 && align == 3) return MCDisassembler::Fail;
2571  if (type == 9 && align == 3) return MCDisassembler::Fail;
2572
2573  unsigned load = fieldFromInstruction(Insn, 21, 1);
2574  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2575              : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2576}
2577
2578static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2579                                   uint64_t Address, const void *Decoder) {
2580  unsigned size = fieldFromInstruction(Insn, 6, 2);
2581  if (size == 3) return MCDisassembler::Fail;
2582
2583  unsigned align = fieldFromInstruction(Insn, 4, 2);
2584  if (align & 2) return MCDisassembler::Fail;
2585
2586  unsigned load = fieldFromInstruction(Insn, 21, 1);
2587  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2588              : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2589}
2590
2591static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2592                                   uint64_t Address, const void *Decoder) {
2593  unsigned size = fieldFromInstruction(Insn, 6, 2);
2594  if (size == 3) return MCDisassembler::Fail;
2595
2596  unsigned load = fieldFromInstruction(Insn, 21, 1);
2597  return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2598              : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2599}
2600
2601static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2602                                 uint64_t Address, const void *Decoder) {
2603  DecodeStatus S = MCDisassembler::Success;
2604
2605  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2606  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2607  unsigned wb = fieldFromInstruction(Insn, 16, 4);
2608  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2609  Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2610  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2611
2612  // Writeback Operand
2613  switch (Inst.getOpcode()) {
2614    case ARM::VST1d8wb_fixed:
2615    case ARM::VST1d16wb_fixed:
2616    case ARM::VST1d32wb_fixed:
2617    case ARM::VST1d64wb_fixed:
2618    case ARM::VST1d8wb_register:
2619    case ARM::VST1d16wb_register:
2620    case ARM::VST1d32wb_register:
2621    case ARM::VST1d64wb_register:
2622    case ARM::VST1q8wb_fixed:
2623    case ARM::VST1q16wb_fixed:
2624    case ARM::VST1q32wb_fixed:
2625    case ARM::VST1q64wb_fixed:
2626    case ARM::VST1q8wb_register:
2627    case ARM::VST1q16wb_register:
2628    case ARM::VST1q32wb_register:
2629    case ARM::VST1q64wb_register:
2630    case ARM::VST1d8Twb_fixed:
2631    case ARM::VST1d16Twb_fixed:
2632    case ARM::VST1d32Twb_fixed:
2633    case ARM::VST1d64Twb_fixed:
2634    case ARM::VST1d8Twb_register:
2635    case ARM::VST1d16Twb_register:
2636    case ARM::VST1d32Twb_register:
2637    case ARM::VST1d64Twb_register:
2638    case ARM::VST1d8Qwb_fixed:
2639    case ARM::VST1d16Qwb_fixed:
2640    case ARM::VST1d32Qwb_fixed:
2641    case ARM::VST1d64Qwb_fixed:
2642    case ARM::VST1d8Qwb_register:
2643    case ARM::VST1d16Qwb_register:
2644    case ARM::VST1d32Qwb_register:
2645    case ARM::VST1d64Qwb_register:
2646    case ARM::VST2d8wb_fixed:
2647    case ARM::VST2d16wb_fixed:
2648    case ARM::VST2d32wb_fixed:
2649    case ARM::VST2d8wb_register:
2650    case ARM::VST2d16wb_register:
2651    case ARM::VST2d32wb_register:
2652    case ARM::VST2q8wb_fixed:
2653    case ARM::VST2q16wb_fixed:
2654    case ARM::VST2q32wb_fixed:
2655    case ARM::VST2q8wb_register:
2656    case ARM::VST2q16wb_register:
2657    case ARM::VST2q32wb_register:
2658    case ARM::VST2b8wb_fixed:
2659    case ARM::VST2b16wb_fixed:
2660    case ARM::VST2b32wb_fixed:
2661    case ARM::VST2b8wb_register:
2662    case ARM::VST2b16wb_register:
2663    case ARM::VST2b32wb_register:
2664      if (Rm == 0xF)
2665        return MCDisassembler::Fail;
2666      Inst.addOperand(MCOperand::createImm(0));
2667      break;
2668    case ARM::VST3d8_UPD:
2669    case ARM::VST3d16_UPD:
2670    case ARM::VST3d32_UPD:
2671    case ARM::VST3q8_UPD:
2672    case ARM::VST3q16_UPD:
2673    case ARM::VST3q32_UPD:
2674    case ARM::VST4d8_UPD:
2675    case ARM::VST4d16_UPD:
2676    case ARM::VST4d32_UPD:
2677    case ARM::VST4q8_UPD:
2678    case ARM::VST4q16_UPD:
2679    case ARM::VST4q32_UPD:
2680      if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2681        return MCDisassembler::Fail;
2682      break;
2683    default:
2684      break;
2685  }
2686
2687  // AddrMode6 Base (register+alignment)
2688  if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2689    return MCDisassembler::Fail;
2690
2691  // AddrMode6 Offset (register)
2692  switch (Inst.getOpcode()) {
2693    default:
2694      if (Rm == 0xD)
2695        Inst.addOperand(MCOperand::createReg(0));
2696      else if (Rm != 0xF) {
2697        if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2698          return MCDisassembler::Fail;
2699      }
2700      break;
2701    case ARM::VST1d8wb_fixed:
2702    case ARM::VST1d16wb_fixed:
2703    case ARM::VST1d32wb_fixed:
2704    case ARM::VST1d64wb_fixed:
2705    case ARM::VST1q8wb_fixed:
2706    case ARM::VST1q16wb_fixed:
2707    case ARM::VST1q32wb_fixed:
2708    case ARM::VST1q64wb_fixed:
2709    case ARM::VST1d8Twb_fixed:
2710    case ARM::VST1d16Twb_fixed:
2711    case ARM::VST1d32Twb_fixed:
2712    case ARM::VST1d64Twb_fixed:
2713    case ARM::VST1d8Qwb_fixed:
2714    case ARM::VST1d16Qwb_fixed:
2715    case ARM::VST1d32Qwb_fixed:
2716    case ARM::VST1d64Qwb_fixed:
2717    case ARM::VST2d8wb_fixed:
2718    case ARM::VST2d16wb_fixed:
2719    case ARM::VST2d32wb_fixed:
2720    case ARM::VST2q8wb_fixed:
2721    case ARM::VST2q16wb_fixed:
2722    case ARM::VST2q32wb_fixed:
2723    case ARM::VST2b8wb_fixed:
2724    case ARM::VST2b16wb_fixed:
2725    case ARM::VST2b32wb_fixed:
2726      break;
2727  }
2728
2729
2730  // First input register
2731  switch (Inst.getOpcode()) {
2732  case ARM::VST1q16:
2733  case ARM::VST1q32:
2734  case ARM::VST1q64:
2735  case ARM::VST1q8:
2736  case ARM::VST1q16wb_fixed:
2737  case ARM::VST1q16wb_register:
2738  case ARM::VST1q32wb_fixed:
2739  case ARM::VST1q32wb_register:
2740  case ARM::VST1q64wb_fixed:
2741  case ARM::VST1q64wb_register:
2742  case ARM::VST1q8wb_fixed:
2743  case ARM::VST1q8wb_register:
2744  case ARM::VST2d16:
2745  case ARM::VST2d32:
2746  case ARM::VST2d8:
2747  case ARM::VST2d16wb_fixed:
2748  case ARM::VST2d16wb_register:
2749  case ARM::VST2d32wb_fixed:
2750  case ARM::VST2d32wb_register:
2751  case ARM::VST2d8wb_fixed:
2752  case ARM::VST2d8wb_register:
2753    if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2754      return MCDisassembler::Fail;
2755    break;
2756  case ARM::VST2b16:
2757  case ARM::VST2b32:
2758  case ARM::VST2b8:
2759  case ARM::VST2b16wb_fixed:
2760  case ARM::VST2b16wb_register:
2761  case ARM::VST2b32wb_fixed:
2762  case ARM::VST2b32wb_register:
2763  case ARM::VST2b8wb_fixed:
2764  case ARM::VST2b8wb_register:
2765    if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2766      return MCDisassembler::Fail;
2767    break;
2768  default:
2769    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2770      return MCDisassembler::Fail;
2771  }
2772
2773  // Second input register
2774  switch (Inst.getOpcode()) {
2775    case ARM::VST3d8:
2776    case ARM::VST3d16:
2777    case ARM::VST3d32:
2778    case ARM::VST3d8_UPD:
2779    case ARM::VST3d16_UPD:
2780    case ARM::VST3d32_UPD:
2781    case ARM::VST4d8:
2782    case ARM::VST4d16:
2783    case ARM::VST4d32:
2784    case ARM::VST4d8_UPD:
2785    case ARM::VST4d16_UPD:
2786    case ARM::VST4d32_UPD:
2787      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2788        return MCDisassembler::Fail;
2789      break;
2790    case ARM::VST3q8:
2791    case ARM::VST3q16:
2792    case ARM::VST3q32:
2793    case ARM::VST3q8_UPD:
2794    case ARM::VST3q16_UPD:
2795    case ARM::VST3q32_UPD:
2796    case ARM::VST4q8:
2797    case ARM::VST4q16:
2798    case ARM::VST4q32:
2799    case ARM::VST4q8_UPD:
2800    case ARM::VST4q16_UPD:
2801    case ARM::VST4q32_UPD:
2802      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2803        return MCDisassembler::Fail;
2804      break;
2805    default:
2806      break;
2807  }
2808
2809  // Third input register
2810  switch (Inst.getOpcode()) {
2811    case ARM::VST3d8:
2812    case ARM::VST3d16:
2813    case ARM::VST3d32:
2814    case ARM::VST3d8_UPD:
2815    case ARM::VST3d16_UPD:
2816    case ARM::VST3d32_UPD:
2817    case ARM::VST4d8:
2818    case ARM::VST4d16:
2819    case ARM::VST4d32:
2820    case ARM::VST4d8_UPD:
2821    case ARM::VST4d16_UPD:
2822    case ARM::VST4d32_UPD:
2823      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2824        return MCDisassembler::Fail;
2825      break;
2826    case ARM::VST3q8:
2827    case ARM::VST3q16:
2828    case ARM::VST3q32:
2829    case ARM::VST3q8_UPD:
2830    case ARM::VST3q16_UPD:
2831    case ARM::VST3q32_UPD:
2832    case ARM::VST4q8:
2833    case ARM::VST4q16:
2834    case ARM::VST4q32:
2835    case ARM::VST4q8_UPD:
2836    case ARM::VST4q16_UPD:
2837    case ARM::VST4q32_UPD:
2838      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2839        return MCDisassembler::Fail;
2840      break;
2841    default:
2842      break;
2843  }
2844
2845  // Fourth input register
2846  switch (Inst.getOpcode()) {
2847    case ARM::VST4d8:
2848    case ARM::VST4d16:
2849    case ARM::VST4d32:
2850    case ARM::VST4d8_UPD:
2851    case ARM::VST4d16_UPD:
2852    case ARM::VST4d32_UPD:
2853      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2854        return MCDisassembler::Fail;
2855      break;
2856    case ARM::VST4q8:
2857    case ARM::VST4q16:
2858    case ARM::VST4q32:
2859    case ARM::VST4q8_UPD:
2860    case ARM::VST4q16_UPD:
2861    case ARM::VST4q32_UPD:
2862      if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2863        return MCDisassembler::Fail;
2864      break;
2865    default:
2866      break;
2867  }
2868
2869  return S;
2870}
2871
2872static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2873                                    uint64_t Address, const void *Decoder) {
2874  DecodeStatus S = MCDisassembler::Success;
2875
2876  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2877  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2878  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2879  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2880  unsigned align = fieldFromInstruction(Insn, 4, 1);
2881  unsigned size = fieldFromInstruction(Insn, 6, 2);
2882
2883  if (size == 0 && align == 1)
2884    return MCDisassembler::Fail;
2885  align *= (1 << size);
2886
2887  switch (Inst.getOpcode()) {
2888  case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2889  case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2890  case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2891  case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2892    if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2893      return MCDisassembler::Fail;
2894    break;
2895  default:
2896    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2897      return MCDisassembler::Fail;
2898    break;
2899  }
2900  if (Rm != 0xF) {
2901    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2902      return MCDisassembler::Fail;
2903  }
2904
2905  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2906    return MCDisassembler::Fail;
2907  Inst.addOperand(MCOperand::createImm(align));
2908
2909  // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2910  // variant encodes Rm == 0xf. Anything else is a register offset post-
2911  // increment and we need to add the register operand to the instruction.
2912  if (Rm != 0xD && Rm != 0xF &&
2913      !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2914    return MCDisassembler::Fail;
2915
2916  return S;
2917}
2918
2919static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2920                                    uint64_t Address, const void *Decoder) {
2921  DecodeStatus S = MCDisassembler::Success;
2922
2923  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2924  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2925  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2926  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2927  unsigned align = fieldFromInstruction(Insn, 4, 1);
2928  unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2929  align *= 2*size;
2930
2931  switch (Inst.getOpcode()) {
2932  case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2933  case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2934  case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2935  case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2936    if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2937      return MCDisassembler::Fail;
2938    break;
2939  case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2940  case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2941  case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2942  case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2943    if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2944      return MCDisassembler::Fail;
2945    break;
2946  default:
2947    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2948      return MCDisassembler::Fail;
2949    break;
2950  }
2951
2952  if (Rm != 0xF)
2953    Inst.addOperand(MCOperand::createImm(0));
2954
2955  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2956    return MCDisassembler::Fail;
2957  Inst.addOperand(MCOperand::createImm(align));
2958
2959  if (Rm != 0xD && Rm != 0xF) {
2960    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2961      return MCDisassembler::Fail;
2962  }
2963
2964  return S;
2965}
2966
2967static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2968                                    uint64_t Address, const void *Decoder) {
2969  DecodeStatus S = MCDisassembler::Success;
2970
2971  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2972  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2973  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2974  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2975  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2976
2977  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2978    return MCDisassembler::Fail;
2979  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2980    return MCDisassembler::Fail;
2981  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2982    return MCDisassembler::Fail;
2983  if (Rm != 0xF) {
2984    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2985      return MCDisassembler::Fail;
2986  }
2987
2988  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2989    return MCDisassembler::Fail;
2990  Inst.addOperand(MCOperand::createImm(0));
2991
2992  if (Rm == 0xD)
2993    Inst.addOperand(MCOperand::createReg(0));
2994  else if (Rm != 0xF) {
2995    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2996      return MCDisassembler::Fail;
2997  }
2998
2999  return S;
3000}
3001
3002static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3003                                    uint64_t Address, const void *Decoder) {
3004  DecodeStatus S = MCDisassembler::Success;
3005
3006  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3007  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3008  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3009  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3010  unsigned size = fieldFromInstruction(Insn, 6, 2);
3011  unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3012  unsigned align = fieldFromInstruction(Insn, 4, 1);
3013
3014  if (size == 0x3) {
3015    if (align == 0)
3016      return MCDisassembler::Fail;
3017    align = 16;
3018  } else {
3019    if (size == 2) {
3020      align *= 8;
3021    } else {
3022      size = 1 << size;
3023      align *= 4*size;
3024    }
3025  }
3026
3027  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3028    return MCDisassembler::Fail;
3029  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3030    return MCDisassembler::Fail;
3031  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3032    return MCDisassembler::Fail;
3033  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3034    return MCDisassembler::Fail;
3035  if (Rm != 0xF) {
3036    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3037      return MCDisassembler::Fail;
3038  }
3039
3040  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3041    return MCDisassembler::Fail;
3042  Inst.addOperand(MCOperand::createImm(align));
3043
3044  if (Rm == 0xD)
3045    Inst.addOperand(MCOperand::createReg(0));
3046  else if (Rm != 0xF) {
3047    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3048      return MCDisassembler::Fail;
3049  }
3050
3051  return S;
3052}
3053
3054static DecodeStatus
3055DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3056                            uint64_t Address, const void *Decoder) {
3057  DecodeStatus S = MCDisassembler::Success;
3058
3059  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3060  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3061  unsigned imm = fieldFromInstruction(Insn, 0, 4);
3062  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3063  imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3064  imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3065  imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3066  unsigned Q = fieldFromInstruction(Insn, 6, 1);
3067
3068  if (Q) {
3069    if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3070    return MCDisassembler::Fail;
3071  } else {
3072    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3073    return MCDisassembler::Fail;
3074  }
3075
3076  Inst.addOperand(MCOperand::createImm(imm));
3077
3078  switch (Inst.getOpcode()) {
3079    case ARM::VORRiv4i16:
3080    case ARM::VORRiv2i32:
3081    case ARM::VBICiv4i16:
3082    case ARM::VBICiv2i32:
3083      if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3084        return MCDisassembler::Fail;
3085      break;
3086    case ARM::VORRiv8i16:
3087    case ARM::VORRiv4i32:
3088    case ARM::VBICiv8i16:
3089    case ARM::VBICiv4i32:
3090      if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3091        return MCDisassembler::Fail;
3092      break;
3093    default:
3094      break;
3095  }
3096
3097  return S;
3098}
3099
3100static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3101                                        uint64_t Address, const void *Decoder) {
3102  DecodeStatus S = MCDisassembler::Success;
3103
3104  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3105  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3106  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3107  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3108  unsigned size = fieldFromInstruction(Insn, 18, 2);
3109
3110  if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3111    return MCDisassembler::Fail;
3112  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3113    return MCDisassembler::Fail;
3114  Inst.addOperand(MCOperand::createImm(8 << size));
3115
3116  return S;
3117}
3118
3119static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3120                               uint64_t Address, const void *Decoder) {
3121  Inst.addOperand(MCOperand::createImm(8 - Val));
3122  return MCDisassembler::Success;
3123}
3124
3125static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3126                               uint64_t Address, const void *Decoder) {
3127  Inst.addOperand(MCOperand::createImm(16 - Val));
3128  return MCDisassembler::Success;
3129}
3130
3131static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3132                               uint64_t Address, const void *Decoder) {
3133  Inst.addOperand(MCOperand::createImm(32 - Val));
3134  return MCDisassembler::Success;
3135}
3136
3137static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3138                               uint64_t Address, const void *Decoder) {
3139  Inst.addOperand(MCOperand::createImm(64 - Val));
3140  return MCDisassembler::Success;
3141}
3142
3143static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3144                               uint64_t Address, const void *Decoder) {
3145  DecodeStatus S = MCDisassembler::Success;
3146
3147  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3148  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3149  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3150  Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3151  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3152  Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3153  unsigned op = fieldFromInstruction(Insn, 6, 1);
3154
3155  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3156    return MCDisassembler::Fail;
3157  if (op) {
3158    if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3159    return MCDisassembler::Fail; // Writeback
3160  }
3161
3162  switch (Inst.getOpcode()) {
3163  case ARM::VTBL2:
3164  case ARM::VTBX2:
3165    if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3166      return MCDisassembler::Fail;
3167    break;
3168  default:
3169    if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3170      return MCDisassembler::Fail;
3171  }
3172
3173  if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3174    return MCDisassembler::Fail;
3175
3176  return S;
3177}
3178
3179static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3180                                     uint64_t Address, const void *Decoder) {
3181  DecodeStatus S = MCDisassembler::Success;
3182
3183  unsigned dst = fieldFromInstruction(Insn, 8, 3);
3184  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3185
3186  if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3187    return MCDisassembler::Fail;
3188
3189  switch(Inst.getOpcode()) {
3190    default:
3191      return MCDisassembler::Fail;
3192    case ARM::tADR:
3193      break; // tADR does not explicitly represent the PC as an operand.
3194    case ARM::tADDrSPi:
3195      Inst.addOperand(MCOperand::createReg(ARM::SP));
3196      break;
3197  }
3198
3199  Inst.addOperand(MCOperand::createImm(imm));
3200  return S;
3201}
3202
3203static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3204                                 uint64_t Address, const void *Decoder) {
3205  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3206                                true, 2, Inst, Decoder))
3207    Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3208  return MCDisassembler::Success;
3209}
3210
3211static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3212                                 uint64_t Address, const void *Decoder) {
3213  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3214                                true, 4, Inst, Decoder))
3215    Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3216  return MCDisassembler::Success;
3217}
3218
3219static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3220                                 uint64_t Address, const void *Decoder) {
3221  if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3222                                true, 2, Inst, Decoder))
3223    Inst.addOperand(MCOperand::createImm(Val << 1));
3224  return MCDisassembler::Success;
3225}
3226
3227static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3228                                 uint64_t Address, const void *Decoder) {
3229  DecodeStatus S = MCDisassembler::Success;
3230
3231  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3232  unsigned Rm = fieldFromInstruction(Val, 3, 3);
3233
3234  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3235    return MCDisassembler::Fail;
3236  if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3237    return MCDisassembler::Fail;
3238
3239  return S;
3240}
3241
3242static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3243                                  uint64_t Address, const void *Decoder) {
3244  DecodeStatus S = MCDisassembler::Success;
3245
3246  unsigned Rn = fieldFromInstruction(Val, 0, 3);
3247  unsigned imm = fieldFromInstruction(Val, 3, 5);
3248
3249  if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3250    return MCDisassembler::Fail;
3251  Inst.addOperand(MCOperand::createImm(imm));
3252
3253  return S;
3254}
3255
3256static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3257                                  uint64_t Address, const void *Decoder) {
3258  unsigned imm = Val << 2;
3259
3260  Inst.addOperand(MCOperand::createImm(imm));
3261  tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3262
3263  return MCDisassembler::Success;
3264}
3265
3266static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3267                                  uint64_t Address, const void *Decoder) {
3268  Inst.addOperand(MCOperand::createReg(ARM::SP));
3269  Inst.addOperand(MCOperand::createImm(Val));
3270
3271  return MCDisassembler::Success;
3272}
3273
3274static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3275                                  uint64_t Address, const void *Decoder) {
3276  DecodeStatus S = MCDisassembler::Success;
3277
3278  unsigned Rn = fieldFromInstruction(Val, 6, 4);
3279  unsigned Rm = fieldFromInstruction(Val, 2, 4);
3280  unsigned imm = fieldFromInstruction(Val, 0, 2);
3281
3282  // Thumb stores cannot use PC as dest register.
3283  switch (Inst.getOpcode()) {
3284  case ARM::t2STRHs:
3285  case ARM::t2STRBs:
3286  case ARM::t2STRs:
3287    if (Rn == 15)
3288      return MCDisassembler::Fail;
3289  default:
3290    break;
3291  }
3292
3293  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3294    return MCDisassembler::Fail;
3295  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3296    return MCDisassembler::Fail;
3297  Inst.addOperand(MCOperand::createImm(imm));
3298
3299  return S;
3300}
3301
3302static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3303                              uint64_t Address, const void *Decoder) {
3304  DecodeStatus S = MCDisassembler::Success;
3305
3306  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3307  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3308
3309  const FeatureBitset &featureBits =
3310    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3311
3312  bool hasMP = featureBits[ARM::FeatureMP];
3313  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3314
3315  if (Rn == 15) {
3316    switch (Inst.getOpcode()) {
3317    case ARM::t2LDRBs:
3318      Inst.setOpcode(ARM::t2LDRBpci);
3319      break;
3320    case ARM::t2LDRHs:
3321      Inst.setOpcode(ARM::t2LDRHpci);
3322      break;
3323    case ARM::t2LDRSHs:
3324      Inst.setOpcode(ARM::t2LDRSHpci);
3325      break;
3326    case ARM::t2LDRSBs:
3327      Inst.setOpcode(ARM::t2LDRSBpci);
3328      break;
3329    case ARM::t2LDRs:
3330      Inst.setOpcode(ARM::t2LDRpci);
3331      break;
3332    case ARM::t2PLDs:
3333      Inst.setOpcode(ARM::t2PLDpci);
3334      break;
3335    case ARM::t2PLIs:
3336      Inst.setOpcode(ARM::t2PLIpci);
3337      break;
3338    default:
3339      return MCDisassembler::Fail;
3340    }
3341
3342    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3343  }
3344
3345  if (Rt == 15) {
3346    switch (Inst.getOpcode()) {
3347    case ARM::t2LDRSHs:
3348      return MCDisassembler::Fail;
3349    case ARM::t2LDRHs:
3350      Inst.setOpcode(ARM::t2PLDWs);
3351      break;
3352    case ARM::t2LDRSBs:
3353      Inst.setOpcode(ARM::t2PLIs);
3354    default:
3355      break;
3356    }
3357  }
3358
3359  switch (Inst.getOpcode()) {
3360    case ARM::t2PLDs:
3361      break;
3362    case ARM::t2PLIs:
3363      if (!hasV7Ops)
3364        return MCDisassembler::Fail;
3365      break;
3366    case ARM::t2PLDWs:
3367      if (!hasV7Ops || !hasMP)
3368        return MCDisassembler::Fail;
3369      break;
3370    default:
3371      if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3372        return MCDisassembler::Fail;
3373  }
3374
3375  unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3376  addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3377  addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3378  if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3379    return MCDisassembler::Fail;
3380
3381  return S;
3382}
3383
3384static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3385                                uint64_t Address, const void* Decoder) {
3386  DecodeStatus S = MCDisassembler::Success;
3387
3388  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3389  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3390  unsigned U = fieldFromInstruction(Insn, 9, 1);
3391  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3392  imm |= (U << 8);
3393  imm |= (Rn << 9);
3394  unsigned add = fieldFromInstruction(Insn, 9, 1);
3395
3396  const FeatureBitset &featureBits =
3397    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3398
3399  bool hasMP = featureBits[ARM::FeatureMP];
3400  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3401
3402  if (Rn == 15) {
3403    switch (Inst.getOpcode()) {
3404    case ARM::t2LDRi8:
3405      Inst.setOpcode(ARM::t2LDRpci);
3406      break;
3407    case ARM::t2LDRBi8:
3408      Inst.setOpcode(ARM::t2LDRBpci);
3409      break;
3410    case ARM::t2LDRSBi8:
3411      Inst.setOpcode(ARM::t2LDRSBpci);
3412      break;
3413    case ARM::t2LDRHi8:
3414      Inst.setOpcode(ARM::t2LDRHpci);
3415      break;
3416    case ARM::t2LDRSHi8:
3417      Inst.setOpcode(ARM::t2LDRSHpci);
3418      break;
3419    case ARM::t2PLDi8:
3420      Inst.setOpcode(ARM::t2PLDpci);
3421      break;
3422    case ARM::t2PLIi8:
3423      Inst.setOpcode(ARM::t2PLIpci);
3424      break;
3425    default:
3426      return MCDisassembler::Fail;
3427    }
3428    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3429  }
3430
3431  if (Rt == 15) {
3432    switch (Inst.getOpcode()) {
3433    case ARM::t2LDRSHi8:
3434      return MCDisassembler::Fail;
3435    case ARM::t2LDRHi8:
3436      if (!add)
3437        Inst.setOpcode(ARM::t2PLDWi8);
3438      break;
3439    case ARM::t2LDRSBi8:
3440      Inst.setOpcode(ARM::t2PLIi8);
3441      break;
3442    default:
3443      break;
3444    }
3445  }
3446
3447  switch (Inst.getOpcode()) {
3448  case ARM::t2PLDi8:
3449    break;
3450  case ARM::t2PLIi8:
3451    if (!hasV7Ops)
3452      return MCDisassembler::Fail;
3453    break;
3454  case ARM::t2PLDWi8:
3455      if (!hasV7Ops || !hasMP)
3456        return MCDisassembler::Fail;
3457      break;
3458  default:
3459    if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3460      return MCDisassembler::Fail;
3461  }
3462
3463  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3464    return MCDisassembler::Fail;
3465  return S;
3466}
3467
3468static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3469                                uint64_t Address, const void* Decoder) {
3470  DecodeStatus S = MCDisassembler::Success;
3471
3472  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3473  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3474  unsigned imm = fieldFromInstruction(Insn, 0, 12);
3475  imm |= (Rn << 13);
3476
3477  const FeatureBitset &featureBits =
3478    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3479
3480  bool hasMP = featureBits[ARM::FeatureMP];
3481  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3482
3483  if (Rn == 15) {
3484    switch (Inst.getOpcode()) {
3485    case ARM::t2LDRi12:
3486      Inst.setOpcode(ARM::t2LDRpci);
3487      break;
3488    case ARM::t2LDRHi12:
3489      Inst.setOpcode(ARM::t2LDRHpci);
3490      break;
3491    case ARM::t2LDRSHi12:
3492      Inst.setOpcode(ARM::t2LDRSHpci);
3493      break;
3494    case ARM::t2LDRBi12:
3495      Inst.setOpcode(ARM::t2LDRBpci);
3496      break;
3497    case ARM::t2LDRSBi12:
3498      Inst.setOpcode(ARM::t2LDRSBpci);
3499      break;
3500    case ARM::t2PLDi12:
3501      Inst.setOpcode(ARM::t2PLDpci);
3502      break;
3503    case ARM::t2PLIi12:
3504      Inst.setOpcode(ARM::t2PLIpci);
3505      break;
3506    default:
3507      return MCDisassembler::Fail;
3508    }
3509    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3510  }
3511
3512  if (Rt == 15) {
3513    switch (Inst.getOpcode()) {
3514    case ARM::t2LDRSHi12:
3515      return MCDisassembler::Fail;
3516    case ARM::t2LDRHi12:
3517      Inst.setOpcode(ARM::t2PLDWi12);
3518      break;
3519    case ARM::t2LDRSBi12:
3520      Inst.setOpcode(ARM::t2PLIi12);
3521      break;
3522    default:
3523      break;
3524    }
3525  }
3526
3527  switch (Inst.getOpcode()) {
3528  case ARM::t2PLDi12:
3529    break;
3530  case ARM::t2PLIi12:
3531    if (!hasV7Ops)
3532      return MCDisassembler::Fail;
3533    break;
3534  case ARM::t2PLDWi12:
3535      if (!hasV7Ops || !hasMP)
3536        return MCDisassembler::Fail;
3537      break;
3538  default:
3539    if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3540      return MCDisassembler::Fail;
3541  }
3542
3543  if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3544    return MCDisassembler::Fail;
3545  return S;
3546}
3547
3548static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3549                                uint64_t Address, const void* Decoder) {
3550  DecodeStatus S = MCDisassembler::Success;
3551
3552  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3553  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3554  unsigned imm = fieldFromInstruction(Insn, 0, 8);
3555  imm |= (Rn << 9);
3556
3557  if (Rn == 15) {
3558    switch (Inst.getOpcode()) {
3559    case ARM::t2LDRT:
3560      Inst.setOpcode(ARM::t2LDRpci);
3561      break;
3562    case ARM::t2LDRBT:
3563      Inst.setOpcode(ARM::t2LDRBpci);
3564      break;
3565    case ARM::t2LDRHT:
3566      Inst.setOpcode(ARM::t2LDRHpci);
3567      break;
3568    case ARM::t2LDRSBT:
3569      Inst.setOpcode(ARM::t2LDRSBpci);
3570      break;
3571    case ARM::t2LDRSHT:
3572      Inst.setOpcode(ARM::t2LDRSHpci);
3573      break;
3574    default:
3575      return MCDisassembler::Fail;
3576    }
3577    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3578  }
3579
3580  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3581    return MCDisassembler::Fail;
3582  if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3583    return MCDisassembler::Fail;
3584  return S;
3585}
3586
3587static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3588                                uint64_t Address, const void* Decoder) {
3589  DecodeStatus S = MCDisassembler::Success;
3590
3591  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3592  unsigned U = fieldFromInstruction(Insn, 23, 1);
3593  int imm = fieldFromInstruction(Insn, 0, 12);
3594
3595  const FeatureBitset &featureBits =
3596    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3597
3598  bool hasV7Ops = featureBits[ARM::HasV7Ops];
3599
3600  if (Rt == 15) {
3601    switch (Inst.getOpcode()) {
3602      case ARM::t2LDRBpci:
3603      case ARM::t2LDRHpci:
3604        Inst.setOpcode(ARM::t2PLDpci);
3605        break;
3606      case ARM::t2LDRSBpci:
3607        Inst.setOpcode(ARM::t2PLIpci);
3608        break;
3609      case ARM::t2LDRSHpci:
3610        return MCDisassembler::Fail;
3611      default:
3612        break;
3613    }
3614  }
3615
3616  switch(Inst.getOpcode()) {
3617  case ARM::t2PLDpci:
3618    break;
3619  case ARM::t2PLIpci:
3620    if (!hasV7Ops)
3621      return MCDisassembler::Fail;
3622    break;
3623  default:
3624    if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3625      return MCDisassembler::Fail;
3626  }
3627
3628  if (!U) {
3629    // Special case for #-0.
3630    if (imm == 0)
3631      imm = INT32_MIN;
3632    else
3633      imm = -imm;
3634  }
3635  Inst.addOperand(MCOperand::createImm(imm));
3636
3637  return S;
3638}
3639
3640static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3641                           uint64_t Address, const void *Decoder) {
3642  if (Val == 0)
3643    Inst.addOperand(MCOperand::createImm(INT32_MIN));
3644  else {
3645    int imm = Val & 0xFF;
3646
3647    if (!(Val & 0x100)) imm *= -1;
3648    Inst.addOperand(MCOperand::createImm(imm * 4));
3649  }
3650
3651  return MCDisassembler::Success;
3652}
3653
3654static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3655                                   uint64_t Address, const void *Decoder) {
3656  DecodeStatus S = MCDisassembler::Success;
3657
3658  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3659  unsigned imm = fieldFromInstruction(Val, 0, 9);
3660
3661  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3662    return MCDisassembler::Fail;
3663  if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3664    return MCDisassembler::Fail;
3665
3666  return S;
3667}
3668
3669static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3670                                   uint64_t Address, const void *Decoder) {
3671  DecodeStatus S = MCDisassembler::Success;
3672
3673  unsigned Rn = fieldFromInstruction(Val, 8, 4);
3674  unsigned imm = fieldFromInstruction(Val, 0, 8);
3675
3676  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3677    return MCDisassembler::Fail;
3678
3679  Inst.addOperand(MCOperand::createImm(imm));
3680
3681  return S;
3682}
3683
3684static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3685                         uint64_t Address, const void *Decoder) {
3686  int imm = Val & 0xFF;
3687  if (Val == 0)
3688    imm = INT32_MIN;
3689  else if (!(Val & 0x100))
3690    imm *= -1;
3691  Inst.addOperand(MCOperand::createImm(imm));
3692
3693  return MCDisassembler::Success;
3694}
3695
3696
3697static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3698                                 uint64_t Address, const void *Decoder) {
3699  DecodeStatus S = MCDisassembler::Success;
3700
3701  unsigned Rn = fieldFromInstruction(Val, 9, 4);
3702  unsigned imm = fieldFromInstruction(Val, 0, 9);
3703
3704  // Thumb stores cannot use PC as dest register.
3705  switch (Inst.getOpcode()) {
3706  case ARM::t2STRT:
3707  case ARM::t2STRBT:
3708  case ARM::t2STRHT:
3709  case ARM::t2STRi8:
3710  case ARM::t2STRHi8:
3711  case ARM::t2STRBi8:
3712    if (Rn == 15)
3713      return MCDisassembler::Fail;
3714    break;
3715  default:
3716    break;
3717  }
3718
3719  // Some instructions always use an additive offset.
3720  switch (Inst.getOpcode()) {
3721    case ARM::t2LDRT:
3722    case ARM::t2LDRBT:
3723    case ARM::t2LDRHT:
3724    case ARM::t2LDRSBT:
3725    case ARM::t2LDRSHT:
3726    case ARM::t2STRT:
3727    case ARM::t2STRBT:
3728    case ARM::t2STRHT:
3729      imm |= 0x100;
3730      break;
3731    default:
3732      break;
3733  }
3734
3735  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3736    return MCDisassembler::Fail;
3737  if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3738    return MCDisassembler::Fail;
3739
3740  return S;
3741}
3742
3743static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3744                                    uint64_t Address, const void *Decoder) {
3745  DecodeStatus S = MCDisassembler::Success;
3746
3747  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3748  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3749  unsigned addr = fieldFromInstruction(Insn, 0, 8);
3750  addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3751  addr |= Rn << 9;
3752  unsigned load = fieldFromInstruction(Insn, 20, 1);
3753
3754  if (Rn == 15) {
3755    switch (Inst.getOpcode()) {
3756    case ARM::t2LDR_PRE:
3757    case ARM::t2LDR_POST:
3758      Inst.setOpcode(ARM::t2LDRpci);
3759      break;
3760    case ARM::t2LDRB_PRE:
3761    case ARM::t2LDRB_POST:
3762      Inst.setOpcode(ARM::t2LDRBpci);
3763      break;
3764    case ARM::t2LDRH_PRE:
3765    case ARM::t2LDRH_POST:
3766      Inst.setOpcode(ARM::t2LDRHpci);
3767      break;
3768    case ARM::t2LDRSB_PRE:
3769    case ARM::t2LDRSB_POST:
3770      if (Rt == 15)
3771        Inst.setOpcode(ARM::t2PLIpci);
3772      else
3773        Inst.setOpcode(ARM::t2LDRSBpci);
3774      break;
3775    case ARM::t2LDRSH_PRE:
3776    case ARM::t2LDRSH_POST:
3777      Inst.setOpcode(ARM::t2LDRSHpci);
3778      break;
3779    default:
3780      return MCDisassembler::Fail;
3781    }
3782    return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3783  }
3784
3785  if (!load) {
3786    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3787      return MCDisassembler::Fail;
3788  }
3789
3790  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3791    return MCDisassembler::Fail;
3792
3793  if (load) {
3794    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3795      return MCDisassembler::Fail;
3796  }
3797
3798  if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3799    return MCDisassembler::Fail;
3800
3801  return S;
3802}
3803
3804static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3805                                  uint64_t Address, const void *Decoder) {
3806  DecodeStatus S = MCDisassembler::Success;
3807
3808  unsigned Rn = fieldFromInstruction(Val, 13, 4);
3809  unsigned imm = fieldFromInstruction(Val, 0, 12);
3810
3811  // Thumb stores cannot use PC as dest register.
3812  switch (Inst.getOpcode()) {
3813  case ARM::t2STRi12:
3814  case ARM::t2STRBi12:
3815  case ARM::t2STRHi12:
3816    if (Rn == 15)
3817      return MCDisassembler::Fail;
3818  default:
3819    break;
3820  }
3821
3822  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3823    return MCDisassembler::Fail;
3824  Inst.addOperand(MCOperand::createImm(imm));
3825
3826  return S;
3827}
3828
3829
3830static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3831                                uint64_t Address, const void *Decoder) {
3832  unsigned imm = fieldFromInstruction(Insn, 0, 7);
3833
3834  Inst.addOperand(MCOperand::createReg(ARM::SP));
3835  Inst.addOperand(MCOperand::createReg(ARM::SP));
3836  Inst.addOperand(MCOperand::createImm(imm));
3837
3838  return MCDisassembler::Success;
3839}
3840
3841static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3842                                uint64_t Address, const void *Decoder) {
3843  DecodeStatus S = MCDisassembler::Success;
3844
3845  if (Inst.getOpcode() == ARM::tADDrSP) {
3846    unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3847    Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3848
3849    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3850    return MCDisassembler::Fail;
3851    Inst.addOperand(MCOperand::createReg(ARM::SP));
3852    if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3853    return MCDisassembler::Fail;
3854  } else if (Inst.getOpcode() == ARM::tADDspr) {
3855    unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3856
3857    Inst.addOperand(MCOperand::createReg(ARM::SP));
3858    Inst.addOperand(MCOperand::createReg(ARM::SP));
3859    if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3860    return MCDisassembler::Fail;
3861  }
3862
3863  return S;
3864}
3865
3866static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3867                           uint64_t Address, const void *Decoder) {
3868  unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3869  unsigned flags = fieldFromInstruction(Insn, 0, 3);
3870
3871  Inst.addOperand(MCOperand::createImm(imod));
3872  Inst.addOperand(MCOperand::createImm(flags));
3873
3874  return MCDisassembler::Success;
3875}
3876
3877static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3878                             uint64_t Address, const void *Decoder) {
3879  DecodeStatus S = MCDisassembler::Success;
3880  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3881  unsigned add = fieldFromInstruction(Insn, 4, 1);
3882
3883  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3884    return MCDisassembler::Fail;
3885  Inst.addOperand(MCOperand::createImm(add));
3886
3887  return S;
3888}
3889
3890static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3891                                 uint64_t Address, const void *Decoder) {
3892  // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3893  // Note only one trailing zero not two.  Also the J1 and J2 values are from
3894  // the encoded instruction.  So here change to I1 and I2 values via:
3895  // I1 = NOT(J1 EOR S);
3896  // I2 = NOT(J2 EOR S);
3897  // and build the imm32 with two trailing zeros as documented:
3898  // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3899  unsigned S = (Val >> 23) & 1;
3900  unsigned J1 = (Val >> 22) & 1;
3901  unsigned J2 = (Val >> 21) & 1;
3902  unsigned I1 = !(J1 ^ S);
3903  unsigned I2 = !(J2 ^ S);
3904  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3905  int imm32 = SignExtend32<25>(tmp << 1);
3906
3907  if (!tryAddingSymbolicOperand(Address,
3908                                (Address & ~2u) + imm32 + 4,
3909                                true, 4, Inst, Decoder))
3910    Inst.addOperand(MCOperand::createImm(imm32));
3911  return MCDisassembler::Success;
3912}
3913
3914static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3915                              uint64_t Address, const void *Decoder) {
3916  if (Val == 0xA || Val == 0xB)
3917    return MCDisassembler::Fail;
3918
3919  const FeatureBitset &featureBits =
3920    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3921
3922  if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3923    return MCDisassembler::Fail;
3924
3925  Inst.addOperand(MCOperand::createImm(Val));
3926  return MCDisassembler::Success;
3927}
3928
3929static DecodeStatus
3930DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3931                       uint64_t Address, const void *Decoder) {
3932  DecodeStatus S = MCDisassembler::Success;
3933
3934  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3935  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3936
3937  if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3938  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3939    return MCDisassembler::Fail;
3940  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3941    return MCDisassembler::Fail;
3942  return S;
3943}
3944
3945static DecodeStatus
3946DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3947                           uint64_t Address, const void *Decoder) {
3948  DecodeStatus S = MCDisassembler::Success;
3949
3950  unsigned pred = fieldFromInstruction(Insn, 22, 4);
3951  if (pred == 0xE || pred == 0xF) {
3952    unsigned opc = fieldFromInstruction(Insn, 4, 28);
3953    switch (opc) {
3954      default:
3955        return MCDisassembler::Fail;
3956      case 0xf3bf8f4:
3957        Inst.setOpcode(ARM::t2DSB);
3958        break;
3959      case 0xf3bf8f5:
3960        Inst.setOpcode(ARM::t2DMB);
3961        break;
3962      case 0xf3bf8f6:
3963        Inst.setOpcode(ARM::t2ISB);
3964        break;
3965    }
3966
3967    unsigned imm = fieldFromInstruction(Insn, 0, 4);
3968    return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3969  }
3970
3971  unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3972  brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3973  brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3974  brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3975  brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3976
3977  if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3978    return MCDisassembler::Fail;
3979  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3980    return MCDisassembler::Fail;
3981
3982  return S;
3983}
3984
3985// Decode a shifted immediate operand.  These basically consist
3986// of an 8-bit value, and a 4-bit directive that specifies either
3987// a splat operation or a rotation.
3988static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3989                          uint64_t Address, const void *Decoder) {
3990  unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3991  if (ctrl == 0) {
3992    unsigned byte = fieldFromInstruction(Val, 8, 2);
3993    unsigned imm = fieldFromInstruction(Val, 0, 8);
3994    switch (byte) {
3995      case 0:
3996        Inst.addOperand(MCOperand::createImm(imm));
3997        break;
3998      case 1:
3999        Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4000        break;
4001      case 2:
4002        Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4003        break;
4004      case 3:
4005        Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4006                                             (imm << 8)  |  imm));
4007        break;
4008    }
4009  } else {
4010    unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4011    unsigned rot = fieldFromInstruction(Val, 7, 5);
4012    unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4013    Inst.addOperand(MCOperand::createImm(imm));
4014  }
4015
4016  return MCDisassembler::Success;
4017}
4018
4019static DecodeStatus
4020DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4021                            uint64_t Address, const void *Decoder){
4022  if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4023                                true, 2, Inst, Decoder))
4024    Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4025  return MCDisassembler::Success;
4026}
4027
4028static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4029                                       uint64_t Address, const void *Decoder){
4030  // Val is passed in as S:J1:J2:imm10:imm11
4031  // Note no trailing zero after imm11.  Also the J1 and J2 values are from
4032  // the encoded instruction.  So here change to I1 and I2 values via:
4033  // I1 = NOT(J1 EOR S);
4034  // I2 = NOT(J2 EOR S);
4035  // and build the imm32 with one trailing zero as documented:
4036  // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4037  unsigned S = (Val >> 23) & 1;
4038  unsigned J1 = (Val >> 22) & 1;
4039  unsigned J2 = (Val >> 21) & 1;
4040  unsigned I1 = !(J1 ^ S);
4041  unsigned I2 = !(J2 ^ S);
4042  unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4043  int imm32 = SignExtend32<25>(tmp << 1);
4044
4045  if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4046                                true, 4, Inst, Decoder))
4047    Inst.addOperand(MCOperand::createImm(imm32));
4048  return MCDisassembler::Success;
4049}
4050
4051static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4052                                   uint64_t Address, const void *Decoder) {
4053  if (Val & ~0xf)
4054    return MCDisassembler::Fail;
4055
4056  Inst.addOperand(MCOperand::createImm(Val));
4057  return MCDisassembler::Success;
4058}
4059
4060static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4061                                        uint64_t Address, const void *Decoder) {
4062  if (Val & ~0xf)
4063    return MCDisassembler::Fail;
4064
4065  Inst.addOperand(MCOperand::createImm(Val));
4066  return MCDisassembler::Success;
4067}
4068
4069static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4070                          uint64_t Address, const void *Decoder) {
4071  DecodeStatus S = MCDisassembler::Success;
4072  const FeatureBitset &FeatureBits =
4073    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4074
4075  if (FeatureBits[ARM::FeatureMClass]) {
4076    unsigned ValLow = Val & 0xff;
4077
4078    // Validate the SYSm value first.
4079    switch (ValLow) {
4080    case  0: // apsr
4081    case  1: // iapsr
4082    case  2: // eapsr
4083    case  3: // xpsr
4084    case  5: // ipsr
4085    case  6: // epsr
4086    case  7: // iepsr
4087    case  8: // msp
4088    case  9: // psp
4089    case 16: // primask
4090    case 20: // control
4091      break;
4092    case 17: // basepri
4093    case 18: // basepri_max
4094    case 19: // faultmask
4095      if (!(FeatureBits[ARM::HasV7Ops]))
4096        // Values basepri, basepri_max and faultmask are only valid for v7m.
4097        return MCDisassembler::Fail;
4098      break;
4099    default:
4100      return MCDisassembler::Fail;
4101    }
4102
4103    if (Inst.getOpcode() == ARM::t2MSR_M) {
4104      unsigned Mask = fieldFromInstruction(Val, 10, 2);
4105      if (!(FeatureBits[ARM::HasV7Ops])) {
4106        // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4107        // unpredictable.
4108        if (Mask != 2)
4109          S = MCDisassembler::SoftFail;
4110      }
4111      else {
4112        // The ARMv7-M architecture stores an additional 2-bit mask value in
4113        // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4114        // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4115        // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4116        // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4117        // only if the processor includes the DSP extension.
4118        if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4119            (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4120          S = MCDisassembler::SoftFail;
4121      }
4122    }
4123  } else {
4124    // A/R class
4125    if (Val == 0)
4126      return MCDisassembler::Fail;
4127  }
4128  Inst.addOperand(MCOperand::createImm(Val));
4129  return S;
4130}
4131
4132static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4133                                    uint64_t Address, const void *Decoder) {
4134
4135  unsigned R = fieldFromInstruction(Val, 5, 1);
4136  unsigned SysM = fieldFromInstruction(Val, 0, 5);
4137
4138  // The table of encodings for these banked registers comes from B9.2.3 of the
4139  // ARM ARM. There are patterns, but nothing regular enough to make this logic
4140  // neater. So by fiat, these values are UNPREDICTABLE:
4141  if (!R) {
4142    if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4143        SysM == 0x1a || SysM == 0x1b)
4144      return MCDisassembler::SoftFail;
4145  } else {
4146    if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4147        SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4148      return MCDisassembler::SoftFail;
4149  }
4150
4151  Inst.addOperand(MCOperand::createImm(Val));
4152  return MCDisassembler::Success;
4153}
4154
4155static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4156                                        uint64_t Address, const void *Decoder) {
4157  DecodeStatus S = MCDisassembler::Success;
4158
4159  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4160  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4161  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4162
4163  if (Rn == 0xF)
4164    S = MCDisassembler::SoftFail;
4165
4166  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4167    return MCDisassembler::Fail;
4168  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4169    return MCDisassembler::Fail;
4170  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4171    return MCDisassembler::Fail;
4172
4173  return S;
4174}
4175
4176static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4177                                         uint64_t Address, const void *Decoder){
4178  DecodeStatus S = MCDisassembler::Success;
4179
4180  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4181  unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4182  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4183  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4184
4185  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4186    return MCDisassembler::Fail;
4187
4188  if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4189    S = MCDisassembler::SoftFail;
4190
4191  if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4192    return MCDisassembler::Fail;
4193  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4194    return MCDisassembler::Fail;
4195  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4196    return MCDisassembler::Fail;
4197
4198  return S;
4199}
4200
4201static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4202                            uint64_t Address, const void *Decoder) {
4203  DecodeStatus S = MCDisassembler::Success;
4204
4205  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4206  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4207  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4208  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4209  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4210  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4211
4212  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4213
4214  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4215    return MCDisassembler::Fail;
4216  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4217    return MCDisassembler::Fail;
4218  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4219    return MCDisassembler::Fail;
4220  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4221    return MCDisassembler::Fail;
4222
4223  return S;
4224}
4225
4226static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4227                            uint64_t Address, const void *Decoder) {
4228  DecodeStatus S = MCDisassembler::Success;
4229
4230  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4231  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4232  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4233  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4234  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4235  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4236  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4237
4238  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4239  if (Rm == 0xF) S = MCDisassembler::SoftFail;
4240
4241  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4242    return MCDisassembler::Fail;
4243  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4244    return MCDisassembler::Fail;
4245  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4246    return MCDisassembler::Fail;
4247  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4248    return MCDisassembler::Fail;
4249
4250  return S;
4251}
4252
4253
4254static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4255                            uint64_t Address, const void *Decoder) {
4256  DecodeStatus S = MCDisassembler::Success;
4257
4258  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4259  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4260  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4261  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4262  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4263  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4264
4265  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4266
4267  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4268    return MCDisassembler::Fail;
4269  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4270    return MCDisassembler::Fail;
4271  if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4272    return MCDisassembler::Fail;
4273  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4274    return MCDisassembler::Fail;
4275
4276  return S;
4277}
4278
4279static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4280                            uint64_t Address, const void *Decoder) {
4281  DecodeStatus S = MCDisassembler::Success;
4282
4283  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4284  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4285  unsigned imm = fieldFromInstruction(Insn, 0, 12);
4286  imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4287  imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4288  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4289
4290  if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4291
4292  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4293    return MCDisassembler::Fail;
4294  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4295    return MCDisassembler::Fail;
4296  if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4297    return MCDisassembler::Fail;
4298  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4299    return MCDisassembler::Fail;
4300
4301  return S;
4302}
4303
4304static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4305                         uint64_t Address, const void *Decoder) {
4306  DecodeStatus S = MCDisassembler::Success;
4307
4308  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4309  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4310  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4311  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4312  unsigned size = fieldFromInstruction(Insn, 10, 2);
4313
4314  unsigned align = 0;
4315  unsigned index = 0;
4316  switch (size) {
4317    default:
4318      return MCDisassembler::Fail;
4319    case 0:
4320      if (fieldFromInstruction(Insn, 4, 1))
4321        return MCDisassembler::Fail; // UNDEFINED
4322      index = fieldFromInstruction(Insn, 5, 3);
4323      break;
4324    case 1:
4325      if (fieldFromInstruction(Insn, 5, 1))
4326        return MCDisassembler::Fail; // UNDEFINED
4327      index = fieldFromInstruction(Insn, 6, 2);
4328      if (fieldFromInstruction(Insn, 4, 1))
4329        align = 2;
4330      break;
4331    case 2:
4332      if (fieldFromInstruction(Insn, 6, 1))
4333        return MCDisassembler::Fail; // UNDEFINED
4334      index = fieldFromInstruction(Insn, 7, 1);
4335
4336      switch (fieldFromInstruction(Insn, 4, 2)) {
4337        case 0 :
4338          align = 0; break;
4339        case 3:
4340          align = 4; break;
4341        default:
4342          return MCDisassembler::Fail;
4343      }
4344      break;
4345  }
4346
4347  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4348    return MCDisassembler::Fail;
4349  if (Rm != 0xF) { // Writeback
4350    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4351      return MCDisassembler::Fail;
4352  }
4353  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4354    return MCDisassembler::Fail;
4355  Inst.addOperand(MCOperand::createImm(align));
4356  if (Rm != 0xF) {
4357    if (Rm != 0xD) {
4358      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4359        return MCDisassembler::Fail;
4360    } else
4361      Inst.addOperand(MCOperand::createReg(0));
4362  }
4363
4364  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4365    return MCDisassembler::Fail;
4366  Inst.addOperand(MCOperand::createImm(index));
4367
4368  return S;
4369}
4370
4371static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4372                         uint64_t Address, const void *Decoder) {
4373  DecodeStatus S = MCDisassembler::Success;
4374
4375  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4376  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4377  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4378  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4379  unsigned size = fieldFromInstruction(Insn, 10, 2);
4380
4381  unsigned align = 0;
4382  unsigned index = 0;
4383  switch (size) {
4384    default:
4385      return MCDisassembler::Fail;
4386    case 0:
4387      if (fieldFromInstruction(Insn, 4, 1))
4388        return MCDisassembler::Fail; // UNDEFINED
4389      index = fieldFromInstruction(Insn, 5, 3);
4390      break;
4391    case 1:
4392      if (fieldFromInstruction(Insn, 5, 1))
4393        return MCDisassembler::Fail; // UNDEFINED
4394      index = fieldFromInstruction(Insn, 6, 2);
4395      if (fieldFromInstruction(Insn, 4, 1))
4396        align = 2;
4397      break;
4398    case 2:
4399      if (fieldFromInstruction(Insn, 6, 1))
4400        return MCDisassembler::Fail; // UNDEFINED
4401      index = fieldFromInstruction(Insn, 7, 1);
4402
4403      switch (fieldFromInstruction(Insn, 4, 2)) {
4404        case 0:
4405          align = 0; break;
4406        case 3:
4407          align = 4; break;
4408        default:
4409          return MCDisassembler::Fail;
4410      }
4411      break;
4412  }
4413
4414  if (Rm != 0xF) { // Writeback
4415    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4416    return MCDisassembler::Fail;
4417  }
4418  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4419    return MCDisassembler::Fail;
4420  Inst.addOperand(MCOperand::createImm(align));
4421  if (Rm != 0xF) {
4422    if (Rm != 0xD) {
4423      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4424    return MCDisassembler::Fail;
4425    } else
4426      Inst.addOperand(MCOperand::createReg(0));
4427  }
4428
4429  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4430    return MCDisassembler::Fail;
4431  Inst.addOperand(MCOperand::createImm(index));
4432
4433  return S;
4434}
4435
4436
4437static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4438                         uint64_t Address, const void *Decoder) {
4439  DecodeStatus S = MCDisassembler::Success;
4440
4441  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4442  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4443  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4444  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4445  unsigned size = fieldFromInstruction(Insn, 10, 2);
4446
4447  unsigned align = 0;
4448  unsigned index = 0;
4449  unsigned inc = 1;
4450  switch (size) {
4451    default:
4452      return MCDisassembler::Fail;
4453    case 0:
4454      index = fieldFromInstruction(Insn, 5, 3);
4455      if (fieldFromInstruction(Insn, 4, 1))
4456        align = 2;
4457      break;
4458    case 1:
4459      index = fieldFromInstruction(Insn, 6, 2);
4460      if (fieldFromInstruction(Insn, 4, 1))
4461        align = 4;
4462      if (fieldFromInstruction(Insn, 5, 1))
4463        inc = 2;
4464      break;
4465    case 2:
4466      if (fieldFromInstruction(Insn, 5, 1))
4467        return MCDisassembler::Fail; // UNDEFINED
4468      index = fieldFromInstruction(Insn, 7, 1);
4469      if (fieldFromInstruction(Insn, 4, 1) != 0)
4470        align = 8;
4471      if (fieldFromInstruction(Insn, 6, 1))
4472        inc = 2;
4473      break;
4474  }
4475
4476  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4477    return MCDisassembler::Fail;
4478  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4479    return MCDisassembler::Fail;
4480  if (Rm != 0xF) { // Writeback
4481    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4482      return MCDisassembler::Fail;
4483  }
4484  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4485    return MCDisassembler::Fail;
4486  Inst.addOperand(MCOperand::createImm(align));
4487  if (Rm != 0xF) {
4488    if (Rm != 0xD) {
4489      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4490        return MCDisassembler::Fail;
4491    } else
4492      Inst.addOperand(MCOperand::createReg(0));
4493  }
4494
4495  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4496    return MCDisassembler::Fail;
4497  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4498    return MCDisassembler::Fail;
4499  Inst.addOperand(MCOperand::createImm(index));
4500
4501  return S;
4502}
4503
4504static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4505                         uint64_t Address, const void *Decoder) {
4506  DecodeStatus S = MCDisassembler::Success;
4507
4508  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4509  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4510  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4511  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4512  unsigned size = fieldFromInstruction(Insn, 10, 2);
4513
4514  unsigned align = 0;
4515  unsigned index = 0;
4516  unsigned inc = 1;
4517  switch (size) {
4518    default:
4519      return MCDisassembler::Fail;
4520    case 0:
4521      index = fieldFromInstruction(Insn, 5, 3);
4522      if (fieldFromInstruction(Insn, 4, 1))
4523        align = 2;
4524      break;
4525    case 1:
4526      index = fieldFromInstruction(Insn, 6, 2);
4527      if (fieldFromInstruction(Insn, 4, 1))
4528        align = 4;
4529      if (fieldFromInstruction(Insn, 5, 1))
4530        inc = 2;
4531      break;
4532    case 2:
4533      if (fieldFromInstruction(Insn, 5, 1))
4534        return MCDisassembler::Fail; // UNDEFINED
4535      index = fieldFromInstruction(Insn, 7, 1);
4536      if (fieldFromInstruction(Insn, 4, 1) != 0)
4537        align = 8;
4538      if (fieldFromInstruction(Insn, 6, 1))
4539        inc = 2;
4540      break;
4541  }
4542
4543  if (Rm != 0xF) { // Writeback
4544    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4545      return MCDisassembler::Fail;
4546  }
4547  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4548    return MCDisassembler::Fail;
4549  Inst.addOperand(MCOperand::createImm(align));
4550  if (Rm != 0xF) {
4551    if (Rm != 0xD) {
4552      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4553        return MCDisassembler::Fail;
4554    } else
4555      Inst.addOperand(MCOperand::createReg(0));
4556  }
4557
4558  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4559    return MCDisassembler::Fail;
4560  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4561    return MCDisassembler::Fail;
4562  Inst.addOperand(MCOperand::createImm(index));
4563
4564  return S;
4565}
4566
4567
4568static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4569                         uint64_t Address, const void *Decoder) {
4570  DecodeStatus S = MCDisassembler::Success;
4571
4572  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4573  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4574  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4575  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4576  unsigned size = fieldFromInstruction(Insn, 10, 2);
4577
4578  unsigned align = 0;
4579  unsigned index = 0;
4580  unsigned inc = 1;
4581  switch (size) {
4582    default:
4583      return MCDisassembler::Fail;
4584    case 0:
4585      if (fieldFromInstruction(Insn, 4, 1))
4586        return MCDisassembler::Fail; // UNDEFINED
4587      index = fieldFromInstruction(Insn, 5, 3);
4588      break;
4589    case 1:
4590      if (fieldFromInstruction(Insn, 4, 1))
4591        return MCDisassembler::Fail; // UNDEFINED
4592      index = fieldFromInstruction(Insn, 6, 2);
4593      if (fieldFromInstruction(Insn, 5, 1))
4594        inc = 2;
4595      break;
4596    case 2:
4597      if (fieldFromInstruction(Insn, 4, 2))
4598        return MCDisassembler::Fail; // UNDEFINED
4599      index = fieldFromInstruction(Insn, 7, 1);
4600      if (fieldFromInstruction(Insn, 6, 1))
4601        inc = 2;
4602      break;
4603  }
4604
4605  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4606    return MCDisassembler::Fail;
4607  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4608    return MCDisassembler::Fail;
4609  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4610    return MCDisassembler::Fail;
4611
4612  if (Rm != 0xF) { // Writeback
4613    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4614    return MCDisassembler::Fail;
4615  }
4616  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4617    return MCDisassembler::Fail;
4618  Inst.addOperand(MCOperand::createImm(align));
4619  if (Rm != 0xF) {
4620    if (Rm != 0xD) {
4621      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4622    return MCDisassembler::Fail;
4623    } else
4624      Inst.addOperand(MCOperand::createReg(0));
4625  }
4626
4627  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4628    return MCDisassembler::Fail;
4629  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4630    return MCDisassembler::Fail;
4631  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4632    return MCDisassembler::Fail;
4633  Inst.addOperand(MCOperand::createImm(index));
4634
4635  return S;
4636}
4637
4638static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4639                         uint64_t Address, const void *Decoder) {
4640  DecodeStatus S = MCDisassembler::Success;
4641
4642  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4643  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4644  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4645  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4646  unsigned size = fieldFromInstruction(Insn, 10, 2);
4647
4648  unsigned align = 0;
4649  unsigned index = 0;
4650  unsigned inc = 1;
4651  switch (size) {
4652    default:
4653      return MCDisassembler::Fail;
4654    case 0:
4655      if (fieldFromInstruction(Insn, 4, 1))
4656        return MCDisassembler::Fail; // UNDEFINED
4657      index = fieldFromInstruction(Insn, 5, 3);
4658      break;
4659    case 1:
4660      if (fieldFromInstruction(Insn, 4, 1))
4661        return MCDisassembler::Fail; // UNDEFINED
4662      index = fieldFromInstruction(Insn, 6, 2);
4663      if (fieldFromInstruction(Insn, 5, 1))
4664        inc = 2;
4665      break;
4666    case 2:
4667      if (fieldFromInstruction(Insn, 4, 2))
4668        return MCDisassembler::Fail; // UNDEFINED
4669      index = fieldFromInstruction(Insn, 7, 1);
4670      if (fieldFromInstruction(Insn, 6, 1))
4671        inc = 2;
4672      break;
4673  }
4674
4675  if (Rm != 0xF) { // Writeback
4676    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4677    return MCDisassembler::Fail;
4678  }
4679  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4680    return MCDisassembler::Fail;
4681  Inst.addOperand(MCOperand::createImm(align));
4682  if (Rm != 0xF) {
4683    if (Rm != 0xD) {
4684      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4685    return MCDisassembler::Fail;
4686    } else
4687      Inst.addOperand(MCOperand::createReg(0));
4688  }
4689
4690  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4691    return MCDisassembler::Fail;
4692  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4693    return MCDisassembler::Fail;
4694  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4695    return MCDisassembler::Fail;
4696  Inst.addOperand(MCOperand::createImm(index));
4697
4698  return S;
4699}
4700
4701
4702static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4703                         uint64_t Address, const void *Decoder) {
4704  DecodeStatus S = MCDisassembler::Success;
4705
4706  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4707  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4708  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4709  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4710  unsigned size = fieldFromInstruction(Insn, 10, 2);
4711
4712  unsigned align = 0;
4713  unsigned index = 0;
4714  unsigned inc = 1;
4715  switch (size) {
4716    default:
4717      return MCDisassembler::Fail;
4718    case 0:
4719      if (fieldFromInstruction(Insn, 4, 1))
4720        align = 4;
4721      index = fieldFromInstruction(Insn, 5, 3);
4722      break;
4723    case 1:
4724      if (fieldFromInstruction(Insn, 4, 1))
4725        align = 8;
4726      index = fieldFromInstruction(Insn, 6, 2);
4727      if (fieldFromInstruction(Insn, 5, 1))
4728        inc = 2;
4729      break;
4730    case 2:
4731      switch (fieldFromInstruction(Insn, 4, 2)) {
4732        case 0:
4733          align = 0; break;
4734        case 3:
4735          return MCDisassembler::Fail;
4736        default:
4737          align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4738      }
4739
4740      index = fieldFromInstruction(Insn, 7, 1);
4741      if (fieldFromInstruction(Insn, 6, 1))
4742        inc = 2;
4743      break;
4744  }
4745
4746  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4747    return MCDisassembler::Fail;
4748  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4749    return MCDisassembler::Fail;
4750  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4751    return MCDisassembler::Fail;
4752  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4753    return MCDisassembler::Fail;
4754
4755  if (Rm != 0xF) { // Writeback
4756    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4757      return MCDisassembler::Fail;
4758  }
4759  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4760    return MCDisassembler::Fail;
4761  Inst.addOperand(MCOperand::createImm(align));
4762  if (Rm != 0xF) {
4763    if (Rm != 0xD) {
4764      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4765        return MCDisassembler::Fail;
4766    } else
4767      Inst.addOperand(MCOperand::createReg(0));
4768  }
4769
4770  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4771    return MCDisassembler::Fail;
4772  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4773    return MCDisassembler::Fail;
4774  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4775    return MCDisassembler::Fail;
4776  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4777    return MCDisassembler::Fail;
4778  Inst.addOperand(MCOperand::createImm(index));
4779
4780  return S;
4781}
4782
4783static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4784                         uint64_t Address, const void *Decoder) {
4785  DecodeStatus S = MCDisassembler::Success;
4786
4787  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4788  unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4789  unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4790  Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4791  unsigned size = fieldFromInstruction(Insn, 10, 2);
4792
4793  unsigned align = 0;
4794  unsigned index = 0;
4795  unsigned inc = 1;
4796  switch (size) {
4797    default:
4798      return MCDisassembler::Fail;
4799    case 0:
4800      if (fieldFromInstruction(Insn, 4, 1))
4801        align = 4;
4802      index = fieldFromInstruction(Insn, 5, 3);
4803      break;
4804    case 1:
4805      if (fieldFromInstruction(Insn, 4, 1))
4806        align = 8;
4807      index = fieldFromInstruction(Insn, 6, 2);
4808      if (fieldFromInstruction(Insn, 5, 1))
4809        inc = 2;
4810      break;
4811    case 2:
4812      switch (fieldFromInstruction(Insn, 4, 2)) {
4813        case 0:
4814          align = 0; break;
4815        case 3:
4816          return MCDisassembler::Fail;
4817        default:
4818          align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4819      }
4820
4821      index = fieldFromInstruction(Insn, 7, 1);
4822      if (fieldFromInstruction(Insn, 6, 1))
4823        inc = 2;
4824      break;
4825  }
4826
4827  if (Rm != 0xF) { // Writeback
4828    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4829    return MCDisassembler::Fail;
4830  }
4831  if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4832    return MCDisassembler::Fail;
4833  Inst.addOperand(MCOperand::createImm(align));
4834  if (Rm != 0xF) {
4835    if (Rm != 0xD) {
4836      if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4837    return MCDisassembler::Fail;
4838    } else
4839      Inst.addOperand(MCOperand::createReg(0));
4840  }
4841
4842  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4843    return MCDisassembler::Fail;
4844  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4845    return MCDisassembler::Fail;
4846  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4847    return MCDisassembler::Fail;
4848  if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4849    return MCDisassembler::Fail;
4850  Inst.addOperand(MCOperand::createImm(index));
4851
4852  return S;
4853}
4854
4855static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4856                                  uint64_t Address, const void *Decoder) {
4857  DecodeStatus S = MCDisassembler::Success;
4858  unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
4859  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4860  unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
4861  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4862  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4863
4864  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4865    S = MCDisassembler::SoftFail;
4866
4867  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
4868    return MCDisassembler::Fail;
4869  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4870    return MCDisassembler::Fail;
4871  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
4872    return MCDisassembler::Fail;
4873  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4874    return MCDisassembler::Fail;
4875  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4876    return MCDisassembler::Fail;
4877
4878  return S;
4879}
4880
4881static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4882                                  uint64_t Address, const void *Decoder) {
4883  DecodeStatus S = MCDisassembler::Success;
4884  unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
4885  unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4886  unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
4887  unsigned pred = fieldFromInstruction(Insn, 28, 4);
4888  Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4889
4890  if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4891    S = MCDisassembler::SoftFail;
4892
4893  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
4894    return MCDisassembler::Fail;
4895  if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4896    return MCDisassembler::Fail;
4897  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
4898    return MCDisassembler::Fail;
4899  if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4900    return MCDisassembler::Fail;
4901  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4902    return MCDisassembler::Fail;
4903
4904  return S;
4905}
4906
4907static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4908                             uint64_t Address, const void *Decoder) {
4909  DecodeStatus S = MCDisassembler::Success;
4910  unsigned pred = fieldFromInstruction(Insn, 4, 4);
4911  unsigned mask = fieldFromInstruction(Insn, 0, 4);
4912
4913  if (pred == 0xF) {
4914    pred = 0xE;
4915    S = MCDisassembler::SoftFail;
4916  }
4917
4918  if (mask == 0x0)
4919    return MCDisassembler::Fail;
4920
4921  Inst.addOperand(MCOperand::createImm(pred));
4922  Inst.addOperand(MCOperand::createImm(mask));
4923  return S;
4924}
4925
4926static DecodeStatus
4927DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4928                           uint64_t Address, const void *Decoder) {
4929  DecodeStatus S = MCDisassembler::Success;
4930
4931  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4932  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4933  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4934  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4935  unsigned W = fieldFromInstruction(Insn, 21, 1);
4936  unsigned U = fieldFromInstruction(Insn, 23, 1);
4937  unsigned P = fieldFromInstruction(Insn, 24, 1);
4938  bool writeback = (W == 1) | (P == 0);
4939
4940  addr |= (U << 8) | (Rn << 9);
4941
4942  if (writeback && (Rn == Rt || Rn == Rt2))
4943    Check(S, MCDisassembler::SoftFail);
4944  if (Rt == Rt2)
4945    Check(S, MCDisassembler::SoftFail);
4946
4947  // Rt
4948  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4949    return MCDisassembler::Fail;
4950  // Rt2
4951  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4952    return MCDisassembler::Fail;
4953  // Writeback operand
4954  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4955    return MCDisassembler::Fail;
4956  // addr
4957  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4958    return MCDisassembler::Fail;
4959
4960  return S;
4961}
4962
4963static DecodeStatus
4964DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4965                           uint64_t Address, const void *Decoder) {
4966  DecodeStatus S = MCDisassembler::Success;
4967
4968  unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4969  unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4970  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4971  unsigned addr = fieldFromInstruction(Insn, 0, 8);
4972  unsigned W = fieldFromInstruction(Insn, 21, 1);
4973  unsigned U = fieldFromInstruction(Insn, 23, 1);
4974  unsigned P = fieldFromInstruction(Insn, 24, 1);
4975  bool writeback = (W == 1) | (P == 0);
4976
4977  addr |= (U << 8) | (Rn << 9);
4978
4979  if (writeback && (Rn == Rt || Rn == Rt2))
4980    Check(S, MCDisassembler::SoftFail);
4981
4982  // Writeback operand
4983  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4984    return MCDisassembler::Fail;
4985  // Rt
4986  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4987    return MCDisassembler::Fail;
4988  // Rt2
4989  if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4990    return MCDisassembler::Fail;
4991  // addr
4992  if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4993    return MCDisassembler::Fail;
4994
4995  return S;
4996}
4997
4998static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4999                                uint64_t Address, const void *Decoder) {
5000  unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5001  unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5002  if (sign1 != sign2) return MCDisassembler::Fail;
5003
5004  unsigned Val = fieldFromInstruction(Insn, 0, 8);
5005  Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5006  Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5007  Val |= sign1 << 12;
5008  Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5009
5010  return MCDisassembler::Success;
5011}
5012
5013static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5014                                              uint64_t Address,
5015                                              const void *Decoder) {
5016  DecodeStatus S = MCDisassembler::Success;
5017
5018  // Shift of "asr #32" is not allowed in Thumb2 mode.
5019  if (Val == 0x20) S = MCDisassembler::Fail;
5020  Inst.addOperand(MCOperand::createImm(Val));
5021  return S;
5022}
5023
5024static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5025                               uint64_t Address, const void *Decoder) {
5026  unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
5027  unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
5028  unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
5029  unsigned pred = fieldFromInstruction(Insn, 28, 4);
5030
5031  if (pred == 0xF)
5032    return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5033
5034  DecodeStatus S = MCDisassembler::Success;
5035
5036  if (Rt == Rn || Rn == Rt2)
5037    S = MCDisassembler::SoftFail;
5038
5039  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5040    return MCDisassembler::Fail;
5041  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5042    return MCDisassembler::Fail;
5043  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5044    return MCDisassembler::Fail;
5045  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5046    return MCDisassembler::Fail;
5047
5048  return S;
5049}
5050
5051static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5052                                uint64_t Address, const void *Decoder) {
5053  const FeatureBitset &featureBits =
5054      ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5055  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5056
5057  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5058  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5059  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5060  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5061  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5062  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5063  unsigned op = fieldFromInstruction(Insn, 5, 1);
5064
5065  DecodeStatus S = MCDisassembler::Success;
5066
5067  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5068  if (!(imm & 0x38)) {
5069    if (cmode == 0xF) {
5070      if (op == 1) return MCDisassembler::Fail;
5071      Inst.setOpcode(ARM::VMOVv2f32);
5072    }
5073    if (hasFullFP16) {
5074      if (cmode == 0xE) {
5075        if (op == 1) {
5076          Inst.setOpcode(ARM::VMOVv1i64);
5077        } else {
5078          Inst.setOpcode(ARM::VMOVv8i8);
5079        }
5080      }
5081      if (cmode == 0xD) {
5082        if (op == 1) {
5083          Inst.setOpcode(ARM::VMVNv2i32);
5084        } else {
5085          Inst.setOpcode(ARM::VMOVv2i32);
5086        }
5087      }
5088      if (cmode == 0xC) {
5089        if (op == 1) {
5090          Inst.setOpcode(ARM::VMVNv2i32);
5091        } else {
5092          Inst.setOpcode(ARM::VMOVv2i32);
5093        }
5094      }
5095    }
5096    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5097  }
5098
5099  if (!(imm & 0x20)) return MCDisassembler::Fail;
5100
5101  if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5102    return MCDisassembler::Fail;
5103  if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5104    return MCDisassembler::Fail;
5105  Inst.addOperand(MCOperand::createImm(64 - imm));
5106
5107  return S;
5108}
5109
5110static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5111                                uint64_t Address, const void *Decoder) {
5112  const FeatureBitset &featureBits =
5113      ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
5114  bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
5115
5116  unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5117  Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5118  unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5119  Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5120  unsigned imm = fieldFromInstruction(Insn, 16, 6);
5121  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5122  unsigned op = fieldFromInstruction(Insn, 5, 1);
5123
5124  DecodeStatus S = MCDisassembler::Success;
5125
5126  // If the top 3 bits of imm are clear, this is a VMOV (immediate)
5127  if (!(imm & 0x38)) {
5128    if (cmode == 0xF) {
5129      if (op == 1) return MCDisassembler::Fail;
5130      Inst.setOpcode(ARM::VMOVv4f32);
5131    }
5132    if (hasFullFP16) {
5133      if (cmode == 0xE) {
5134        if (op == 1) {
5135          Inst.setOpcode(ARM::VMOVv2i64);
5136        } else {
5137          Inst.setOpcode(ARM::VMOVv16i8);
5138        }
5139      }
5140      if (cmode == 0xD) {
5141        if (op == 1) {
5142          Inst.setOpcode(ARM::VMVNv4i32);
5143        } else {
5144          Inst.setOpcode(ARM::VMOVv4i32);
5145        }
5146      }
5147      if (cmode == 0xC) {
5148        if (op == 1) {
5149          Inst.setOpcode(ARM::VMVNv4i32);
5150        } else {
5151          Inst.setOpcode(ARM::VMOVv4i32);
5152        }
5153      }
5154    }
5155    return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5156  }
5157
5158  if (!(imm & 0x20)) return MCDisassembler::Fail;
5159
5160  if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5161    return MCDisassembler::Fail;
5162  if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5163    return MCDisassembler::Fail;
5164  Inst.addOperand(MCOperand::createImm(64 - imm));
5165
5166  return S;
5167}
5168
5169static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5170                                uint64_t Address, const void *Decoder) {
5171  DecodeStatus S = MCDisassembler::Success;
5172
5173  unsigned Rn = fieldFromInstruction(Val, 16, 4);
5174  unsigned Rt = fieldFromInstruction(Val, 12, 4);
5175  unsigned Rm = fieldFromInstruction(Val, 0, 4);
5176  Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5177  unsigned Cond = fieldFromInstruction(Val, 28, 4);
5178
5179  if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5180    S = MCDisassembler::SoftFail;
5181
5182  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5183    return MCDisassembler::Fail;
5184  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5185    return MCDisassembler::Fail;
5186  if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5187    return MCDisassembler::Fail;
5188  if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5189    return MCDisassembler::Fail;
5190  if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5191    return MCDisassembler::Fail;
5192
5193  return S;
5194}
5195
5196static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5197                                uint64_t Address, const void *Decoder) {
5198
5199  DecodeStatus S = MCDisassembler::Success;
5200
5201  unsigned CRm = fieldFromInstruction(Val, 0, 4);
5202  unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5203  unsigned cop = fieldFromInstruction(Val, 8, 4);
5204  unsigned Rt = fieldFromInstruction(Val, 12, 4);
5205  unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5206
5207  if ((cop & ~0x1) == 0xa)
5208    return MCDisassembler::Fail;
5209
5210  if (Rt == Rt2)
5211    S = MCDisassembler::SoftFail;
5212
5213  Inst.addOperand(MCOperand::createImm(cop));
5214  Inst.addOperand(MCOperand::createImm(opc1));
5215  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5216    return MCDisassembler::Fail;
5217  if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5218    return MCDisassembler::Fail;
5219  Inst.addOperand(MCOperand::createImm(CRm));
5220
5221  return S;
5222}
5223
5224