HexagonInstrInfo.cpp revision 15e56ad8855ff2d135a79efa71b540852acf3b97
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Hexagon implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "HexagonInstrInfo.h" 15#include "HexagonRegisterInfo.h" 16#include "HexagonSubtarget.h" 17#include "Hexagon.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/DFAPacketizer.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Support/MathExtras.h" 27#define GET_INSTRINFO_CTOR 28#include "HexagonGenInstrInfo.inc" 29#include "HexagonGenDFAPacketizer.inc" 30 31using namespace llvm; 32 33/// 34/// Constants for Hexagon instructions. 35/// 36const int Hexagon_MEMW_OFFSET_MAX = 4095; 37const int Hexagon_MEMW_OFFSET_MIN = -4096; 38const int Hexagon_MEMD_OFFSET_MAX = 8191; 39const int Hexagon_MEMD_OFFSET_MIN = -8192; 40const int Hexagon_MEMH_OFFSET_MAX = 2047; 41const int Hexagon_MEMH_OFFSET_MIN = -2048; 42const int Hexagon_MEMB_OFFSET_MAX = 1023; 43const int Hexagon_MEMB_OFFSET_MIN = -1024; 44const int Hexagon_ADDI_OFFSET_MAX = 32767; 45const int Hexagon_ADDI_OFFSET_MIN = -32768; 46const int Hexagon_MEMD_AUTOINC_MAX = 56; 47const int Hexagon_MEMD_AUTOINC_MIN = -64; 48const int Hexagon_MEMW_AUTOINC_MAX = 28; 49const int Hexagon_MEMW_AUTOINC_MIN = -32; 50const int Hexagon_MEMH_AUTOINC_MAX = 14; 51const int Hexagon_MEMH_AUTOINC_MIN = -16; 52const int Hexagon_MEMB_AUTOINC_MAX = 7; 53const int Hexagon_MEMB_AUTOINC_MIN = -8; 54 55 56 57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) 58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), 59 RI(ST, *this), Subtarget(ST) { 60} 61 62 63/// isLoadFromStackSlot - If the specified machine instruction is a direct 64/// load from a stack slot, return the virtual or physical register number of 65/// the destination along with the FrameIndex of the loaded stack slot. If 66/// not, return 0. This predicate must return 0 if the instruction has 67/// any side effects other than loading from the stack slot. 68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 69 int &FrameIndex) const { 70 71 72 switch (MI->getOpcode()) { 73 default: break; 74 case Hexagon::LDriw: 75 case Hexagon::LDrid: 76 case Hexagon::LDrih: 77 case Hexagon::LDrib: 78 case Hexagon::LDriub: 79 if (MI->getOperand(2).isFI() && 80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 81 FrameIndex = MI->getOperand(2).getIndex(); 82 return MI->getOperand(0).getReg(); 83 } 84 break; 85 } 86 return 0; 87} 88 89 90/// isStoreToStackSlot - If the specified machine instruction is a direct 91/// store to a stack slot, return the virtual or physical register number of 92/// the source reg along with the FrameIndex of the loaded stack slot. If 93/// not, return 0. This predicate must return 0 if the instruction has 94/// any side effects other than storing to the stack slot. 95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const { 97 switch (MI->getOpcode()) { 98 default: break; 99 case Hexagon::STriw: 100 case Hexagon::STrid: 101 case Hexagon::STrih: 102 case Hexagon::STrib: 103 if (MI->getOperand(2).isFI() && 104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 105 FrameIndex = MI->getOperand(2).getIndex(); 106 return MI->getOperand(0).getReg(); 107 } 108 break; 109 } 110 return 0; 111} 112 113 114unsigned 115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 116 MachineBasicBlock *FBB, 117 const SmallVectorImpl<MachineOperand> &Cond, 118 DebugLoc DL) const{ 119 120 int BOpc = Hexagon::JMP; 121 int BccOpc = Hexagon::JMP_c; 122 123 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 124 125 int regPos = 0; 126 // Check if ReverseBranchCondition has asked to reverse this branch 127 // If we want to reverse the branch an odd number of times, we want 128 // JMP_cNot. 129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 130 BccOpc = Hexagon::JMP_cNot; 131 regPos = 1; 132 } 133 134 if (FBB == 0) { 135 if (Cond.empty()) { 136 // Due to a bug in TailMerging/CFG Optimization, we need to add a 137 // special case handling of a predicated jump followed by an 138 // unconditional jump. If not, Tail Merging and CFG Optimization go 139 // into an infinite loop. 140 MachineBasicBlock *NewTBB, *NewFBB; 141 SmallVector<MachineOperand, 4> Cond; 142 MachineInstr *Term = MBB.getFirstTerminator(); 143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, 144 false)) { 145 MachineBasicBlock *NextBB = 146 llvm::next(MachineFunction::iterator(&MBB)); 147 if (NewTBB == NextBB) { 148 ReverseBranchCondition(Cond); 149 RemoveBranch(MBB); 150 return InsertBranch(MBB, TBB, 0, Cond, DL); 151 } 152 } 153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 154 } else { 155 BuildMI(&MBB, DL, 156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 157 } 158 return 1; 159 } 160 161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 163 164 return 2; 165} 166 167 168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 169 MachineBasicBlock *&TBB, 170 MachineBasicBlock *&FBB, 171 SmallVectorImpl<MachineOperand> &Cond, 172 bool AllowModify) const { 173 FBB = NULL; 174 175 // If the block has no terminators, it just falls into the block after it. 176 MachineBasicBlock::iterator I = MBB.end(); 177 if (I == MBB.begin()) 178 return false; 179 180 // A basic block may looks like this: 181 // 182 // [ insn 183 // EH_LABEL 184 // insn 185 // insn 186 // insn 187 // EH_LABEL 188 // insn ] 189 // 190 // It has two succs but does not have a terminator 191 // Don't know how to handle it. 192 do { 193 --I; 194 if (I->isEHLabel()) 195 return true; 196 } while (I != MBB.begin()); 197 198 I = MBB.end(); 199 --I; 200 201 while (I->isDebugValue()) { 202 if (I == MBB.begin()) 203 return false; 204 --I; 205 } 206 if (!isUnpredicatedTerminator(I)) 207 return false; 208 209 // Get the last instruction in the block. 210 MachineInstr *LastInst = I; 211 212 // If there is only one terminator instruction, process it. 213 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 214 if (LastInst->getOpcode() == Hexagon::JMP) { 215 TBB = LastInst->getOperand(0).getMBB(); 216 return false; 217 } 218 if (LastInst->getOpcode() == Hexagon::JMP_c) { 219 // Block ends with fall-through true condbranch. 220 TBB = LastInst->getOperand(1).getMBB(); 221 Cond.push_back(LastInst->getOperand(0)); 222 return false; 223 } 224 if (LastInst->getOpcode() == Hexagon::JMP_cNot) { 225 // Block ends with fall-through false condbranch. 226 TBB = LastInst->getOperand(1).getMBB(); 227 Cond.push_back(MachineOperand::CreateImm(0)); 228 Cond.push_back(LastInst->getOperand(0)); 229 return false; 230 } 231 // Otherwise, don't know what this is. 232 return true; 233 } 234 235 // Get the instruction before it if it's a terminator. 236 MachineInstr *SecondLastInst = I; 237 238 // If there are three terminators, we don't know what sort of block this is. 239 if (SecondLastInst && I != MBB.begin() && 240 isUnpredicatedTerminator(--I)) 241 return true; 242 243 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. 244 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || 245 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && 246 LastInst->getOpcode() == Hexagon::JMP) { 247 TBB = SecondLastInst->getOperand(1).getMBB(); 248 Cond.push_back(SecondLastInst->getOperand(0)); 249 FBB = LastInst->getOperand(0).getMBB(); 250 return false; 251 } 252 253 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. 254 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && 255 LastInst->getOpcode() == Hexagon::JMP) { 256 TBB = SecondLastInst->getOperand(1).getMBB(); 257 Cond.push_back(MachineOperand::CreateImm(0)); 258 Cond.push_back(SecondLastInst->getOperand(0)); 259 FBB = LastInst->getOperand(0).getMBB(); 260 return false; 261 } 262 263 // If the block ends with two Hexagon:JMPs, handle it. The second one is not 264 // executed, so remove it. 265 if (SecondLastInst->getOpcode() == Hexagon::JMP && 266 LastInst->getOpcode() == Hexagon::JMP) { 267 TBB = SecondLastInst->getOperand(0).getMBB(); 268 I = LastInst; 269 if (AllowModify) 270 I->eraseFromParent(); 271 return false; 272 } 273 274 // Otherwise, can't handle this. 275 return true; 276} 277 278 279unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 280 int BOpc = Hexagon::JMP; 281 int BccOpc = Hexagon::JMP_c; 282 int BccOpcNot = Hexagon::JMP_cNot; 283 284 MachineBasicBlock::iterator I = MBB.end(); 285 if (I == MBB.begin()) return 0; 286 --I; 287 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc && 288 I->getOpcode() != BccOpcNot) 289 return 0; 290 291 // Remove the branch. 292 I->eraseFromParent(); 293 294 I = MBB.end(); 295 296 if (I == MBB.begin()) return 1; 297 --I; 298 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot) 299 return 1; 300 301 // Remove the branch. 302 I->eraseFromParent(); 303 return 2; 304} 305 306 307void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 308 MachineBasicBlock::iterator I, DebugLoc DL, 309 unsigned DestReg, unsigned SrcReg, 310 bool KillSrc) const { 311 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 312 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 313 return; 314 } 315 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 316 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg); 317 return; 318 } 319 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 320 // Map Pd = Ps to Pd = or(Ps, Ps). 321 BuildMI(MBB, I, DL, get(Hexagon::OR_pp), 322 DestReg).addReg(SrcReg).addReg(SrcReg); 323 return; 324 } 325 if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) { 326 // We can have an overlap between single and double reg: r1:0 = r0. 327 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 328 // r1:0 = r0 329 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 330 Hexagon::subreg_hireg))).addImm(0); 331 } else { 332 // r1:0 = r1 or no overlap. 333 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 334 Hexagon::subreg_loreg))).addReg(SrcReg); 335 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 336 Hexagon::subreg_hireg))).addImm(0); 337 } 338 return; 339 } 340 if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) { 341 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); 342 return; 343 } 344 345 llvm_unreachable("Unimplemented"); 346} 347 348 349void HexagonInstrInfo:: 350storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 351 unsigned SrcReg, bool isKill, int FI, 352 const TargetRegisterClass *RC, 353 const TargetRegisterInfo *TRI) const { 354 355 DebugLoc DL = MBB.findDebugLoc(I); 356 MachineFunction &MF = *MBB.getParent(); 357 MachineFrameInfo &MFI = *MF.getFrameInfo(); 358 unsigned Align = MFI.getObjectAlignment(FI); 359 360 MachineMemOperand *MMO = 361 MF.getMachineMemOperand( 362 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 363 MachineMemOperand::MOStore, 364 MFI.getObjectSize(FI), 365 Align); 366 367 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 368 BuildMI(MBB, I, DL, get(Hexagon::STriw)) 369 .addFrameIndex(FI).addImm(0) 370 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 371 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 372 BuildMI(MBB, I, DL, get(Hexagon::STrid)) 373 .addFrameIndex(FI).addImm(0) 374 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 375 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 376 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) 377 .addFrameIndex(FI).addImm(0) 378 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 379 } else { 380 llvm_unreachable("Unimplemented"); 381 } 382} 383 384 385void HexagonInstrInfo::storeRegToAddr( 386 MachineFunction &MF, unsigned SrcReg, 387 bool isKill, 388 SmallVectorImpl<MachineOperand> &Addr, 389 const TargetRegisterClass *RC, 390 SmallVectorImpl<MachineInstr*> &NewMIs) const 391{ 392 llvm_unreachable("Unimplemented"); 393} 394 395 396void HexagonInstrInfo:: 397loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 398 unsigned DestReg, int FI, 399 const TargetRegisterClass *RC, 400 const TargetRegisterInfo *TRI) const { 401 DebugLoc DL = MBB.findDebugLoc(I); 402 MachineFunction &MF = *MBB.getParent(); 403 MachineFrameInfo &MFI = *MF.getFrameInfo(); 404 unsigned Align = MFI.getObjectAlignment(FI); 405 406 MachineMemOperand *MMO = 407 MF.getMachineMemOperand( 408 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 409 MachineMemOperand::MOLoad, 410 MFI.getObjectSize(FI), 411 Align); 412 if (RC == &Hexagon::IntRegsRegClass) { 413 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) 414 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 415 } else if (RC == &Hexagon::DoubleRegsRegClass) { 416 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) 417 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 418 } else if (RC == &Hexagon::PredRegsRegClass) { 419 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) 420 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 421 } else { 422 llvm_unreachable("Can't store this register to stack slot"); 423 } 424} 425 426 427void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 428 SmallVectorImpl<MachineOperand> &Addr, 429 const TargetRegisterClass *RC, 430 SmallVectorImpl<MachineInstr*> &NewMIs) const { 431 llvm_unreachable("Unimplemented"); 432} 433 434 435MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 436 MachineInstr* MI, 437 const SmallVectorImpl<unsigned> &Ops, 438 int FI) const { 439 // Hexagon_TODO: Implement. 440 return(0); 441} 442 443 444unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { 445 446 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 447 const TargetRegisterClass *TRC; 448 if (VT == MVT::i1) { 449 TRC = &Hexagon::PredRegsRegClass; 450 } else if (VT == MVT::i32 || VT == MVT::f32) { 451 TRC = &Hexagon::IntRegsRegClass; 452 } else if (VT == MVT::i64 || VT == MVT::f64) { 453 TRC = &Hexagon::DoubleRegsRegClass; 454 } else { 455 llvm_unreachable("Cannot handle this register class"); 456 } 457 458 unsigned NewReg = RegInfo.createVirtualRegister(TRC); 459 return NewReg; 460} 461 462bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { 463 switch(MI->getOpcode()) { 464 default: return false; 465 // JMP_EQri 466 case Hexagon::JMP_EQriPt_nv_V4: 467 case Hexagon::JMP_EQriPnt_nv_V4: 468 case Hexagon::JMP_EQriNotPt_nv_V4: 469 case Hexagon::JMP_EQriNotPnt_nv_V4: 470 471 // JMP_EQri - with -1 472 case Hexagon::JMP_EQriPtneg_nv_V4: 473 case Hexagon::JMP_EQriPntneg_nv_V4: 474 case Hexagon::JMP_EQriNotPtneg_nv_V4: 475 case Hexagon::JMP_EQriNotPntneg_nv_V4: 476 477 // JMP_EQrr 478 case Hexagon::JMP_EQrrPt_nv_V4: 479 case Hexagon::JMP_EQrrPnt_nv_V4: 480 case Hexagon::JMP_EQrrNotPt_nv_V4: 481 case Hexagon::JMP_EQrrNotPnt_nv_V4: 482 483 // JMP_GTri 484 case Hexagon::JMP_GTriPt_nv_V4: 485 case Hexagon::JMP_GTriPnt_nv_V4: 486 case Hexagon::JMP_GTriNotPt_nv_V4: 487 case Hexagon::JMP_GTriNotPnt_nv_V4: 488 489 // JMP_GTri - with -1 490 case Hexagon::JMP_GTriPtneg_nv_V4: 491 case Hexagon::JMP_GTriPntneg_nv_V4: 492 case Hexagon::JMP_GTriNotPtneg_nv_V4: 493 case Hexagon::JMP_GTriNotPntneg_nv_V4: 494 495 // JMP_GTrr 496 case Hexagon::JMP_GTrrPt_nv_V4: 497 case Hexagon::JMP_GTrrPnt_nv_V4: 498 case Hexagon::JMP_GTrrNotPt_nv_V4: 499 case Hexagon::JMP_GTrrNotPnt_nv_V4: 500 501 // JMP_GTrrdn 502 case Hexagon::JMP_GTrrdnPt_nv_V4: 503 case Hexagon::JMP_GTrrdnPnt_nv_V4: 504 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 505 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 506 507 // JMP_GTUri 508 case Hexagon::JMP_GTUriPt_nv_V4: 509 case Hexagon::JMP_GTUriPnt_nv_V4: 510 case Hexagon::JMP_GTUriNotPt_nv_V4: 511 case Hexagon::JMP_GTUriNotPnt_nv_V4: 512 513 // JMP_GTUrr 514 case Hexagon::JMP_GTUrrPt_nv_V4: 515 case Hexagon::JMP_GTUrrPnt_nv_V4: 516 case Hexagon::JMP_GTUrrNotPt_nv_V4: 517 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 518 519 // JMP_GTUrrdn 520 case Hexagon::JMP_GTUrrdnPt_nv_V4: 521 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 522 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 523 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 524 525 // TFR_FI 526 case Hexagon::TFR_FI: 527 return true; 528 } 529} 530 531bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { 532 switch(MI->getOpcode()) { 533 default: return false; 534 // JMP_EQri 535 case Hexagon::JMP_EQriPt_ie_nv_V4: 536 case Hexagon::JMP_EQriPnt_ie_nv_V4: 537 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 538 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 539 540 // JMP_EQri - with -1 541 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 542 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 543 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 544 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 545 546 // JMP_EQrr 547 case Hexagon::JMP_EQrrPt_ie_nv_V4: 548 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 549 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 550 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 551 552 // JMP_GTri 553 case Hexagon::JMP_GTriPt_ie_nv_V4: 554 case Hexagon::JMP_GTriPnt_ie_nv_V4: 555 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 556 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 557 558 // JMP_GTri - with -1 559 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 560 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 561 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 562 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 563 564 // JMP_GTrr 565 case Hexagon::JMP_GTrrPt_ie_nv_V4: 566 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 567 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 568 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 569 570 // JMP_GTrrdn 571 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 572 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 573 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 574 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 575 576 // JMP_GTUri 577 case Hexagon::JMP_GTUriPt_ie_nv_V4: 578 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 579 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 580 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 581 582 // JMP_GTUrr 583 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 584 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 585 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 586 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 587 588 // JMP_GTUrrdn 589 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 590 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 591 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 592 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 593 594 // V4 absolute set addressing. 595 case Hexagon::LDrid_abs_setimm_V4: 596 case Hexagon::LDriw_abs_setimm_V4: 597 case Hexagon::LDrih_abs_setimm_V4: 598 case Hexagon::LDrib_abs_setimm_V4: 599 case Hexagon::LDriuh_abs_setimm_V4: 600 case Hexagon::LDriub_abs_setimm_V4: 601 602 case Hexagon::STrid_abs_setimm_V4: 603 case Hexagon::STrib_abs_setimm_V4: 604 case Hexagon::STrih_abs_setimm_V4: 605 case Hexagon::STriw_abs_setimm_V4: 606 607 // V4 global address load. 608 case Hexagon::LDrid_GP_cPt_V4 : 609 case Hexagon::LDrid_GP_cNotPt_V4 : 610 case Hexagon::LDrid_GP_cdnPt_V4 : 611 case Hexagon::LDrid_GP_cdnNotPt_V4 : 612 case Hexagon::LDrib_GP_cPt_V4 : 613 case Hexagon::LDrib_GP_cNotPt_V4 : 614 case Hexagon::LDrib_GP_cdnPt_V4 : 615 case Hexagon::LDrib_GP_cdnNotPt_V4 : 616 case Hexagon::LDriub_GP_cPt_V4 : 617 case Hexagon::LDriub_GP_cNotPt_V4 : 618 case Hexagon::LDriub_GP_cdnPt_V4 : 619 case Hexagon::LDriub_GP_cdnNotPt_V4 : 620 case Hexagon::LDrih_GP_cPt_V4 : 621 case Hexagon::LDrih_GP_cNotPt_V4 : 622 case Hexagon::LDrih_GP_cdnPt_V4 : 623 case Hexagon::LDrih_GP_cdnNotPt_V4 : 624 case Hexagon::LDriuh_GP_cPt_V4 : 625 case Hexagon::LDriuh_GP_cNotPt_V4 : 626 case Hexagon::LDriuh_GP_cdnPt_V4 : 627 case Hexagon::LDriuh_GP_cdnNotPt_V4 : 628 case Hexagon::LDriw_GP_cPt_V4 : 629 case Hexagon::LDriw_GP_cNotPt_V4 : 630 case Hexagon::LDriw_GP_cdnPt_V4 : 631 case Hexagon::LDriw_GP_cdnNotPt_V4 : 632 case Hexagon::LDd_GP_cPt_V4 : 633 case Hexagon::LDd_GP_cNotPt_V4 : 634 case Hexagon::LDd_GP_cdnPt_V4 : 635 case Hexagon::LDd_GP_cdnNotPt_V4 : 636 case Hexagon::LDb_GP_cPt_V4 : 637 case Hexagon::LDb_GP_cNotPt_V4 : 638 case Hexagon::LDb_GP_cdnPt_V4 : 639 case Hexagon::LDb_GP_cdnNotPt_V4 : 640 case Hexagon::LDub_GP_cPt_V4 : 641 case Hexagon::LDub_GP_cNotPt_V4 : 642 case Hexagon::LDub_GP_cdnPt_V4 : 643 case Hexagon::LDub_GP_cdnNotPt_V4 : 644 case Hexagon::LDh_GP_cPt_V4 : 645 case Hexagon::LDh_GP_cNotPt_V4 : 646 case Hexagon::LDh_GP_cdnPt_V4 : 647 case Hexagon::LDh_GP_cdnNotPt_V4 : 648 case Hexagon::LDuh_GP_cPt_V4 : 649 case Hexagon::LDuh_GP_cNotPt_V4 : 650 case Hexagon::LDuh_GP_cdnPt_V4 : 651 case Hexagon::LDuh_GP_cdnNotPt_V4 : 652 case Hexagon::LDw_GP_cPt_V4 : 653 case Hexagon::LDw_GP_cNotPt_V4 : 654 case Hexagon::LDw_GP_cdnPt_V4 : 655 case Hexagon::LDw_GP_cdnNotPt_V4 : 656 657 // V4 global address store. 658 case Hexagon::STrid_GP_cPt_V4 : 659 case Hexagon::STrid_GP_cNotPt_V4 : 660 case Hexagon::STrid_GP_cdnPt_V4 : 661 case Hexagon::STrid_GP_cdnNotPt_V4 : 662 case Hexagon::STrib_GP_cPt_V4 : 663 case Hexagon::STrib_GP_cNotPt_V4 : 664 case Hexagon::STrib_GP_cdnPt_V4 : 665 case Hexagon::STrib_GP_cdnNotPt_V4 : 666 case Hexagon::STrih_GP_cPt_V4 : 667 case Hexagon::STrih_GP_cNotPt_V4 : 668 case Hexagon::STrih_GP_cdnPt_V4 : 669 case Hexagon::STrih_GP_cdnNotPt_V4 : 670 case Hexagon::STriw_GP_cPt_V4 : 671 case Hexagon::STriw_GP_cNotPt_V4 : 672 case Hexagon::STriw_GP_cdnPt_V4 : 673 case Hexagon::STriw_GP_cdnNotPt_V4 : 674 case Hexagon::STd_GP_cPt_V4 : 675 case Hexagon::STd_GP_cNotPt_V4 : 676 case Hexagon::STd_GP_cdnPt_V4 : 677 case Hexagon::STd_GP_cdnNotPt_V4 : 678 case Hexagon::STb_GP_cPt_V4 : 679 case Hexagon::STb_GP_cNotPt_V4 : 680 case Hexagon::STb_GP_cdnPt_V4 : 681 case Hexagon::STb_GP_cdnNotPt_V4 : 682 case Hexagon::STh_GP_cPt_V4 : 683 case Hexagon::STh_GP_cNotPt_V4 : 684 case Hexagon::STh_GP_cdnPt_V4 : 685 case Hexagon::STh_GP_cdnNotPt_V4 : 686 case Hexagon::STw_GP_cPt_V4 : 687 case Hexagon::STw_GP_cNotPt_V4 : 688 case Hexagon::STw_GP_cdnPt_V4 : 689 case Hexagon::STw_GP_cdnNotPt_V4 : 690 691 // V4 predicated global address new value store. 692 case Hexagon::STrib_GP_cPt_nv_V4 : 693 case Hexagon::STrib_GP_cNotPt_nv_V4 : 694 case Hexagon::STrib_GP_cdnPt_nv_V4 : 695 case Hexagon::STrib_GP_cdnNotPt_nv_V4 : 696 case Hexagon::STrih_GP_cPt_nv_V4 : 697 case Hexagon::STrih_GP_cNotPt_nv_V4 : 698 case Hexagon::STrih_GP_cdnPt_nv_V4 : 699 case Hexagon::STrih_GP_cdnNotPt_nv_V4 : 700 case Hexagon::STriw_GP_cPt_nv_V4 : 701 case Hexagon::STriw_GP_cNotPt_nv_V4 : 702 case Hexagon::STriw_GP_cdnPt_nv_V4 : 703 case Hexagon::STriw_GP_cdnNotPt_nv_V4 : 704 case Hexagon::STb_GP_cPt_nv_V4 : 705 case Hexagon::STb_GP_cNotPt_nv_V4 : 706 case Hexagon::STb_GP_cdnPt_nv_V4 : 707 case Hexagon::STb_GP_cdnNotPt_nv_V4 : 708 case Hexagon::STh_GP_cPt_nv_V4 : 709 case Hexagon::STh_GP_cNotPt_nv_V4 : 710 case Hexagon::STh_GP_cdnPt_nv_V4 : 711 case Hexagon::STh_GP_cdnNotPt_nv_V4 : 712 case Hexagon::STw_GP_cPt_nv_V4 : 713 case Hexagon::STw_GP_cNotPt_nv_V4 : 714 case Hexagon::STw_GP_cdnPt_nv_V4 : 715 case Hexagon::STw_GP_cdnNotPt_nv_V4 : 716 717 // TFR_FI 718 case Hexagon::TFR_FI_immext_V4: 719 720 // TFRI_F 721 case Hexagon::TFRI_f: 722 case Hexagon::TFRI_cPt_f: 723 case Hexagon::TFRI_cNotPt_f: 724 case Hexagon::CONST64_Float_Real: 725 return true; 726 } 727} 728 729bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { 730 switch (MI->getOpcode()) { 731 default: return false; 732 // JMP_EQri 733 case Hexagon::JMP_EQriPt_nv_V4: 734 case Hexagon::JMP_EQriPnt_nv_V4: 735 case Hexagon::JMP_EQriNotPt_nv_V4: 736 case Hexagon::JMP_EQriNotPnt_nv_V4: 737 case Hexagon::JMP_EQriPt_ie_nv_V4: 738 case Hexagon::JMP_EQriPnt_ie_nv_V4: 739 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 740 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 741 742 // JMP_EQri - with -1 743 case Hexagon::JMP_EQriPtneg_nv_V4: 744 case Hexagon::JMP_EQriPntneg_nv_V4: 745 case Hexagon::JMP_EQriNotPtneg_nv_V4: 746 case Hexagon::JMP_EQriNotPntneg_nv_V4: 747 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 748 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 749 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 750 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 751 752 // JMP_EQrr 753 case Hexagon::JMP_EQrrPt_nv_V4: 754 case Hexagon::JMP_EQrrPnt_nv_V4: 755 case Hexagon::JMP_EQrrNotPt_nv_V4: 756 case Hexagon::JMP_EQrrNotPnt_nv_V4: 757 case Hexagon::JMP_EQrrPt_ie_nv_V4: 758 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 759 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 760 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 761 762 // JMP_GTri 763 case Hexagon::JMP_GTriPt_nv_V4: 764 case Hexagon::JMP_GTriPnt_nv_V4: 765 case Hexagon::JMP_GTriNotPt_nv_V4: 766 case Hexagon::JMP_GTriNotPnt_nv_V4: 767 case Hexagon::JMP_GTriPt_ie_nv_V4: 768 case Hexagon::JMP_GTriPnt_ie_nv_V4: 769 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 770 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 771 772 // JMP_GTri - with -1 773 case Hexagon::JMP_GTriPtneg_nv_V4: 774 case Hexagon::JMP_GTriPntneg_nv_V4: 775 case Hexagon::JMP_GTriNotPtneg_nv_V4: 776 case Hexagon::JMP_GTriNotPntneg_nv_V4: 777 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 778 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 779 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 780 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 781 782 // JMP_GTrr 783 case Hexagon::JMP_GTrrPt_nv_V4: 784 case Hexagon::JMP_GTrrPnt_nv_V4: 785 case Hexagon::JMP_GTrrNotPt_nv_V4: 786 case Hexagon::JMP_GTrrNotPnt_nv_V4: 787 case Hexagon::JMP_GTrrPt_ie_nv_V4: 788 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 789 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 790 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 791 792 // JMP_GTrrdn 793 case Hexagon::JMP_GTrrdnPt_nv_V4: 794 case Hexagon::JMP_GTrrdnPnt_nv_V4: 795 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 796 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 797 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 798 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 799 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 800 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 801 802 // JMP_GTUri 803 case Hexagon::JMP_GTUriPt_nv_V4: 804 case Hexagon::JMP_GTUriPnt_nv_V4: 805 case Hexagon::JMP_GTUriNotPt_nv_V4: 806 case Hexagon::JMP_GTUriNotPnt_nv_V4: 807 case Hexagon::JMP_GTUriPt_ie_nv_V4: 808 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 809 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 810 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 811 812 // JMP_GTUrr 813 case Hexagon::JMP_GTUrrPt_nv_V4: 814 case Hexagon::JMP_GTUrrPnt_nv_V4: 815 case Hexagon::JMP_GTUrrNotPt_nv_V4: 816 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 817 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 818 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 819 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 820 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 821 822 // JMP_GTUrrdn 823 case Hexagon::JMP_GTUrrdnPt_nv_V4: 824 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 825 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 826 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 827 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 828 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 829 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 830 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 831 return true; 832 } 833} 834 835unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const { 836 switch(MI->getOpcode()) { 837 default: llvm_unreachable("Unknown type of instruction."); 838 // JMP_EQri 839 case Hexagon::JMP_EQriPt_nv_V4: 840 return Hexagon::JMP_EQriPt_ie_nv_V4; 841 case Hexagon::JMP_EQriNotPt_nv_V4: 842 return Hexagon::JMP_EQriNotPt_ie_nv_V4; 843 case Hexagon::JMP_EQriPnt_nv_V4: 844 return Hexagon::JMP_EQriPnt_ie_nv_V4; 845 case Hexagon::JMP_EQriNotPnt_nv_V4: 846 return Hexagon::JMP_EQriNotPnt_ie_nv_V4; 847 848 // JMP_EQri -- with -1 849 case Hexagon::JMP_EQriPtneg_nv_V4: 850 return Hexagon::JMP_EQriPtneg_ie_nv_V4; 851 case Hexagon::JMP_EQriNotPtneg_nv_V4: 852 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4; 853 case Hexagon::JMP_EQriPntneg_nv_V4: 854 return Hexagon::JMP_EQriPntneg_ie_nv_V4; 855 case Hexagon::JMP_EQriNotPntneg_nv_V4: 856 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4; 857 858 // JMP_EQrr 859 case Hexagon::JMP_EQrrPt_nv_V4: 860 return Hexagon::JMP_EQrrPt_ie_nv_V4; 861 case Hexagon::JMP_EQrrNotPt_nv_V4: 862 return Hexagon::JMP_EQrrNotPt_ie_nv_V4; 863 case Hexagon::JMP_EQrrPnt_nv_V4: 864 return Hexagon::JMP_EQrrPnt_ie_nv_V4; 865 case Hexagon::JMP_EQrrNotPnt_nv_V4: 866 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4; 867 868 // JMP_GTri 869 case Hexagon::JMP_GTriPt_nv_V4: 870 return Hexagon::JMP_GTriPt_ie_nv_V4; 871 case Hexagon::JMP_GTriNotPt_nv_V4: 872 return Hexagon::JMP_GTriNotPt_ie_nv_V4; 873 case Hexagon::JMP_GTriPnt_nv_V4: 874 return Hexagon::JMP_GTriPnt_ie_nv_V4; 875 case Hexagon::JMP_GTriNotPnt_nv_V4: 876 return Hexagon::JMP_GTriNotPnt_ie_nv_V4; 877 878 // JMP_GTri -- with -1 879 case Hexagon::JMP_GTriPtneg_nv_V4: 880 return Hexagon::JMP_GTriPtneg_ie_nv_V4; 881 case Hexagon::JMP_GTriNotPtneg_nv_V4: 882 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4; 883 case Hexagon::JMP_GTriPntneg_nv_V4: 884 return Hexagon::JMP_GTriPntneg_ie_nv_V4; 885 case Hexagon::JMP_GTriNotPntneg_nv_V4: 886 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4; 887 888 // JMP_GTrr 889 case Hexagon::JMP_GTrrPt_nv_V4: 890 return Hexagon::JMP_GTrrPt_ie_nv_V4; 891 case Hexagon::JMP_GTrrNotPt_nv_V4: 892 return Hexagon::JMP_GTrrNotPt_ie_nv_V4; 893 case Hexagon::JMP_GTrrPnt_nv_V4: 894 return Hexagon::JMP_GTrrPnt_ie_nv_V4; 895 case Hexagon::JMP_GTrrNotPnt_nv_V4: 896 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4; 897 898 // JMP_GTrrdn 899 case Hexagon::JMP_GTrrdnPt_nv_V4: 900 return Hexagon::JMP_GTrrdnPt_ie_nv_V4; 901 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 902 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4; 903 case Hexagon::JMP_GTrrdnPnt_nv_V4: 904 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4; 905 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 906 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4; 907 908 // JMP_GTUri 909 case Hexagon::JMP_GTUriPt_nv_V4: 910 return Hexagon::JMP_GTUriPt_ie_nv_V4; 911 case Hexagon::JMP_GTUriNotPt_nv_V4: 912 return Hexagon::JMP_GTUriNotPt_ie_nv_V4; 913 case Hexagon::JMP_GTUriPnt_nv_V4: 914 return Hexagon::JMP_GTUriPnt_ie_nv_V4; 915 case Hexagon::JMP_GTUriNotPnt_nv_V4: 916 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4; 917 918 // JMP_GTUrr 919 case Hexagon::JMP_GTUrrPt_nv_V4: 920 return Hexagon::JMP_GTUrrPt_ie_nv_V4; 921 case Hexagon::JMP_GTUrrNotPt_nv_V4: 922 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4; 923 case Hexagon::JMP_GTUrrPnt_nv_V4: 924 return Hexagon::JMP_GTUrrPnt_ie_nv_V4; 925 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 926 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4; 927 928 // JMP_GTUrrdn 929 case Hexagon::JMP_GTUrrdnPt_nv_V4: 930 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4; 931 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 932 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4; 933 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 934 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4; 935 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 936 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4; 937 938 case Hexagon::TFR_FI: 939 return Hexagon::TFR_FI_immext_V4; 940 941 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 942 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 943 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 944 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 945 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 946 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 947 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 948 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 949 case Hexagon::MEMw_ADDi_MEM_V4 : 950 case Hexagon::MEMw_SUBi_MEM_V4 : 951 case Hexagon::MEMw_ADDr_MEM_V4 : 952 case Hexagon::MEMw_SUBr_MEM_V4 : 953 case Hexagon::MEMw_ANDr_MEM_V4 : 954 case Hexagon::MEMw_ORr_MEM_V4 : 955 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 956 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 957 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 958 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 959 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 960 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 961 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 962 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 963 case Hexagon::MEMh_ADDi_MEM_V4 : 964 case Hexagon::MEMh_SUBi_MEM_V4 : 965 case Hexagon::MEMh_ADDr_MEM_V4 : 966 case Hexagon::MEMh_SUBr_MEM_V4 : 967 case Hexagon::MEMh_ANDr_MEM_V4 : 968 case Hexagon::MEMh_ORr_MEM_V4 : 969 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 970 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 971 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 972 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 973 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 974 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 975 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 976 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 977 case Hexagon::MEMb_ADDi_MEM_V4 : 978 case Hexagon::MEMb_SUBi_MEM_V4 : 979 case Hexagon::MEMb_ADDr_MEM_V4 : 980 case Hexagon::MEMb_SUBr_MEM_V4 : 981 case Hexagon::MEMb_ANDr_MEM_V4 : 982 case Hexagon::MEMb_ORr_MEM_V4 : 983 llvm_unreachable("Needs implementing"); 984 } 985} 986 987unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const { 988 switch(MI->getOpcode()) { 989 default: llvm_unreachable("Unknown type of jump instruction."); 990 // JMP_EQri 991 case Hexagon::JMP_EQriPt_ie_nv_V4: 992 return Hexagon::JMP_EQriPt_nv_V4; 993 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 994 return Hexagon::JMP_EQriNotPt_nv_V4; 995 case Hexagon::JMP_EQriPnt_ie_nv_V4: 996 return Hexagon::JMP_EQriPnt_nv_V4; 997 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 998 return Hexagon::JMP_EQriNotPnt_nv_V4; 999 1000 // JMP_EQri -- with -1 1001 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 1002 return Hexagon::JMP_EQriPtneg_nv_V4; 1003 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 1004 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1005 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 1006 return Hexagon::JMP_EQriPntneg_nv_V4; 1007 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 1008 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1009 1010 // JMP_EQrr 1011 case Hexagon::JMP_EQrrPt_ie_nv_V4: 1012 return Hexagon::JMP_EQrrPt_nv_V4; 1013 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 1014 return Hexagon::JMP_EQrrNotPt_nv_V4; 1015 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 1016 return Hexagon::JMP_EQrrPnt_nv_V4; 1017 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 1018 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1019 1020 // JMP_GTri 1021 case Hexagon::JMP_GTriPt_ie_nv_V4: 1022 return Hexagon::JMP_GTriPt_nv_V4; 1023 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 1024 return Hexagon::JMP_GTriNotPt_nv_V4; 1025 case Hexagon::JMP_GTriPnt_ie_nv_V4: 1026 return Hexagon::JMP_GTriPnt_nv_V4; 1027 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 1028 return Hexagon::JMP_GTriNotPnt_nv_V4; 1029 1030 // JMP_GTri -- with -1 1031 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 1032 return Hexagon::JMP_GTriPtneg_nv_V4; 1033 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 1034 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1035 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 1036 return Hexagon::JMP_GTriPntneg_nv_V4; 1037 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 1038 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1039 1040 // JMP_GTrr 1041 case Hexagon::JMP_GTrrPt_ie_nv_V4: 1042 return Hexagon::JMP_GTrrPt_nv_V4; 1043 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 1044 return Hexagon::JMP_GTrrNotPt_nv_V4; 1045 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 1046 return Hexagon::JMP_GTrrPnt_nv_V4; 1047 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 1048 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1049 1050 // JMP_GTrrdn 1051 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 1052 return Hexagon::JMP_GTrrdnPt_nv_V4; 1053 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 1054 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1055 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 1056 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1057 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 1058 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1059 1060 // JMP_GTUri 1061 case Hexagon::JMP_GTUriPt_ie_nv_V4: 1062 return Hexagon::JMP_GTUriPt_nv_V4; 1063 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 1064 return Hexagon::JMP_GTUriNotPt_nv_V4; 1065 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 1066 return Hexagon::JMP_GTUriPnt_nv_V4; 1067 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 1068 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1069 1070 // JMP_GTUrr 1071 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 1072 return Hexagon::JMP_GTUrrPt_nv_V4; 1073 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 1074 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1075 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 1076 return Hexagon::JMP_GTUrrPnt_nv_V4; 1077 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 1078 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1079 1080 // JMP_GTUrrdn 1081 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 1082 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1083 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 1084 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1085 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 1086 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1087 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 1088 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1089 } 1090} 1091 1092 1093bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { 1094 switch (MI->getOpcode()) { 1095 default: return false; 1096 // Store Byte 1097 case Hexagon::STrib_nv_V4: 1098 case Hexagon::STrib_indexed_nv_V4: 1099 case Hexagon::STrib_indexed_shl_nv_V4: 1100 case Hexagon::STrib_shl_nv_V4: 1101 case Hexagon::STrib_GP_nv_V4: 1102 case Hexagon::STb_GP_nv_V4: 1103 case Hexagon::POST_STbri_nv_V4: 1104 case Hexagon::STrib_cPt_nv_V4: 1105 case Hexagon::STrib_cdnPt_nv_V4: 1106 case Hexagon::STrib_cNotPt_nv_V4: 1107 case Hexagon::STrib_cdnNotPt_nv_V4: 1108 case Hexagon::STrib_indexed_cPt_nv_V4: 1109 case Hexagon::STrib_indexed_cdnPt_nv_V4: 1110 case Hexagon::STrib_indexed_cNotPt_nv_V4: 1111 case Hexagon::STrib_indexed_cdnNotPt_nv_V4: 1112 case Hexagon::STrib_indexed_shl_cPt_nv_V4: 1113 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: 1114 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: 1115 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: 1116 case Hexagon::POST_STbri_cPt_nv_V4: 1117 case Hexagon::POST_STbri_cdnPt_nv_V4: 1118 case Hexagon::POST_STbri_cNotPt_nv_V4: 1119 case Hexagon::POST_STbri_cdnNotPt_nv_V4: 1120 case Hexagon::STb_GP_cPt_nv_V4: 1121 case Hexagon::STb_GP_cNotPt_nv_V4: 1122 case Hexagon::STb_GP_cdnPt_nv_V4: 1123 case Hexagon::STb_GP_cdnNotPt_nv_V4: 1124 case Hexagon::STrib_GP_cPt_nv_V4: 1125 case Hexagon::STrib_GP_cNotPt_nv_V4: 1126 case Hexagon::STrib_GP_cdnPt_nv_V4: 1127 case Hexagon::STrib_GP_cdnNotPt_nv_V4: 1128 case Hexagon::STrib_abs_nv_V4: 1129 case Hexagon::STrib_abs_cPt_nv_V4: 1130 case Hexagon::STrib_abs_cdnPt_nv_V4: 1131 case Hexagon::STrib_abs_cNotPt_nv_V4: 1132 case Hexagon::STrib_abs_cdnNotPt_nv_V4: 1133 case Hexagon::STrib_imm_abs_nv_V4: 1134 case Hexagon::STrib_imm_abs_cPt_nv_V4: 1135 case Hexagon::STrib_imm_abs_cdnPt_nv_V4: 1136 case Hexagon::STrib_imm_abs_cNotPt_nv_V4: 1137 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: 1138 1139 // Store Halfword 1140 case Hexagon::STrih_nv_V4: 1141 case Hexagon::STrih_indexed_nv_V4: 1142 case Hexagon::STrih_indexed_shl_nv_V4: 1143 case Hexagon::STrih_shl_nv_V4: 1144 case Hexagon::STrih_GP_nv_V4: 1145 case Hexagon::STh_GP_nv_V4: 1146 case Hexagon::POST_SThri_nv_V4: 1147 case Hexagon::STrih_cPt_nv_V4: 1148 case Hexagon::STrih_cdnPt_nv_V4: 1149 case Hexagon::STrih_cNotPt_nv_V4: 1150 case Hexagon::STrih_cdnNotPt_nv_V4: 1151 case Hexagon::STrih_indexed_cPt_nv_V4: 1152 case Hexagon::STrih_indexed_cdnPt_nv_V4: 1153 case Hexagon::STrih_indexed_cNotPt_nv_V4: 1154 case Hexagon::STrih_indexed_cdnNotPt_nv_V4: 1155 case Hexagon::STrih_indexed_shl_cPt_nv_V4: 1156 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: 1157 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: 1158 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: 1159 case Hexagon::POST_SThri_cPt_nv_V4: 1160 case Hexagon::POST_SThri_cdnPt_nv_V4: 1161 case Hexagon::POST_SThri_cNotPt_nv_V4: 1162 case Hexagon::POST_SThri_cdnNotPt_nv_V4: 1163 case Hexagon::STh_GP_cPt_nv_V4: 1164 case Hexagon::STh_GP_cNotPt_nv_V4: 1165 case Hexagon::STh_GP_cdnPt_nv_V4: 1166 case Hexagon::STh_GP_cdnNotPt_nv_V4: 1167 case Hexagon::STrih_GP_cPt_nv_V4: 1168 case Hexagon::STrih_GP_cNotPt_nv_V4: 1169 case Hexagon::STrih_GP_cdnPt_nv_V4: 1170 case Hexagon::STrih_GP_cdnNotPt_nv_V4: 1171 case Hexagon::STrih_abs_nv_V4: 1172 case Hexagon::STrih_abs_cPt_nv_V4: 1173 case Hexagon::STrih_abs_cdnPt_nv_V4: 1174 case Hexagon::STrih_abs_cNotPt_nv_V4: 1175 case Hexagon::STrih_abs_cdnNotPt_nv_V4: 1176 case Hexagon::STrih_imm_abs_nv_V4: 1177 case Hexagon::STrih_imm_abs_cPt_nv_V4: 1178 case Hexagon::STrih_imm_abs_cdnPt_nv_V4: 1179 case Hexagon::STrih_imm_abs_cNotPt_nv_V4: 1180 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: 1181 1182 // Store Word 1183 case Hexagon::STriw_nv_V4: 1184 case Hexagon::STriw_indexed_nv_V4: 1185 case Hexagon::STriw_indexed_shl_nv_V4: 1186 case Hexagon::STriw_shl_nv_V4: 1187 case Hexagon::STriw_GP_nv_V4: 1188 case Hexagon::STw_GP_nv_V4: 1189 case Hexagon::POST_STwri_nv_V4: 1190 case Hexagon::STriw_cPt_nv_V4: 1191 case Hexagon::STriw_cdnPt_nv_V4: 1192 case Hexagon::STriw_cNotPt_nv_V4: 1193 case Hexagon::STriw_cdnNotPt_nv_V4: 1194 case Hexagon::STriw_indexed_cPt_nv_V4: 1195 case Hexagon::STriw_indexed_cdnPt_nv_V4: 1196 case Hexagon::STriw_indexed_cNotPt_nv_V4: 1197 case Hexagon::STriw_indexed_cdnNotPt_nv_V4: 1198 case Hexagon::STriw_indexed_shl_cPt_nv_V4: 1199 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: 1200 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: 1201 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: 1202 case Hexagon::POST_STwri_cPt_nv_V4: 1203 case Hexagon::POST_STwri_cdnPt_nv_V4: 1204 case Hexagon::POST_STwri_cNotPt_nv_V4: 1205 case Hexagon::POST_STwri_cdnNotPt_nv_V4: 1206 case Hexagon::STw_GP_cPt_nv_V4: 1207 case Hexagon::STw_GP_cNotPt_nv_V4: 1208 case Hexagon::STw_GP_cdnPt_nv_V4: 1209 case Hexagon::STw_GP_cdnNotPt_nv_V4: 1210 case Hexagon::STriw_GP_cPt_nv_V4: 1211 case Hexagon::STriw_GP_cNotPt_nv_V4: 1212 case Hexagon::STriw_GP_cdnPt_nv_V4: 1213 case Hexagon::STriw_GP_cdnNotPt_nv_V4: 1214 case Hexagon::STriw_abs_nv_V4: 1215 case Hexagon::STriw_abs_cPt_nv_V4: 1216 case Hexagon::STriw_abs_cdnPt_nv_V4: 1217 case Hexagon::STriw_abs_cNotPt_nv_V4: 1218 case Hexagon::STriw_abs_cdnNotPt_nv_V4: 1219 case Hexagon::STriw_imm_abs_nv_V4: 1220 case Hexagon::STriw_imm_abs_cPt_nv_V4: 1221 case Hexagon::STriw_imm_abs_cdnPt_nv_V4: 1222 case Hexagon::STriw_imm_abs_cNotPt_nv_V4: 1223 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: 1224 return true; 1225 } 1226} 1227 1228bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { 1229 switch (MI->getOpcode()) 1230 { 1231 default: return false; 1232 // Load Byte 1233 case Hexagon::POST_LDrib: 1234 case Hexagon::POST_LDrib_cPt: 1235 case Hexagon::POST_LDrib_cNotPt: 1236 case Hexagon::POST_LDrib_cdnPt_V4: 1237 case Hexagon::POST_LDrib_cdnNotPt_V4: 1238 1239 // Load unsigned byte 1240 case Hexagon::POST_LDriub: 1241 case Hexagon::POST_LDriub_cPt: 1242 case Hexagon::POST_LDriub_cNotPt: 1243 case Hexagon::POST_LDriub_cdnPt_V4: 1244 case Hexagon::POST_LDriub_cdnNotPt_V4: 1245 1246 // Load halfword 1247 case Hexagon::POST_LDrih: 1248 case Hexagon::POST_LDrih_cPt: 1249 case Hexagon::POST_LDrih_cNotPt: 1250 case Hexagon::POST_LDrih_cdnPt_V4: 1251 case Hexagon::POST_LDrih_cdnNotPt_V4: 1252 1253 // Load unsigned halfword 1254 case Hexagon::POST_LDriuh: 1255 case Hexagon::POST_LDriuh_cPt: 1256 case Hexagon::POST_LDriuh_cNotPt: 1257 case Hexagon::POST_LDriuh_cdnPt_V4: 1258 case Hexagon::POST_LDriuh_cdnNotPt_V4: 1259 1260 // Load word 1261 case Hexagon::POST_LDriw: 1262 case Hexagon::POST_LDriw_cPt: 1263 case Hexagon::POST_LDriw_cNotPt: 1264 case Hexagon::POST_LDriw_cdnPt_V4: 1265 case Hexagon::POST_LDriw_cdnNotPt_V4: 1266 1267 // Load double word 1268 case Hexagon::POST_LDrid: 1269 case Hexagon::POST_LDrid_cPt: 1270 case Hexagon::POST_LDrid_cNotPt: 1271 case Hexagon::POST_LDrid_cdnPt_V4: 1272 case Hexagon::POST_LDrid_cdnNotPt_V4: 1273 1274 // Store byte 1275 case Hexagon::POST_STbri: 1276 case Hexagon::POST_STbri_cPt: 1277 case Hexagon::POST_STbri_cNotPt: 1278 case Hexagon::POST_STbri_cdnPt_V4: 1279 case Hexagon::POST_STbri_cdnNotPt_V4: 1280 1281 // Store halfword 1282 case Hexagon::POST_SThri: 1283 case Hexagon::POST_SThri_cPt: 1284 case Hexagon::POST_SThri_cNotPt: 1285 case Hexagon::POST_SThri_cdnPt_V4: 1286 case Hexagon::POST_SThri_cdnNotPt_V4: 1287 1288 // Store word 1289 case Hexagon::POST_STwri: 1290 case Hexagon::POST_STwri_cPt: 1291 case Hexagon::POST_STwri_cNotPt: 1292 case Hexagon::POST_STwri_cdnPt_V4: 1293 case Hexagon::POST_STwri_cdnNotPt_V4: 1294 1295 // Store double word 1296 case Hexagon::POST_STdri: 1297 case Hexagon::POST_STdri_cPt: 1298 case Hexagon::POST_STdri_cNotPt: 1299 case Hexagon::POST_STdri_cdnPt_V4: 1300 case Hexagon::POST_STdri_cdnNotPt_V4: 1301 return true; 1302 } 1303} 1304 1305bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { 1306 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; 1307} 1308 1309bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { 1310 bool isPred = MI->getDesc().isPredicable(); 1311 1312 if (!isPred) 1313 return false; 1314 1315 const int Opc = MI->getOpcode(); 1316 1317 switch(Opc) { 1318 case Hexagon::TFRI: 1319 return isInt<12>(MI->getOperand(1).getImm()); 1320 1321 case Hexagon::STrid: 1322 case Hexagon::STrid_indexed: 1323 return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); 1324 1325 case Hexagon::STriw: 1326 case Hexagon::STriw_indexed: 1327 case Hexagon::STriw_nv_V4: 1328 return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); 1329 1330 case Hexagon::STrih: 1331 case Hexagon::STrih_indexed: 1332 case Hexagon::STrih_nv_V4: 1333 return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); 1334 1335 case Hexagon::STrib: 1336 case Hexagon::STrib_indexed: 1337 case Hexagon::STrib_nv_V4: 1338 return isUInt<6>(MI->getOperand(1).getImm()); 1339 1340 case Hexagon::LDrid: 1341 case Hexagon::LDrid_indexed: 1342 return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); 1343 1344 case Hexagon::LDriw: 1345 case Hexagon::LDriw_indexed: 1346 return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); 1347 1348 case Hexagon::LDrih: 1349 case Hexagon::LDriuh: 1350 case Hexagon::LDrih_indexed: 1351 case Hexagon::LDriuh_indexed: 1352 return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); 1353 1354 case Hexagon::LDrib: 1355 case Hexagon::LDriub: 1356 case Hexagon::LDrib_indexed: 1357 case Hexagon::LDriub_indexed: 1358 return isUInt<6>(MI->getOperand(2).getImm()); 1359 1360 case Hexagon::POST_LDrid: 1361 return isShiftedInt<4,3>(MI->getOperand(3).getImm()); 1362 1363 case Hexagon::POST_LDriw: 1364 return isShiftedInt<4,2>(MI->getOperand(3).getImm()); 1365 1366 case Hexagon::POST_LDrih: 1367 case Hexagon::POST_LDriuh: 1368 return isShiftedInt<4,1>(MI->getOperand(3).getImm()); 1369 1370 case Hexagon::POST_LDrib: 1371 case Hexagon::POST_LDriub: 1372 return isInt<4>(MI->getOperand(3).getImm()); 1373 1374 case Hexagon::STrib_imm_V4: 1375 case Hexagon::STrih_imm_V4: 1376 case Hexagon::STriw_imm_V4: 1377 return (isUInt<6>(MI->getOperand(1).getImm()) && 1378 isInt<6>(MI->getOperand(2).getImm())); 1379 1380 case Hexagon::ADD_ri: 1381 return isInt<8>(MI->getOperand(2).getImm()); 1382 1383 case Hexagon::ASLH: 1384 case Hexagon::ASRH: 1385 case Hexagon::SXTB: 1386 case Hexagon::SXTH: 1387 case Hexagon::ZXTB: 1388 case Hexagon::ZXTH: 1389 return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4; 1390 1391 case Hexagon::JMPR: 1392 return false; 1393 } 1394 1395 return true; 1396} 1397 1398unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { 1399 switch(Opc) { 1400 default: llvm_unreachable("Unexpected predicated instruction"); 1401 case Hexagon::TFR_cPt: 1402 return Hexagon::TFR_cNotPt; 1403 case Hexagon::TFR_cNotPt: 1404 return Hexagon::TFR_cPt; 1405 1406 case Hexagon::TFRI_cPt: 1407 return Hexagon::TFRI_cNotPt; 1408 case Hexagon::TFRI_cNotPt: 1409 return Hexagon::TFRI_cPt; 1410 1411 case Hexagon::JMP_c: 1412 return Hexagon::JMP_cNot; 1413 case Hexagon::JMP_cNot: 1414 return Hexagon::JMP_c; 1415 1416 case Hexagon::ADD_ri_cPt: 1417 return Hexagon::ADD_ri_cNotPt; 1418 case Hexagon::ADD_ri_cNotPt: 1419 return Hexagon::ADD_ri_cPt; 1420 1421 case Hexagon::ADD_rr_cPt: 1422 return Hexagon::ADD_rr_cNotPt; 1423 case Hexagon::ADD_rr_cNotPt: 1424 return Hexagon::ADD_rr_cPt; 1425 1426 case Hexagon::XOR_rr_cPt: 1427 return Hexagon::XOR_rr_cNotPt; 1428 case Hexagon::XOR_rr_cNotPt: 1429 return Hexagon::XOR_rr_cPt; 1430 1431 case Hexagon::AND_rr_cPt: 1432 return Hexagon::AND_rr_cNotPt; 1433 case Hexagon::AND_rr_cNotPt: 1434 return Hexagon::AND_rr_cPt; 1435 1436 case Hexagon::OR_rr_cPt: 1437 return Hexagon::OR_rr_cNotPt; 1438 case Hexagon::OR_rr_cNotPt: 1439 return Hexagon::OR_rr_cPt; 1440 1441 case Hexagon::SUB_rr_cPt: 1442 return Hexagon::SUB_rr_cNotPt; 1443 case Hexagon::SUB_rr_cNotPt: 1444 return Hexagon::SUB_rr_cPt; 1445 1446 case Hexagon::COMBINE_rr_cPt: 1447 return Hexagon::COMBINE_rr_cNotPt; 1448 case Hexagon::COMBINE_rr_cNotPt: 1449 return Hexagon::COMBINE_rr_cPt; 1450 1451 case Hexagon::ASLH_cPt_V4: 1452 return Hexagon::ASLH_cNotPt_V4; 1453 case Hexagon::ASLH_cNotPt_V4: 1454 return Hexagon::ASLH_cPt_V4; 1455 1456 case Hexagon::ASRH_cPt_V4: 1457 return Hexagon::ASRH_cNotPt_V4; 1458 case Hexagon::ASRH_cNotPt_V4: 1459 return Hexagon::ASRH_cPt_V4; 1460 1461 case Hexagon::SXTB_cPt_V4: 1462 return Hexagon::SXTB_cNotPt_V4; 1463 case Hexagon::SXTB_cNotPt_V4: 1464 return Hexagon::SXTB_cPt_V4; 1465 1466 case Hexagon::SXTH_cPt_V4: 1467 return Hexagon::SXTH_cNotPt_V4; 1468 case Hexagon::SXTH_cNotPt_V4: 1469 return Hexagon::SXTH_cPt_V4; 1470 1471 case Hexagon::ZXTB_cPt_V4: 1472 return Hexagon::ZXTB_cNotPt_V4; 1473 case Hexagon::ZXTB_cNotPt_V4: 1474 return Hexagon::ZXTB_cPt_V4; 1475 1476 case Hexagon::ZXTH_cPt_V4: 1477 return Hexagon::ZXTH_cNotPt_V4; 1478 case Hexagon::ZXTH_cNotPt_V4: 1479 return Hexagon::ZXTH_cPt_V4; 1480 1481 1482 case Hexagon::JMPR_cPt: 1483 return Hexagon::JMPR_cNotPt; 1484 case Hexagon::JMPR_cNotPt: 1485 return Hexagon::JMPR_cPt; 1486 1487 // V4 indexed+scaled load. 1488 case Hexagon::LDrid_indexed_cPt_V4: 1489 return Hexagon::LDrid_indexed_cNotPt_V4; 1490 case Hexagon::LDrid_indexed_cNotPt_V4: 1491 return Hexagon::LDrid_indexed_cPt_V4; 1492 1493 case Hexagon::LDrid_indexed_shl_cPt_V4: 1494 return Hexagon::LDrid_indexed_shl_cNotPt_V4; 1495 case Hexagon::LDrid_indexed_shl_cNotPt_V4: 1496 return Hexagon::LDrid_indexed_shl_cPt_V4; 1497 1498 case Hexagon::LDrib_indexed_cPt_V4: 1499 return Hexagon::LDrib_indexed_cNotPt_V4; 1500 case Hexagon::LDrib_indexed_cNotPt_V4: 1501 return Hexagon::LDrib_indexed_cPt_V4; 1502 1503 case Hexagon::LDriub_indexed_cPt_V4: 1504 return Hexagon::LDriub_indexed_cNotPt_V4; 1505 case Hexagon::LDriub_indexed_cNotPt_V4: 1506 return Hexagon::LDriub_indexed_cPt_V4; 1507 1508 case Hexagon::LDrib_indexed_shl_cPt_V4: 1509 return Hexagon::LDrib_indexed_shl_cNotPt_V4; 1510 case Hexagon::LDrib_indexed_shl_cNotPt_V4: 1511 return Hexagon::LDrib_indexed_shl_cPt_V4; 1512 1513 case Hexagon::LDriub_indexed_shl_cPt_V4: 1514 return Hexagon::LDriub_indexed_shl_cNotPt_V4; 1515 case Hexagon::LDriub_indexed_shl_cNotPt_V4: 1516 return Hexagon::LDriub_indexed_shl_cPt_V4; 1517 1518 case Hexagon::LDrih_indexed_cPt_V4: 1519 return Hexagon::LDrih_indexed_cNotPt_V4; 1520 case Hexagon::LDrih_indexed_cNotPt_V4: 1521 return Hexagon::LDrih_indexed_cPt_V4; 1522 1523 case Hexagon::LDriuh_indexed_cPt_V4: 1524 return Hexagon::LDriuh_indexed_cNotPt_V4; 1525 case Hexagon::LDriuh_indexed_cNotPt_V4: 1526 return Hexagon::LDriuh_indexed_cPt_V4; 1527 1528 case Hexagon::LDrih_indexed_shl_cPt_V4: 1529 return Hexagon::LDrih_indexed_shl_cNotPt_V4; 1530 case Hexagon::LDrih_indexed_shl_cNotPt_V4: 1531 return Hexagon::LDrih_indexed_shl_cPt_V4; 1532 1533 case Hexagon::LDriuh_indexed_shl_cPt_V4: 1534 return Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1535 case Hexagon::LDriuh_indexed_shl_cNotPt_V4: 1536 return Hexagon::LDriuh_indexed_shl_cPt_V4; 1537 1538 case Hexagon::LDriw_indexed_cPt_V4: 1539 return Hexagon::LDriw_indexed_cNotPt_V4; 1540 case Hexagon::LDriw_indexed_cNotPt_V4: 1541 return Hexagon::LDriw_indexed_cPt_V4; 1542 1543 case Hexagon::LDriw_indexed_shl_cPt_V4: 1544 return Hexagon::LDriw_indexed_shl_cNotPt_V4; 1545 case Hexagon::LDriw_indexed_shl_cNotPt_V4: 1546 return Hexagon::LDriw_indexed_shl_cPt_V4; 1547 1548 // Byte. 1549 case Hexagon::POST_STbri_cPt: 1550 return Hexagon::POST_STbri_cNotPt; 1551 case Hexagon::POST_STbri_cNotPt: 1552 return Hexagon::POST_STbri_cPt; 1553 1554 case Hexagon::STrib_cPt: 1555 return Hexagon::STrib_cNotPt; 1556 case Hexagon::STrib_cNotPt: 1557 return Hexagon::STrib_cPt; 1558 1559 case Hexagon::STrib_indexed_cPt: 1560 return Hexagon::STrib_indexed_cNotPt; 1561 case Hexagon::STrib_indexed_cNotPt: 1562 return Hexagon::STrib_indexed_cPt; 1563 1564 case Hexagon::STrib_imm_cPt_V4: 1565 return Hexagon::STrib_imm_cNotPt_V4; 1566 case Hexagon::STrib_imm_cNotPt_V4: 1567 return Hexagon::STrib_imm_cPt_V4; 1568 1569 case Hexagon::STrib_indexed_shl_cPt_V4: 1570 return Hexagon::STrib_indexed_shl_cNotPt_V4; 1571 case Hexagon::STrib_indexed_shl_cNotPt_V4: 1572 return Hexagon::STrib_indexed_shl_cPt_V4; 1573 1574 // Halfword. 1575 case Hexagon::POST_SThri_cPt: 1576 return Hexagon::POST_SThri_cNotPt; 1577 case Hexagon::POST_SThri_cNotPt: 1578 return Hexagon::POST_SThri_cPt; 1579 1580 case Hexagon::STrih_cPt: 1581 return Hexagon::STrih_cNotPt; 1582 case Hexagon::STrih_cNotPt: 1583 return Hexagon::STrih_cPt; 1584 1585 case Hexagon::STrih_indexed_cPt: 1586 return Hexagon::STrih_indexed_cNotPt; 1587 case Hexagon::STrih_indexed_cNotPt: 1588 return Hexagon::STrih_indexed_cPt; 1589 1590 case Hexagon::STrih_imm_cPt_V4: 1591 return Hexagon::STrih_imm_cNotPt_V4; 1592 case Hexagon::STrih_imm_cNotPt_V4: 1593 return Hexagon::STrih_imm_cPt_V4; 1594 1595 case Hexagon::STrih_indexed_shl_cPt_V4: 1596 return Hexagon::STrih_indexed_shl_cNotPt_V4; 1597 case Hexagon::STrih_indexed_shl_cNotPt_V4: 1598 return Hexagon::STrih_indexed_shl_cPt_V4; 1599 1600 // Word. 1601 case Hexagon::POST_STwri_cPt: 1602 return Hexagon::POST_STwri_cNotPt; 1603 case Hexagon::POST_STwri_cNotPt: 1604 return Hexagon::POST_STwri_cPt; 1605 1606 case Hexagon::STriw_cPt: 1607 return Hexagon::STriw_cNotPt; 1608 case Hexagon::STriw_cNotPt: 1609 return Hexagon::STriw_cPt; 1610 1611 case Hexagon::STriw_indexed_cPt: 1612 return Hexagon::STriw_indexed_cNotPt; 1613 case Hexagon::STriw_indexed_cNotPt: 1614 return Hexagon::STriw_indexed_cPt; 1615 1616 case Hexagon::STriw_indexed_shl_cPt_V4: 1617 return Hexagon::STriw_indexed_shl_cNotPt_V4; 1618 case Hexagon::STriw_indexed_shl_cNotPt_V4: 1619 return Hexagon::STriw_indexed_shl_cPt_V4; 1620 1621 case Hexagon::STriw_imm_cPt_V4: 1622 return Hexagon::STriw_imm_cNotPt_V4; 1623 case Hexagon::STriw_imm_cNotPt_V4: 1624 return Hexagon::STriw_imm_cPt_V4; 1625 1626 // Double word. 1627 case Hexagon::POST_STdri_cPt: 1628 return Hexagon::POST_STdri_cNotPt; 1629 case Hexagon::POST_STdri_cNotPt: 1630 return Hexagon::POST_STdri_cPt; 1631 1632 case Hexagon::STrid_cPt: 1633 return Hexagon::STrid_cNotPt; 1634 case Hexagon::STrid_cNotPt: 1635 return Hexagon::STrid_cPt; 1636 1637 case Hexagon::STrid_indexed_cPt: 1638 return Hexagon::STrid_indexed_cNotPt; 1639 case Hexagon::STrid_indexed_cNotPt: 1640 return Hexagon::STrid_indexed_cPt; 1641 1642 case Hexagon::STrid_indexed_shl_cPt_V4: 1643 return Hexagon::STrid_indexed_shl_cNotPt_V4; 1644 case Hexagon::STrid_indexed_shl_cNotPt_V4: 1645 return Hexagon::STrid_indexed_shl_cPt_V4; 1646 1647 // V4 Store to global address. 1648 case Hexagon::STd_GP_cPt_V4: 1649 return Hexagon::STd_GP_cNotPt_V4; 1650 case Hexagon::STd_GP_cNotPt_V4: 1651 return Hexagon::STd_GP_cPt_V4; 1652 1653 case Hexagon::STb_GP_cPt_V4: 1654 return Hexagon::STb_GP_cNotPt_V4; 1655 case Hexagon::STb_GP_cNotPt_V4: 1656 return Hexagon::STb_GP_cPt_V4; 1657 1658 case Hexagon::STh_GP_cPt_V4: 1659 return Hexagon::STh_GP_cNotPt_V4; 1660 case Hexagon::STh_GP_cNotPt_V4: 1661 return Hexagon::STh_GP_cPt_V4; 1662 1663 case Hexagon::STw_GP_cPt_V4: 1664 return Hexagon::STw_GP_cNotPt_V4; 1665 case Hexagon::STw_GP_cNotPt_V4: 1666 return Hexagon::STw_GP_cPt_V4; 1667 1668 case Hexagon::STrid_GP_cPt_V4: 1669 return Hexagon::STrid_GP_cNotPt_V4; 1670 case Hexagon::STrid_GP_cNotPt_V4: 1671 return Hexagon::STrid_GP_cPt_V4; 1672 1673 case Hexagon::STrib_GP_cPt_V4: 1674 return Hexagon::STrib_GP_cNotPt_V4; 1675 case Hexagon::STrib_GP_cNotPt_V4: 1676 return Hexagon::STrib_GP_cPt_V4; 1677 1678 case Hexagon::STrih_GP_cPt_V4: 1679 return Hexagon::STrih_GP_cNotPt_V4; 1680 case Hexagon::STrih_GP_cNotPt_V4: 1681 return Hexagon::STrih_GP_cPt_V4; 1682 1683 case Hexagon::STriw_GP_cPt_V4: 1684 return Hexagon::STriw_GP_cNotPt_V4; 1685 case Hexagon::STriw_GP_cNotPt_V4: 1686 return Hexagon::STriw_GP_cPt_V4; 1687 1688 // Load. 1689 case Hexagon::LDrid_cPt: 1690 return Hexagon::LDrid_cNotPt; 1691 case Hexagon::LDrid_cNotPt: 1692 return Hexagon::LDrid_cPt; 1693 1694 case Hexagon::LDriw_cPt: 1695 return Hexagon::LDriw_cNotPt; 1696 case Hexagon::LDriw_cNotPt: 1697 return Hexagon::LDriw_cPt; 1698 1699 case Hexagon::LDrih_cPt: 1700 return Hexagon::LDrih_cNotPt; 1701 case Hexagon::LDrih_cNotPt: 1702 return Hexagon::LDrih_cPt; 1703 1704 case Hexagon::LDriuh_cPt: 1705 return Hexagon::LDriuh_cNotPt; 1706 case Hexagon::LDriuh_cNotPt: 1707 return Hexagon::LDriuh_cPt; 1708 1709 case Hexagon::LDrib_cPt: 1710 return Hexagon::LDrib_cNotPt; 1711 case Hexagon::LDrib_cNotPt: 1712 return Hexagon::LDrib_cPt; 1713 1714 case Hexagon::LDriub_cPt: 1715 return Hexagon::LDriub_cNotPt; 1716 case Hexagon::LDriub_cNotPt: 1717 return Hexagon::LDriub_cPt; 1718 1719 // Load Indexed. 1720 case Hexagon::LDrid_indexed_cPt: 1721 return Hexagon::LDrid_indexed_cNotPt; 1722 case Hexagon::LDrid_indexed_cNotPt: 1723 return Hexagon::LDrid_indexed_cPt; 1724 1725 case Hexagon::LDriw_indexed_cPt: 1726 return Hexagon::LDriw_indexed_cNotPt; 1727 case Hexagon::LDriw_indexed_cNotPt: 1728 return Hexagon::LDriw_indexed_cPt; 1729 1730 case Hexagon::LDrih_indexed_cPt: 1731 return Hexagon::LDrih_indexed_cNotPt; 1732 case Hexagon::LDrih_indexed_cNotPt: 1733 return Hexagon::LDrih_indexed_cPt; 1734 1735 case Hexagon::LDriuh_indexed_cPt: 1736 return Hexagon::LDriuh_indexed_cNotPt; 1737 case Hexagon::LDriuh_indexed_cNotPt: 1738 return Hexagon::LDriuh_indexed_cPt; 1739 1740 case Hexagon::LDrib_indexed_cPt: 1741 return Hexagon::LDrib_indexed_cNotPt; 1742 case Hexagon::LDrib_indexed_cNotPt: 1743 return Hexagon::LDrib_indexed_cPt; 1744 1745 case Hexagon::LDriub_indexed_cPt: 1746 return Hexagon::LDriub_indexed_cNotPt; 1747 case Hexagon::LDriub_indexed_cNotPt: 1748 return Hexagon::LDriub_indexed_cPt; 1749 1750 // Post Inc Load. 1751 case Hexagon::POST_LDrid_cPt: 1752 return Hexagon::POST_LDrid_cNotPt; 1753 case Hexagon::POST_LDriw_cNotPt: 1754 return Hexagon::POST_LDriw_cPt; 1755 1756 case Hexagon::POST_LDrih_cPt: 1757 return Hexagon::POST_LDrih_cNotPt; 1758 case Hexagon::POST_LDrih_cNotPt: 1759 return Hexagon::POST_LDrih_cPt; 1760 1761 case Hexagon::POST_LDriuh_cPt: 1762 return Hexagon::POST_LDriuh_cNotPt; 1763 case Hexagon::POST_LDriuh_cNotPt: 1764 return Hexagon::POST_LDriuh_cPt; 1765 1766 case Hexagon::POST_LDrib_cPt: 1767 return Hexagon::POST_LDrib_cNotPt; 1768 case Hexagon::POST_LDrib_cNotPt: 1769 return Hexagon::POST_LDrib_cPt; 1770 1771 case Hexagon::POST_LDriub_cPt: 1772 return Hexagon::POST_LDriub_cNotPt; 1773 case Hexagon::POST_LDriub_cNotPt: 1774 return Hexagon::POST_LDriub_cPt; 1775 1776 // Dealloc_return. 1777 case Hexagon::DEALLOC_RET_cPt_V4: 1778 return Hexagon::DEALLOC_RET_cNotPt_V4; 1779 case Hexagon::DEALLOC_RET_cNotPt_V4: 1780 return Hexagon::DEALLOC_RET_cPt_V4; 1781 1782 // New Value Jump. 1783 // JMPEQ_ri - with -1. 1784 case Hexagon::JMP_EQriPtneg_nv_V4: 1785 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1786 case Hexagon::JMP_EQriNotPtneg_nv_V4: 1787 return Hexagon::JMP_EQriPtneg_nv_V4; 1788 1789 case Hexagon::JMP_EQriPntneg_nv_V4: 1790 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1791 case Hexagon::JMP_EQriNotPntneg_nv_V4: 1792 return Hexagon::JMP_EQriPntneg_nv_V4; 1793 1794 // JMPEQ_ri. 1795 case Hexagon::JMP_EQriPt_nv_V4: 1796 return Hexagon::JMP_EQriNotPt_nv_V4; 1797 case Hexagon::JMP_EQriNotPt_nv_V4: 1798 return Hexagon::JMP_EQriPt_nv_V4; 1799 1800 case Hexagon::JMP_EQriPnt_nv_V4: 1801 return Hexagon::JMP_EQriNotPnt_nv_V4; 1802 case Hexagon::JMP_EQriNotPnt_nv_V4: 1803 return Hexagon::JMP_EQriPnt_nv_V4; 1804 1805 // JMPEQ_rr. 1806 case Hexagon::JMP_EQrrPt_nv_V4: 1807 return Hexagon::JMP_EQrrNotPt_nv_V4; 1808 case Hexagon::JMP_EQrrNotPt_nv_V4: 1809 return Hexagon::JMP_EQrrPt_nv_V4; 1810 1811 case Hexagon::JMP_EQrrPnt_nv_V4: 1812 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1813 case Hexagon::JMP_EQrrNotPnt_nv_V4: 1814 return Hexagon::JMP_EQrrPnt_nv_V4; 1815 1816 // JMPGT_ri - with -1. 1817 case Hexagon::JMP_GTriPtneg_nv_V4: 1818 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1819 case Hexagon::JMP_GTriNotPtneg_nv_V4: 1820 return Hexagon::JMP_GTriPtneg_nv_V4; 1821 1822 case Hexagon::JMP_GTriPntneg_nv_V4: 1823 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1824 case Hexagon::JMP_GTriNotPntneg_nv_V4: 1825 return Hexagon::JMP_GTriPntneg_nv_V4; 1826 1827 // JMPGT_ri. 1828 case Hexagon::JMP_GTriPt_nv_V4: 1829 return Hexagon::JMP_GTriNotPt_nv_V4; 1830 case Hexagon::JMP_GTriNotPt_nv_V4: 1831 return Hexagon::JMP_GTriPt_nv_V4; 1832 1833 case Hexagon::JMP_GTriPnt_nv_V4: 1834 return Hexagon::JMP_GTriNotPnt_nv_V4; 1835 case Hexagon::JMP_GTriNotPnt_nv_V4: 1836 return Hexagon::JMP_GTriPnt_nv_V4; 1837 1838 // JMPGT_rr. 1839 case Hexagon::JMP_GTrrPt_nv_V4: 1840 return Hexagon::JMP_GTrrNotPt_nv_V4; 1841 case Hexagon::JMP_GTrrNotPt_nv_V4: 1842 return Hexagon::JMP_GTrrPt_nv_V4; 1843 1844 case Hexagon::JMP_GTrrPnt_nv_V4: 1845 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1846 case Hexagon::JMP_GTrrNotPnt_nv_V4: 1847 return Hexagon::JMP_GTrrPnt_nv_V4; 1848 1849 // JMPGT_rrdn. 1850 case Hexagon::JMP_GTrrdnPt_nv_V4: 1851 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1852 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 1853 return Hexagon::JMP_GTrrdnPt_nv_V4; 1854 1855 case Hexagon::JMP_GTrrdnPnt_nv_V4: 1856 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1857 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 1858 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1859 1860 // JMPGTU_ri. 1861 case Hexagon::JMP_GTUriPt_nv_V4: 1862 return Hexagon::JMP_GTUriNotPt_nv_V4; 1863 case Hexagon::JMP_GTUriNotPt_nv_V4: 1864 return Hexagon::JMP_GTUriPt_nv_V4; 1865 1866 case Hexagon::JMP_GTUriPnt_nv_V4: 1867 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1868 case Hexagon::JMP_GTUriNotPnt_nv_V4: 1869 return Hexagon::JMP_GTUriPnt_nv_V4; 1870 1871 // JMPGTU_rr. 1872 case Hexagon::JMP_GTUrrPt_nv_V4: 1873 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1874 case Hexagon::JMP_GTUrrNotPt_nv_V4: 1875 return Hexagon::JMP_GTUrrPt_nv_V4; 1876 1877 case Hexagon::JMP_GTUrrPnt_nv_V4: 1878 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1879 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 1880 return Hexagon::JMP_GTUrrPnt_nv_V4; 1881 1882 // JMPGTU_rrdn. 1883 case Hexagon::JMP_GTUrrdnPt_nv_V4: 1884 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1885 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 1886 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1887 1888 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 1889 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1890 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 1891 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1892 } 1893} 1894 1895 1896int HexagonInstrInfo:: 1897getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { 1898 switch(Opc) { 1899 case Hexagon::TFR: 1900 return !invertPredicate ? Hexagon::TFR_cPt : 1901 Hexagon::TFR_cNotPt; 1902 case Hexagon::TFRI_f: 1903 return !invertPredicate ? Hexagon::TFRI_cPt_f : 1904 Hexagon::TFRI_cNotPt_f; 1905 case Hexagon::TFRI: 1906 return !invertPredicate ? Hexagon::TFRI_cPt : 1907 Hexagon::TFRI_cNotPt; 1908 case Hexagon::JMP: 1909 return !invertPredicate ? Hexagon::JMP_c : 1910 Hexagon::JMP_cNot; 1911 case Hexagon::JMP_EQrrPt_nv_V4: 1912 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : 1913 Hexagon::JMP_EQrrNotPt_nv_V4; 1914 case Hexagon::JMP_EQriPt_nv_V4: 1915 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : 1916 Hexagon::JMP_EQriNotPt_nv_V4; 1917 case Hexagon::ADD_ri: 1918 return !invertPredicate ? Hexagon::ADD_ri_cPt : 1919 Hexagon::ADD_ri_cNotPt; 1920 case Hexagon::ADD_rr: 1921 return !invertPredicate ? Hexagon::ADD_rr_cPt : 1922 Hexagon::ADD_rr_cNotPt; 1923 case Hexagon::XOR_rr: 1924 return !invertPredicate ? Hexagon::XOR_rr_cPt : 1925 Hexagon::XOR_rr_cNotPt; 1926 case Hexagon::AND_rr: 1927 return !invertPredicate ? Hexagon::AND_rr_cPt : 1928 Hexagon::AND_rr_cNotPt; 1929 case Hexagon::OR_rr: 1930 return !invertPredicate ? Hexagon::OR_rr_cPt : 1931 Hexagon::OR_rr_cNotPt; 1932 case Hexagon::SUB_rr: 1933 return !invertPredicate ? Hexagon::SUB_rr_cPt : 1934 Hexagon::SUB_rr_cNotPt; 1935 case Hexagon::COMBINE_rr: 1936 return !invertPredicate ? Hexagon::COMBINE_rr_cPt : 1937 Hexagon::COMBINE_rr_cNotPt; 1938 case Hexagon::ASLH: 1939 return !invertPredicate ? Hexagon::ASLH_cPt_V4 : 1940 Hexagon::ASLH_cNotPt_V4; 1941 case Hexagon::ASRH: 1942 return !invertPredicate ? Hexagon::ASRH_cPt_V4 : 1943 Hexagon::ASRH_cNotPt_V4; 1944 case Hexagon::SXTB: 1945 return !invertPredicate ? Hexagon::SXTB_cPt_V4 : 1946 Hexagon::SXTB_cNotPt_V4; 1947 case Hexagon::SXTH: 1948 return !invertPredicate ? Hexagon::SXTH_cPt_V4 : 1949 Hexagon::SXTH_cNotPt_V4; 1950 case Hexagon::ZXTB: 1951 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 : 1952 Hexagon::ZXTB_cNotPt_V4; 1953 case Hexagon::ZXTH: 1954 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 : 1955 Hexagon::ZXTH_cNotPt_V4; 1956 1957 case Hexagon::JMPR: 1958 return !invertPredicate ? Hexagon::JMPR_cPt : 1959 Hexagon::JMPR_cNotPt; 1960 1961 // V4 indexed+scaled load. 1962 case Hexagon::LDrid_indexed_V4: 1963 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 : 1964 Hexagon::LDrid_indexed_cNotPt_V4; 1965 case Hexagon::LDrid_indexed_shl_V4: 1966 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 : 1967 Hexagon::LDrid_indexed_shl_cNotPt_V4; 1968 case Hexagon::LDrib_indexed_V4: 1969 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 : 1970 Hexagon::LDrib_indexed_cNotPt_V4; 1971 case Hexagon::LDriub_indexed_V4: 1972 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1973 Hexagon::LDriub_indexed_cNotPt_V4; 1974 case Hexagon::LDriub_ae_indexed_V4: 1975 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1976 Hexagon::LDriub_indexed_cNotPt_V4; 1977 case Hexagon::LDrib_indexed_shl_V4: 1978 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 : 1979 Hexagon::LDrib_indexed_shl_cNotPt_V4; 1980 case Hexagon::LDriub_indexed_shl_V4: 1981 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1982 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1983 case Hexagon::LDriub_ae_indexed_shl_V4: 1984 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1985 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1986 case Hexagon::LDrih_indexed_V4: 1987 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 : 1988 Hexagon::LDrih_indexed_cNotPt_V4; 1989 case Hexagon::LDriuh_indexed_V4: 1990 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 1991 Hexagon::LDriuh_indexed_cNotPt_V4; 1992 case Hexagon::LDriuh_ae_indexed_V4: 1993 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 1994 Hexagon::LDriuh_indexed_cNotPt_V4; 1995 case Hexagon::LDrih_indexed_shl_V4: 1996 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 : 1997 Hexagon::LDrih_indexed_shl_cNotPt_V4; 1998 case Hexagon::LDriuh_indexed_shl_V4: 1999 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2000 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2001 case Hexagon::LDriuh_ae_indexed_shl_V4: 2002 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2003 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2004 case Hexagon::LDriw_indexed_V4: 2005 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 : 2006 Hexagon::LDriw_indexed_cNotPt_V4; 2007 case Hexagon::LDriw_indexed_shl_V4: 2008 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : 2009 Hexagon::LDriw_indexed_shl_cNotPt_V4; 2010 2011 // V4 Load from global address 2012 case Hexagon::LDrid_GP_V4: 2013 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 : 2014 Hexagon::LDrid_GP_cNotPt_V4; 2015 case Hexagon::LDrib_GP_V4: 2016 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 : 2017 Hexagon::LDrib_GP_cNotPt_V4; 2018 case Hexagon::LDriub_GP_V4: 2019 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 : 2020 Hexagon::LDriub_GP_cNotPt_V4; 2021 case Hexagon::LDrih_GP_V4: 2022 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 : 2023 Hexagon::LDrih_GP_cNotPt_V4; 2024 case Hexagon::LDriuh_GP_V4: 2025 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 : 2026 Hexagon::LDriuh_GP_cNotPt_V4; 2027 case Hexagon::LDriw_GP_V4: 2028 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 : 2029 Hexagon::LDriw_GP_cNotPt_V4; 2030 2031 case Hexagon::LDd_GP_V4: 2032 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : 2033 Hexagon::LDd_GP_cNotPt_V4; 2034 case Hexagon::LDb_GP_V4: 2035 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : 2036 Hexagon::LDb_GP_cNotPt_V4; 2037 case Hexagon::LDub_GP_V4: 2038 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : 2039 Hexagon::LDub_GP_cNotPt_V4; 2040 case Hexagon::LDh_GP_V4: 2041 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : 2042 Hexagon::LDh_GP_cNotPt_V4; 2043 case Hexagon::LDuh_GP_V4: 2044 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : 2045 Hexagon::LDuh_GP_cNotPt_V4; 2046 case Hexagon::LDw_GP_V4: 2047 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : 2048 Hexagon::LDw_GP_cNotPt_V4; 2049 2050 // Byte. 2051 case Hexagon::POST_STbri: 2052 return !invertPredicate ? Hexagon::POST_STbri_cPt : 2053 Hexagon::POST_STbri_cNotPt; 2054 case Hexagon::STrib: 2055 return !invertPredicate ? Hexagon::STrib_cPt : 2056 Hexagon::STrib_cNotPt; 2057 case Hexagon::STrib_indexed: 2058 return !invertPredicate ? Hexagon::STrib_indexed_cPt : 2059 Hexagon::STrib_indexed_cNotPt; 2060 case Hexagon::STrib_imm_V4: 2061 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 : 2062 Hexagon::STrib_imm_cNotPt_V4; 2063 case Hexagon::STrib_indexed_shl_V4: 2064 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 : 2065 Hexagon::STrib_indexed_shl_cNotPt_V4; 2066 // Halfword. 2067 case Hexagon::POST_SThri: 2068 return !invertPredicate ? Hexagon::POST_SThri_cPt : 2069 Hexagon::POST_SThri_cNotPt; 2070 case Hexagon::STrih: 2071 return !invertPredicate ? Hexagon::STrih_cPt : 2072 Hexagon::STrih_cNotPt; 2073 case Hexagon::STrih_indexed: 2074 return !invertPredicate ? Hexagon::STrih_indexed_cPt : 2075 Hexagon::STrih_indexed_cNotPt; 2076 case Hexagon::STrih_imm_V4: 2077 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 : 2078 Hexagon::STrih_imm_cNotPt_V4; 2079 case Hexagon::STrih_indexed_shl_V4: 2080 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 : 2081 Hexagon::STrih_indexed_shl_cNotPt_V4; 2082 // Word. 2083 case Hexagon::POST_STwri: 2084 return !invertPredicate ? Hexagon::POST_STwri_cPt : 2085 Hexagon::POST_STwri_cNotPt; 2086 case Hexagon::STriw: 2087 return !invertPredicate ? Hexagon::STriw_cPt : 2088 Hexagon::STriw_cNotPt; 2089 case Hexagon::STriw_indexed: 2090 return !invertPredicate ? Hexagon::STriw_indexed_cPt : 2091 Hexagon::STriw_indexed_cNotPt; 2092 case Hexagon::STriw_indexed_shl_V4: 2093 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 : 2094 Hexagon::STriw_indexed_shl_cNotPt_V4; 2095 case Hexagon::STriw_imm_V4: 2096 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 : 2097 Hexagon::STriw_imm_cNotPt_V4; 2098 // Double word. 2099 case Hexagon::POST_STdri: 2100 return !invertPredicate ? Hexagon::POST_STdri_cPt : 2101 Hexagon::POST_STdri_cNotPt; 2102 case Hexagon::STrid: 2103 return !invertPredicate ? Hexagon::STrid_cPt : 2104 Hexagon::STrid_cNotPt; 2105 case Hexagon::STrid_indexed: 2106 return !invertPredicate ? Hexagon::STrid_indexed_cPt : 2107 Hexagon::STrid_indexed_cNotPt; 2108 case Hexagon::STrid_indexed_shl_V4: 2109 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : 2110 Hexagon::STrid_indexed_shl_cNotPt_V4; 2111 2112 // V4 Store to global address 2113 case Hexagon::STrid_GP_V4: 2114 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 : 2115 Hexagon::STrid_GP_cNotPt_V4; 2116 case Hexagon::STrib_GP_V4: 2117 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 : 2118 Hexagon::STrib_GP_cNotPt_V4; 2119 case Hexagon::STrih_GP_V4: 2120 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 : 2121 Hexagon::STrih_GP_cNotPt_V4; 2122 case Hexagon::STriw_GP_V4: 2123 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 : 2124 Hexagon::STriw_GP_cNotPt_V4; 2125 2126 case Hexagon::STd_GP_V4: 2127 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : 2128 Hexagon::STd_GP_cNotPt_V4; 2129 case Hexagon::STb_GP_V4: 2130 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : 2131 Hexagon::STb_GP_cNotPt_V4; 2132 case Hexagon::STh_GP_V4: 2133 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : 2134 Hexagon::STh_GP_cNotPt_V4; 2135 case Hexagon::STw_GP_V4: 2136 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : 2137 Hexagon::STw_GP_cNotPt_V4; 2138 2139 // Load. 2140 case Hexagon::LDrid: 2141 return !invertPredicate ? Hexagon::LDrid_cPt : 2142 Hexagon::LDrid_cNotPt; 2143 case Hexagon::LDriw: 2144 return !invertPredicate ? Hexagon::LDriw_cPt : 2145 Hexagon::LDriw_cNotPt; 2146 case Hexagon::LDrih: 2147 return !invertPredicate ? Hexagon::LDrih_cPt : 2148 Hexagon::LDrih_cNotPt; 2149 case Hexagon::LDriuh: 2150 return !invertPredicate ? Hexagon::LDriuh_cPt : 2151 Hexagon::LDriuh_cNotPt; 2152 case Hexagon::LDrib: 2153 return !invertPredicate ? Hexagon::LDrib_cPt : 2154 Hexagon::LDrib_cNotPt; 2155 case Hexagon::LDriub: 2156 return !invertPredicate ? Hexagon::LDriub_cPt : 2157 Hexagon::LDriub_cNotPt; 2158 // Load Indexed. 2159 case Hexagon::LDrid_indexed: 2160 return !invertPredicate ? Hexagon::LDrid_indexed_cPt : 2161 Hexagon::LDrid_indexed_cNotPt; 2162 case Hexagon::LDriw_indexed: 2163 return !invertPredicate ? Hexagon::LDriw_indexed_cPt : 2164 Hexagon::LDriw_indexed_cNotPt; 2165 case Hexagon::LDrih_indexed: 2166 return !invertPredicate ? Hexagon::LDrih_indexed_cPt : 2167 Hexagon::LDrih_indexed_cNotPt; 2168 case Hexagon::LDriuh_indexed: 2169 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt : 2170 Hexagon::LDriuh_indexed_cNotPt; 2171 case Hexagon::LDrib_indexed: 2172 return !invertPredicate ? Hexagon::LDrib_indexed_cPt : 2173 Hexagon::LDrib_indexed_cNotPt; 2174 case Hexagon::LDriub_indexed: 2175 return !invertPredicate ? Hexagon::LDriub_indexed_cPt : 2176 Hexagon::LDriub_indexed_cNotPt; 2177 // Post Increment Load. 2178 case Hexagon::POST_LDrid: 2179 return !invertPredicate ? Hexagon::POST_LDrid_cPt : 2180 Hexagon::POST_LDrid_cNotPt; 2181 case Hexagon::POST_LDriw: 2182 return !invertPredicate ? Hexagon::POST_LDriw_cPt : 2183 Hexagon::POST_LDriw_cNotPt; 2184 case Hexagon::POST_LDrih: 2185 return !invertPredicate ? Hexagon::POST_LDrih_cPt : 2186 Hexagon::POST_LDrih_cNotPt; 2187 case Hexagon::POST_LDriuh: 2188 return !invertPredicate ? Hexagon::POST_LDriuh_cPt : 2189 Hexagon::POST_LDriuh_cNotPt; 2190 case Hexagon::POST_LDrib: 2191 return !invertPredicate ? Hexagon::POST_LDrib_cPt : 2192 Hexagon::POST_LDrib_cNotPt; 2193 case Hexagon::POST_LDriub: 2194 return !invertPredicate ? Hexagon::POST_LDriub_cPt : 2195 Hexagon::POST_LDriub_cNotPt; 2196 // DEALLOC_RETURN. 2197 case Hexagon::DEALLOC_RET_V4: 2198 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : 2199 Hexagon::DEALLOC_RET_cNotPt_V4; 2200 } 2201 llvm_unreachable("Unexpected predicable instruction"); 2202} 2203 2204 2205bool HexagonInstrInfo:: 2206PredicateInstruction(MachineInstr *MI, 2207 const SmallVectorImpl<MachineOperand> &Cond) const { 2208 int Opc = MI->getOpcode(); 2209 assert (isPredicable(MI) && "Expected predicable instruction"); 2210 bool invertJump = (!Cond.empty() && Cond[0].isImm() && 2211 (Cond[0].getImm() == 0)); 2212 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); 2213 // 2214 // This assumes that the predicate is always the first operand 2215 // in the set of inputs. 2216 // 2217 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 2218 int oper; 2219 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) { 2220 MachineOperand MO = MI->getOperand(oper); 2221 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) { 2222 break; 2223 } 2224 2225 if (MO.isReg()) { 2226 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 2227 MO.isImplicit(), MO.isKill(), 2228 MO.isDead(), MO.isUndef(), 2229 MO.isDebug()); 2230 } else if (MO.isImm()) { 2231 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); 2232 } else { 2233 llvm_unreachable("Unexpected operand type"); 2234 } 2235 } 2236 2237 int regPos = invertJump ? 1 : 0; 2238 MachineOperand PredMO = Cond[regPos]; 2239 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(), 2240 PredMO.isImplicit(), PredMO.isKill(), 2241 PredMO.isDead(), PredMO.isUndef(), 2242 PredMO.isDebug()); 2243 2244 return true; 2245} 2246 2247 2248bool 2249HexagonInstrInfo:: 2250isProfitableToIfCvt(MachineBasicBlock &MBB, 2251 unsigned NumCyles, 2252 unsigned ExtraPredCycles, 2253 const BranchProbability &Probability) const { 2254 return true; 2255} 2256 2257 2258bool 2259HexagonInstrInfo:: 2260isProfitableToIfCvt(MachineBasicBlock &TMBB, 2261 unsigned NumTCycles, 2262 unsigned ExtraTCycles, 2263 MachineBasicBlock &FMBB, 2264 unsigned NumFCycles, 2265 unsigned ExtraFCycles, 2266 const BranchProbability &Probability) const { 2267 return true; 2268} 2269 2270 2271bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { 2272 const uint64_t F = MI->getDesc().TSFlags; 2273 2274 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); 2275} 2276 2277bool 2278HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, 2279 std::vector<MachineOperand> &Pred) const { 2280 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) { 2281 MachineOperand MO = MI->getOperand(oper); 2282 if (MO.isReg() && MO.isDef()) { 2283 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); 2284 if (RC == &Hexagon::PredRegsRegClass) { 2285 Pred.push_back(MO); 2286 return true; 2287 } 2288 } 2289 } 2290 return false; 2291} 2292 2293 2294bool 2295HexagonInstrInfo:: 2296SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 2297 const SmallVectorImpl<MachineOperand> &Pred2) const { 2298 // TODO: Fix this 2299 return false; 2300} 2301 2302 2303// 2304// We indicate that we want to reverse the branch by 2305// inserting a 0 at the beginning of the Cond vector. 2306// 2307bool HexagonInstrInfo:: 2308ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2309 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 2310 Cond.erase(Cond.begin()); 2311 } else { 2312 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0)); 2313 } 2314 return false; 2315} 2316 2317 2318bool HexagonInstrInfo:: 2319isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, 2320 const BranchProbability &Probability) const { 2321 return (NumInstrs <= 4); 2322} 2323 2324bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { 2325 switch (MI->getOpcode()) { 2326 default: return false; 2327 case Hexagon::DEALLOC_RET_V4 : 2328 case Hexagon::DEALLOC_RET_cPt_V4 : 2329 case Hexagon::DEALLOC_RET_cNotPt_V4 : 2330 case Hexagon::DEALLOC_RET_cdnPnt_V4 : 2331 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 : 2332 case Hexagon::DEALLOC_RET_cdnPt_V4 : 2333 case Hexagon::DEALLOC_RET_cNotdnPt_V4 : 2334 return true; 2335 } 2336} 2337 2338 2339bool HexagonInstrInfo:: 2340isValidOffset(const int Opcode, const int Offset) const { 2341 // This function is to check whether the "Offset" is in the correct range of 2342 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is 2343 // inserted to calculate the final address. Due to this reason, the function 2344 // assumes that the "Offset" has correct alignment. 2345 2346 switch(Opcode) { 2347 2348 case Hexagon::LDriw: 2349 case Hexagon::LDriw_f: 2350 case Hexagon::STriw: 2351 case Hexagon::STriw_f: 2352 assert((Offset % 4 == 0) && "Offset has incorrect alignment"); 2353 return (Offset >= Hexagon_MEMW_OFFSET_MIN) && 2354 (Offset <= Hexagon_MEMW_OFFSET_MAX); 2355 2356 case Hexagon::LDrid: 2357 case Hexagon::LDrid_f: 2358 case Hexagon::STrid: 2359 case Hexagon::STrid_f: 2360 assert((Offset % 8 == 0) && "Offset has incorrect alignment"); 2361 return (Offset >= Hexagon_MEMD_OFFSET_MIN) && 2362 (Offset <= Hexagon_MEMD_OFFSET_MAX); 2363 2364 case Hexagon::LDrih: 2365 case Hexagon::LDriuh: 2366 case Hexagon::STrih: 2367 assert((Offset % 2 == 0) && "Offset has incorrect alignment"); 2368 return (Offset >= Hexagon_MEMH_OFFSET_MIN) && 2369 (Offset <= Hexagon_MEMH_OFFSET_MAX); 2370 2371 case Hexagon::LDrib: 2372 case Hexagon::STrib: 2373 case Hexagon::LDriub: 2374 return (Offset >= Hexagon_MEMB_OFFSET_MIN) && 2375 (Offset <= Hexagon_MEMB_OFFSET_MAX); 2376 2377 case Hexagon::ADD_ri: 2378 case Hexagon::TFR_FI: 2379 return (Offset >= Hexagon_ADDI_OFFSET_MIN) && 2380 (Offset <= Hexagon_ADDI_OFFSET_MAX); 2381 2382 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2383 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2384 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2385 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2386 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2387 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2388 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2389 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2390 case Hexagon::MEMw_ADDi_MEM_V4 : 2391 case Hexagon::MEMw_SUBi_MEM_V4 : 2392 case Hexagon::MEMw_ADDr_MEM_V4 : 2393 case Hexagon::MEMw_SUBr_MEM_V4 : 2394 case Hexagon::MEMw_ANDr_MEM_V4 : 2395 case Hexagon::MEMw_ORr_MEM_V4 : 2396 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." ); 2397 return (0 <= Offset && Offset <= 255); 2398 2399 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2400 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2401 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2402 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2403 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2404 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2405 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2406 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2407 case Hexagon::MEMh_ADDi_MEM_V4 : 2408 case Hexagon::MEMh_SUBi_MEM_V4 : 2409 case Hexagon::MEMh_ADDr_MEM_V4 : 2410 case Hexagon::MEMh_SUBr_MEM_V4 : 2411 case Hexagon::MEMh_ANDr_MEM_V4 : 2412 case Hexagon::MEMh_ORr_MEM_V4 : 2413 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." ); 2414 return (0 <= Offset && Offset <= 127); 2415 2416 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2417 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2418 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2419 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2420 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2421 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2422 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2423 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2424 case Hexagon::MEMb_ADDi_MEM_V4 : 2425 case Hexagon::MEMb_SUBi_MEM_V4 : 2426 case Hexagon::MEMb_ADDr_MEM_V4 : 2427 case Hexagon::MEMb_SUBr_MEM_V4 : 2428 case Hexagon::MEMb_ANDr_MEM_V4 : 2429 case Hexagon::MEMb_ORr_MEM_V4 : 2430 return (0 <= Offset && Offset <= 63); 2431 2432 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of 2433 // any size. Later pass knows how to handle it. 2434 case Hexagon::STriw_pred: 2435 case Hexagon::LDriw_pred: 2436 return true; 2437 2438 // INLINEASM is very special. 2439 case Hexagon::INLINEASM: 2440 return true; 2441 } 2442 2443 llvm_unreachable("No offset range is defined for this opcode. " 2444 "Please define it in the above switch statement!"); 2445} 2446 2447 2448// 2449// Check if the Offset is a valid auto-inc imm by Load/Store Type. 2450// 2451bool HexagonInstrInfo:: 2452isValidAutoIncImm(const EVT VT, const int Offset) const { 2453 2454 if (VT == MVT::i64) { 2455 return (Offset >= Hexagon_MEMD_AUTOINC_MIN && 2456 Offset <= Hexagon_MEMD_AUTOINC_MAX && 2457 (Offset & 0x7) == 0); 2458 } 2459 if (VT == MVT::i32) { 2460 return (Offset >= Hexagon_MEMW_AUTOINC_MIN && 2461 Offset <= Hexagon_MEMW_AUTOINC_MAX && 2462 (Offset & 0x3) == 0); 2463 } 2464 if (VT == MVT::i16) { 2465 return (Offset >= Hexagon_MEMH_AUTOINC_MIN && 2466 Offset <= Hexagon_MEMH_AUTOINC_MAX && 2467 (Offset & 0x1) == 0); 2468 } 2469 if (VT == MVT::i8) { 2470 return (Offset >= Hexagon_MEMB_AUTOINC_MIN && 2471 Offset <= Hexagon_MEMB_AUTOINC_MAX); 2472 } 2473 llvm_unreachable("Not an auto-inc opc!"); 2474} 2475 2476 2477bool HexagonInstrInfo:: 2478isMemOp(const MachineInstr *MI) const { 2479 switch (MI->getOpcode()) 2480 { 2481 default: return false; 2482 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2483 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2484 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2485 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2486 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2487 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2488 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2489 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2490 case Hexagon::MEMw_ADDi_MEM_V4 : 2491 case Hexagon::MEMw_SUBi_MEM_V4 : 2492 case Hexagon::MEMw_ADDr_MEM_V4 : 2493 case Hexagon::MEMw_SUBr_MEM_V4 : 2494 case Hexagon::MEMw_ANDr_MEM_V4 : 2495 case Hexagon::MEMw_ORr_MEM_V4 : 2496 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2497 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2498 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2499 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2500 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2501 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2502 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2503 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2504 case Hexagon::MEMh_ADDi_MEM_V4 : 2505 case Hexagon::MEMh_SUBi_MEM_V4 : 2506 case Hexagon::MEMh_ADDr_MEM_V4 : 2507 case Hexagon::MEMh_SUBr_MEM_V4 : 2508 case Hexagon::MEMh_ANDr_MEM_V4 : 2509 case Hexagon::MEMh_ORr_MEM_V4 : 2510 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2511 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2512 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2513 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2514 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2515 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2516 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2517 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2518 case Hexagon::MEMb_ADDi_MEM_V4 : 2519 case Hexagon::MEMb_SUBi_MEM_V4 : 2520 case Hexagon::MEMb_ADDr_MEM_V4 : 2521 case Hexagon::MEMb_SUBr_MEM_V4 : 2522 case Hexagon::MEMb_ANDr_MEM_V4 : 2523 case Hexagon::MEMb_ORr_MEM_V4 : 2524 return true; 2525 } 2526} 2527 2528 2529bool HexagonInstrInfo:: 2530isSpillPredRegOp(const MachineInstr *MI) const { 2531 switch (MI->getOpcode()) { 2532 default: return false; 2533 case Hexagon::STriw_pred : 2534 case Hexagon::LDriw_pred : 2535 return true; 2536 } 2537} 2538 2539bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { 2540 switch (MI->getOpcode()) { 2541 case Hexagon::CMPEQrr: 2542 case Hexagon::CMPEQri: 2543 case Hexagon::CMPLTrr: 2544 case Hexagon::CMPGTrr: 2545 case Hexagon::CMPGTri: 2546 case Hexagon::CMPLTUrr: 2547 case Hexagon::CMPGTUrr: 2548 case Hexagon::CMPGTUri: 2549 case Hexagon::CMPGEri: 2550 case Hexagon::CMPGEUri: 2551 return true; 2552 2553 default: 2554 return false; 2555 } 2556 return false; 2557} 2558 2559bool HexagonInstrInfo:: 2560isConditionalTransfer (const MachineInstr *MI) const { 2561 switch (MI->getOpcode()) { 2562 default: return false; 2563 case Hexagon::TFR_cPt: 2564 case Hexagon::TFR_cNotPt: 2565 case Hexagon::TFRI_cPt: 2566 case Hexagon::TFRI_cNotPt: 2567 case Hexagon::TFR_cdnPt: 2568 case Hexagon::TFR_cdnNotPt: 2569 case Hexagon::TFRI_cdnPt: 2570 case Hexagon::TFRI_cdnNotPt: 2571 return true; 2572 } 2573} 2574 2575bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { 2576 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2577 switch (MI->getOpcode()) 2578 { 2579 default: return false; 2580 case Hexagon::ADD_ri_cPt: 2581 case Hexagon::ADD_ri_cNotPt: 2582 case Hexagon::ADD_rr_cPt: 2583 case Hexagon::ADD_rr_cNotPt: 2584 case Hexagon::XOR_rr_cPt: 2585 case Hexagon::XOR_rr_cNotPt: 2586 case Hexagon::AND_rr_cPt: 2587 case Hexagon::AND_rr_cNotPt: 2588 case Hexagon::OR_rr_cPt: 2589 case Hexagon::OR_rr_cNotPt: 2590 case Hexagon::SUB_rr_cPt: 2591 case Hexagon::SUB_rr_cNotPt: 2592 case Hexagon::COMBINE_rr_cPt: 2593 case Hexagon::COMBINE_rr_cNotPt: 2594 return true; 2595 case Hexagon::ASLH_cPt_V4: 2596 case Hexagon::ASLH_cNotPt_V4: 2597 case Hexagon::ASRH_cPt_V4: 2598 case Hexagon::ASRH_cNotPt_V4: 2599 case Hexagon::SXTB_cPt_V4: 2600 case Hexagon::SXTB_cNotPt_V4: 2601 case Hexagon::SXTH_cPt_V4: 2602 case Hexagon::SXTH_cNotPt_V4: 2603 case Hexagon::ZXTB_cPt_V4: 2604 case Hexagon::ZXTB_cNotPt_V4: 2605 case Hexagon::ZXTH_cPt_V4: 2606 case Hexagon::ZXTH_cNotPt_V4: 2607 return QRI.Subtarget.hasV4TOps(); 2608 } 2609} 2610 2611bool HexagonInstrInfo:: 2612isConditionalLoad (const MachineInstr* MI) const { 2613 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2614 switch (MI->getOpcode()) 2615 { 2616 default: return false; 2617 case Hexagon::LDrid_cPt : 2618 case Hexagon::LDrid_cNotPt : 2619 case Hexagon::LDrid_indexed_cPt : 2620 case Hexagon::LDrid_indexed_cNotPt : 2621 case Hexagon::LDriw_cPt : 2622 case Hexagon::LDriw_cNotPt : 2623 case Hexagon::LDriw_indexed_cPt : 2624 case Hexagon::LDriw_indexed_cNotPt : 2625 case Hexagon::LDrih_cPt : 2626 case Hexagon::LDrih_cNotPt : 2627 case Hexagon::LDrih_indexed_cPt : 2628 case Hexagon::LDrih_indexed_cNotPt : 2629 case Hexagon::LDrib_cPt : 2630 case Hexagon::LDrib_cNotPt : 2631 case Hexagon::LDrib_indexed_cPt : 2632 case Hexagon::LDrib_indexed_cNotPt : 2633 case Hexagon::LDriuh_cPt : 2634 case Hexagon::LDriuh_cNotPt : 2635 case Hexagon::LDriuh_indexed_cPt : 2636 case Hexagon::LDriuh_indexed_cNotPt : 2637 case Hexagon::LDriub_cPt : 2638 case Hexagon::LDriub_cNotPt : 2639 case Hexagon::LDriub_indexed_cPt : 2640 case Hexagon::LDriub_indexed_cNotPt : 2641 return true; 2642 case Hexagon::POST_LDrid_cPt : 2643 case Hexagon::POST_LDrid_cNotPt : 2644 case Hexagon::POST_LDriw_cPt : 2645 case Hexagon::POST_LDriw_cNotPt : 2646 case Hexagon::POST_LDrih_cPt : 2647 case Hexagon::POST_LDrih_cNotPt : 2648 case Hexagon::POST_LDrib_cPt : 2649 case Hexagon::POST_LDrib_cNotPt : 2650 case Hexagon::POST_LDriuh_cPt : 2651 case Hexagon::POST_LDriuh_cNotPt : 2652 case Hexagon::POST_LDriub_cPt : 2653 case Hexagon::POST_LDriub_cNotPt : 2654 return QRI.Subtarget.hasV4TOps(); 2655 case Hexagon::LDrid_indexed_cPt_V4 : 2656 case Hexagon::LDrid_indexed_cNotPt_V4 : 2657 case Hexagon::LDrid_indexed_shl_cPt_V4 : 2658 case Hexagon::LDrid_indexed_shl_cNotPt_V4 : 2659 case Hexagon::LDrib_indexed_cPt_V4 : 2660 case Hexagon::LDrib_indexed_cNotPt_V4 : 2661 case Hexagon::LDrib_indexed_shl_cPt_V4 : 2662 case Hexagon::LDrib_indexed_shl_cNotPt_V4 : 2663 case Hexagon::LDriub_indexed_cPt_V4 : 2664 case Hexagon::LDriub_indexed_cNotPt_V4 : 2665 case Hexagon::LDriub_indexed_shl_cPt_V4 : 2666 case Hexagon::LDriub_indexed_shl_cNotPt_V4 : 2667 case Hexagon::LDrih_indexed_cPt_V4 : 2668 case Hexagon::LDrih_indexed_cNotPt_V4 : 2669 case Hexagon::LDrih_indexed_shl_cPt_V4 : 2670 case Hexagon::LDrih_indexed_shl_cNotPt_V4 : 2671 case Hexagon::LDriuh_indexed_cPt_V4 : 2672 case Hexagon::LDriuh_indexed_cNotPt_V4 : 2673 case Hexagon::LDriuh_indexed_shl_cPt_V4 : 2674 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : 2675 case Hexagon::LDriw_indexed_cPt_V4 : 2676 case Hexagon::LDriw_indexed_cNotPt_V4 : 2677 case Hexagon::LDriw_indexed_shl_cPt_V4 : 2678 case Hexagon::LDriw_indexed_shl_cNotPt_V4 : 2679 return QRI.Subtarget.hasV4TOps(); 2680 } 2681} 2682 2683// Returns true if an instruction is a conditional store. 2684// 2685// Note: It doesn't include conditional new-value stores as they can't be 2686// converted to .new predicate. 2687// 2688// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] 2689// ^ ^ 2690// / \ (not OK. it will cause new-value store to be 2691// / X conditional on p0.new while R2 producer is 2692// / \ on p0) 2693// / \. 2694// p.new store p.old NV store 2695// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] 2696// ^ ^ 2697// \ / 2698// \ / 2699// \ / 2700// p.old store 2701// [if (p0)memw(R0+#0)=R2] 2702// 2703// The above diagram shows the steps involoved in the conversion of a predicated 2704// store instruction to its .new predicated new-value form. 2705// 2706// The following set of instructions further explains the scenario where 2707// conditional new-value store becomes invalid when promoted to .new predicate 2708// form. 2709// 2710// { 1) if (p0) r0 = add(r1, r2) 2711// 2) p0 = cmp.eq(r3, #0) } 2712// 2713// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with 2714// the first two instructions because in instr 1, r0 is conditional on old value 2715// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which 2716// is not valid for new-value stores. 2717bool HexagonInstrInfo:: 2718isConditionalStore (const MachineInstr* MI) const { 2719 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2720 switch (MI->getOpcode()) 2721 { 2722 default: return false; 2723 case Hexagon::STrib_imm_cPt_V4 : 2724 case Hexagon::STrib_imm_cNotPt_V4 : 2725 case Hexagon::STrib_indexed_shl_cPt_V4 : 2726 case Hexagon::STrib_indexed_shl_cNotPt_V4 : 2727 case Hexagon::STrib_cPt : 2728 case Hexagon::STrib_cNotPt : 2729 case Hexagon::POST_STbri_cPt : 2730 case Hexagon::POST_STbri_cNotPt : 2731 case Hexagon::STrid_indexed_cPt : 2732 case Hexagon::STrid_indexed_cNotPt : 2733 case Hexagon::STrid_indexed_shl_cPt_V4 : 2734 case Hexagon::POST_STdri_cPt : 2735 case Hexagon::POST_STdri_cNotPt : 2736 case Hexagon::STrih_cPt : 2737 case Hexagon::STrih_cNotPt : 2738 case Hexagon::STrih_indexed_cPt : 2739 case Hexagon::STrih_indexed_cNotPt : 2740 case Hexagon::STrih_imm_cPt_V4 : 2741 case Hexagon::STrih_imm_cNotPt_V4 : 2742 case Hexagon::STrih_indexed_shl_cPt_V4 : 2743 case Hexagon::STrih_indexed_shl_cNotPt_V4 : 2744 case Hexagon::POST_SThri_cPt : 2745 case Hexagon::POST_SThri_cNotPt : 2746 case Hexagon::STriw_cPt : 2747 case Hexagon::STriw_cNotPt : 2748 case Hexagon::STriw_indexed_cPt : 2749 case Hexagon::STriw_indexed_cNotPt : 2750 case Hexagon::STriw_imm_cPt_V4 : 2751 case Hexagon::STriw_imm_cNotPt_V4 : 2752 case Hexagon::STriw_indexed_shl_cPt_V4 : 2753 case Hexagon::STriw_indexed_shl_cNotPt_V4 : 2754 case Hexagon::POST_STwri_cPt : 2755 case Hexagon::POST_STwri_cNotPt : 2756 return QRI.Subtarget.hasV4TOps(); 2757 2758 // V4 global address store before promoting to dot new. 2759 case Hexagon::STrid_GP_cPt_V4 : 2760 case Hexagon::STrid_GP_cNotPt_V4 : 2761 case Hexagon::STrib_GP_cPt_V4 : 2762 case Hexagon::STrib_GP_cNotPt_V4 : 2763 case Hexagon::STrih_GP_cPt_V4 : 2764 case Hexagon::STrih_GP_cNotPt_V4 : 2765 case Hexagon::STriw_GP_cPt_V4 : 2766 case Hexagon::STriw_GP_cNotPt_V4 : 2767 case Hexagon::STd_GP_cPt_V4 : 2768 case Hexagon::STd_GP_cNotPt_V4 : 2769 case Hexagon::STb_GP_cPt_V4 : 2770 case Hexagon::STb_GP_cNotPt_V4 : 2771 case Hexagon::STh_GP_cPt_V4 : 2772 case Hexagon::STh_GP_cNotPt_V4 : 2773 case Hexagon::STw_GP_cPt_V4 : 2774 case Hexagon::STw_GP_cNotPt_V4 : 2775 return QRI.Subtarget.hasV4TOps(); 2776 2777 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded 2778 // from the "Conditional Store" list. Because a predicated new value store 2779 // would NOT be promoted to a double dot new store. See diagram below: 2780 // This function returns yes for those stores that are predicated but not 2781 // yet promoted to predicate dot new instructions. 2782 // 2783 // +---------------------+ 2784 // /-----| if (p0) memw(..)=r0 |---------\~ 2785 // || +---------------------+ || 2786 // promote || /\ /\ || promote 2787 // || /||\ /||\ || 2788 // \||/ demote || \||/ 2789 // \/ || || \/ 2790 // +-------------------------+ || +-------------------------+ 2791 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | 2792 // +-------------------------+ || +-------------------------+ 2793 // || || || 2794 // || demote \||/ 2795 // promote || \/ NOT possible 2796 // || || /\~ 2797 // \||/ || /||\~ 2798 // \/ || || 2799 // +-----------------------------+ 2800 // | if (p0.new) memw(..)=r0.new | 2801 // +-----------------------------+ 2802 // Double Dot New Store 2803 // 2804 } 2805} 2806 2807 2808 2809DFAPacketizer *HexagonInstrInfo:: 2810CreateTargetScheduleState(const TargetMachine *TM, 2811 const ScheduleDAG *DAG) const { 2812 const InstrItineraryData *II = TM->getInstrItineraryData(); 2813 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); 2814} 2815 2816bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 2817 const MachineBasicBlock *MBB, 2818 const MachineFunction &MF) const { 2819 // Debug info is never a scheduling boundary. It's necessary to be explicit 2820 // due to the special treatment of IT instructions below, otherwise a 2821 // dbg_value followed by an IT will result in the IT instruction being 2822 // considered a scheduling hazard, which is wrong. It should be the actual 2823 // instruction preceding the dbg_value instruction(s), just like it is 2824 // when debug info is not present. 2825 if (MI->isDebugValue()) 2826 return false; 2827 2828 // Terminators and labels can't be scheduled around. 2829 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) 2830 return true; 2831 2832 return false; 2833} 2834