HexagonInstrInfo.cpp revision 26f61a158b3cce69252c05cc0e79f500d6c3d92e 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "HexagonRegisterInfo.h"
16#include "HexagonSubtarget.h"
17#include "Hexagon.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#include "HexagonGenInstrInfo.inc"
29#include "HexagonGenDFAPacketizer.inc"
30
31using namespace llvm;
32
33///
34/// Constants for Hexagon instructions.
35///
36const int Hexagon_MEMW_OFFSET_MAX = 4095;
37const int Hexagon_MEMW_OFFSET_MIN = -4096;
38const int Hexagon_MEMD_OFFSET_MAX = 8191;
39const int Hexagon_MEMD_OFFSET_MIN = -8192;
40const int Hexagon_MEMH_OFFSET_MAX = 2047;
41const int Hexagon_MEMH_OFFSET_MIN = -2048;
42const int Hexagon_MEMB_OFFSET_MAX = 1023;
43const int Hexagon_MEMB_OFFSET_MIN = -1024;
44const int Hexagon_ADDI_OFFSET_MAX = 32767;
45const int Hexagon_ADDI_OFFSET_MIN = -32768;
46const int Hexagon_MEMD_AUTOINC_MAX = 56;
47const int Hexagon_MEMD_AUTOINC_MIN = -64;
48const int Hexagon_MEMW_AUTOINC_MAX = 28;
49const int Hexagon_MEMW_AUTOINC_MIN = -32;
50const int Hexagon_MEMH_AUTOINC_MAX = 14;
51const int Hexagon_MEMH_AUTOINC_MIN = -16;
52const int Hexagon_MEMB_AUTOINC_MAX = 7;
53const int Hexagon_MEMB_AUTOINC_MIN = -8;
54
55
56HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
57  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
58    RI(ST, *this), Subtarget(ST) {
59}
60
61
62/// isLoadFromStackSlot - If the specified machine instruction is a direct
63/// load from a stack slot, return the virtual or physical register number of
64/// the destination along with the FrameIndex of the loaded stack slot.  If
65/// not, return 0.  This predicate must return 0 if the instruction has
66/// any side effects other than loading from the stack slot.
67unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
68                                             int &FrameIndex) const {
69
70
71  switch (MI->getOpcode()) {
72  default: break;
73  case Hexagon::LDriw:
74  case Hexagon::LDrid:
75  case Hexagon::LDrih:
76  case Hexagon::LDrib:
77  case Hexagon::LDriub:
78    if (MI->getOperand(2).isFI() &&
79        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80      FrameIndex = MI->getOperand(2).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83    break;
84  }
85  return 0;
86}
87
88
89/// isStoreToStackSlot - If the specified machine instruction is a direct
90/// store to a stack slot, return the virtual or physical register number of
91/// the source reg along with the FrameIndex of the loaded stack slot.  If
92/// not, return 0.  This predicate must return 0 if the instruction has
93/// any side effects other than storing to the stack slot.
94unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
95                                            int &FrameIndex) const {
96  switch (MI->getOpcode()) {
97  default: break;
98  case Hexagon::STriw:
99  case Hexagon::STrid:
100  case Hexagon::STrih:
101  case Hexagon::STrib:
102    if (MI->getOperand(2).isFI() &&
103        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
104      FrameIndex = MI->getOperand(2).getIndex();
105      return MI->getOperand(0).getReg();
106    }
107    break;
108  }
109  return 0;
110}
111
112
113unsigned
114HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
115                             MachineBasicBlock *FBB,
116                             const SmallVectorImpl<MachineOperand> &Cond,
117                             DebugLoc DL) const{
118
119    int BOpc   = Hexagon::JMP;
120    int BccOpc = Hexagon::JMP_c;
121
122    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
123
124    int regPos = 0;
125    // Check if ReverseBranchCondition has asked to reverse this branch
126    // If we want to reverse the branch an odd number of times, we want
127    // JMP_cNot.
128    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
129      BccOpc = Hexagon::JMP_cNot;
130      regPos = 1;
131    }
132
133    if (FBB == 0) {
134      if (Cond.empty()) {
135        // Due to a bug in TailMerging/CFG Optimization, we need to add a
136        // special case handling of a predicated jump followed by an
137        // unconditional jump. If not, Tail Merging and CFG Optimization go
138        // into an infinite loop.
139        MachineBasicBlock *NewTBB, *NewFBB;
140        SmallVector<MachineOperand, 4> Cond;
141        MachineInstr *Term = MBB.getFirstTerminator();
142        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
143                                                 false)) {
144          MachineBasicBlock *NextBB =
145            llvm::next(MachineFunction::iterator(&MBB));
146          if (NewTBB == NextBB) {
147            ReverseBranchCondition(Cond);
148            RemoveBranch(MBB);
149            return InsertBranch(MBB, TBB, 0, Cond, DL);
150          }
151        }
152        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
153      } else {
154        BuildMI(&MBB, DL,
155                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
156      }
157      return 1;
158    }
159
160    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
161    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
162
163    return 2;
164}
165
166
167bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
168                                     MachineBasicBlock *&TBB,
169                                 MachineBasicBlock *&FBB,
170                                 SmallVectorImpl<MachineOperand> &Cond,
171                                 bool AllowModify) const {
172  FBB = NULL;
173
174  // If the block has no terminators, it just falls into the block after it.
175  MachineBasicBlock::iterator I = MBB.end();
176  if (I == MBB.begin())
177    return false;
178
179  // A basic block may looks like this:
180  //
181  //  [   insn
182  //     EH_LABEL
183  //      insn
184  //      insn
185  //      insn
186  //     EH_LABEL
187  //      insn     ]
188  //
189  // It has two succs but does not have a terminator
190  // Don't know how to handle it.
191  do {
192    --I;
193    if (I->isEHLabel())
194      return true;
195  } while (I != MBB.begin());
196
197  I = MBB.end();
198  --I;
199
200  while (I->isDebugValue()) {
201    if (I == MBB.begin())
202      return false;
203    --I;
204  }
205  if (!isUnpredicatedTerminator(I))
206    return false;
207
208  // Get the last instruction in the block.
209  MachineInstr *LastInst = I;
210
211  // If there is only one terminator instruction, process it.
212  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
213    if (LastInst->getOpcode() == Hexagon::JMP) {
214      TBB = LastInst->getOperand(0).getMBB();
215      return false;
216    }
217    if (LastInst->getOpcode() == Hexagon::JMP_c) {
218      // Block ends with fall-through true condbranch.
219      TBB = LastInst->getOperand(1).getMBB();
220      Cond.push_back(LastInst->getOperand(0));
221      return false;
222    }
223    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
224      // Block ends with fall-through false condbranch.
225      TBB = LastInst->getOperand(1).getMBB();
226      Cond.push_back(MachineOperand::CreateImm(0));
227      Cond.push_back(LastInst->getOperand(0));
228      return false;
229    }
230    // Otherwise, don't know what this is.
231    return true;
232  }
233
234  // Get the instruction before it if it's a terminator.
235  MachineInstr *SecondLastInst = I;
236
237  // If there are three terminators, we don't know what sort of block this is.
238  if (SecondLastInst && I != MBB.begin() &&
239      isUnpredicatedTerminator(--I))
240    return true;
241
242  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
243  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
244      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
245      LastInst->getOpcode() == Hexagon::JMP) {
246    TBB =  SecondLastInst->getOperand(1).getMBB();
247    Cond.push_back(SecondLastInst->getOperand(0));
248    FBB = LastInst->getOperand(0).getMBB();
249    return false;
250  }
251
252  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
253  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
254      LastInst->getOpcode() == Hexagon::JMP) {
255    TBB =  SecondLastInst->getOperand(1).getMBB();
256    Cond.push_back(MachineOperand::CreateImm(0));
257    Cond.push_back(SecondLastInst->getOperand(0));
258    FBB = LastInst->getOperand(0).getMBB();
259    return false;
260  }
261
262  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
263  // executed, so remove it.
264  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
265      LastInst->getOpcode() == Hexagon::JMP) {
266    TBB = SecondLastInst->getOperand(0).getMBB();
267    I = LastInst;
268    if (AllowModify)
269      I->eraseFromParent();
270    return false;
271  }
272
273  // Otherwise, can't handle this.
274  return true;
275}
276
277
278unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
279  int BOpc   = Hexagon::JMP;
280  int BccOpc = Hexagon::JMP_c;
281  int BccOpcNot = Hexagon::JMP_cNot;
282
283  MachineBasicBlock::iterator I = MBB.end();
284  if (I == MBB.begin()) return 0;
285  --I;
286  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
287      I->getOpcode() != BccOpcNot)
288    return 0;
289
290  // Remove the branch.
291  I->eraseFromParent();
292
293  I = MBB.end();
294
295  if (I == MBB.begin()) return 1;
296  --I;
297  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
298    return 1;
299
300  // Remove the branch.
301  I->eraseFromParent();
302  return 2;
303}
304
305
306void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
307                                 MachineBasicBlock::iterator I, DebugLoc DL,
308                                 unsigned DestReg, unsigned SrcReg,
309                                 bool KillSrc) const {
310  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
311    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
312    return;
313  }
314  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
315    BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
316    return;
317  }
318  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
319    // Map Pd = Ps to Pd = or(Ps, Ps).
320    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
321            DestReg).addReg(SrcReg).addReg(SrcReg);
322    return;
323  }
324  if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
325    // We can have an overlap between single and double reg: r1:0 = r0.
326    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
327        // r1:0 = r0
328        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
329                Hexagon::subreg_hireg))).addImm(0);
330    } else {
331        // r1:0 = r1 or no overlap.
332        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
333                Hexagon::subreg_loreg))).addReg(SrcReg);
334        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
335                Hexagon::subreg_hireg))).addImm(0);
336    }
337    return;
338  }
339  if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
340    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
341    return;
342  }
343
344  llvm_unreachable("Unimplemented");
345}
346
347
348void HexagonInstrInfo::
349storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
350                    unsigned SrcReg, bool isKill, int FI,
351                    const TargetRegisterClass *RC,
352                    const TargetRegisterInfo *TRI) const {
353
354  DebugLoc DL = MBB.findDebugLoc(I);
355  MachineFunction &MF = *MBB.getParent();
356  MachineFrameInfo &MFI = *MF.getFrameInfo();
357  unsigned Align = MFI.getObjectAlignment(FI);
358
359  MachineMemOperand *MMO =
360      MF.getMachineMemOperand(
361                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
362                      MachineMemOperand::MOStore,
363                      MFI.getObjectSize(FI),
364                      Align);
365
366  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
367    BuildMI(MBB, I, DL, get(Hexagon::STriw))
368          .addFrameIndex(FI).addImm(0)
369          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
370  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
371    BuildMI(MBB, I, DL, get(Hexagon::STrid))
372          .addFrameIndex(FI).addImm(0)
373          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
374  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
375    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
376          .addFrameIndex(FI).addImm(0)
377          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
378  } else {
379    llvm_unreachable("Unimplemented");
380  }
381}
382
383
384void HexagonInstrInfo::storeRegToAddr(
385                                 MachineFunction &MF, unsigned SrcReg,
386                                 bool isKill,
387                                 SmallVectorImpl<MachineOperand> &Addr,
388                                 const TargetRegisterClass *RC,
389                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
390{
391  llvm_unreachable("Unimplemented");
392}
393
394
395void HexagonInstrInfo::
396loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
397                     unsigned DestReg, int FI,
398                     const TargetRegisterClass *RC,
399                     const TargetRegisterInfo *TRI) const {
400  DebugLoc DL = MBB.findDebugLoc(I);
401  MachineFunction &MF = *MBB.getParent();
402  MachineFrameInfo &MFI = *MF.getFrameInfo();
403  unsigned Align = MFI.getObjectAlignment(FI);
404
405  MachineMemOperand *MMO =
406      MF.getMachineMemOperand(
407                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
408                      MachineMemOperand::MOLoad,
409                      MFI.getObjectSize(FI),
410                      Align);
411  if (RC == &Hexagon::IntRegsRegClass) {
412    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
413          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
414  } else if (RC == &Hexagon::DoubleRegsRegClass) {
415    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
416          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
417  } else if (RC == &Hexagon::PredRegsRegClass) {
418    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
419          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
420  } else {
421    llvm_unreachable("Can't store this register to stack slot");
422  }
423}
424
425
426void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
427                                        SmallVectorImpl<MachineOperand> &Addr,
428                                        const TargetRegisterClass *RC,
429                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
430  llvm_unreachable("Unimplemented");
431}
432
433
434MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
435                                                    MachineInstr* MI,
436                                          const SmallVectorImpl<unsigned> &Ops,
437                                                    int FI) const {
438  // Hexagon_TODO: Implement.
439  return(0);
440}
441
442
443unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
444
445  MachineRegisterInfo &RegInfo = MF->getRegInfo();
446  const TargetRegisterClass *TRC;
447  if (VT == MVT::i1)
448    TRC = &Hexagon::PredRegsRegClass;
449  else if (VT == MVT::i32)
450    TRC = &Hexagon::IntRegsRegClass;
451  else if (VT == MVT::i64)
452    TRC = &Hexagon::DoubleRegsRegClass;
453  else
454    llvm_unreachable("Cannot handle this register class");
455
456  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
457  return NewReg;
458}
459
460bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
461  switch(MI->getOpcode()) {
462    default: return false;
463    // JMP_EQri
464    case Hexagon::JMP_EQriPt_nv_V4:
465    case Hexagon::JMP_EQriPnt_nv_V4:
466    case Hexagon::JMP_EQriNotPt_nv_V4:
467    case Hexagon::JMP_EQriNotPnt_nv_V4:
468
469    // JMP_EQri - with -1
470    case Hexagon::JMP_EQriPtneg_nv_V4:
471    case Hexagon::JMP_EQriPntneg_nv_V4:
472    case Hexagon::JMP_EQriNotPtneg_nv_V4:
473    case Hexagon::JMP_EQriNotPntneg_nv_V4:
474
475    // JMP_EQrr
476    case Hexagon::JMP_EQrrPt_nv_V4:
477    case Hexagon::JMP_EQrrPnt_nv_V4:
478    case Hexagon::JMP_EQrrNotPt_nv_V4:
479    case Hexagon::JMP_EQrrNotPnt_nv_V4:
480
481    // JMP_GTri
482    case Hexagon::JMP_GTriPt_nv_V4:
483    case Hexagon::JMP_GTriPnt_nv_V4:
484    case Hexagon::JMP_GTriNotPt_nv_V4:
485    case Hexagon::JMP_GTriNotPnt_nv_V4:
486
487    // JMP_GTri - with -1
488    case Hexagon::JMP_GTriPtneg_nv_V4:
489    case Hexagon::JMP_GTriPntneg_nv_V4:
490    case Hexagon::JMP_GTriNotPtneg_nv_V4:
491    case Hexagon::JMP_GTriNotPntneg_nv_V4:
492
493    // JMP_GTrr
494    case Hexagon::JMP_GTrrPt_nv_V4:
495    case Hexagon::JMP_GTrrPnt_nv_V4:
496    case Hexagon::JMP_GTrrNotPt_nv_V4:
497    case Hexagon::JMP_GTrrNotPnt_nv_V4:
498
499    // JMP_GTrrdn
500    case Hexagon::JMP_GTrrdnPt_nv_V4:
501    case Hexagon::JMP_GTrrdnPnt_nv_V4:
502    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
503    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
504
505    // JMP_GTUri
506    case Hexagon::JMP_GTUriPt_nv_V4:
507    case Hexagon::JMP_GTUriPnt_nv_V4:
508    case Hexagon::JMP_GTUriNotPt_nv_V4:
509    case Hexagon::JMP_GTUriNotPnt_nv_V4:
510
511    // JMP_GTUrr
512    case Hexagon::JMP_GTUrrPt_nv_V4:
513    case Hexagon::JMP_GTUrrPnt_nv_V4:
514    case Hexagon::JMP_GTUrrNotPt_nv_V4:
515    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
516
517    // JMP_GTUrrdn
518    case Hexagon::JMP_GTUrrdnPt_nv_V4:
519    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
520    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
521    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
522
523    // TFR_FI
524    case Hexagon::TFR_FI:
525      return true;
526  }
527}
528
529bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
530  switch(MI->getOpcode()) {
531    default: return false;
532    // JMP_EQri
533    case Hexagon::JMP_EQriPt_ie_nv_V4:
534    case Hexagon::JMP_EQriPnt_ie_nv_V4:
535    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
536    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
537
538    // JMP_EQri - with -1
539    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
540    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
541    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
542    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
543
544    // JMP_EQrr
545    case Hexagon::JMP_EQrrPt_ie_nv_V4:
546    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
547    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
548    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
549
550    // JMP_GTri
551    case Hexagon::JMP_GTriPt_ie_nv_V4:
552    case Hexagon::JMP_GTriPnt_ie_nv_V4:
553    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
554    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
555
556    // JMP_GTri - with -1
557    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
558    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
559    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
560    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
561
562    // JMP_GTrr
563    case Hexagon::JMP_GTrrPt_ie_nv_V4:
564    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
565    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
566    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
567
568    // JMP_GTrrdn
569    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
570    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
571    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
572    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
573
574    // JMP_GTUri
575    case Hexagon::JMP_GTUriPt_ie_nv_V4:
576    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
577    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
578    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
579
580    // JMP_GTUrr
581    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
582    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
583    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
584    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
585
586    // JMP_GTUrrdn
587    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
588    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
589    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
590    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
591
592    // V4 absolute set addressing.
593    case Hexagon::LDrid_abs_setimm_V4:
594    case Hexagon::LDriw_abs_setimm_V4:
595    case Hexagon::LDrih_abs_setimm_V4:
596    case Hexagon::LDrib_abs_setimm_V4:
597    case Hexagon::LDriuh_abs_setimm_V4:
598    case Hexagon::LDriub_abs_setimm_V4:
599
600    case Hexagon::STrid_abs_setimm_V4:
601    case Hexagon::STrib_abs_setimm_V4:
602    case Hexagon::STrih_abs_setimm_V4:
603    case Hexagon::STriw_abs_setimm_V4:
604
605    // V4 global address load.
606    case Hexagon::LDrid_GP_cPt_V4 :
607    case Hexagon::LDrid_GP_cNotPt_V4 :
608    case Hexagon::LDrid_GP_cdnPt_V4 :
609    case Hexagon::LDrid_GP_cdnNotPt_V4 :
610    case Hexagon::LDrib_GP_cPt_V4 :
611    case Hexagon::LDrib_GP_cNotPt_V4 :
612    case Hexagon::LDrib_GP_cdnPt_V4 :
613    case Hexagon::LDrib_GP_cdnNotPt_V4 :
614    case Hexagon::LDriub_GP_cPt_V4 :
615    case Hexagon::LDriub_GP_cNotPt_V4 :
616    case Hexagon::LDriub_GP_cdnPt_V4 :
617    case Hexagon::LDriub_GP_cdnNotPt_V4 :
618    case Hexagon::LDrih_GP_cPt_V4 :
619    case Hexagon::LDrih_GP_cNotPt_V4 :
620    case Hexagon::LDrih_GP_cdnPt_V4 :
621    case Hexagon::LDrih_GP_cdnNotPt_V4 :
622    case Hexagon::LDriuh_GP_cPt_V4 :
623    case Hexagon::LDriuh_GP_cNotPt_V4 :
624    case Hexagon::LDriuh_GP_cdnPt_V4 :
625    case Hexagon::LDriuh_GP_cdnNotPt_V4 :
626    case Hexagon::LDriw_GP_cPt_V4 :
627    case Hexagon::LDriw_GP_cNotPt_V4 :
628    case Hexagon::LDriw_GP_cdnPt_V4 :
629    case Hexagon::LDriw_GP_cdnNotPt_V4 :
630    case Hexagon::LDd_GP_cPt_V4 :
631    case Hexagon::LDd_GP_cNotPt_V4 :
632    case Hexagon::LDd_GP_cdnPt_V4 :
633    case Hexagon::LDd_GP_cdnNotPt_V4 :
634    case Hexagon::LDb_GP_cPt_V4 :
635    case Hexagon::LDb_GP_cNotPt_V4 :
636    case Hexagon::LDb_GP_cdnPt_V4 :
637    case Hexagon::LDb_GP_cdnNotPt_V4 :
638    case Hexagon::LDub_GP_cPt_V4 :
639    case Hexagon::LDub_GP_cNotPt_V4 :
640    case Hexagon::LDub_GP_cdnPt_V4 :
641    case Hexagon::LDub_GP_cdnNotPt_V4 :
642    case Hexagon::LDh_GP_cPt_V4 :
643    case Hexagon::LDh_GP_cNotPt_V4 :
644    case Hexagon::LDh_GP_cdnPt_V4 :
645    case Hexagon::LDh_GP_cdnNotPt_V4 :
646    case Hexagon::LDuh_GP_cPt_V4 :
647    case Hexagon::LDuh_GP_cNotPt_V4 :
648    case Hexagon::LDuh_GP_cdnPt_V4 :
649    case Hexagon::LDuh_GP_cdnNotPt_V4 :
650    case Hexagon::LDw_GP_cPt_V4 :
651    case Hexagon::LDw_GP_cNotPt_V4 :
652    case Hexagon::LDw_GP_cdnPt_V4 :
653    case Hexagon::LDw_GP_cdnNotPt_V4 :
654
655    // V4 global address store.
656    case Hexagon::STrid_GP_cPt_V4 :
657    case Hexagon::STrid_GP_cNotPt_V4 :
658    case Hexagon::STrid_GP_cdnPt_V4 :
659    case Hexagon::STrid_GP_cdnNotPt_V4 :
660    case Hexagon::STrib_GP_cPt_V4 :
661    case Hexagon::STrib_GP_cNotPt_V4 :
662    case Hexagon::STrib_GP_cdnPt_V4 :
663    case Hexagon::STrib_GP_cdnNotPt_V4 :
664    case Hexagon::STrih_GP_cPt_V4 :
665    case Hexagon::STrih_GP_cNotPt_V4 :
666    case Hexagon::STrih_GP_cdnPt_V4 :
667    case Hexagon::STrih_GP_cdnNotPt_V4 :
668    case Hexagon::STriw_GP_cPt_V4 :
669    case Hexagon::STriw_GP_cNotPt_V4 :
670    case Hexagon::STriw_GP_cdnPt_V4 :
671    case Hexagon::STriw_GP_cdnNotPt_V4 :
672    case Hexagon::STd_GP_cPt_V4 :
673    case Hexagon::STd_GP_cNotPt_V4 :
674    case Hexagon::STd_GP_cdnPt_V4 :
675    case Hexagon::STd_GP_cdnNotPt_V4 :
676    case Hexagon::STb_GP_cPt_V4 :
677    case Hexagon::STb_GP_cNotPt_V4 :
678    case Hexagon::STb_GP_cdnPt_V4 :
679    case Hexagon::STb_GP_cdnNotPt_V4 :
680    case Hexagon::STh_GP_cPt_V4 :
681    case Hexagon::STh_GP_cNotPt_V4 :
682    case Hexagon::STh_GP_cdnPt_V4 :
683    case Hexagon::STh_GP_cdnNotPt_V4 :
684    case Hexagon::STw_GP_cPt_V4 :
685    case Hexagon::STw_GP_cNotPt_V4 :
686    case Hexagon::STw_GP_cdnPt_V4 :
687    case Hexagon::STw_GP_cdnNotPt_V4 :
688
689    // V4 predicated global address new value store.
690    case Hexagon::STrib_GP_cPt_nv_V4 :
691    case Hexagon::STrib_GP_cNotPt_nv_V4 :
692    case Hexagon::STrib_GP_cdnPt_nv_V4 :
693    case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
694    case Hexagon::STrih_GP_cPt_nv_V4 :
695    case Hexagon::STrih_GP_cNotPt_nv_V4 :
696    case Hexagon::STrih_GP_cdnPt_nv_V4 :
697    case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
698    case Hexagon::STriw_GP_cPt_nv_V4 :
699    case Hexagon::STriw_GP_cNotPt_nv_V4 :
700    case Hexagon::STriw_GP_cdnPt_nv_V4 :
701    case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
702    case Hexagon::STb_GP_cPt_nv_V4 :
703    case Hexagon::STb_GP_cNotPt_nv_V4 :
704    case Hexagon::STb_GP_cdnPt_nv_V4 :
705    case Hexagon::STb_GP_cdnNotPt_nv_V4 :
706    case Hexagon::STh_GP_cPt_nv_V4 :
707    case Hexagon::STh_GP_cNotPt_nv_V4 :
708    case Hexagon::STh_GP_cdnPt_nv_V4 :
709    case Hexagon::STh_GP_cdnNotPt_nv_V4 :
710    case Hexagon::STw_GP_cPt_nv_V4 :
711    case Hexagon::STw_GP_cNotPt_nv_V4 :
712    case Hexagon::STw_GP_cdnPt_nv_V4 :
713    case Hexagon::STw_GP_cdnNotPt_nv_V4 :
714
715    // TFR_FI
716    case Hexagon::TFR_FI_immext_V4:
717      return true;
718
719  }
720}
721
722bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
723  switch (MI->getOpcode()) {
724    default: return false;
725    // JMP_EQri
726    case Hexagon::JMP_EQriPt_nv_V4:
727    case Hexagon::JMP_EQriPnt_nv_V4:
728    case Hexagon::JMP_EQriNotPt_nv_V4:
729    case Hexagon::JMP_EQriNotPnt_nv_V4:
730    case Hexagon::JMP_EQriPt_ie_nv_V4:
731    case Hexagon::JMP_EQriPnt_ie_nv_V4:
732    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
733    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
734
735    // JMP_EQri - with -1
736    case Hexagon::JMP_EQriPtneg_nv_V4:
737    case Hexagon::JMP_EQriPntneg_nv_V4:
738    case Hexagon::JMP_EQriNotPtneg_nv_V4:
739    case Hexagon::JMP_EQriNotPntneg_nv_V4:
740    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
741    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
742    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
743    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
744
745    // JMP_EQrr
746    case Hexagon::JMP_EQrrPt_nv_V4:
747    case Hexagon::JMP_EQrrPnt_nv_V4:
748    case Hexagon::JMP_EQrrNotPt_nv_V4:
749    case Hexagon::JMP_EQrrNotPnt_nv_V4:
750    case Hexagon::JMP_EQrrPt_ie_nv_V4:
751    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
752    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
753    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
754
755    // JMP_GTri
756    case Hexagon::JMP_GTriPt_nv_V4:
757    case Hexagon::JMP_GTriPnt_nv_V4:
758    case Hexagon::JMP_GTriNotPt_nv_V4:
759    case Hexagon::JMP_GTriNotPnt_nv_V4:
760    case Hexagon::JMP_GTriPt_ie_nv_V4:
761    case Hexagon::JMP_GTriPnt_ie_nv_V4:
762    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
763    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
764
765    // JMP_GTri - with -1
766    case Hexagon::JMP_GTriPtneg_nv_V4:
767    case Hexagon::JMP_GTriPntneg_nv_V4:
768    case Hexagon::JMP_GTriNotPtneg_nv_V4:
769    case Hexagon::JMP_GTriNotPntneg_nv_V4:
770    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
771    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
772    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
773    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
774
775    // JMP_GTrr
776    case Hexagon::JMP_GTrrPt_nv_V4:
777    case Hexagon::JMP_GTrrPnt_nv_V4:
778    case Hexagon::JMP_GTrrNotPt_nv_V4:
779    case Hexagon::JMP_GTrrNotPnt_nv_V4:
780    case Hexagon::JMP_GTrrPt_ie_nv_V4:
781    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
782    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
783    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
784
785    // JMP_GTrrdn
786    case Hexagon::JMP_GTrrdnPt_nv_V4:
787    case Hexagon::JMP_GTrrdnPnt_nv_V4:
788    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
789    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
790    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
791    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
792    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
793    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
794
795    // JMP_GTUri
796    case Hexagon::JMP_GTUriPt_nv_V4:
797    case Hexagon::JMP_GTUriPnt_nv_V4:
798    case Hexagon::JMP_GTUriNotPt_nv_V4:
799    case Hexagon::JMP_GTUriNotPnt_nv_V4:
800    case Hexagon::JMP_GTUriPt_ie_nv_V4:
801    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
802    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
803    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
804
805    // JMP_GTUrr
806    case Hexagon::JMP_GTUrrPt_nv_V4:
807    case Hexagon::JMP_GTUrrPnt_nv_V4:
808    case Hexagon::JMP_GTUrrNotPt_nv_V4:
809    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
810    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
811    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
812    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
813    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
814
815    // JMP_GTUrrdn
816    case Hexagon::JMP_GTUrrdnPt_nv_V4:
817    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
818    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
819    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
820    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
821    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
822    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
823    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
824      return true;
825  }
826}
827
828unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
829  switch(MI->getOpcode()) {
830    default: llvm_unreachable("Unknown type of instruction.");
831    // JMP_EQri
832    case Hexagon::JMP_EQriPt_nv_V4:
833      return Hexagon::JMP_EQriPt_ie_nv_V4;
834    case Hexagon::JMP_EQriNotPt_nv_V4:
835      return Hexagon::JMP_EQriNotPt_ie_nv_V4;
836    case Hexagon::JMP_EQriPnt_nv_V4:
837      return Hexagon::JMP_EQriPnt_ie_nv_V4;
838    case Hexagon::JMP_EQriNotPnt_nv_V4:
839      return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
840
841    // JMP_EQri -- with -1
842    case Hexagon::JMP_EQriPtneg_nv_V4:
843      return Hexagon::JMP_EQriPtneg_ie_nv_V4;
844    case Hexagon::JMP_EQriNotPtneg_nv_V4:
845      return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
846    case Hexagon::JMP_EQriPntneg_nv_V4:
847      return Hexagon::JMP_EQriPntneg_ie_nv_V4;
848    case Hexagon::JMP_EQriNotPntneg_nv_V4:
849      return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
850
851    // JMP_EQrr
852    case Hexagon::JMP_EQrrPt_nv_V4:
853      return Hexagon::JMP_EQrrPt_ie_nv_V4;
854    case Hexagon::JMP_EQrrNotPt_nv_V4:
855      return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
856    case Hexagon::JMP_EQrrPnt_nv_V4:
857      return Hexagon::JMP_EQrrPnt_ie_nv_V4;
858    case Hexagon::JMP_EQrrNotPnt_nv_V4:
859      return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
860
861    // JMP_GTri
862    case Hexagon::JMP_GTriPt_nv_V4:
863      return Hexagon::JMP_GTriPt_ie_nv_V4;
864    case Hexagon::JMP_GTriNotPt_nv_V4:
865      return Hexagon::JMP_GTriNotPt_ie_nv_V4;
866    case Hexagon::JMP_GTriPnt_nv_V4:
867      return Hexagon::JMP_GTriPnt_ie_nv_V4;
868    case Hexagon::JMP_GTriNotPnt_nv_V4:
869      return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
870
871    // JMP_GTri -- with -1
872    case Hexagon::JMP_GTriPtneg_nv_V4:
873      return Hexagon::JMP_GTriPtneg_ie_nv_V4;
874    case Hexagon::JMP_GTriNotPtneg_nv_V4:
875      return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
876    case Hexagon::JMP_GTriPntneg_nv_V4:
877      return Hexagon::JMP_GTriPntneg_ie_nv_V4;
878    case Hexagon::JMP_GTriNotPntneg_nv_V4:
879      return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
880
881    // JMP_GTrr
882    case Hexagon::JMP_GTrrPt_nv_V4:
883      return Hexagon::JMP_GTrrPt_ie_nv_V4;
884    case Hexagon::JMP_GTrrNotPt_nv_V4:
885      return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
886    case Hexagon::JMP_GTrrPnt_nv_V4:
887      return Hexagon::JMP_GTrrPnt_ie_nv_V4;
888    case Hexagon::JMP_GTrrNotPnt_nv_V4:
889      return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
890
891    // JMP_GTrrdn
892    case Hexagon::JMP_GTrrdnPt_nv_V4:
893      return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
894    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
895      return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
896    case Hexagon::JMP_GTrrdnPnt_nv_V4:
897      return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
898    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
899      return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
900
901    // JMP_GTUri
902    case Hexagon::JMP_GTUriPt_nv_V4:
903      return Hexagon::JMP_GTUriPt_ie_nv_V4;
904    case Hexagon::JMP_GTUriNotPt_nv_V4:
905      return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
906    case Hexagon::JMP_GTUriPnt_nv_V4:
907      return Hexagon::JMP_GTUriPnt_ie_nv_V4;
908    case Hexagon::JMP_GTUriNotPnt_nv_V4:
909      return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
910
911    // JMP_GTUrr
912    case Hexagon::JMP_GTUrrPt_nv_V4:
913      return Hexagon::JMP_GTUrrPt_ie_nv_V4;
914    case Hexagon::JMP_GTUrrNotPt_nv_V4:
915      return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
916    case Hexagon::JMP_GTUrrPnt_nv_V4:
917      return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
918    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
919      return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
920
921    // JMP_GTUrrdn
922    case Hexagon::JMP_GTUrrdnPt_nv_V4:
923      return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
924    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
925      return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
926    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
927      return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
928    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
929      return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
930
931    case Hexagon::TFR_FI:
932        return Hexagon::TFR_FI_immext_V4;
933
934    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
935    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
936    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
937    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
938    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
939    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
940    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
941    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
942    case Hexagon::MEMw_ADDi_MEM_V4 :
943    case Hexagon::MEMw_SUBi_MEM_V4 :
944    case Hexagon::MEMw_ADDr_MEM_V4 :
945    case Hexagon::MEMw_SUBr_MEM_V4 :
946    case Hexagon::MEMw_ANDr_MEM_V4 :
947    case Hexagon::MEMw_ORr_MEM_V4 :
948    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
949    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
950    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
951    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
952    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
953    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
954    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
955    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
956    case Hexagon::MEMh_ADDi_MEM_V4 :
957    case Hexagon::MEMh_SUBi_MEM_V4 :
958    case Hexagon::MEMh_ADDr_MEM_V4 :
959    case Hexagon::MEMh_SUBr_MEM_V4 :
960    case Hexagon::MEMh_ANDr_MEM_V4 :
961    case Hexagon::MEMh_ORr_MEM_V4 :
962    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
963    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
964    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
965    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
966    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
967    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
968    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
969    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
970    case Hexagon::MEMb_ADDi_MEM_V4 :
971    case Hexagon::MEMb_SUBi_MEM_V4 :
972    case Hexagon::MEMb_ADDr_MEM_V4 :
973    case Hexagon::MEMb_SUBr_MEM_V4 :
974    case Hexagon::MEMb_ANDr_MEM_V4 :
975    case Hexagon::MEMb_ORr_MEM_V4 :
976      llvm_unreachable("Needs implementing.");
977  }
978}
979
980unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
981  switch(MI->getOpcode()) {
982    default: llvm_unreachable("Unknown type of jump instruction.");
983    // JMP_EQri
984    case Hexagon::JMP_EQriPt_ie_nv_V4:
985      return Hexagon::JMP_EQriPt_nv_V4;
986    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
987      return Hexagon::JMP_EQriNotPt_nv_V4;
988    case Hexagon::JMP_EQriPnt_ie_nv_V4:
989      return Hexagon::JMP_EQriPnt_nv_V4;
990    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
991      return Hexagon::JMP_EQriNotPnt_nv_V4;
992
993    // JMP_EQri -- with -1
994    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
995      return Hexagon::JMP_EQriPtneg_nv_V4;
996    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
997      return Hexagon::JMP_EQriNotPtneg_nv_V4;
998    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
999      return Hexagon::JMP_EQriPntneg_nv_V4;
1000    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1001      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1002
1003    // JMP_EQrr
1004    case Hexagon::JMP_EQrrPt_ie_nv_V4:
1005      return Hexagon::JMP_EQrrPt_nv_V4;
1006    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1007      return Hexagon::JMP_EQrrNotPt_nv_V4;
1008    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1009      return Hexagon::JMP_EQrrPnt_nv_V4;
1010    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1011      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1012
1013    // JMP_GTri
1014    case Hexagon::JMP_GTriPt_ie_nv_V4:
1015      return Hexagon::JMP_GTriPt_nv_V4;
1016    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1017      return Hexagon::JMP_GTriNotPt_nv_V4;
1018    case Hexagon::JMP_GTriPnt_ie_nv_V4:
1019      return Hexagon::JMP_GTriPnt_nv_V4;
1020    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1021      return Hexagon::JMP_GTriNotPnt_nv_V4;
1022
1023    // JMP_GTri -- with -1
1024    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1025      return Hexagon::JMP_GTriPtneg_nv_V4;
1026    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1027      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1028    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1029      return Hexagon::JMP_GTriPntneg_nv_V4;
1030    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1031      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1032
1033    // JMP_GTrr
1034    case Hexagon::JMP_GTrrPt_ie_nv_V4:
1035      return Hexagon::JMP_GTrrPt_nv_V4;
1036    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1037      return Hexagon::JMP_GTrrNotPt_nv_V4;
1038    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1039      return Hexagon::JMP_GTrrPnt_nv_V4;
1040    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1041      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1042
1043    // JMP_GTrrdn
1044    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1045      return Hexagon::JMP_GTrrdnPt_nv_V4;
1046    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1047      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1048    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1049      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1050    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1051      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1052
1053    // JMP_GTUri
1054    case Hexagon::JMP_GTUriPt_ie_nv_V4:
1055      return Hexagon::JMP_GTUriPt_nv_V4;
1056    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1057      return Hexagon::JMP_GTUriNotPt_nv_V4;
1058    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1059      return Hexagon::JMP_GTUriPnt_nv_V4;
1060    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1061      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1062
1063    // JMP_GTUrr
1064    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1065      return Hexagon::JMP_GTUrrPt_nv_V4;
1066    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1067      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1068    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1069      return Hexagon::JMP_GTUrrPnt_nv_V4;
1070    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1071      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1072
1073    // JMP_GTUrrdn
1074    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1075      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1076    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1077      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1078    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1079      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1080    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1081      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1082  }
1083}
1084
1085
1086bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1087  switch (MI->getOpcode()) {
1088    default: return false;
1089    // Store Byte
1090    case Hexagon::STrib_nv_V4:
1091    case Hexagon::STrib_indexed_nv_V4:
1092    case Hexagon::STrib_indexed_shl_nv_V4:
1093    case Hexagon::STrib_shl_nv_V4:
1094    case Hexagon::STrib_GP_nv_V4:
1095    case Hexagon::STb_GP_nv_V4:
1096    case Hexagon::POST_STbri_nv_V4:
1097    case Hexagon::STrib_cPt_nv_V4:
1098    case Hexagon::STrib_cdnPt_nv_V4:
1099    case Hexagon::STrib_cNotPt_nv_V4:
1100    case Hexagon::STrib_cdnNotPt_nv_V4:
1101    case Hexagon::STrib_indexed_cPt_nv_V4:
1102    case Hexagon::STrib_indexed_cdnPt_nv_V4:
1103    case Hexagon::STrib_indexed_cNotPt_nv_V4:
1104    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1105    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1106    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1107    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1108    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1109    case Hexagon::POST_STbri_cPt_nv_V4:
1110    case Hexagon::POST_STbri_cdnPt_nv_V4:
1111    case Hexagon::POST_STbri_cNotPt_nv_V4:
1112    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1113    case Hexagon::STb_GP_cPt_nv_V4:
1114    case Hexagon::STb_GP_cNotPt_nv_V4:
1115    case Hexagon::STb_GP_cdnPt_nv_V4:
1116    case Hexagon::STb_GP_cdnNotPt_nv_V4:
1117    case Hexagon::STrib_GP_cPt_nv_V4:
1118    case Hexagon::STrib_GP_cNotPt_nv_V4:
1119    case Hexagon::STrib_GP_cdnPt_nv_V4:
1120    case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1121    case Hexagon::STrib_abs_nv_V4:
1122    case Hexagon::STrib_abs_cPt_nv_V4:
1123    case Hexagon::STrib_abs_cdnPt_nv_V4:
1124    case Hexagon::STrib_abs_cNotPt_nv_V4:
1125    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1126    case Hexagon::STrib_imm_abs_nv_V4:
1127    case Hexagon::STrib_imm_abs_cPt_nv_V4:
1128    case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1129    case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1130    case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1131
1132    // Store Halfword
1133    case Hexagon::STrih_nv_V4:
1134    case Hexagon::STrih_indexed_nv_V4:
1135    case Hexagon::STrih_indexed_shl_nv_V4:
1136    case Hexagon::STrih_shl_nv_V4:
1137    case Hexagon::STrih_GP_nv_V4:
1138    case Hexagon::STh_GP_nv_V4:
1139    case Hexagon::POST_SThri_nv_V4:
1140    case Hexagon::STrih_cPt_nv_V4:
1141    case Hexagon::STrih_cdnPt_nv_V4:
1142    case Hexagon::STrih_cNotPt_nv_V4:
1143    case Hexagon::STrih_cdnNotPt_nv_V4:
1144    case Hexagon::STrih_indexed_cPt_nv_V4:
1145    case Hexagon::STrih_indexed_cdnPt_nv_V4:
1146    case Hexagon::STrih_indexed_cNotPt_nv_V4:
1147    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1148    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1149    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1150    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1151    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1152    case Hexagon::POST_SThri_cPt_nv_V4:
1153    case Hexagon::POST_SThri_cdnPt_nv_V4:
1154    case Hexagon::POST_SThri_cNotPt_nv_V4:
1155    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1156    case Hexagon::STh_GP_cPt_nv_V4:
1157    case Hexagon::STh_GP_cNotPt_nv_V4:
1158    case Hexagon::STh_GP_cdnPt_nv_V4:
1159    case Hexagon::STh_GP_cdnNotPt_nv_V4:
1160    case Hexagon::STrih_GP_cPt_nv_V4:
1161    case Hexagon::STrih_GP_cNotPt_nv_V4:
1162    case Hexagon::STrih_GP_cdnPt_nv_V4:
1163    case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1164    case Hexagon::STrih_abs_nv_V4:
1165    case Hexagon::STrih_abs_cPt_nv_V4:
1166    case Hexagon::STrih_abs_cdnPt_nv_V4:
1167    case Hexagon::STrih_abs_cNotPt_nv_V4:
1168    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1169    case Hexagon::STrih_imm_abs_nv_V4:
1170    case Hexagon::STrih_imm_abs_cPt_nv_V4:
1171    case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1172    case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1173    case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1174
1175    // Store Word
1176    case Hexagon::STriw_nv_V4:
1177    case Hexagon::STriw_indexed_nv_V4:
1178    case Hexagon::STriw_indexed_shl_nv_V4:
1179    case Hexagon::STriw_shl_nv_V4:
1180    case Hexagon::STriw_GP_nv_V4:
1181    case Hexagon::STw_GP_nv_V4:
1182    case Hexagon::POST_STwri_nv_V4:
1183    case Hexagon::STriw_cPt_nv_V4:
1184    case Hexagon::STriw_cdnPt_nv_V4:
1185    case Hexagon::STriw_cNotPt_nv_V4:
1186    case Hexagon::STriw_cdnNotPt_nv_V4:
1187    case Hexagon::STriw_indexed_cPt_nv_V4:
1188    case Hexagon::STriw_indexed_cdnPt_nv_V4:
1189    case Hexagon::STriw_indexed_cNotPt_nv_V4:
1190    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1191    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1192    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1193    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1194    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1195    case Hexagon::POST_STwri_cPt_nv_V4:
1196    case Hexagon::POST_STwri_cdnPt_nv_V4:
1197    case Hexagon::POST_STwri_cNotPt_nv_V4:
1198    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1199    case Hexagon::STw_GP_cPt_nv_V4:
1200    case Hexagon::STw_GP_cNotPt_nv_V4:
1201    case Hexagon::STw_GP_cdnPt_nv_V4:
1202    case Hexagon::STw_GP_cdnNotPt_nv_V4:
1203    case Hexagon::STriw_GP_cPt_nv_V4:
1204    case Hexagon::STriw_GP_cNotPt_nv_V4:
1205    case Hexagon::STriw_GP_cdnPt_nv_V4:
1206    case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1207    case Hexagon::STriw_abs_nv_V4:
1208    case Hexagon::STriw_abs_cPt_nv_V4:
1209    case Hexagon::STriw_abs_cdnPt_nv_V4:
1210    case Hexagon::STriw_abs_cNotPt_nv_V4:
1211    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1212    case Hexagon::STriw_imm_abs_nv_V4:
1213    case Hexagon::STriw_imm_abs_cPt_nv_V4:
1214    case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1215    case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1216    case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1217      return true;
1218  }
1219}
1220
1221bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1222  switch (MI->getOpcode())
1223  {
1224    default: return false;
1225    // Load Byte
1226    case Hexagon::POST_LDrib:
1227    case Hexagon::POST_LDrib_cPt:
1228    case Hexagon::POST_LDrib_cNotPt:
1229    case Hexagon::POST_LDrib_cdnPt_V4:
1230    case Hexagon::POST_LDrib_cdnNotPt_V4:
1231
1232    // Load unsigned byte
1233    case Hexagon::POST_LDriub:
1234    case Hexagon::POST_LDriub_cPt:
1235    case Hexagon::POST_LDriub_cNotPt:
1236    case Hexagon::POST_LDriub_cdnPt_V4:
1237    case Hexagon::POST_LDriub_cdnNotPt_V4:
1238
1239    // Load halfword
1240    case Hexagon::POST_LDrih:
1241    case Hexagon::POST_LDrih_cPt:
1242    case Hexagon::POST_LDrih_cNotPt:
1243    case Hexagon::POST_LDrih_cdnPt_V4:
1244    case Hexagon::POST_LDrih_cdnNotPt_V4:
1245
1246    // Load unsigned halfword
1247    case Hexagon::POST_LDriuh:
1248    case Hexagon::POST_LDriuh_cPt:
1249    case Hexagon::POST_LDriuh_cNotPt:
1250    case Hexagon::POST_LDriuh_cdnPt_V4:
1251    case Hexagon::POST_LDriuh_cdnNotPt_V4:
1252
1253    // Load word
1254    case Hexagon::POST_LDriw:
1255    case Hexagon::POST_LDriw_cPt:
1256    case Hexagon::POST_LDriw_cNotPt:
1257    case Hexagon::POST_LDriw_cdnPt_V4:
1258    case Hexagon::POST_LDriw_cdnNotPt_V4:
1259
1260    // Load double word
1261    case Hexagon::POST_LDrid:
1262    case Hexagon::POST_LDrid_cPt:
1263    case Hexagon::POST_LDrid_cNotPt:
1264    case Hexagon::POST_LDrid_cdnPt_V4:
1265    case Hexagon::POST_LDrid_cdnNotPt_V4:
1266
1267    // Store byte
1268    case Hexagon::POST_STbri:
1269    case Hexagon::POST_STbri_cPt:
1270    case Hexagon::POST_STbri_cNotPt:
1271    case Hexagon::POST_STbri_cdnPt_V4:
1272    case Hexagon::POST_STbri_cdnNotPt_V4:
1273
1274    // Store halfword
1275    case Hexagon::POST_SThri:
1276    case Hexagon::POST_SThri_cPt:
1277    case Hexagon::POST_SThri_cNotPt:
1278    case Hexagon::POST_SThri_cdnPt_V4:
1279    case Hexagon::POST_SThri_cdnNotPt_V4:
1280
1281    // Store word
1282    case Hexagon::POST_STwri:
1283    case Hexagon::POST_STwri_cPt:
1284    case Hexagon::POST_STwri_cNotPt:
1285    case Hexagon::POST_STwri_cdnPt_V4:
1286    case Hexagon::POST_STwri_cdnNotPt_V4:
1287
1288    // Store double word
1289    case Hexagon::POST_STdri:
1290    case Hexagon::POST_STdri_cPt:
1291    case Hexagon::POST_STdri_cNotPt:
1292    case Hexagon::POST_STdri_cdnPt_V4:
1293    case Hexagon::POST_STdri_cdnNotPt_V4:
1294      return true;
1295  }
1296}
1297
1298bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1299  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1300}
1301
1302bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1303  bool isPred = MI->getDesc().isPredicable();
1304
1305  if (!isPred)
1306    return false;
1307
1308  const int Opc = MI->getOpcode();
1309
1310  switch(Opc) {
1311  case Hexagon::TFRI:
1312    return isInt<12>(MI->getOperand(1).getImm());
1313
1314  case Hexagon::STrid:
1315  case Hexagon::STrid_indexed:
1316    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1317
1318  case Hexagon::STriw:
1319  case Hexagon::STriw_indexed:
1320  case Hexagon::STriw_nv_V4:
1321    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1322
1323  case Hexagon::STrih:
1324  case Hexagon::STrih_indexed:
1325  case Hexagon::STrih_nv_V4:
1326    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1327
1328  case Hexagon::STrib:
1329  case Hexagon::STrib_indexed:
1330  case Hexagon::STrib_nv_V4:
1331    return isUInt<6>(MI->getOperand(1).getImm());
1332
1333  case Hexagon::LDrid:
1334  case Hexagon::LDrid_indexed:
1335    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1336
1337  case Hexagon::LDriw:
1338  case Hexagon::LDriw_indexed:
1339    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1340
1341  case Hexagon::LDrih:
1342  case Hexagon::LDriuh:
1343  case Hexagon::LDrih_indexed:
1344  case Hexagon::LDriuh_indexed:
1345    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1346
1347  case Hexagon::LDrib:
1348  case Hexagon::LDriub:
1349  case Hexagon::LDrib_indexed:
1350  case Hexagon::LDriub_indexed:
1351    return isUInt<6>(MI->getOperand(2).getImm());
1352
1353  case Hexagon::POST_LDrid:
1354    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1355
1356  case Hexagon::POST_LDriw:
1357    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1358
1359  case Hexagon::POST_LDrih:
1360  case Hexagon::POST_LDriuh:
1361    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1362
1363  case Hexagon::POST_LDrib:
1364  case Hexagon::POST_LDriub:
1365    return isInt<4>(MI->getOperand(3).getImm());
1366
1367  case Hexagon::STrib_imm_V4:
1368  case Hexagon::STrih_imm_V4:
1369  case Hexagon::STriw_imm_V4:
1370    return (isUInt<6>(MI->getOperand(1).getImm()) &&
1371            isInt<6>(MI->getOperand(2).getImm()));
1372
1373  case Hexagon::ADD_ri:
1374    return isInt<8>(MI->getOperand(2).getImm());
1375
1376  case Hexagon::ASLH:
1377  case Hexagon::ASRH:
1378  case Hexagon::SXTB:
1379  case Hexagon::SXTH:
1380  case Hexagon::ZXTB:
1381  case Hexagon::ZXTH:
1382    return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1383
1384  case Hexagon::JMPR:
1385    return false;
1386  }
1387
1388  return true;
1389}
1390
1391unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1392  switch(Opc) {
1393    default: llvm_unreachable("Unexpected predicated instruction");
1394    case Hexagon::TFR_cPt:
1395      return Hexagon::TFR_cNotPt;
1396    case Hexagon::TFR_cNotPt:
1397      return Hexagon::TFR_cPt;
1398
1399    case Hexagon::TFRI_cPt:
1400      return Hexagon::TFRI_cNotPt;
1401    case Hexagon::TFRI_cNotPt:
1402      return Hexagon::TFRI_cPt;
1403
1404    case Hexagon::JMP_c:
1405      return Hexagon::JMP_cNot;
1406    case Hexagon::JMP_cNot:
1407      return Hexagon::JMP_c;
1408
1409    case Hexagon::ADD_ri_cPt:
1410      return Hexagon::ADD_ri_cNotPt;
1411    case Hexagon::ADD_ri_cNotPt:
1412      return Hexagon::ADD_ri_cPt;
1413
1414    case Hexagon::ADD_rr_cPt:
1415      return Hexagon::ADD_rr_cNotPt;
1416    case Hexagon::ADD_rr_cNotPt:
1417      return Hexagon::ADD_rr_cPt;
1418
1419    case Hexagon::XOR_rr_cPt:
1420      return Hexagon::XOR_rr_cNotPt;
1421    case Hexagon::XOR_rr_cNotPt:
1422      return Hexagon::XOR_rr_cPt;
1423
1424    case Hexagon::AND_rr_cPt:
1425      return Hexagon::AND_rr_cNotPt;
1426    case Hexagon::AND_rr_cNotPt:
1427      return Hexagon::AND_rr_cPt;
1428
1429    case Hexagon::OR_rr_cPt:
1430      return Hexagon::OR_rr_cNotPt;
1431    case Hexagon::OR_rr_cNotPt:
1432      return Hexagon::OR_rr_cPt;
1433
1434    case Hexagon::SUB_rr_cPt:
1435      return Hexagon::SUB_rr_cNotPt;
1436    case Hexagon::SUB_rr_cNotPt:
1437      return Hexagon::SUB_rr_cPt;
1438
1439    case Hexagon::COMBINE_rr_cPt:
1440      return Hexagon::COMBINE_rr_cNotPt;
1441    case Hexagon::COMBINE_rr_cNotPt:
1442      return Hexagon::COMBINE_rr_cPt;
1443
1444    case Hexagon::ASLH_cPt_V4:
1445      return Hexagon::ASLH_cNotPt_V4;
1446    case Hexagon::ASLH_cNotPt_V4:
1447      return Hexagon::ASLH_cPt_V4;
1448
1449    case Hexagon::ASRH_cPt_V4:
1450      return Hexagon::ASRH_cNotPt_V4;
1451    case Hexagon::ASRH_cNotPt_V4:
1452      return Hexagon::ASRH_cPt_V4;
1453
1454    case Hexagon::SXTB_cPt_V4:
1455      return Hexagon::SXTB_cNotPt_V4;
1456    case Hexagon::SXTB_cNotPt_V4:
1457      return Hexagon::SXTB_cPt_V4;
1458
1459    case Hexagon::SXTH_cPt_V4:
1460      return Hexagon::SXTH_cNotPt_V4;
1461    case Hexagon::SXTH_cNotPt_V4:
1462      return Hexagon::SXTH_cPt_V4;
1463
1464    case Hexagon::ZXTB_cPt_V4:
1465      return Hexagon::ZXTB_cNotPt_V4;
1466    case Hexagon::ZXTB_cNotPt_V4:
1467      return Hexagon::ZXTB_cPt_V4;
1468
1469    case Hexagon::ZXTH_cPt_V4:
1470      return Hexagon::ZXTH_cNotPt_V4;
1471    case Hexagon::ZXTH_cNotPt_V4:
1472      return Hexagon::ZXTH_cPt_V4;
1473
1474
1475    case Hexagon::JMPR_cPt:
1476      return Hexagon::JMPR_cNotPt;
1477    case Hexagon::JMPR_cNotPt:
1478      return Hexagon::JMPR_cPt;
1479
1480  // V4 indexed+scaled load.
1481    case Hexagon::LDrid_indexed_cPt_V4:
1482      return Hexagon::LDrid_indexed_cNotPt_V4;
1483    case Hexagon::LDrid_indexed_cNotPt_V4:
1484      return Hexagon::LDrid_indexed_cPt_V4;
1485
1486    case Hexagon::LDrid_indexed_shl_cPt_V4:
1487      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1488    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1489      return Hexagon::LDrid_indexed_shl_cPt_V4;
1490
1491    case Hexagon::LDrib_indexed_cPt_V4:
1492      return Hexagon::LDrib_indexed_cNotPt_V4;
1493    case Hexagon::LDrib_indexed_cNotPt_V4:
1494      return Hexagon::LDrib_indexed_cPt_V4;
1495
1496    case Hexagon::LDriub_indexed_cPt_V4:
1497      return Hexagon::LDriub_indexed_cNotPt_V4;
1498    case Hexagon::LDriub_indexed_cNotPt_V4:
1499      return Hexagon::LDriub_indexed_cPt_V4;
1500
1501    case Hexagon::LDrib_indexed_shl_cPt_V4:
1502      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1503    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1504      return Hexagon::LDrib_indexed_shl_cPt_V4;
1505
1506    case Hexagon::LDriub_indexed_shl_cPt_V4:
1507      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1508    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1509      return Hexagon::LDriub_indexed_shl_cPt_V4;
1510
1511    case Hexagon::LDrih_indexed_cPt_V4:
1512      return Hexagon::LDrih_indexed_cNotPt_V4;
1513    case Hexagon::LDrih_indexed_cNotPt_V4:
1514      return Hexagon::LDrih_indexed_cPt_V4;
1515
1516    case Hexagon::LDriuh_indexed_cPt_V4:
1517      return Hexagon::LDriuh_indexed_cNotPt_V4;
1518    case Hexagon::LDriuh_indexed_cNotPt_V4:
1519      return Hexagon::LDriuh_indexed_cPt_V4;
1520
1521    case Hexagon::LDrih_indexed_shl_cPt_V4:
1522      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1523    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1524      return Hexagon::LDrih_indexed_shl_cPt_V4;
1525
1526    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1527      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1528    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1529      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1530
1531    case Hexagon::LDriw_indexed_cPt_V4:
1532      return Hexagon::LDriw_indexed_cNotPt_V4;
1533    case Hexagon::LDriw_indexed_cNotPt_V4:
1534      return Hexagon::LDriw_indexed_cPt_V4;
1535
1536    case Hexagon::LDriw_indexed_shl_cPt_V4:
1537      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1538    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1539      return Hexagon::LDriw_indexed_shl_cPt_V4;
1540
1541    // Byte.
1542    case Hexagon::POST_STbri_cPt:
1543      return Hexagon::POST_STbri_cNotPt;
1544    case Hexagon::POST_STbri_cNotPt:
1545      return Hexagon::POST_STbri_cPt;
1546
1547    case Hexagon::STrib_cPt:
1548      return Hexagon::STrib_cNotPt;
1549    case Hexagon::STrib_cNotPt:
1550      return Hexagon::STrib_cPt;
1551
1552    case Hexagon::STrib_indexed_cPt:
1553      return Hexagon::STrib_indexed_cNotPt;
1554    case Hexagon::STrib_indexed_cNotPt:
1555      return Hexagon::STrib_indexed_cPt;
1556
1557    case Hexagon::STrib_imm_cPt_V4:
1558      return Hexagon::STrib_imm_cNotPt_V4;
1559    case Hexagon::STrib_imm_cNotPt_V4:
1560      return Hexagon::STrib_imm_cPt_V4;
1561
1562    case Hexagon::STrib_indexed_shl_cPt_V4:
1563      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1564    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1565      return Hexagon::STrib_indexed_shl_cPt_V4;
1566
1567  // Halfword.
1568    case Hexagon::POST_SThri_cPt:
1569      return Hexagon::POST_SThri_cNotPt;
1570    case Hexagon::POST_SThri_cNotPt:
1571      return Hexagon::POST_SThri_cPt;
1572
1573    case Hexagon::STrih_cPt:
1574      return Hexagon::STrih_cNotPt;
1575    case Hexagon::STrih_cNotPt:
1576      return Hexagon::STrih_cPt;
1577
1578    case Hexagon::STrih_indexed_cPt:
1579      return Hexagon::STrih_indexed_cNotPt;
1580    case Hexagon::STrih_indexed_cNotPt:
1581      return Hexagon::STrih_indexed_cPt;
1582
1583    case Hexagon::STrih_imm_cPt_V4:
1584      return Hexagon::STrih_imm_cNotPt_V4;
1585    case Hexagon::STrih_imm_cNotPt_V4:
1586      return Hexagon::STrih_imm_cPt_V4;
1587
1588    case Hexagon::STrih_indexed_shl_cPt_V4:
1589      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1590    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1591      return Hexagon::STrih_indexed_shl_cPt_V4;
1592
1593  // Word.
1594    case Hexagon::POST_STwri_cPt:
1595      return Hexagon::POST_STwri_cNotPt;
1596    case Hexagon::POST_STwri_cNotPt:
1597      return Hexagon::POST_STwri_cPt;
1598
1599    case Hexagon::STriw_cPt:
1600      return Hexagon::STriw_cNotPt;
1601    case Hexagon::STriw_cNotPt:
1602      return Hexagon::STriw_cPt;
1603
1604    case Hexagon::STriw_indexed_cPt:
1605      return Hexagon::STriw_indexed_cNotPt;
1606    case Hexagon::STriw_indexed_cNotPt:
1607      return Hexagon::STriw_indexed_cPt;
1608
1609    case Hexagon::STriw_indexed_shl_cPt_V4:
1610      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1611    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1612      return Hexagon::STriw_indexed_shl_cPt_V4;
1613
1614    case Hexagon::STriw_imm_cPt_V4:
1615      return Hexagon::STriw_imm_cNotPt_V4;
1616    case Hexagon::STriw_imm_cNotPt_V4:
1617      return Hexagon::STriw_imm_cPt_V4;
1618
1619  // Double word.
1620    case Hexagon::POST_STdri_cPt:
1621      return Hexagon::POST_STdri_cNotPt;
1622    case Hexagon::POST_STdri_cNotPt:
1623      return Hexagon::POST_STdri_cPt;
1624
1625    case Hexagon::STrid_cPt:
1626      return Hexagon::STrid_cNotPt;
1627    case Hexagon::STrid_cNotPt:
1628      return Hexagon::STrid_cPt;
1629
1630    case Hexagon::STrid_indexed_cPt:
1631      return Hexagon::STrid_indexed_cNotPt;
1632    case Hexagon::STrid_indexed_cNotPt:
1633      return Hexagon::STrid_indexed_cPt;
1634
1635    case Hexagon::STrid_indexed_shl_cPt_V4:
1636      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1637    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1638      return Hexagon::STrid_indexed_shl_cPt_V4;
1639
1640    // V4 Store to global address.
1641    case Hexagon::STd_GP_cPt_V4:
1642      return Hexagon::STd_GP_cNotPt_V4;
1643    case Hexagon::STd_GP_cNotPt_V4:
1644      return Hexagon::STd_GP_cPt_V4;
1645
1646    case Hexagon::STb_GP_cPt_V4:
1647      return Hexagon::STb_GP_cNotPt_V4;
1648    case Hexagon::STb_GP_cNotPt_V4:
1649      return Hexagon::STb_GP_cPt_V4;
1650
1651    case Hexagon::STh_GP_cPt_V4:
1652      return Hexagon::STh_GP_cNotPt_V4;
1653    case Hexagon::STh_GP_cNotPt_V4:
1654      return Hexagon::STh_GP_cPt_V4;
1655
1656    case Hexagon::STw_GP_cPt_V4:
1657      return Hexagon::STw_GP_cNotPt_V4;
1658    case Hexagon::STw_GP_cNotPt_V4:
1659      return Hexagon::STw_GP_cPt_V4;
1660
1661    case Hexagon::STrid_GP_cPt_V4:
1662      return Hexagon::STrid_GP_cNotPt_V4;
1663    case Hexagon::STrid_GP_cNotPt_V4:
1664      return Hexagon::STrid_GP_cPt_V4;
1665
1666    case Hexagon::STrib_GP_cPt_V4:
1667      return Hexagon::STrib_GP_cNotPt_V4;
1668    case Hexagon::STrib_GP_cNotPt_V4:
1669      return Hexagon::STrib_GP_cPt_V4;
1670
1671    case Hexagon::STrih_GP_cPt_V4:
1672      return Hexagon::STrih_GP_cNotPt_V4;
1673    case Hexagon::STrih_GP_cNotPt_V4:
1674      return Hexagon::STrih_GP_cPt_V4;
1675
1676    case Hexagon::STriw_GP_cPt_V4:
1677      return Hexagon::STriw_GP_cNotPt_V4;
1678    case Hexagon::STriw_GP_cNotPt_V4:
1679      return Hexagon::STriw_GP_cPt_V4;
1680
1681  // Load.
1682    case Hexagon::LDrid_cPt:
1683      return Hexagon::LDrid_cNotPt;
1684    case Hexagon::LDrid_cNotPt:
1685      return Hexagon::LDrid_cPt;
1686
1687    case Hexagon::LDriw_cPt:
1688      return Hexagon::LDriw_cNotPt;
1689    case Hexagon::LDriw_cNotPt:
1690      return Hexagon::LDriw_cPt;
1691
1692    case Hexagon::LDrih_cPt:
1693      return Hexagon::LDrih_cNotPt;
1694    case Hexagon::LDrih_cNotPt:
1695      return Hexagon::LDrih_cPt;
1696
1697    case Hexagon::LDriuh_cPt:
1698      return Hexagon::LDriuh_cNotPt;
1699    case Hexagon::LDriuh_cNotPt:
1700      return Hexagon::LDriuh_cPt;
1701
1702    case Hexagon::LDrib_cPt:
1703      return Hexagon::LDrib_cNotPt;
1704    case Hexagon::LDrib_cNotPt:
1705      return Hexagon::LDrib_cPt;
1706
1707    case Hexagon::LDriub_cPt:
1708      return Hexagon::LDriub_cNotPt;
1709    case Hexagon::LDriub_cNotPt:
1710      return Hexagon::LDriub_cPt;
1711
1712 // Load Indexed.
1713    case Hexagon::LDrid_indexed_cPt:
1714      return Hexagon::LDrid_indexed_cNotPt;
1715    case Hexagon::LDrid_indexed_cNotPt:
1716      return Hexagon::LDrid_indexed_cPt;
1717
1718    case Hexagon::LDriw_indexed_cPt:
1719      return Hexagon::LDriw_indexed_cNotPt;
1720    case Hexagon::LDriw_indexed_cNotPt:
1721      return Hexagon::LDriw_indexed_cPt;
1722
1723    case Hexagon::LDrih_indexed_cPt:
1724      return Hexagon::LDrih_indexed_cNotPt;
1725    case Hexagon::LDrih_indexed_cNotPt:
1726      return Hexagon::LDrih_indexed_cPt;
1727
1728    case Hexagon::LDriuh_indexed_cPt:
1729      return Hexagon::LDriuh_indexed_cNotPt;
1730    case Hexagon::LDriuh_indexed_cNotPt:
1731      return Hexagon::LDriuh_indexed_cPt;
1732
1733    case Hexagon::LDrib_indexed_cPt:
1734      return Hexagon::LDrib_indexed_cNotPt;
1735    case Hexagon::LDrib_indexed_cNotPt:
1736      return Hexagon::LDrib_indexed_cPt;
1737
1738    case Hexagon::LDriub_indexed_cPt:
1739      return Hexagon::LDriub_indexed_cNotPt;
1740    case Hexagon::LDriub_indexed_cNotPt:
1741      return Hexagon::LDriub_indexed_cPt;
1742
1743  // Post Inc Load.
1744    case Hexagon::POST_LDrid_cPt:
1745      return Hexagon::POST_LDrid_cNotPt;
1746    case Hexagon::POST_LDriw_cNotPt:
1747      return Hexagon::POST_LDriw_cPt;
1748
1749    case Hexagon::POST_LDrih_cPt:
1750      return Hexagon::POST_LDrih_cNotPt;
1751    case Hexagon::POST_LDrih_cNotPt:
1752      return Hexagon::POST_LDrih_cPt;
1753
1754    case Hexagon::POST_LDriuh_cPt:
1755      return Hexagon::POST_LDriuh_cNotPt;
1756    case Hexagon::POST_LDriuh_cNotPt:
1757      return Hexagon::POST_LDriuh_cPt;
1758
1759    case Hexagon::POST_LDrib_cPt:
1760      return Hexagon::POST_LDrib_cNotPt;
1761    case Hexagon::POST_LDrib_cNotPt:
1762      return Hexagon::POST_LDrib_cPt;
1763
1764    case Hexagon::POST_LDriub_cPt:
1765      return Hexagon::POST_LDriub_cNotPt;
1766    case Hexagon::POST_LDriub_cNotPt:
1767      return Hexagon::POST_LDriub_cPt;
1768
1769  // Dealloc_return.
1770    case Hexagon::DEALLOC_RET_cPt_V4:
1771      return Hexagon::DEALLOC_RET_cNotPt_V4;
1772    case Hexagon::DEALLOC_RET_cNotPt_V4:
1773      return Hexagon::DEALLOC_RET_cPt_V4;
1774
1775   // New Value Jump.
1776   // JMPEQ_ri - with -1.
1777    case Hexagon::JMP_EQriPtneg_nv_V4:
1778      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1779    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1780      return Hexagon::JMP_EQriPtneg_nv_V4;
1781
1782    case Hexagon::JMP_EQriPntneg_nv_V4:
1783      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1784    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1785      return Hexagon::JMP_EQriPntneg_nv_V4;
1786
1787   // JMPEQ_ri.
1788     case Hexagon::JMP_EQriPt_nv_V4:
1789      return Hexagon::JMP_EQriNotPt_nv_V4;
1790    case Hexagon::JMP_EQriNotPt_nv_V4:
1791      return Hexagon::JMP_EQriPt_nv_V4;
1792
1793     case Hexagon::JMP_EQriPnt_nv_V4:
1794      return Hexagon::JMP_EQriNotPnt_nv_V4;
1795    case Hexagon::JMP_EQriNotPnt_nv_V4:
1796      return Hexagon::JMP_EQriPnt_nv_V4;
1797
1798   // JMPEQ_rr.
1799     case Hexagon::JMP_EQrrPt_nv_V4:
1800      return Hexagon::JMP_EQrrNotPt_nv_V4;
1801    case Hexagon::JMP_EQrrNotPt_nv_V4:
1802      return Hexagon::JMP_EQrrPt_nv_V4;
1803
1804     case Hexagon::JMP_EQrrPnt_nv_V4:
1805      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1806    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1807      return Hexagon::JMP_EQrrPnt_nv_V4;
1808
1809   // JMPGT_ri - with -1.
1810    case Hexagon::JMP_GTriPtneg_nv_V4:
1811      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1812    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1813      return Hexagon::JMP_GTriPtneg_nv_V4;
1814
1815    case Hexagon::JMP_GTriPntneg_nv_V4:
1816      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1817    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1818      return Hexagon::JMP_GTriPntneg_nv_V4;
1819
1820   // JMPGT_ri.
1821     case Hexagon::JMP_GTriPt_nv_V4:
1822      return Hexagon::JMP_GTriNotPt_nv_V4;
1823    case Hexagon::JMP_GTriNotPt_nv_V4:
1824      return Hexagon::JMP_GTriPt_nv_V4;
1825
1826     case Hexagon::JMP_GTriPnt_nv_V4:
1827      return Hexagon::JMP_GTriNotPnt_nv_V4;
1828    case Hexagon::JMP_GTriNotPnt_nv_V4:
1829      return Hexagon::JMP_GTriPnt_nv_V4;
1830
1831   // JMPGT_rr.
1832     case Hexagon::JMP_GTrrPt_nv_V4:
1833      return Hexagon::JMP_GTrrNotPt_nv_V4;
1834    case Hexagon::JMP_GTrrNotPt_nv_V4:
1835      return Hexagon::JMP_GTrrPt_nv_V4;
1836
1837     case Hexagon::JMP_GTrrPnt_nv_V4:
1838      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1839    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1840      return Hexagon::JMP_GTrrPnt_nv_V4;
1841
1842   // JMPGT_rrdn.
1843     case Hexagon::JMP_GTrrdnPt_nv_V4:
1844      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1845    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1846      return Hexagon::JMP_GTrrdnPt_nv_V4;
1847
1848     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1849      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1850    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1851      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1852
1853   // JMPGTU_ri.
1854     case Hexagon::JMP_GTUriPt_nv_V4:
1855      return Hexagon::JMP_GTUriNotPt_nv_V4;
1856    case Hexagon::JMP_GTUriNotPt_nv_V4:
1857      return Hexagon::JMP_GTUriPt_nv_V4;
1858
1859     case Hexagon::JMP_GTUriPnt_nv_V4:
1860      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1861    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1862      return Hexagon::JMP_GTUriPnt_nv_V4;
1863
1864   // JMPGTU_rr.
1865     case Hexagon::JMP_GTUrrPt_nv_V4:
1866      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1867    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1868      return Hexagon::JMP_GTUrrPt_nv_V4;
1869
1870     case Hexagon::JMP_GTUrrPnt_nv_V4:
1871      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1872    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1873      return Hexagon::JMP_GTUrrPnt_nv_V4;
1874
1875   // JMPGTU_rrdn.
1876     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1877      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1878    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1879      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1880
1881     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1882      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1883    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1884      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1885  }
1886}
1887
1888
1889int HexagonInstrInfo::
1890getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1891  switch(Opc) {
1892  case Hexagon::TFR:
1893    return !invertPredicate ? Hexagon::TFR_cPt :
1894                              Hexagon::TFR_cNotPt;
1895  case Hexagon::TFRI:
1896    return !invertPredicate ? Hexagon::TFRI_cPt :
1897                              Hexagon::TFRI_cNotPt;
1898  case Hexagon::JMP:
1899    return !invertPredicate ? Hexagon::JMP_c :
1900                              Hexagon::JMP_cNot;
1901  case Hexagon::ADD_ri:
1902    return !invertPredicate ? Hexagon::ADD_ri_cPt :
1903                              Hexagon::ADD_ri_cNotPt;
1904  case Hexagon::ADD_rr:
1905    return !invertPredicate ? Hexagon::ADD_rr_cPt :
1906                              Hexagon::ADD_rr_cNotPt;
1907  case Hexagon::XOR_rr:
1908    return !invertPredicate ? Hexagon::XOR_rr_cPt :
1909                              Hexagon::XOR_rr_cNotPt;
1910  case Hexagon::AND_rr:
1911    return !invertPredicate ? Hexagon::AND_rr_cPt :
1912                              Hexagon::AND_rr_cNotPt;
1913  case Hexagon::OR_rr:
1914    return !invertPredicate ? Hexagon::OR_rr_cPt :
1915                              Hexagon::OR_rr_cNotPt;
1916  case Hexagon::SUB_rr:
1917    return !invertPredicate ? Hexagon::SUB_rr_cPt :
1918                              Hexagon::SUB_rr_cNotPt;
1919  case Hexagon::COMBINE_rr:
1920    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1921                              Hexagon::COMBINE_rr_cNotPt;
1922  case Hexagon::ASLH:
1923    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1924                              Hexagon::ASLH_cNotPt_V4;
1925  case Hexagon::ASRH:
1926    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1927                              Hexagon::ASRH_cNotPt_V4;
1928  case Hexagon::SXTB:
1929    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1930                              Hexagon::SXTB_cNotPt_V4;
1931  case Hexagon::SXTH:
1932    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1933                              Hexagon::SXTH_cNotPt_V4;
1934  case Hexagon::ZXTB:
1935    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1936                              Hexagon::ZXTB_cNotPt_V4;
1937  case Hexagon::ZXTH:
1938    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1939                              Hexagon::ZXTH_cNotPt_V4;
1940
1941  case Hexagon::JMPR:
1942    return !invertPredicate ? Hexagon::JMPR_cPt :
1943                              Hexagon::JMPR_cNotPt;
1944
1945  // V4 indexed+scaled load.
1946  case Hexagon::LDrid_indexed_V4:
1947    return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1948                              Hexagon::LDrid_indexed_cNotPt_V4;
1949  case Hexagon::LDrid_indexed_shl_V4:
1950    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1951                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1952  case Hexagon::LDrib_indexed_V4:
1953    return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1954                              Hexagon::LDrib_indexed_cNotPt_V4;
1955  case Hexagon::LDriub_indexed_V4:
1956    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1957                              Hexagon::LDriub_indexed_cNotPt_V4;
1958  case Hexagon::LDriub_ae_indexed_V4:
1959    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1960                              Hexagon::LDriub_indexed_cNotPt_V4;
1961  case Hexagon::LDrib_indexed_shl_V4:
1962    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1963                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1964  case Hexagon::LDriub_indexed_shl_V4:
1965    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1966                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1967  case Hexagon::LDriub_ae_indexed_shl_V4:
1968    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1969                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1970  case Hexagon::LDrih_indexed_V4:
1971    return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1972                              Hexagon::LDrih_indexed_cNotPt_V4;
1973  case Hexagon::LDriuh_indexed_V4:
1974    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1975                              Hexagon::LDriuh_indexed_cNotPt_V4;
1976  case Hexagon::LDriuh_ae_indexed_V4:
1977    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1978                              Hexagon::LDriuh_indexed_cNotPt_V4;
1979  case Hexagon::LDrih_indexed_shl_V4:
1980    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1981                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1982  case Hexagon::LDriuh_indexed_shl_V4:
1983    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1984                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1985  case Hexagon::LDriuh_ae_indexed_shl_V4:
1986    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1987                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1988  case Hexagon::LDriw_indexed_V4:
1989    return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1990                              Hexagon::LDriw_indexed_cNotPt_V4;
1991  case Hexagon::LDriw_indexed_shl_V4:
1992    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1993                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1994
1995  // V4 Load from global address
1996  case Hexagon::LDrid_GP_V4:
1997    return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 :
1998                              Hexagon::LDrid_GP_cNotPt_V4;
1999  case Hexagon::LDrib_GP_V4:
2000    return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 :
2001                              Hexagon::LDrib_GP_cNotPt_V4;
2002  case Hexagon::LDriub_GP_V4:
2003    return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 :
2004                              Hexagon::LDriub_GP_cNotPt_V4;
2005  case Hexagon::LDrih_GP_V4:
2006    return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 :
2007                              Hexagon::LDrih_GP_cNotPt_V4;
2008  case Hexagon::LDriuh_GP_V4:
2009    return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 :
2010                              Hexagon::LDriuh_GP_cNotPt_V4;
2011  case Hexagon::LDriw_GP_V4:
2012    return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 :
2013                              Hexagon::LDriw_GP_cNotPt_V4;
2014
2015  case Hexagon::LDd_GP_V4:
2016    return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
2017                              Hexagon::LDd_GP_cNotPt_V4;
2018  case Hexagon::LDb_GP_V4:
2019    return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
2020                              Hexagon::LDb_GP_cNotPt_V4;
2021  case Hexagon::LDub_GP_V4:
2022    return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
2023                              Hexagon::LDub_GP_cNotPt_V4;
2024  case Hexagon::LDh_GP_V4:
2025    return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
2026                              Hexagon::LDh_GP_cNotPt_V4;
2027  case Hexagon::LDuh_GP_V4:
2028    return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
2029                              Hexagon::LDuh_GP_cNotPt_V4;
2030  case Hexagon::LDw_GP_V4:
2031    return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
2032                              Hexagon::LDw_GP_cNotPt_V4;
2033
2034    // Byte.
2035  case Hexagon::POST_STbri:
2036    return !invertPredicate ? Hexagon::POST_STbri_cPt :
2037                              Hexagon::POST_STbri_cNotPt;
2038  case Hexagon::STrib:
2039    return !invertPredicate ? Hexagon::STrib_cPt :
2040                              Hexagon::STrib_cNotPt;
2041  case Hexagon::STrib_indexed:
2042    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
2043                              Hexagon::STrib_indexed_cNotPt;
2044  case Hexagon::STrib_imm_V4:
2045    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
2046                              Hexagon::STrib_imm_cNotPt_V4;
2047  case Hexagon::STrib_indexed_shl_V4:
2048    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2049                              Hexagon::STrib_indexed_shl_cNotPt_V4;
2050  // Halfword.
2051  case Hexagon::POST_SThri:
2052    return !invertPredicate ? Hexagon::POST_SThri_cPt :
2053                              Hexagon::POST_SThri_cNotPt;
2054  case Hexagon::STrih:
2055    return !invertPredicate ? Hexagon::STrih_cPt :
2056                              Hexagon::STrih_cNotPt;
2057  case Hexagon::STrih_indexed:
2058    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2059                              Hexagon::STrih_indexed_cNotPt;
2060  case Hexagon::STrih_imm_V4:
2061    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2062                              Hexagon::STrih_imm_cNotPt_V4;
2063  case Hexagon::STrih_indexed_shl_V4:
2064    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2065                              Hexagon::STrih_indexed_shl_cNotPt_V4;
2066  // Word.
2067  case Hexagon::POST_STwri:
2068    return !invertPredicate ? Hexagon::POST_STwri_cPt :
2069                              Hexagon::POST_STwri_cNotPt;
2070  case Hexagon::STriw:
2071    return !invertPredicate ? Hexagon::STriw_cPt :
2072                              Hexagon::STriw_cNotPt;
2073  case Hexagon::STriw_indexed:
2074    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2075                              Hexagon::STriw_indexed_cNotPt;
2076  case Hexagon::STriw_indexed_shl_V4:
2077    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2078                              Hexagon::STriw_indexed_shl_cNotPt_V4;
2079  case Hexagon::STriw_imm_V4:
2080    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2081                              Hexagon::STriw_imm_cNotPt_V4;
2082  // Double word.
2083  case Hexagon::POST_STdri:
2084    return !invertPredicate ? Hexagon::POST_STdri_cPt :
2085                              Hexagon::POST_STdri_cNotPt;
2086  case Hexagon::STrid:
2087    return !invertPredicate ? Hexagon::STrid_cPt :
2088                              Hexagon::STrid_cNotPt;
2089  case Hexagon::STrid_indexed:
2090    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2091                              Hexagon::STrid_indexed_cNotPt;
2092  case Hexagon::STrid_indexed_shl_V4:
2093    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2094                              Hexagon::STrid_indexed_shl_cNotPt_V4;
2095
2096  // V4 Store to global address
2097  case Hexagon::STrid_GP_V4:
2098    return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 :
2099                              Hexagon::STrid_GP_cNotPt_V4;
2100  case Hexagon::STrib_GP_V4:
2101    return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 :
2102                              Hexagon::STrib_GP_cNotPt_V4;
2103  case Hexagon::STrih_GP_V4:
2104    return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 :
2105                              Hexagon::STrih_GP_cNotPt_V4;
2106  case Hexagon::STriw_GP_V4:
2107    return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 :
2108                              Hexagon::STriw_GP_cNotPt_V4;
2109
2110  case Hexagon::STd_GP_V4:
2111    return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
2112                              Hexagon::STd_GP_cNotPt_V4;
2113  case Hexagon::STb_GP_V4:
2114    return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
2115                              Hexagon::STb_GP_cNotPt_V4;
2116  case Hexagon::STh_GP_V4:
2117    return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
2118                              Hexagon::STh_GP_cNotPt_V4;
2119  case Hexagon::STw_GP_V4:
2120    return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
2121                              Hexagon::STw_GP_cNotPt_V4;
2122
2123  // Load.
2124  case Hexagon::LDrid:
2125    return !invertPredicate ? Hexagon::LDrid_cPt :
2126                              Hexagon::LDrid_cNotPt;
2127  case Hexagon::LDriw:
2128    return !invertPredicate ? Hexagon::LDriw_cPt :
2129                              Hexagon::LDriw_cNotPt;
2130  case Hexagon::LDrih:
2131    return !invertPredicate ? Hexagon::LDrih_cPt :
2132                              Hexagon::LDrih_cNotPt;
2133  case Hexagon::LDriuh:
2134    return !invertPredicate ? Hexagon::LDriuh_cPt :
2135                              Hexagon::LDriuh_cNotPt;
2136  case Hexagon::LDrib:
2137    return !invertPredicate ? Hexagon::LDrib_cPt :
2138                              Hexagon::LDrib_cNotPt;
2139  case Hexagon::LDriub:
2140    return !invertPredicate ? Hexagon::LDriub_cPt :
2141                              Hexagon::LDriub_cNotPt;
2142 // Load Indexed.
2143  case Hexagon::LDrid_indexed:
2144    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2145                              Hexagon::LDrid_indexed_cNotPt;
2146  case Hexagon::LDriw_indexed:
2147    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2148                              Hexagon::LDriw_indexed_cNotPt;
2149  case Hexagon::LDrih_indexed:
2150    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2151                              Hexagon::LDrih_indexed_cNotPt;
2152  case Hexagon::LDriuh_indexed:
2153    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2154                              Hexagon::LDriuh_indexed_cNotPt;
2155  case Hexagon::LDrib_indexed:
2156    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2157                              Hexagon::LDrib_indexed_cNotPt;
2158  case Hexagon::LDriub_indexed:
2159    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2160                              Hexagon::LDriub_indexed_cNotPt;
2161  // Post Increment Load.
2162  case Hexagon::POST_LDrid:
2163    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2164                              Hexagon::POST_LDrid_cNotPt;
2165  case Hexagon::POST_LDriw:
2166    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2167                              Hexagon::POST_LDriw_cNotPt;
2168  case Hexagon::POST_LDrih:
2169    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2170                              Hexagon::POST_LDrih_cNotPt;
2171  case Hexagon::POST_LDriuh:
2172    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2173                              Hexagon::POST_LDriuh_cNotPt;
2174  case Hexagon::POST_LDrib:
2175    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2176                              Hexagon::POST_LDrib_cNotPt;
2177  case Hexagon::POST_LDriub:
2178    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2179                              Hexagon::POST_LDriub_cNotPt;
2180  // DEALLOC_RETURN.
2181  case Hexagon::DEALLOC_RET_V4:
2182    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2183                              Hexagon::DEALLOC_RET_cNotPt_V4;
2184  }
2185  llvm_unreachable("Unexpected predicable instruction");
2186}
2187
2188
2189bool HexagonInstrInfo::
2190PredicateInstruction(MachineInstr *MI,
2191                     const SmallVectorImpl<MachineOperand> &Cond) const {
2192  int Opc = MI->getOpcode();
2193  assert (isPredicable(MI) && "Expected predicable instruction");
2194  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2195                     (Cond[0].getImm() == 0));
2196  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2197  //
2198  // This assumes that the predicate is always the first operand
2199  // in the set of inputs.
2200  //
2201  MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2202  int oper;
2203  for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2204    MachineOperand MO = MI->getOperand(oper);
2205    if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2206      break;
2207    }
2208
2209    if (MO.isReg()) {
2210      MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2211                                              MO.isImplicit(), MO.isKill(),
2212                                              MO.isDead(), MO.isUndef(),
2213                                              MO.isDebug());
2214    } else if (MO.isImm()) {
2215      MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2216    } else {
2217      llvm_unreachable("Unexpected operand type");
2218    }
2219  }
2220
2221  int regPos = invertJump ? 1 : 0;
2222  MachineOperand PredMO = Cond[regPos];
2223  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2224                                          PredMO.isImplicit(), PredMO.isKill(),
2225                                          PredMO.isDead(), PredMO.isUndef(),
2226                                          PredMO.isDebug());
2227
2228  return true;
2229}
2230
2231
2232bool
2233HexagonInstrInfo::
2234isProfitableToIfCvt(MachineBasicBlock &MBB,
2235                    unsigned NumCyles,
2236                    unsigned ExtraPredCycles,
2237                    const BranchProbability &Probability) const {
2238  return true;
2239}
2240
2241
2242bool
2243HexagonInstrInfo::
2244isProfitableToIfCvt(MachineBasicBlock &TMBB,
2245                    unsigned NumTCycles,
2246                    unsigned ExtraTCycles,
2247                    MachineBasicBlock &FMBB,
2248                    unsigned NumFCycles,
2249                    unsigned ExtraFCycles,
2250                    const BranchProbability &Probability) const {
2251  return true;
2252}
2253
2254
2255bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2256  const uint64_t F = MI->getDesc().TSFlags;
2257
2258  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2259}
2260
2261bool
2262HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2263                                   std::vector<MachineOperand> &Pred) const {
2264  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2265    MachineOperand MO = MI->getOperand(oper);
2266    if (MO.isReg() && MO.isDef()) {
2267      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2268      if (RC == &Hexagon::PredRegsRegClass) {
2269        Pred.push_back(MO);
2270        return true;
2271      }
2272    }
2273  }
2274  return false;
2275}
2276
2277
2278bool
2279HexagonInstrInfo::
2280SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2281                  const SmallVectorImpl<MachineOperand> &Pred2) const {
2282  // TODO: Fix this
2283  return false;
2284}
2285
2286
2287//
2288// We indicate that we want to reverse the branch by
2289// inserting a 0 at the beginning of the Cond vector.
2290//
2291bool HexagonInstrInfo::
2292ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2293  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2294    Cond.erase(Cond.begin());
2295  } else {
2296    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2297  }
2298  return false;
2299}
2300
2301
2302bool HexagonInstrInfo::
2303isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2304                          const BranchProbability &Probability) const {
2305  return (NumInstrs <= 4);
2306}
2307
2308bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2309  switch (MI->getOpcode()) {
2310  default: return false;
2311  case Hexagon::DEALLOC_RET_V4 :
2312  case Hexagon::DEALLOC_RET_cPt_V4 :
2313  case Hexagon::DEALLOC_RET_cNotPt_V4 :
2314  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2315  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2316  case Hexagon::DEALLOC_RET_cdnPt_V4 :
2317  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2318   return true;
2319  }
2320}
2321
2322
2323bool HexagonInstrInfo::
2324isValidOffset(const int Opcode, const int Offset) const {
2325  // This function is to check whether the "Offset" is in the correct range of
2326  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2327  // inserted to calculate the final address. Due to this reason, the function
2328  // assumes that the "Offset" has correct alignment.
2329
2330  switch(Opcode) {
2331
2332  case Hexagon::LDriw:
2333  case Hexagon::STriw:
2334    assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2335    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2336      (Offset <= Hexagon_MEMW_OFFSET_MAX);
2337
2338  case Hexagon::LDrid:
2339  case Hexagon::STrid:
2340    assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2341    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2342      (Offset <= Hexagon_MEMD_OFFSET_MAX);
2343
2344  case Hexagon::LDrih:
2345  case Hexagon::LDriuh:
2346  case Hexagon::STrih:
2347    assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2348    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2349      (Offset <= Hexagon_MEMH_OFFSET_MAX);
2350
2351  case Hexagon::LDrib:
2352  case Hexagon::STrib:
2353  case Hexagon::LDriub:
2354    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2355      (Offset <= Hexagon_MEMB_OFFSET_MAX);
2356
2357  case Hexagon::ADD_ri:
2358  case Hexagon::TFR_FI:
2359    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2360      (Offset <= Hexagon_ADDI_OFFSET_MAX);
2361
2362  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2363  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2364  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2365  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2366  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2367  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2368  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2369  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2370  case Hexagon::MEMw_ADDi_MEM_V4 :
2371  case Hexagon::MEMw_SUBi_MEM_V4 :
2372  case Hexagon::MEMw_ADDr_MEM_V4 :
2373  case Hexagon::MEMw_SUBr_MEM_V4 :
2374  case Hexagon::MEMw_ANDr_MEM_V4 :
2375  case Hexagon::MEMw_ORr_MEM_V4 :
2376    assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2377    return (0 <= Offset && Offset <= 255);
2378
2379  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2380  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2381  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2382  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2383  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2384  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2385  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2386  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2387  case Hexagon::MEMh_ADDi_MEM_V4 :
2388  case Hexagon::MEMh_SUBi_MEM_V4 :
2389  case Hexagon::MEMh_ADDr_MEM_V4 :
2390  case Hexagon::MEMh_SUBr_MEM_V4 :
2391  case Hexagon::MEMh_ANDr_MEM_V4 :
2392  case Hexagon::MEMh_ORr_MEM_V4 :
2393    assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2394    return (0 <= Offset && Offset <= 127);
2395
2396  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2397  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2398  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2399  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2400  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2401  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2402  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2403  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2404  case Hexagon::MEMb_ADDi_MEM_V4 :
2405  case Hexagon::MEMb_SUBi_MEM_V4 :
2406  case Hexagon::MEMb_ADDr_MEM_V4 :
2407  case Hexagon::MEMb_SUBr_MEM_V4 :
2408  case Hexagon::MEMb_ANDr_MEM_V4 :
2409  case Hexagon::MEMb_ORr_MEM_V4 :
2410    return (0 <= Offset && Offset <= 63);
2411
2412  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2413  // any size. Later pass knows how to handle it.
2414  case Hexagon::STriw_pred:
2415  case Hexagon::LDriw_pred:
2416    return true;
2417
2418  // INLINEASM is very special.
2419  case Hexagon::INLINEASM:
2420    return true;
2421  }
2422
2423  llvm_unreachable("No offset range is defined for this opcode. "
2424                   "Please define it in the above switch statement!");
2425}
2426
2427
2428//
2429// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2430//
2431bool HexagonInstrInfo::
2432isValidAutoIncImm(const EVT VT, const int Offset) const {
2433
2434  if (VT == MVT::i64) {
2435      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2436              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2437              (Offset & 0x7) == 0);
2438  }
2439  if (VT == MVT::i32) {
2440      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2441              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2442              (Offset & 0x3) == 0);
2443  }
2444  if (VT == MVT::i16) {
2445      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2446              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2447              (Offset & 0x1) == 0);
2448  }
2449  if (VT == MVT::i8) {
2450      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2451              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2452  }
2453  llvm_unreachable("Not an auto-inc opc!");
2454}
2455
2456
2457bool HexagonInstrInfo::
2458isMemOp(const MachineInstr *MI) const {
2459  switch (MI->getOpcode())
2460  {
2461    default: return false;
2462    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2463    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2464    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2465    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2466    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2467    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2468    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2469    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2470    case Hexagon::MEMw_ADDi_MEM_V4 :
2471    case Hexagon::MEMw_SUBi_MEM_V4 :
2472    case Hexagon::MEMw_ADDr_MEM_V4 :
2473    case Hexagon::MEMw_SUBr_MEM_V4 :
2474    case Hexagon::MEMw_ANDr_MEM_V4 :
2475    case Hexagon::MEMw_ORr_MEM_V4 :
2476    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2477    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2478    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2479    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2480    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2481    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2482    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2483    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2484    case Hexagon::MEMh_ADDi_MEM_V4 :
2485    case Hexagon::MEMh_SUBi_MEM_V4 :
2486    case Hexagon::MEMh_ADDr_MEM_V4 :
2487    case Hexagon::MEMh_SUBr_MEM_V4 :
2488    case Hexagon::MEMh_ANDr_MEM_V4 :
2489    case Hexagon::MEMh_ORr_MEM_V4 :
2490    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2491    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2492    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2493    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2494    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2495    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2496    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2497    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2498    case Hexagon::MEMb_ADDi_MEM_V4 :
2499    case Hexagon::MEMb_SUBi_MEM_V4 :
2500    case Hexagon::MEMb_ADDr_MEM_V4 :
2501    case Hexagon::MEMb_SUBr_MEM_V4 :
2502    case Hexagon::MEMb_ANDr_MEM_V4 :
2503    case Hexagon::MEMb_ORr_MEM_V4 :
2504      return true;
2505  }
2506}
2507
2508
2509bool HexagonInstrInfo::
2510isSpillPredRegOp(const MachineInstr *MI) const {
2511  switch (MI->getOpcode()) {
2512    default: return false;
2513    case Hexagon::STriw_pred :
2514    case Hexagon::LDriw_pred :
2515      return true;
2516  }
2517  return false;
2518}
2519
2520bool HexagonInstrInfo::
2521isConditionalTransfer (const MachineInstr *MI) const {
2522  switch (MI->getOpcode()) {
2523    default: return false;
2524    case Hexagon::TFR_cPt:
2525    case Hexagon::TFR_cNotPt:
2526    case Hexagon::TFRI_cPt:
2527    case Hexagon::TFRI_cNotPt:
2528    case Hexagon::TFR_cdnPt:
2529    case Hexagon::TFR_cdnNotPt:
2530    case Hexagon::TFRI_cdnPt:
2531    case Hexagon::TFRI_cdnNotPt:
2532      return true;
2533  }
2534}
2535
2536bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2537  const HexagonRegisterInfo& QRI = getRegisterInfo();
2538  switch (MI->getOpcode())
2539  {
2540    default: return false;
2541    case Hexagon::ADD_ri_cPt:
2542    case Hexagon::ADD_ri_cNotPt:
2543    case Hexagon::ADD_rr_cPt:
2544    case Hexagon::ADD_rr_cNotPt:
2545    case Hexagon::XOR_rr_cPt:
2546    case Hexagon::XOR_rr_cNotPt:
2547    case Hexagon::AND_rr_cPt:
2548    case Hexagon::AND_rr_cNotPt:
2549    case Hexagon::OR_rr_cPt:
2550    case Hexagon::OR_rr_cNotPt:
2551    case Hexagon::SUB_rr_cPt:
2552    case Hexagon::SUB_rr_cNotPt:
2553    case Hexagon::COMBINE_rr_cPt:
2554    case Hexagon::COMBINE_rr_cNotPt:
2555      return true;
2556    case Hexagon::ASLH_cPt_V4:
2557    case Hexagon::ASLH_cNotPt_V4:
2558    case Hexagon::ASRH_cPt_V4:
2559    case Hexagon::ASRH_cNotPt_V4:
2560    case Hexagon::SXTB_cPt_V4:
2561    case Hexagon::SXTB_cNotPt_V4:
2562    case Hexagon::SXTH_cPt_V4:
2563    case Hexagon::SXTH_cNotPt_V4:
2564    case Hexagon::ZXTB_cPt_V4:
2565    case Hexagon::ZXTB_cNotPt_V4:
2566    case Hexagon::ZXTH_cPt_V4:
2567    case Hexagon::ZXTH_cNotPt_V4:
2568      return QRI.Subtarget.hasV4TOps();
2569  }
2570}
2571
2572bool HexagonInstrInfo::
2573isConditionalLoad (const MachineInstr* MI) const {
2574  const HexagonRegisterInfo& QRI = getRegisterInfo();
2575  switch (MI->getOpcode())
2576  {
2577    default: return false;
2578    case Hexagon::LDrid_cPt :
2579    case Hexagon::LDrid_cNotPt :
2580    case Hexagon::LDrid_indexed_cPt :
2581    case Hexagon::LDrid_indexed_cNotPt :
2582    case Hexagon::LDriw_cPt :
2583    case Hexagon::LDriw_cNotPt :
2584    case Hexagon::LDriw_indexed_cPt :
2585    case Hexagon::LDriw_indexed_cNotPt :
2586    case Hexagon::LDrih_cPt :
2587    case Hexagon::LDrih_cNotPt :
2588    case Hexagon::LDrih_indexed_cPt :
2589    case Hexagon::LDrih_indexed_cNotPt :
2590    case Hexagon::LDrib_cPt :
2591    case Hexagon::LDrib_cNotPt :
2592    case Hexagon::LDrib_indexed_cPt :
2593    case Hexagon::LDrib_indexed_cNotPt :
2594    case Hexagon::LDriuh_cPt :
2595    case Hexagon::LDriuh_cNotPt :
2596    case Hexagon::LDriuh_indexed_cPt :
2597    case Hexagon::LDriuh_indexed_cNotPt :
2598    case Hexagon::LDriub_cPt :
2599    case Hexagon::LDriub_cNotPt :
2600    case Hexagon::LDriub_indexed_cPt :
2601    case Hexagon::LDriub_indexed_cNotPt :
2602      return true;
2603    case Hexagon::POST_LDrid_cPt :
2604    case Hexagon::POST_LDrid_cNotPt :
2605    case Hexagon::POST_LDriw_cPt :
2606    case Hexagon::POST_LDriw_cNotPt :
2607    case Hexagon::POST_LDrih_cPt :
2608    case Hexagon::POST_LDrih_cNotPt :
2609    case Hexagon::POST_LDrib_cPt :
2610    case Hexagon::POST_LDrib_cNotPt :
2611    case Hexagon::POST_LDriuh_cPt :
2612    case Hexagon::POST_LDriuh_cNotPt :
2613    case Hexagon::POST_LDriub_cPt :
2614    case Hexagon::POST_LDriub_cNotPt :
2615      return QRI.Subtarget.hasV4TOps();
2616    case Hexagon::LDrid_indexed_cPt_V4 :
2617    case Hexagon::LDrid_indexed_cNotPt_V4 :
2618    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2619    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2620    case Hexagon::LDrib_indexed_cPt_V4 :
2621    case Hexagon::LDrib_indexed_cNotPt_V4 :
2622    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2623    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2624    case Hexagon::LDriub_indexed_cPt_V4 :
2625    case Hexagon::LDriub_indexed_cNotPt_V4 :
2626    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2627    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2628    case Hexagon::LDrih_indexed_cPt_V4 :
2629    case Hexagon::LDrih_indexed_cNotPt_V4 :
2630    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2631    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2632    case Hexagon::LDriuh_indexed_cPt_V4 :
2633    case Hexagon::LDriuh_indexed_cNotPt_V4 :
2634    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2635    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2636    case Hexagon::LDriw_indexed_cPt_V4 :
2637    case Hexagon::LDriw_indexed_cNotPt_V4 :
2638    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2639    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2640      return QRI.Subtarget.hasV4TOps();
2641  }
2642}
2643
2644// Returns true if an instruction is a conditional store.
2645//
2646// Note: It doesn't include conditional new-value stores as they can't be
2647// converted to .new predicate.
2648//
2649//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2650//                ^           ^
2651//               /             \ (not OK. it will cause new-value store to be
2652//              /               X conditional on p0.new while R2 producer is
2653//             /                 \ on p0)
2654//            /                   \.
2655//     p.new store                 p.old NV store
2656// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2657//            ^                  ^
2658//             \                /
2659//              \              /
2660//               \            /
2661//                 p.old store
2662//             [if (p0)memw(R0+#0)=R2]
2663//
2664// The above diagram shows the steps involoved in the conversion of a predicated
2665// store instruction to its .new predicated new-value form.
2666//
2667// The following set of instructions further explains the scenario where
2668// conditional new-value store becomes invalid when promoted to .new predicate
2669// form.
2670//
2671// { 1) if (p0) r0 = add(r1, r2)
2672//   2) p0 = cmp.eq(r3, #0) }
2673//
2674//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2675// the first two instructions because in instr 1, r0 is conditional on old value
2676// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2677// is not valid for new-value stores.
2678bool HexagonInstrInfo::
2679isConditionalStore (const MachineInstr* MI) const {
2680  const HexagonRegisterInfo& QRI = getRegisterInfo();
2681  switch (MI->getOpcode())
2682  {
2683    default: return false;
2684    case Hexagon::STrib_imm_cPt_V4 :
2685    case Hexagon::STrib_imm_cNotPt_V4 :
2686    case Hexagon::STrib_indexed_shl_cPt_V4 :
2687    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2688    case Hexagon::STrib_cPt :
2689    case Hexagon::STrib_cNotPt :
2690    case Hexagon::POST_STbri_cPt :
2691    case Hexagon::POST_STbri_cNotPt :
2692    case Hexagon::STrid_indexed_cPt :
2693    case Hexagon::STrid_indexed_cNotPt :
2694    case Hexagon::STrid_indexed_shl_cPt_V4 :
2695    case Hexagon::POST_STdri_cPt :
2696    case Hexagon::POST_STdri_cNotPt :
2697    case Hexagon::STrih_cPt :
2698    case Hexagon::STrih_cNotPt :
2699    case Hexagon::STrih_indexed_cPt :
2700    case Hexagon::STrih_indexed_cNotPt :
2701    case Hexagon::STrih_imm_cPt_V4 :
2702    case Hexagon::STrih_imm_cNotPt_V4 :
2703    case Hexagon::STrih_indexed_shl_cPt_V4 :
2704    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2705    case Hexagon::POST_SThri_cPt :
2706    case Hexagon::POST_SThri_cNotPt :
2707    case Hexagon::STriw_cPt :
2708    case Hexagon::STriw_cNotPt :
2709    case Hexagon::STriw_indexed_cPt :
2710    case Hexagon::STriw_indexed_cNotPt :
2711    case Hexagon::STriw_imm_cPt_V4 :
2712    case Hexagon::STriw_imm_cNotPt_V4 :
2713    case Hexagon::STriw_indexed_shl_cPt_V4 :
2714    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2715    case Hexagon::POST_STwri_cPt :
2716    case Hexagon::POST_STwri_cNotPt :
2717      return QRI.Subtarget.hasV4TOps();
2718
2719    // V4 global address store before promoting to dot new.
2720    case Hexagon::STrid_GP_cPt_V4 :
2721    case Hexagon::STrid_GP_cNotPt_V4 :
2722    case Hexagon::STrib_GP_cPt_V4 :
2723    case Hexagon::STrib_GP_cNotPt_V4 :
2724    case Hexagon::STrih_GP_cPt_V4 :
2725    case Hexagon::STrih_GP_cNotPt_V4 :
2726    case Hexagon::STriw_GP_cPt_V4 :
2727    case Hexagon::STriw_GP_cNotPt_V4 :
2728    case Hexagon::STd_GP_cPt_V4 :
2729    case Hexagon::STd_GP_cNotPt_V4 :
2730    case Hexagon::STb_GP_cPt_V4 :
2731    case Hexagon::STb_GP_cNotPt_V4 :
2732    case Hexagon::STh_GP_cPt_V4 :
2733    case Hexagon::STh_GP_cNotPt_V4 :
2734    case Hexagon::STw_GP_cPt_V4 :
2735    case Hexagon::STw_GP_cNotPt_V4 :
2736      return QRI.Subtarget.hasV4TOps();
2737
2738    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2739    // from the "Conditional Store" list. Because a predicated new value store
2740    // would NOT be promoted to a double dot new store. See diagram below:
2741    // This function returns yes for those stores that are predicated but not
2742    // yet promoted to predicate dot new instructions.
2743    //
2744    //                          +---------------------+
2745    //                    /-----| if (p0) memw(..)=r0 |---------\~
2746    //                   ||     +---------------------+         ||
2747    //          promote  ||       /\       /\                   ||  promote
2748    //                   ||      /||\     /||\                  ||
2749    //                  \||/    demote     ||                  \||/
2750    //                   \/       ||       ||                   \/
2751    //       +-------------------------+   ||   +-------------------------+
2752    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2753    //       +-------------------------+   ||   +-------------------------+
2754    //                        ||           ||         ||
2755    //                        ||         demote      \||/
2756    //                      promote        ||         \/ NOT possible
2757    //                        ||           ||         /\~
2758    //                       \||/          ||        /||\~
2759    //                        \/           ||         ||
2760    //                      +-----------------------------+
2761    //                      | if (p0.new) memw(..)=r0.new |
2762    //                      +-----------------------------+
2763    //                           Double Dot New Store
2764    //
2765  }
2766}
2767
2768
2769
2770DFAPacketizer *HexagonInstrInfo::
2771CreateTargetScheduleState(const TargetMachine *TM,
2772                           const ScheduleDAG *DAG) const {
2773  const InstrItineraryData *II = TM->getInstrItineraryData();
2774  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2775}
2776
2777bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2778                                            const MachineBasicBlock *MBB,
2779                                            const MachineFunction &MF) const {
2780  // Debug info is never a scheduling boundary. It's necessary to be explicit
2781  // due to the special treatment of IT instructions below, otherwise a
2782  // dbg_value followed by an IT will result in the IT instruction being
2783  // considered a scheduling hazard, which is wrong. It should be the actual
2784  // instruction preceding the dbg_value instruction(s), just like it is
2785  // when debug info is not present.
2786  if (MI->isDebugValue())
2787    return false;
2788
2789  // Terminators and labels can't be scheduled around.
2790  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2791    return true;
2792
2793  return false;
2794}
2795