HexagonInstrInfo.cpp revision 8aa138c12282e8bccac665f2197e817e32c2adcf
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Hexagon implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "HexagonInstrInfo.h" 15#include "HexagonRegisterInfo.h" 16#include "HexagonSubtarget.h" 17#include "Hexagon.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/DFAPacketizer.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Support/MathExtras.h" 27#define GET_INSTRINFO_CTOR 28#define GET_INSTRMAP_INFO 29#include "HexagonGenInstrInfo.inc" 30#include "HexagonGenDFAPacketizer.inc" 31 32using namespace llvm; 33 34/// 35/// Constants for Hexagon instructions. 36/// 37const int Hexagon_MEMW_OFFSET_MAX = 4095; 38const int Hexagon_MEMW_OFFSET_MIN = -4096; 39const int Hexagon_MEMD_OFFSET_MAX = 8191; 40const int Hexagon_MEMD_OFFSET_MIN = -8192; 41const int Hexagon_MEMH_OFFSET_MAX = 2047; 42const int Hexagon_MEMH_OFFSET_MIN = -2048; 43const int Hexagon_MEMB_OFFSET_MAX = 1023; 44const int Hexagon_MEMB_OFFSET_MIN = -1024; 45const int Hexagon_ADDI_OFFSET_MAX = 32767; 46const int Hexagon_ADDI_OFFSET_MIN = -32768; 47const int Hexagon_MEMD_AUTOINC_MAX = 56; 48const int Hexagon_MEMD_AUTOINC_MIN = -64; 49const int Hexagon_MEMW_AUTOINC_MAX = 28; 50const int Hexagon_MEMW_AUTOINC_MIN = -32; 51const int Hexagon_MEMH_AUTOINC_MAX = 14; 52const int Hexagon_MEMH_AUTOINC_MIN = -16; 53const int Hexagon_MEMB_AUTOINC_MAX = 7; 54const int Hexagon_MEMB_AUTOINC_MIN = -8; 55 56 57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) 58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), 59 RI(ST, *this), Subtarget(ST) { 60} 61 62 63/// isLoadFromStackSlot - If the specified machine instruction is a direct 64/// load from a stack slot, return the virtual or physical register number of 65/// the destination along with the FrameIndex of the loaded stack slot. If 66/// not, return 0. This predicate must return 0 if the instruction has 67/// any side effects other than loading from the stack slot. 68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 69 int &FrameIndex) const { 70 71 72 switch (MI->getOpcode()) { 73 default: break; 74 case Hexagon::LDriw: 75 case Hexagon::LDrid: 76 case Hexagon::LDrih: 77 case Hexagon::LDrib: 78 case Hexagon::LDriub: 79 if (MI->getOperand(2).isFI() && 80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 81 FrameIndex = MI->getOperand(2).getIndex(); 82 return MI->getOperand(0).getReg(); 83 } 84 break; 85 } 86 return 0; 87} 88 89 90/// isStoreToStackSlot - If the specified machine instruction is a direct 91/// store to a stack slot, return the virtual or physical register number of 92/// the source reg along with the FrameIndex of the loaded stack slot. If 93/// not, return 0. This predicate must return 0 if the instruction has 94/// any side effects other than storing to the stack slot. 95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const { 97 switch (MI->getOpcode()) { 98 default: break; 99 case Hexagon::STriw: 100 case Hexagon::STrid: 101 case Hexagon::STrih: 102 case Hexagon::STrib: 103 if (MI->getOperand(2).isFI() && 104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 105 FrameIndex = MI->getOperand(0).getIndex(); 106 return MI->getOperand(2).getReg(); 107 } 108 break; 109 } 110 return 0; 111} 112 113 114unsigned 115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 116 MachineBasicBlock *FBB, 117 const SmallVectorImpl<MachineOperand> &Cond, 118 DebugLoc DL) const{ 119 120 int BOpc = Hexagon::JMP; 121 int BccOpc = Hexagon::JMP_c; 122 123 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 124 125 int regPos = 0; 126 // Check if ReverseBranchCondition has asked to reverse this branch 127 // If we want to reverse the branch an odd number of times, we want 128 // JMP_cNot. 129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 130 BccOpc = Hexagon::JMP_cNot; 131 regPos = 1; 132 } 133 134 if (FBB == 0) { 135 if (Cond.empty()) { 136 // Due to a bug in TailMerging/CFG Optimization, we need to add a 137 // special case handling of a predicated jump followed by an 138 // unconditional jump. If not, Tail Merging and CFG Optimization go 139 // into an infinite loop. 140 MachineBasicBlock *NewTBB, *NewFBB; 141 SmallVector<MachineOperand, 4> Cond; 142 MachineInstr *Term = MBB.getFirstTerminator(); 143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, 144 false)) { 145 MachineBasicBlock *NextBB = 146 llvm::next(MachineFunction::iterator(&MBB)); 147 if (NewTBB == NextBB) { 148 ReverseBranchCondition(Cond); 149 RemoveBranch(MBB); 150 return InsertBranch(MBB, TBB, 0, Cond, DL); 151 } 152 } 153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 154 } else { 155 BuildMI(&MBB, DL, 156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 157 } 158 return 1; 159 } 160 161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 163 164 return 2; 165} 166 167 168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 169 MachineBasicBlock *&TBB, 170 MachineBasicBlock *&FBB, 171 SmallVectorImpl<MachineOperand> &Cond, 172 bool AllowModify) const { 173 TBB = NULL; 174 FBB = NULL; 175 176 // If the block has no terminators, it just falls into the block after it. 177 MachineBasicBlock::iterator I = MBB.end(); 178 if (I == MBB.begin()) 179 return false; 180 181 // A basic block may looks like this: 182 // 183 // [ insn 184 // EH_LABEL 185 // insn 186 // insn 187 // insn 188 // EH_LABEL 189 // insn ] 190 // 191 // It has two succs but does not have a terminator 192 // Don't know how to handle it. 193 do { 194 --I; 195 if (I->isEHLabel()) 196 return true; 197 } while (I != MBB.begin()); 198 199 I = MBB.end(); 200 --I; 201 202 while (I->isDebugValue()) { 203 if (I == MBB.begin()) 204 return false; 205 --I; 206 } 207 if (!isUnpredicatedTerminator(I)) 208 return false; 209 210 // Get the last instruction in the block. 211 MachineInstr *LastInst = I; 212 213 // If there is only one terminator instruction, process it. 214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 215 if (LastInst->getOpcode() == Hexagon::JMP) { 216 TBB = LastInst->getOperand(0).getMBB(); 217 return false; 218 } 219 if (LastInst->getOpcode() == Hexagon::JMP_c) { 220 // Block ends with fall-through true condbranch. 221 TBB = LastInst->getOperand(1).getMBB(); 222 Cond.push_back(LastInst->getOperand(0)); 223 return false; 224 } 225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) { 226 // Block ends with fall-through false condbranch. 227 TBB = LastInst->getOperand(1).getMBB(); 228 Cond.push_back(MachineOperand::CreateImm(0)); 229 Cond.push_back(LastInst->getOperand(0)); 230 return false; 231 } 232 // Otherwise, don't know what this is. 233 return true; 234 } 235 236 // Get the instruction before it if it's a terminator. 237 MachineInstr *SecondLastInst = I; 238 239 // If there are three terminators, we don't know what sort of block this is. 240 if (SecondLastInst && I != MBB.begin() && 241 isUnpredicatedTerminator(--I)) 242 return true; 243 244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. 245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || 246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && 247 LastInst->getOpcode() == Hexagon::JMP) { 248 TBB = SecondLastInst->getOperand(1).getMBB(); 249 Cond.push_back(SecondLastInst->getOperand(0)); 250 FBB = LastInst->getOperand(0).getMBB(); 251 return false; 252 } 253 254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. 255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && 256 LastInst->getOpcode() == Hexagon::JMP) { 257 TBB = SecondLastInst->getOperand(1).getMBB(); 258 Cond.push_back(MachineOperand::CreateImm(0)); 259 Cond.push_back(SecondLastInst->getOperand(0)); 260 FBB = LastInst->getOperand(0).getMBB(); 261 return false; 262 } 263 264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not 265 // executed, so remove it. 266 if (SecondLastInst->getOpcode() == Hexagon::JMP && 267 LastInst->getOpcode() == Hexagon::JMP) { 268 TBB = SecondLastInst->getOperand(0).getMBB(); 269 I = LastInst; 270 if (AllowModify) 271 I->eraseFromParent(); 272 return false; 273 } 274 275 // Otherwise, can't handle this. 276 return true; 277} 278 279 280unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 281 int BOpc = Hexagon::JMP; 282 int BccOpc = Hexagon::JMP_c; 283 int BccOpcNot = Hexagon::JMP_cNot; 284 285 MachineBasicBlock::iterator I = MBB.end(); 286 if (I == MBB.begin()) return 0; 287 --I; 288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc && 289 I->getOpcode() != BccOpcNot) 290 return 0; 291 292 // Remove the branch. 293 I->eraseFromParent(); 294 295 I = MBB.end(); 296 297 if (I == MBB.begin()) return 1; 298 --I; 299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot) 300 return 1; 301 302 // Remove the branch. 303 I->eraseFromParent(); 304 return 2; 305} 306 307 308void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 309 MachineBasicBlock::iterator I, DebugLoc DL, 310 unsigned DestReg, unsigned SrcReg, 311 bool KillSrc) const { 312 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 313 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 314 return; 315 } 316 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 317 BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg); 318 return; 319 } 320 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 321 // Map Pd = Ps to Pd = or(Ps, Ps). 322 BuildMI(MBB, I, DL, get(Hexagon::OR_pp), 323 DestReg).addReg(SrcReg).addReg(SrcReg); 324 return; 325 } 326 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && 327 Hexagon::IntRegsRegClass.contains(SrcReg)) { 328 // We can have an overlap between single and double reg: r1:0 = r0. 329 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 330 // r1:0 = r0 331 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 332 Hexagon::subreg_hireg))).addImm(0); 333 } else { 334 // r1:0 = r1 or no overlap. 335 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 336 Hexagon::subreg_loreg))).addReg(SrcReg); 337 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 338 Hexagon::subreg_hireg))).addImm(0); 339 } 340 return; 341 } 342 if (Hexagon::CRRegsRegClass.contains(DestReg) && 343 Hexagon::IntRegsRegClass.contains(SrcReg)) { 344 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); 345 return; 346 } 347 348 llvm_unreachable("Unimplemented"); 349} 350 351 352void HexagonInstrInfo:: 353storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 354 unsigned SrcReg, bool isKill, int FI, 355 const TargetRegisterClass *RC, 356 const TargetRegisterInfo *TRI) const { 357 358 DebugLoc DL = MBB.findDebugLoc(I); 359 MachineFunction &MF = *MBB.getParent(); 360 MachineFrameInfo &MFI = *MF.getFrameInfo(); 361 unsigned Align = MFI.getObjectAlignment(FI); 362 363 MachineMemOperand *MMO = 364 MF.getMachineMemOperand( 365 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 366 MachineMemOperand::MOStore, 367 MFI.getObjectSize(FI), 368 Align); 369 370 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 371 BuildMI(MBB, I, DL, get(Hexagon::STriw)) 372 .addFrameIndex(FI).addImm(0) 373 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 374 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 375 BuildMI(MBB, I, DL, get(Hexagon::STrid)) 376 .addFrameIndex(FI).addImm(0) 377 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 378 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 379 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) 380 .addFrameIndex(FI).addImm(0) 381 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 382 } else { 383 llvm_unreachable("Unimplemented"); 384 } 385} 386 387 388void HexagonInstrInfo::storeRegToAddr( 389 MachineFunction &MF, unsigned SrcReg, 390 bool isKill, 391 SmallVectorImpl<MachineOperand> &Addr, 392 const TargetRegisterClass *RC, 393 SmallVectorImpl<MachineInstr*> &NewMIs) const 394{ 395 llvm_unreachable("Unimplemented"); 396} 397 398 399void HexagonInstrInfo:: 400loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 401 unsigned DestReg, int FI, 402 const TargetRegisterClass *RC, 403 const TargetRegisterInfo *TRI) const { 404 DebugLoc DL = MBB.findDebugLoc(I); 405 MachineFunction &MF = *MBB.getParent(); 406 MachineFrameInfo &MFI = *MF.getFrameInfo(); 407 unsigned Align = MFI.getObjectAlignment(FI); 408 409 MachineMemOperand *MMO = 410 MF.getMachineMemOperand( 411 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 412 MachineMemOperand::MOLoad, 413 MFI.getObjectSize(FI), 414 Align); 415 if (RC == &Hexagon::IntRegsRegClass) { 416 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) 417 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 418 } else if (RC == &Hexagon::DoubleRegsRegClass) { 419 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) 420 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 421 } else if (RC == &Hexagon::PredRegsRegClass) { 422 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) 423 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 424 } else { 425 llvm_unreachable("Can't store this register to stack slot"); 426 } 427} 428 429 430void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 431 SmallVectorImpl<MachineOperand> &Addr, 432 const TargetRegisterClass *RC, 433 SmallVectorImpl<MachineInstr*> &NewMIs) const { 434 llvm_unreachable("Unimplemented"); 435} 436 437 438MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 439 MachineInstr* MI, 440 const SmallVectorImpl<unsigned> &Ops, 441 int FI) const { 442 // Hexagon_TODO: Implement. 443 return(0); 444} 445 446 447unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { 448 449 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 450 const TargetRegisterClass *TRC; 451 if (VT == MVT::i1) { 452 TRC = &Hexagon::PredRegsRegClass; 453 } else if (VT == MVT::i32 || VT == MVT::f32) { 454 TRC = &Hexagon::IntRegsRegClass; 455 } else if (VT == MVT::i64 || VT == MVT::f64) { 456 TRC = &Hexagon::DoubleRegsRegClass; 457 } else { 458 llvm_unreachable("Cannot handle this register class"); 459 } 460 461 unsigned NewReg = RegInfo.createVirtualRegister(TRC); 462 return NewReg; 463} 464 465bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { 466 switch(MI->getOpcode()) { 467 default: return false; 468 // JMP_EQri 469 case Hexagon::JMP_EQriPt_nv_V4: 470 case Hexagon::JMP_EQriPnt_nv_V4: 471 case Hexagon::JMP_EQriNotPt_nv_V4: 472 case Hexagon::JMP_EQriNotPnt_nv_V4: 473 474 // JMP_EQri - with -1 475 case Hexagon::JMP_EQriPtneg_nv_V4: 476 case Hexagon::JMP_EQriPntneg_nv_V4: 477 case Hexagon::JMP_EQriNotPtneg_nv_V4: 478 case Hexagon::JMP_EQriNotPntneg_nv_V4: 479 480 // JMP_EQrr 481 case Hexagon::JMP_EQrrPt_nv_V4: 482 case Hexagon::JMP_EQrrPnt_nv_V4: 483 case Hexagon::JMP_EQrrNotPt_nv_V4: 484 case Hexagon::JMP_EQrrNotPnt_nv_V4: 485 486 // JMP_GTri 487 case Hexagon::JMP_GTriPt_nv_V4: 488 case Hexagon::JMP_GTriPnt_nv_V4: 489 case Hexagon::JMP_GTriNotPt_nv_V4: 490 case Hexagon::JMP_GTriNotPnt_nv_V4: 491 492 // JMP_GTri - with -1 493 case Hexagon::JMP_GTriPtneg_nv_V4: 494 case Hexagon::JMP_GTriPntneg_nv_V4: 495 case Hexagon::JMP_GTriNotPtneg_nv_V4: 496 case Hexagon::JMP_GTriNotPntneg_nv_V4: 497 498 // JMP_GTrr 499 case Hexagon::JMP_GTrrPt_nv_V4: 500 case Hexagon::JMP_GTrrPnt_nv_V4: 501 case Hexagon::JMP_GTrrNotPt_nv_V4: 502 case Hexagon::JMP_GTrrNotPnt_nv_V4: 503 504 // JMP_GTrrdn 505 case Hexagon::JMP_GTrrdnPt_nv_V4: 506 case Hexagon::JMP_GTrrdnPnt_nv_V4: 507 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 508 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 509 510 // JMP_GTUri 511 case Hexagon::JMP_GTUriPt_nv_V4: 512 case Hexagon::JMP_GTUriPnt_nv_V4: 513 case Hexagon::JMP_GTUriNotPt_nv_V4: 514 case Hexagon::JMP_GTUriNotPnt_nv_V4: 515 516 // JMP_GTUrr 517 case Hexagon::JMP_GTUrrPt_nv_V4: 518 case Hexagon::JMP_GTUrrPnt_nv_V4: 519 case Hexagon::JMP_GTUrrNotPt_nv_V4: 520 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 521 522 // JMP_GTUrrdn 523 case Hexagon::JMP_GTUrrdnPt_nv_V4: 524 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 525 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 526 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 527 528 // TFR_FI 529 case Hexagon::TFR_FI: 530 return true; 531 } 532} 533 534bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { 535 switch(MI->getOpcode()) { 536 default: return false; 537 // JMP_EQri 538 case Hexagon::JMP_EQriPt_ie_nv_V4: 539 case Hexagon::JMP_EQriPnt_ie_nv_V4: 540 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 541 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 542 543 // JMP_EQri - with -1 544 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 545 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 546 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 547 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 548 549 // JMP_EQrr 550 case Hexagon::JMP_EQrrPt_ie_nv_V4: 551 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 552 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 553 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 554 555 // JMP_GTri 556 case Hexagon::JMP_GTriPt_ie_nv_V4: 557 case Hexagon::JMP_GTriPnt_ie_nv_V4: 558 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 559 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 560 561 // JMP_GTri - with -1 562 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 563 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 564 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 565 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 566 567 // JMP_GTrr 568 case Hexagon::JMP_GTrrPt_ie_nv_V4: 569 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 570 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 571 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 572 573 // JMP_GTrrdn 574 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 575 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 576 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 577 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 578 579 // JMP_GTUri 580 case Hexagon::JMP_GTUriPt_ie_nv_V4: 581 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 582 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 583 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 584 585 // JMP_GTUrr 586 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 587 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 588 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 589 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 590 591 // JMP_GTUrrdn 592 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 593 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 594 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 595 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 596 597 // V4 absolute set addressing. 598 case Hexagon::LDrid_abs_setimm_V4: 599 case Hexagon::LDriw_abs_setimm_V4: 600 case Hexagon::LDrih_abs_setimm_V4: 601 case Hexagon::LDrib_abs_setimm_V4: 602 case Hexagon::LDriuh_abs_setimm_V4: 603 case Hexagon::LDriub_abs_setimm_V4: 604 605 case Hexagon::STrid_abs_setimm_V4: 606 case Hexagon::STrib_abs_setimm_V4: 607 case Hexagon::STrih_abs_setimm_V4: 608 case Hexagon::STriw_abs_setimm_V4: 609 610 // V4 global address load. 611 case Hexagon::LDrid_GP_cPt_V4 : 612 case Hexagon::LDrid_GP_cNotPt_V4 : 613 case Hexagon::LDrid_GP_cdnPt_V4 : 614 case Hexagon::LDrid_GP_cdnNotPt_V4 : 615 case Hexagon::LDrib_GP_cPt_V4 : 616 case Hexagon::LDrib_GP_cNotPt_V4 : 617 case Hexagon::LDrib_GP_cdnPt_V4 : 618 case Hexagon::LDrib_GP_cdnNotPt_V4 : 619 case Hexagon::LDriub_GP_cPt_V4 : 620 case Hexagon::LDriub_GP_cNotPt_V4 : 621 case Hexagon::LDriub_GP_cdnPt_V4 : 622 case Hexagon::LDriub_GP_cdnNotPt_V4 : 623 case Hexagon::LDrih_GP_cPt_V4 : 624 case Hexagon::LDrih_GP_cNotPt_V4 : 625 case Hexagon::LDrih_GP_cdnPt_V4 : 626 case Hexagon::LDrih_GP_cdnNotPt_V4 : 627 case Hexagon::LDriuh_GP_cPt_V4 : 628 case Hexagon::LDriuh_GP_cNotPt_V4 : 629 case Hexagon::LDriuh_GP_cdnPt_V4 : 630 case Hexagon::LDriuh_GP_cdnNotPt_V4 : 631 case Hexagon::LDriw_GP_cPt_V4 : 632 case Hexagon::LDriw_GP_cNotPt_V4 : 633 case Hexagon::LDriw_GP_cdnPt_V4 : 634 case Hexagon::LDriw_GP_cdnNotPt_V4 : 635 case Hexagon::LDd_GP_cPt_V4 : 636 case Hexagon::LDd_GP_cNotPt_V4 : 637 case Hexagon::LDd_GP_cdnPt_V4 : 638 case Hexagon::LDd_GP_cdnNotPt_V4 : 639 case Hexagon::LDb_GP_cPt_V4 : 640 case Hexagon::LDb_GP_cNotPt_V4 : 641 case Hexagon::LDb_GP_cdnPt_V4 : 642 case Hexagon::LDb_GP_cdnNotPt_V4 : 643 case Hexagon::LDub_GP_cPt_V4 : 644 case Hexagon::LDub_GP_cNotPt_V4 : 645 case Hexagon::LDub_GP_cdnPt_V4 : 646 case Hexagon::LDub_GP_cdnNotPt_V4 : 647 case Hexagon::LDh_GP_cPt_V4 : 648 case Hexagon::LDh_GP_cNotPt_V4 : 649 case Hexagon::LDh_GP_cdnPt_V4 : 650 case Hexagon::LDh_GP_cdnNotPt_V4 : 651 case Hexagon::LDuh_GP_cPt_V4 : 652 case Hexagon::LDuh_GP_cNotPt_V4 : 653 case Hexagon::LDuh_GP_cdnPt_V4 : 654 case Hexagon::LDuh_GP_cdnNotPt_V4 : 655 case Hexagon::LDw_GP_cPt_V4 : 656 case Hexagon::LDw_GP_cNotPt_V4 : 657 case Hexagon::LDw_GP_cdnPt_V4 : 658 case Hexagon::LDw_GP_cdnNotPt_V4 : 659 660 // V4 global address store. 661 case Hexagon::STrid_GP_cPt_V4 : 662 case Hexagon::STrid_GP_cNotPt_V4 : 663 case Hexagon::STrid_GP_cdnPt_V4 : 664 case Hexagon::STrid_GP_cdnNotPt_V4 : 665 case Hexagon::STrib_GP_cPt_V4 : 666 case Hexagon::STrib_GP_cNotPt_V4 : 667 case Hexagon::STrib_GP_cdnPt_V4 : 668 case Hexagon::STrib_GP_cdnNotPt_V4 : 669 case Hexagon::STrih_GP_cPt_V4 : 670 case Hexagon::STrih_GP_cNotPt_V4 : 671 case Hexagon::STrih_GP_cdnPt_V4 : 672 case Hexagon::STrih_GP_cdnNotPt_V4 : 673 case Hexagon::STriw_GP_cPt_V4 : 674 case Hexagon::STriw_GP_cNotPt_V4 : 675 case Hexagon::STriw_GP_cdnPt_V4 : 676 case Hexagon::STriw_GP_cdnNotPt_V4 : 677 case Hexagon::STd_GP_cPt_V4 : 678 case Hexagon::STd_GP_cNotPt_V4 : 679 case Hexagon::STd_GP_cdnPt_V4 : 680 case Hexagon::STd_GP_cdnNotPt_V4 : 681 case Hexagon::STb_GP_cPt_V4 : 682 case Hexagon::STb_GP_cNotPt_V4 : 683 case Hexagon::STb_GP_cdnPt_V4 : 684 case Hexagon::STb_GP_cdnNotPt_V4 : 685 case Hexagon::STh_GP_cPt_V4 : 686 case Hexagon::STh_GP_cNotPt_V4 : 687 case Hexagon::STh_GP_cdnPt_V4 : 688 case Hexagon::STh_GP_cdnNotPt_V4 : 689 case Hexagon::STw_GP_cPt_V4 : 690 case Hexagon::STw_GP_cNotPt_V4 : 691 case Hexagon::STw_GP_cdnPt_V4 : 692 case Hexagon::STw_GP_cdnNotPt_V4 : 693 694 // V4 predicated global address new value store. 695 case Hexagon::STrib_GP_cPt_nv_V4 : 696 case Hexagon::STrib_GP_cNotPt_nv_V4 : 697 case Hexagon::STrib_GP_cdnPt_nv_V4 : 698 case Hexagon::STrib_GP_cdnNotPt_nv_V4 : 699 case Hexagon::STrih_GP_cPt_nv_V4 : 700 case Hexagon::STrih_GP_cNotPt_nv_V4 : 701 case Hexagon::STrih_GP_cdnPt_nv_V4 : 702 case Hexagon::STrih_GP_cdnNotPt_nv_V4 : 703 case Hexagon::STriw_GP_cPt_nv_V4 : 704 case Hexagon::STriw_GP_cNotPt_nv_V4 : 705 case Hexagon::STriw_GP_cdnPt_nv_V4 : 706 case Hexagon::STriw_GP_cdnNotPt_nv_V4 : 707 case Hexagon::STb_GP_cPt_nv_V4 : 708 case Hexagon::STb_GP_cNotPt_nv_V4 : 709 case Hexagon::STb_GP_cdnPt_nv_V4 : 710 case Hexagon::STb_GP_cdnNotPt_nv_V4 : 711 case Hexagon::STh_GP_cPt_nv_V4 : 712 case Hexagon::STh_GP_cNotPt_nv_V4 : 713 case Hexagon::STh_GP_cdnPt_nv_V4 : 714 case Hexagon::STh_GP_cdnNotPt_nv_V4 : 715 case Hexagon::STw_GP_cPt_nv_V4 : 716 case Hexagon::STw_GP_cNotPt_nv_V4 : 717 case Hexagon::STw_GP_cdnPt_nv_V4 : 718 case Hexagon::STw_GP_cdnNotPt_nv_V4 : 719 720 // TFR_FI 721 case Hexagon::TFR_FI_immext_V4: 722 723 // TFRI_F 724 case Hexagon::TFRI_f: 725 case Hexagon::TFRI_cPt_f: 726 case Hexagon::TFRI_cNotPt_f: 727 case Hexagon::CONST64_Float_Real: 728 return true; 729 } 730} 731 732bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { 733 switch (MI->getOpcode()) { 734 default: return false; 735 // JMP_EQri 736 case Hexagon::JMP_EQriPt_nv_V4: 737 case Hexagon::JMP_EQriPnt_nv_V4: 738 case Hexagon::JMP_EQriNotPt_nv_V4: 739 case Hexagon::JMP_EQriNotPnt_nv_V4: 740 case Hexagon::JMP_EQriPt_ie_nv_V4: 741 case Hexagon::JMP_EQriPnt_ie_nv_V4: 742 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 743 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 744 745 // JMP_EQri - with -1 746 case Hexagon::JMP_EQriPtneg_nv_V4: 747 case Hexagon::JMP_EQriPntneg_nv_V4: 748 case Hexagon::JMP_EQriNotPtneg_nv_V4: 749 case Hexagon::JMP_EQriNotPntneg_nv_V4: 750 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 751 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 752 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 753 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 754 755 // JMP_EQrr 756 case Hexagon::JMP_EQrrPt_nv_V4: 757 case Hexagon::JMP_EQrrPnt_nv_V4: 758 case Hexagon::JMP_EQrrNotPt_nv_V4: 759 case Hexagon::JMP_EQrrNotPnt_nv_V4: 760 case Hexagon::JMP_EQrrPt_ie_nv_V4: 761 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 762 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 763 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 764 765 // JMP_GTri 766 case Hexagon::JMP_GTriPt_nv_V4: 767 case Hexagon::JMP_GTriPnt_nv_V4: 768 case Hexagon::JMP_GTriNotPt_nv_V4: 769 case Hexagon::JMP_GTriNotPnt_nv_V4: 770 case Hexagon::JMP_GTriPt_ie_nv_V4: 771 case Hexagon::JMP_GTriPnt_ie_nv_V4: 772 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 773 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 774 775 // JMP_GTri - with -1 776 case Hexagon::JMP_GTriPtneg_nv_V4: 777 case Hexagon::JMP_GTriPntneg_nv_V4: 778 case Hexagon::JMP_GTriNotPtneg_nv_V4: 779 case Hexagon::JMP_GTriNotPntneg_nv_V4: 780 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 781 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 782 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 783 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 784 785 // JMP_GTrr 786 case Hexagon::JMP_GTrrPt_nv_V4: 787 case Hexagon::JMP_GTrrPnt_nv_V4: 788 case Hexagon::JMP_GTrrNotPt_nv_V4: 789 case Hexagon::JMP_GTrrNotPnt_nv_V4: 790 case Hexagon::JMP_GTrrPt_ie_nv_V4: 791 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 792 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 793 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 794 795 // JMP_GTrrdn 796 case Hexagon::JMP_GTrrdnPt_nv_V4: 797 case Hexagon::JMP_GTrrdnPnt_nv_V4: 798 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 799 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 800 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 801 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 802 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 803 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 804 805 // JMP_GTUri 806 case Hexagon::JMP_GTUriPt_nv_V4: 807 case Hexagon::JMP_GTUriPnt_nv_V4: 808 case Hexagon::JMP_GTUriNotPt_nv_V4: 809 case Hexagon::JMP_GTUriNotPnt_nv_V4: 810 case Hexagon::JMP_GTUriPt_ie_nv_V4: 811 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 812 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 813 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 814 815 // JMP_GTUrr 816 case Hexagon::JMP_GTUrrPt_nv_V4: 817 case Hexagon::JMP_GTUrrPnt_nv_V4: 818 case Hexagon::JMP_GTUrrNotPt_nv_V4: 819 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 820 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 821 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 822 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 823 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 824 825 // JMP_GTUrrdn 826 case Hexagon::JMP_GTUrrdnPt_nv_V4: 827 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 828 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 829 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 830 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 831 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 832 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 833 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 834 return true; 835 } 836} 837 838unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const { 839 switch(MI->getOpcode()) { 840 default: llvm_unreachable("Unknown type of instruction."); 841 // JMP_EQri 842 case Hexagon::JMP_EQriPt_nv_V4: 843 return Hexagon::JMP_EQriPt_ie_nv_V4; 844 case Hexagon::JMP_EQriNotPt_nv_V4: 845 return Hexagon::JMP_EQriNotPt_ie_nv_V4; 846 case Hexagon::JMP_EQriPnt_nv_V4: 847 return Hexagon::JMP_EQriPnt_ie_nv_V4; 848 case Hexagon::JMP_EQriNotPnt_nv_V4: 849 return Hexagon::JMP_EQriNotPnt_ie_nv_V4; 850 851 // JMP_EQri -- with -1 852 case Hexagon::JMP_EQriPtneg_nv_V4: 853 return Hexagon::JMP_EQriPtneg_ie_nv_V4; 854 case Hexagon::JMP_EQriNotPtneg_nv_V4: 855 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4; 856 case Hexagon::JMP_EQriPntneg_nv_V4: 857 return Hexagon::JMP_EQriPntneg_ie_nv_V4; 858 case Hexagon::JMP_EQriNotPntneg_nv_V4: 859 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4; 860 861 // JMP_EQrr 862 case Hexagon::JMP_EQrrPt_nv_V4: 863 return Hexagon::JMP_EQrrPt_ie_nv_V4; 864 case Hexagon::JMP_EQrrNotPt_nv_V4: 865 return Hexagon::JMP_EQrrNotPt_ie_nv_V4; 866 case Hexagon::JMP_EQrrPnt_nv_V4: 867 return Hexagon::JMP_EQrrPnt_ie_nv_V4; 868 case Hexagon::JMP_EQrrNotPnt_nv_V4: 869 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4; 870 871 // JMP_GTri 872 case Hexagon::JMP_GTriPt_nv_V4: 873 return Hexagon::JMP_GTriPt_ie_nv_V4; 874 case Hexagon::JMP_GTriNotPt_nv_V4: 875 return Hexagon::JMP_GTriNotPt_ie_nv_V4; 876 case Hexagon::JMP_GTriPnt_nv_V4: 877 return Hexagon::JMP_GTriPnt_ie_nv_V4; 878 case Hexagon::JMP_GTriNotPnt_nv_V4: 879 return Hexagon::JMP_GTriNotPnt_ie_nv_V4; 880 881 // JMP_GTri -- with -1 882 case Hexagon::JMP_GTriPtneg_nv_V4: 883 return Hexagon::JMP_GTriPtneg_ie_nv_V4; 884 case Hexagon::JMP_GTriNotPtneg_nv_V4: 885 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4; 886 case Hexagon::JMP_GTriPntneg_nv_V4: 887 return Hexagon::JMP_GTriPntneg_ie_nv_V4; 888 case Hexagon::JMP_GTriNotPntneg_nv_V4: 889 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4; 890 891 // JMP_GTrr 892 case Hexagon::JMP_GTrrPt_nv_V4: 893 return Hexagon::JMP_GTrrPt_ie_nv_V4; 894 case Hexagon::JMP_GTrrNotPt_nv_V4: 895 return Hexagon::JMP_GTrrNotPt_ie_nv_V4; 896 case Hexagon::JMP_GTrrPnt_nv_V4: 897 return Hexagon::JMP_GTrrPnt_ie_nv_V4; 898 case Hexagon::JMP_GTrrNotPnt_nv_V4: 899 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4; 900 901 // JMP_GTrrdn 902 case Hexagon::JMP_GTrrdnPt_nv_V4: 903 return Hexagon::JMP_GTrrdnPt_ie_nv_V4; 904 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 905 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4; 906 case Hexagon::JMP_GTrrdnPnt_nv_V4: 907 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4; 908 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 909 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4; 910 911 // JMP_GTUri 912 case Hexagon::JMP_GTUriPt_nv_V4: 913 return Hexagon::JMP_GTUriPt_ie_nv_V4; 914 case Hexagon::JMP_GTUriNotPt_nv_V4: 915 return Hexagon::JMP_GTUriNotPt_ie_nv_V4; 916 case Hexagon::JMP_GTUriPnt_nv_V4: 917 return Hexagon::JMP_GTUriPnt_ie_nv_V4; 918 case Hexagon::JMP_GTUriNotPnt_nv_V4: 919 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4; 920 921 // JMP_GTUrr 922 case Hexagon::JMP_GTUrrPt_nv_V4: 923 return Hexagon::JMP_GTUrrPt_ie_nv_V4; 924 case Hexagon::JMP_GTUrrNotPt_nv_V4: 925 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4; 926 case Hexagon::JMP_GTUrrPnt_nv_V4: 927 return Hexagon::JMP_GTUrrPnt_ie_nv_V4; 928 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 929 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4; 930 931 // JMP_GTUrrdn 932 case Hexagon::JMP_GTUrrdnPt_nv_V4: 933 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4; 934 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 935 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4; 936 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 937 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4; 938 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 939 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4; 940 941 case Hexagon::TFR_FI: 942 return Hexagon::TFR_FI_immext_V4; 943 944 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 945 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 946 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 947 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 948 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 949 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 950 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 951 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 952 case Hexagon::MEMw_ADDi_MEM_V4 : 953 case Hexagon::MEMw_SUBi_MEM_V4 : 954 case Hexagon::MEMw_ADDr_MEM_V4 : 955 case Hexagon::MEMw_SUBr_MEM_V4 : 956 case Hexagon::MEMw_ANDr_MEM_V4 : 957 case Hexagon::MEMw_ORr_MEM_V4 : 958 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 959 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 960 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 961 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 962 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 963 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 964 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 965 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 966 case Hexagon::MEMh_ADDi_MEM_V4 : 967 case Hexagon::MEMh_SUBi_MEM_V4 : 968 case Hexagon::MEMh_ADDr_MEM_V4 : 969 case Hexagon::MEMh_SUBr_MEM_V4 : 970 case Hexagon::MEMh_ANDr_MEM_V4 : 971 case Hexagon::MEMh_ORr_MEM_V4 : 972 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 973 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 974 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 975 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 976 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 977 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 978 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 979 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 980 case Hexagon::MEMb_ADDi_MEM_V4 : 981 case Hexagon::MEMb_SUBi_MEM_V4 : 982 case Hexagon::MEMb_ADDr_MEM_V4 : 983 case Hexagon::MEMb_SUBr_MEM_V4 : 984 case Hexagon::MEMb_ANDr_MEM_V4 : 985 case Hexagon::MEMb_ORr_MEM_V4 : 986 llvm_unreachable("Needs implementing."); 987 } 988} 989 990unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const { 991 switch(MI->getOpcode()) { 992 default: llvm_unreachable("Unknown type of jump instruction."); 993 // JMP_EQri 994 case Hexagon::JMP_EQriPt_ie_nv_V4: 995 return Hexagon::JMP_EQriPt_nv_V4; 996 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 997 return Hexagon::JMP_EQriNotPt_nv_V4; 998 case Hexagon::JMP_EQriPnt_ie_nv_V4: 999 return Hexagon::JMP_EQriPnt_nv_V4; 1000 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 1001 return Hexagon::JMP_EQriNotPnt_nv_V4; 1002 1003 // JMP_EQri -- with -1 1004 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 1005 return Hexagon::JMP_EQriPtneg_nv_V4; 1006 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 1007 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1008 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 1009 return Hexagon::JMP_EQriPntneg_nv_V4; 1010 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 1011 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1012 1013 // JMP_EQrr 1014 case Hexagon::JMP_EQrrPt_ie_nv_V4: 1015 return Hexagon::JMP_EQrrPt_nv_V4; 1016 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 1017 return Hexagon::JMP_EQrrNotPt_nv_V4; 1018 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 1019 return Hexagon::JMP_EQrrPnt_nv_V4; 1020 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 1021 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1022 1023 // JMP_GTri 1024 case Hexagon::JMP_GTriPt_ie_nv_V4: 1025 return Hexagon::JMP_GTriPt_nv_V4; 1026 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 1027 return Hexagon::JMP_GTriNotPt_nv_V4; 1028 case Hexagon::JMP_GTriPnt_ie_nv_V4: 1029 return Hexagon::JMP_GTriPnt_nv_V4; 1030 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 1031 return Hexagon::JMP_GTriNotPnt_nv_V4; 1032 1033 // JMP_GTri -- with -1 1034 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 1035 return Hexagon::JMP_GTriPtneg_nv_V4; 1036 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 1037 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1038 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 1039 return Hexagon::JMP_GTriPntneg_nv_V4; 1040 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 1041 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1042 1043 // JMP_GTrr 1044 case Hexagon::JMP_GTrrPt_ie_nv_V4: 1045 return Hexagon::JMP_GTrrPt_nv_V4; 1046 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 1047 return Hexagon::JMP_GTrrNotPt_nv_V4; 1048 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 1049 return Hexagon::JMP_GTrrPnt_nv_V4; 1050 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 1051 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1052 1053 // JMP_GTrrdn 1054 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 1055 return Hexagon::JMP_GTrrdnPt_nv_V4; 1056 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 1057 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1058 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 1059 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1060 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 1061 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1062 1063 // JMP_GTUri 1064 case Hexagon::JMP_GTUriPt_ie_nv_V4: 1065 return Hexagon::JMP_GTUriPt_nv_V4; 1066 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 1067 return Hexagon::JMP_GTUriNotPt_nv_V4; 1068 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 1069 return Hexagon::JMP_GTUriPnt_nv_V4; 1070 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 1071 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1072 1073 // JMP_GTUrr 1074 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 1075 return Hexagon::JMP_GTUrrPt_nv_V4; 1076 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 1077 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1078 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 1079 return Hexagon::JMP_GTUrrPnt_nv_V4; 1080 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 1081 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1082 1083 // JMP_GTUrrdn 1084 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 1085 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1086 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 1087 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1088 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 1089 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1090 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 1091 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1092 } 1093} 1094 1095 1096bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { 1097 switch (MI->getOpcode()) { 1098 default: return false; 1099 // Store Byte 1100 case Hexagon::STrib_nv_V4: 1101 case Hexagon::STrib_indexed_nv_V4: 1102 case Hexagon::STrib_indexed_shl_nv_V4: 1103 case Hexagon::STrib_shl_nv_V4: 1104 case Hexagon::STrib_GP_nv_V4: 1105 case Hexagon::STb_GP_nv_V4: 1106 case Hexagon::POST_STbri_nv_V4: 1107 case Hexagon::STrib_cPt_nv_V4: 1108 case Hexagon::STrib_cdnPt_nv_V4: 1109 case Hexagon::STrib_cNotPt_nv_V4: 1110 case Hexagon::STrib_cdnNotPt_nv_V4: 1111 case Hexagon::STrib_indexed_cPt_nv_V4: 1112 case Hexagon::STrib_indexed_cdnPt_nv_V4: 1113 case Hexagon::STrib_indexed_cNotPt_nv_V4: 1114 case Hexagon::STrib_indexed_cdnNotPt_nv_V4: 1115 case Hexagon::STrib_indexed_shl_cPt_nv_V4: 1116 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: 1117 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: 1118 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: 1119 case Hexagon::POST_STbri_cPt_nv_V4: 1120 case Hexagon::POST_STbri_cdnPt_nv_V4: 1121 case Hexagon::POST_STbri_cNotPt_nv_V4: 1122 case Hexagon::POST_STbri_cdnNotPt_nv_V4: 1123 case Hexagon::STb_GP_cPt_nv_V4: 1124 case Hexagon::STb_GP_cNotPt_nv_V4: 1125 case Hexagon::STb_GP_cdnPt_nv_V4: 1126 case Hexagon::STb_GP_cdnNotPt_nv_V4: 1127 case Hexagon::STrib_GP_cPt_nv_V4: 1128 case Hexagon::STrib_GP_cNotPt_nv_V4: 1129 case Hexagon::STrib_GP_cdnPt_nv_V4: 1130 case Hexagon::STrib_GP_cdnNotPt_nv_V4: 1131 case Hexagon::STrib_abs_nv_V4: 1132 case Hexagon::STrib_abs_cPt_nv_V4: 1133 case Hexagon::STrib_abs_cdnPt_nv_V4: 1134 case Hexagon::STrib_abs_cNotPt_nv_V4: 1135 case Hexagon::STrib_abs_cdnNotPt_nv_V4: 1136 case Hexagon::STrib_imm_abs_nv_V4: 1137 case Hexagon::STrib_imm_abs_cPt_nv_V4: 1138 case Hexagon::STrib_imm_abs_cdnPt_nv_V4: 1139 case Hexagon::STrib_imm_abs_cNotPt_nv_V4: 1140 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: 1141 1142 // Store Halfword 1143 case Hexagon::STrih_nv_V4: 1144 case Hexagon::STrih_indexed_nv_V4: 1145 case Hexagon::STrih_indexed_shl_nv_V4: 1146 case Hexagon::STrih_shl_nv_V4: 1147 case Hexagon::STrih_GP_nv_V4: 1148 case Hexagon::STh_GP_nv_V4: 1149 case Hexagon::POST_SThri_nv_V4: 1150 case Hexagon::STrih_cPt_nv_V4: 1151 case Hexagon::STrih_cdnPt_nv_V4: 1152 case Hexagon::STrih_cNotPt_nv_V4: 1153 case Hexagon::STrih_cdnNotPt_nv_V4: 1154 case Hexagon::STrih_indexed_cPt_nv_V4: 1155 case Hexagon::STrih_indexed_cdnPt_nv_V4: 1156 case Hexagon::STrih_indexed_cNotPt_nv_V4: 1157 case Hexagon::STrih_indexed_cdnNotPt_nv_V4: 1158 case Hexagon::STrih_indexed_shl_cPt_nv_V4: 1159 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: 1160 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: 1161 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: 1162 case Hexagon::POST_SThri_cPt_nv_V4: 1163 case Hexagon::POST_SThri_cdnPt_nv_V4: 1164 case Hexagon::POST_SThri_cNotPt_nv_V4: 1165 case Hexagon::POST_SThri_cdnNotPt_nv_V4: 1166 case Hexagon::STh_GP_cPt_nv_V4: 1167 case Hexagon::STh_GP_cNotPt_nv_V4: 1168 case Hexagon::STh_GP_cdnPt_nv_V4: 1169 case Hexagon::STh_GP_cdnNotPt_nv_V4: 1170 case Hexagon::STrih_GP_cPt_nv_V4: 1171 case Hexagon::STrih_GP_cNotPt_nv_V4: 1172 case Hexagon::STrih_GP_cdnPt_nv_V4: 1173 case Hexagon::STrih_GP_cdnNotPt_nv_V4: 1174 case Hexagon::STrih_abs_nv_V4: 1175 case Hexagon::STrih_abs_cPt_nv_V4: 1176 case Hexagon::STrih_abs_cdnPt_nv_V4: 1177 case Hexagon::STrih_abs_cNotPt_nv_V4: 1178 case Hexagon::STrih_abs_cdnNotPt_nv_V4: 1179 case Hexagon::STrih_imm_abs_nv_V4: 1180 case Hexagon::STrih_imm_abs_cPt_nv_V4: 1181 case Hexagon::STrih_imm_abs_cdnPt_nv_V4: 1182 case Hexagon::STrih_imm_abs_cNotPt_nv_V4: 1183 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: 1184 1185 // Store Word 1186 case Hexagon::STriw_nv_V4: 1187 case Hexagon::STriw_indexed_nv_V4: 1188 case Hexagon::STriw_indexed_shl_nv_V4: 1189 case Hexagon::STriw_shl_nv_V4: 1190 case Hexagon::STriw_GP_nv_V4: 1191 case Hexagon::STw_GP_nv_V4: 1192 case Hexagon::POST_STwri_nv_V4: 1193 case Hexagon::STriw_cPt_nv_V4: 1194 case Hexagon::STriw_cdnPt_nv_V4: 1195 case Hexagon::STriw_cNotPt_nv_V4: 1196 case Hexagon::STriw_cdnNotPt_nv_V4: 1197 case Hexagon::STriw_indexed_cPt_nv_V4: 1198 case Hexagon::STriw_indexed_cdnPt_nv_V4: 1199 case Hexagon::STriw_indexed_cNotPt_nv_V4: 1200 case Hexagon::STriw_indexed_cdnNotPt_nv_V4: 1201 case Hexagon::STriw_indexed_shl_cPt_nv_V4: 1202 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: 1203 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: 1204 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: 1205 case Hexagon::POST_STwri_cPt_nv_V4: 1206 case Hexagon::POST_STwri_cdnPt_nv_V4: 1207 case Hexagon::POST_STwri_cNotPt_nv_V4: 1208 case Hexagon::POST_STwri_cdnNotPt_nv_V4: 1209 case Hexagon::STw_GP_cPt_nv_V4: 1210 case Hexagon::STw_GP_cNotPt_nv_V4: 1211 case Hexagon::STw_GP_cdnPt_nv_V4: 1212 case Hexagon::STw_GP_cdnNotPt_nv_V4: 1213 case Hexagon::STriw_GP_cPt_nv_V4: 1214 case Hexagon::STriw_GP_cNotPt_nv_V4: 1215 case Hexagon::STriw_GP_cdnPt_nv_V4: 1216 case Hexagon::STriw_GP_cdnNotPt_nv_V4: 1217 case Hexagon::STriw_abs_nv_V4: 1218 case Hexagon::STriw_abs_cPt_nv_V4: 1219 case Hexagon::STriw_abs_cdnPt_nv_V4: 1220 case Hexagon::STriw_abs_cNotPt_nv_V4: 1221 case Hexagon::STriw_abs_cdnNotPt_nv_V4: 1222 case Hexagon::STriw_imm_abs_nv_V4: 1223 case Hexagon::STriw_imm_abs_cPt_nv_V4: 1224 case Hexagon::STriw_imm_abs_cdnPt_nv_V4: 1225 case Hexagon::STriw_imm_abs_cNotPt_nv_V4: 1226 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: 1227 return true; 1228 } 1229} 1230 1231bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { 1232 switch (MI->getOpcode()) 1233 { 1234 default: return false; 1235 // Load Byte 1236 case Hexagon::POST_LDrib: 1237 case Hexagon::POST_LDrib_cPt: 1238 case Hexagon::POST_LDrib_cNotPt: 1239 case Hexagon::POST_LDrib_cdnPt_V4: 1240 case Hexagon::POST_LDrib_cdnNotPt_V4: 1241 1242 // Load unsigned byte 1243 case Hexagon::POST_LDriub: 1244 case Hexagon::POST_LDriub_cPt: 1245 case Hexagon::POST_LDriub_cNotPt: 1246 case Hexagon::POST_LDriub_cdnPt_V4: 1247 case Hexagon::POST_LDriub_cdnNotPt_V4: 1248 1249 // Load halfword 1250 case Hexagon::POST_LDrih: 1251 case Hexagon::POST_LDrih_cPt: 1252 case Hexagon::POST_LDrih_cNotPt: 1253 case Hexagon::POST_LDrih_cdnPt_V4: 1254 case Hexagon::POST_LDrih_cdnNotPt_V4: 1255 1256 // Load unsigned halfword 1257 case Hexagon::POST_LDriuh: 1258 case Hexagon::POST_LDriuh_cPt: 1259 case Hexagon::POST_LDriuh_cNotPt: 1260 case Hexagon::POST_LDriuh_cdnPt_V4: 1261 case Hexagon::POST_LDriuh_cdnNotPt_V4: 1262 1263 // Load word 1264 case Hexagon::POST_LDriw: 1265 case Hexagon::POST_LDriw_cPt: 1266 case Hexagon::POST_LDriw_cNotPt: 1267 case Hexagon::POST_LDriw_cdnPt_V4: 1268 case Hexagon::POST_LDriw_cdnNotPt_V4: 1269 1270 // Load double word 1271 case Hexagon::POST_LDrid: 1272 case Hexagon::POST_LDrid_cPt: 1273 case Hexagon::POST_LDrid_cNotPt: 1274 case Hexagon::POST_LDrid_cdnPt_V4: 1275 case Hexagon::POST_LDrid_cdnNotPt_V4: 1276 1277 // Store byte 1278 case Hexagon::POST_STbri: 1279 case Hexagon::POST_STbri_cPt: 1280 case Hexagon::POST_STbri_cNotPt: 1281 case Hexagon::POST_STbri_cdnPt_V4: 1282 case Hexagon::POST_STbri_cdnNotPt_V4: 1283 1284 // Store halfword 1285 case Hexagon::POST_SThri: 1286 case Hexagon::POST_SThri_cPt: 1287 case Hexagon::POST_SThri_cNotPt: 1288 case Hexagon::POST_SThri_cdnPt_V4: 1289 case Hexagon::POST_SThri_cdnNotPt_V4: 1290 1291 // Store word 1292 case Hexagon::POST_STwri: 1293 case Hexagon::POST_STwri_cPt: 1294 case Hexagon::POST_STwri_cNotPt: 1295 case Hexagon::POST_STwri_cdnPt_V4: 1296 case Hexagon::POST_STwri_cdnNotPt_V4: 1297 1298 // Store double word 1299 case Hexagon::POST_STdri: 1300 case Hexagon::POST_STdri_cPt: 1301 case Hexagon::POST_STdri_cNotPt: 1302 case Hexagon::POST_STdri_cdnPt_V4: 1303 case Hexagon::POST_STdri_cdnNotPt_V4: 1304 return true; 1305 } 1306} 1307 1308bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { 1309 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; 1310} 1311 1312bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { 1313 bool isPred = MI->getDesc().isPredicable(); 1314 1315 if (!isPred) 1316 return false; 1317 1318 const int Opc = MI->getOpcode(); 1319 1320 switch(Opc) { 1321 case Hexagon::TFRI: 1322 return isInt<12>(MI->getOperand(1).getImm()); 1323 1324 case Hexagon::STrid: 1325 case Hexagon::STrid_indexed: 1326 return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); 1327 1328 case Hexagon::STriw: 1329 case Hexagon::STriw_indexed: 1330 case Hexagon::STriw_nv_V4: 1331 return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); 1332 1333 case Hexagon::STrih: 1334 case Hexagon::STrih_indexed: 1335 case Hexagon::STrih_nv_V4: 1336 return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); 1337 1338 case Hexagon::STrib: 1339 case Hexagon::STrib_indexed: 1340 case Hexagon::STrib_nv_V4: 1341 return isUInt<6>(MI->getOperand(1).getImm()); 1342 1343 case Hexagon::LDrid: 1344 case Hexagon::LDrid_indexed: 1345 return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); 1346 1347 case Hexagon::LDriw: 1348 case Hexagon::LDriw_indexed: 1349 return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); 1350 1351 case Hexagon::LDrih: 1352 case Hexagon::LDriuh: 1353 case Hexagon::LDrih_indexed: 1354 case Hexagon::LDriuh_indexed: 1355 return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); 1356 1357 case Hexagon::LDrib: 1358 case Hexagon::LDriub: 1359 case Hexagon::LDrib_indexed: 1360 case Hexagon::LDriub_indexed: 1361 return isUInt<6>(MI->getOperand(2).getImm()); 1362 1363 case Hexagon::POST_LDrid: 1364 return isShiftedInt<4,3>(MI->getOperand(3).getImm()); 1365 1366 case Hexagon::POST_LDriw: 1367 return isShiftedInt<4,2>(MI->getOperand(3).getImm()); 1368 1369 case Hexagon::POST_LDrih: 1370 case Hexagon::POST_LDriuh: 1371 return isShiftedInt<4,1>(MI->getOperand(3).getImm()); 1372 1373 case Hexagon::POST_LDrib: 1374 case Hexagon::POST_LDriub: 1375 return isInt<4>(MI->getOperand(3).getImm()); 1376 1377 case Hexagon::STrib_imm_V4: 1378 case Hexagon::STrih_imm_V4: 1379 case Hexagon::STriw_imm_V4: 1380 return (isUInt<6>(MI->getOperand(1).getImm()) && 1381 isInt<6>(MI->getOperand(2).getImm())); 1382 1383 case Hexagon::ADD_ri: 1384 return isInt<8>(MI->getOperand(2).getImm()); 1385 1386 case Hexagon::ASLH: 1387 case Hexagon::ASRH: 1388 case Hexagon::SXTB: 1389 case Hexagon::SXTH: 1390 case Hexagon::ZXTB: 1391 case Hexagon::ZXTH: 1392 return Subtarget.hasV4TOps(); 1393 1394 case Hexagon::JMPR: 1395 return false; 1396 } 1397 1398 return true; 1399} 1400 1401// This function performs the following inversiones: 1402// 1403// cPt ---> cNotPt 1404// cNotPt ---> cPt 1405// 1406// however, these inversiones are NOT included: 1407// 1408// cdnPt -X-> cdnNotPt 1409// cdnNotPt -X-> cdnPt 1410// cPt_nv -X-> cNotPt_nv (new value stores) 1411// cNotPt_nv -X-> cPt_nv (new value stores) 1412// 1413// because only the following transformations are allowed: 1414// 1415// cNotPt ---> cdnNotPt 1416// cPt ---> cdnPt 1417// cNotPt ---> cNotPt_nv 1418// cPt ---> cPt_nv 1419unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { 1420 switch(Opc) { 1421 default: llvm_unreachable("Unexpected predicated instruction"); 1422 case Hexagon::TFR_cPt: 1423 return Hexagon::TFR_cNotPt; 1424 case Hexagon::TFR_cNotPt: 1425 return Hexagon::TFR_cPt; 1426 1427 case Hexagon::TFRI_cPt: 1428 return Hexagon::TFRI_cNotPt; 1429 case Hexagon::TFRI_cNotPt: 1430 return Hexagon::TFRI_cPt; 1431 1432 case Hexagon::JMP_c: 1433 return Hexagon::JMP_cNot; 1434 case Hexagon::JMP_cNot: 1435 return Hexagon::JMP_c; 1436 1437 case Hexagon::ADD_ri_cPt: 1438 return Hexagon::ADD_ri_cNotPt; 1439 case Hexagon::ADD_ri_cNotPt: 1440 return Hexagon::ADD_ri_cPt; 1441 1442 case Hexagon::ADD_rr_cPt: 1443 return Hexagon::ADD_rr_cNotPt; 1444 case Hexagon::ADD_rr_cNotPt: 1445 return Hexagon::ADD_rr_cPt; 1446 1447 case Hexagon::XOR_rr_cPt: 1448 return Hexagon::XOR_rr_cNotPt; 1449 case Hexagon::XOR_rr_cNotPt: 1450 return Hexagon::XOR_rr_cPt; 1451 1452 case Hexagon::AND_rr_cPt: 1453 return Hexagon::AND_rr_cNotPt; 1454 case Hexagon::AND_rr_cNotPt: 1455 return Hexagon::AND_rr_cPt; 1456 1457 case Hexagon::OR_rr_cPt: 1458 return Hexagon::OR_rr_cNotPt; 1459 case Hexagon::OR_rr_cNotPt: 1460 return Hexagon::OR_rr_cPt; 1461 1462 case Hexagon::SUB_rr_cPt: 1463 return Hexagon::SUB_rr_cNotPt; 1464 case Hexagon::SUB_rr_cNotPt: 1465 return Hexagon::SUB_rr_cPt; 1466 1467 case Hexagon::COMBINE_rr_cPt: 1468 return Hexagon::COMBINE_rr_cNotPt; 1469 case Hexagon::COMBINE_rr_cNotPt: 1470 return Hexagon::COMBINE_rr_cPt; 1471 1472 case Hexagon::ASLH_cPt_V4: 1473 return Hexagon::ASLH_cNotPt_V4; 1474 case Hexagon::ASLH_cNotPt_V4: 1475 return Hexagon::ASLH_cPt_V4; 1476 1477 case Hexagon::ASRH_cPt_V4: 1478 return Hexagon::ASRH_cNotPt_V4; 1479 case Hexagon::ASRH_cNotPt_V4: 1480 return Hexagon::ASRH_cPt_V4; 1481 1482 case Hexagon::SXTB_cPt_V4: 1483 return Hexagon::SXTB_cNotPt_V4; 1484 case Hexagon::SXTB_cNotPt_V4: 1485 return Hexagon::SXTB_cPt_V4; 1486 1487 case Hexagon::SXTH_cPt_V4: 1488 return Hexagon::SXTH_cNotPt_V4; 1489 case Hexagon::SXTH_cNotPt_V4: 1490 return Hexagon::SXTH_cPt_V4; 1491 1492 case Hexagon::ZXTB_cPt_V4: 1493 return Hexagon::ZXTB_cNotPt_V4; 1494 case Hexagon::ZXTB_cNotPt_V4: 1495 return Hexagon::ZXTB_cPt_V4; 1496 1497 case Hexagon::ZXTH_cPt_V4: 1498 return Hexagon::ZXTH_cNotPt_V4; 1499 case Hexagon::ZXTH_cNotPt_V4: 1500 return Hexagon::ZXTH_cPt_V4; 1501 1502 1503 case Hexagon::JMPR_cPt: 1504 return Hexagon::JMPR_cNotPt; 1505 case Hexagon::JMPR_cNotPt: 1506 return Hexagon::JMPR_cPt; 1507 1508 // V4 indexed+scaled load. 1509 case Hexagon::LDrid_indexed_cPt_V4: 1510 return Hexagon::LDrid_indexed_cNotPt_V4; 1511 case Hexagon::LDrid_indexed_cNotPt_V4: 1512 return Hexagon::LDrid_indexed_cPt_V4; 1513 1514 case Hexagon::LDrid_indexed_shl_cPt_V4: 1515 return Hexagon::LDrid_indexed_shl_cNotPt_V4; 1516 case Hexagon::LDrid_indexed_shl_cNotPt_V4: 1517 return Hexagon::LDrid_indexed_shl_cPt_V4; 1518 1519 case Hexagon::LDrib_indexed_cPt_V4: 1520 return Hexagon::LDrib_indexed_cNotPt_V4; 1521 case Hexagon::LDrib_indexed_cNotPt_V4: 1522 return Hexagon::LDrib_indexed_cPt_V4; 1523 1524 case Hexagon::LDriub_indexed_cPt_V4: 1525 return Hexagon::LDriub_indexed_cNotPt_V4; 1526 case Hexagon::LDriub_indexed_cNotPt_V4: 1527 return Hexagon::LDriub_indexed_cPt_V4; 1528 1529 case Hexagon::LDrib_indexed_shl_cPt_V4: 1530 return Hexagon::LDrib_indexed_shl_cNotPt_V4; 1531 case Hexagon::LDrib_indexed_shl_cNotPt_V4: 1532 return Hexagon::LDrib_indexed_shl_cPt_V4; 1533 1534 case Hexagon::LDriub_indexed_shl_cPt_V4: 1535 return Hexagon::LDriub_indexed_shl_cNotPt_V4; 1536 case Hexagon::LDriub_indexed_shl_cNotPt_V4: 1537 return Hexagon::LDriub_indexed_shl_cPt_V4; 1538 1539 case Hexagon::LDrih_indexed_cPt_V4: 1540 return Hexagon::LDrih_indexed_cNotPt_V4; 1541 case Hexagon::LDrih_indexed_cNotPt_V4: 1542 return Hexagon::LDrih_indexed_cPt_V4; 1543 1544 case Hexagon::LDriuh_indexed_cPt_V4: 1545 return Hexagon::LDriuh_indexed_cNotPt_V4; 1546 case Hexagon::LDriuh_indexed_cNotPt_V4: 1547 return Hexagon::LDriuh_indexed_cPt_V4; 1548 1549 case Hexagon::LDrih_indexed_shl_cPt_V4: 1550 return Hexagon::LDrih_indexed_shl_cNotPt_V4; 1551 case Hexagon::LDrih_indexed_shl_cNotPt_V4: 1552 return Hexagon::LDrih_indexed_shl_cPt_V4; 1553 1554 case Hexagon::LDriuh_indexed_shl_cPt_V4: 1555 return Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1556 case Hexagon::LDriuh_indexed_shl_cNotPt_V4: 1557 return Hexagon::LDriuh_indexed_shl_cPt_V4; 1558 1559 case Hexagon::LDriw_indexed_cPt_V4: 1560 return Hexagon::LDriw_indexed_cNotPt_V4; 1561 case Hexagon::LDriw_indexed_cNotPt_V4: 1562 return Hexagon::LDriw_indexed_cPt_V4; 1563 1564 case Hexagon::LDriw_indexed_shl_cPt_V4: 1565 return Hexagon::LDriw_indexed_shl_cNotPt_V4; 1566 case Hexagon::LDriw_indexed_shl_cNotPt_V4: 1567 return Hexagon::LDriw_indexed_shl_cPt_V4; 1568 1569 // Byte. 1570 case Hexagon::POST_STbri_cPt: 1571 return Hexagon::POST_STbri_cNotPt; 1572 case Hexagon::POST_STbri_cNotPt: 1573 return Hexagon::POST_STbri_cPt; 1574 1575 case Hexagon::STrib_cPt: 1576 return Hexagon::STrib_cNotPt; 1577 case Hexagon::STrib_cNotPt: 1578 return Hexagon::STrib_cPt; 1579 1580 case Hexagon::STrib_indexed_cPt: 1581 return Hexagon::STrib_indexed_cNotPt; 1582 case Hexagon::STrib_indexed_cNotPt: 1583 return Hexagon::STrib_indexed_cPt; 1584 1585 case Hexagon::STrib_imm_cPt_V4: 1586 return Hexagon::STrib_imm_cNotPt_V4; 1587 case Hexagon::STrib_imm_cNotPt_V4: 1588 return Hexagon::STrib_imm_cPt_V4; 1589 1590 case Hexagon::STrib_indexed_shl_cPt_V4: 1591 return Hexagon::STrib_indexed_shl_cNotPt_V4; 1592 case Hexagon::STrib_indexed_shl_cNotPt_V4: 1593 return Hexagon::STrib_indexed_shl_cPt_V4; 1594 1595 // Halfword. 1596 case Hexagon::POST_SThri_cPt: 1597 return Hexagon::POST_SThri_cNotPt; 1598 case Hexagon::POST_SThri_cNotPt: 1599 return Hexagon::POST_SThri_cPt; 1600 1601 case Hexagon::STrih_cPt: 1602 return Hexagon::STrih_cNotPt; 1603 case Hexagon::STrih_cNotPt: 1604 return Hexagon::STrih_cPt; 1605 1606 case Hexagon::STrih_indexed_cPt: 1607 return Hexagon::STrih_indexed_cNotPt; 1608 case Hexagon::STrih_indexed_cNotPt: 1609 return Hexagon::STrih_indexed_cPt; 1610 1611 case Hexagon::STrih_imm_cPt_V4: 1612 return Hexagon::STrih_imm_cNotPt_V4; 1613 case Hexagon::STrih_imm_cNotPt_V4: 1614 return Hexagon::STrih_imm_cPt_V4; 1615 1616 case Hexagon::STrih_indexed_shl_cPt_V4: 1617 return Hexagon::STrih_indexed_shl_cNotPt_V4; 1618 case Hexagon::STrih_indexed_shl_cNotPt_V4: 1619 return Hexagon::STrih_indexed_shl_cPt_V4; 1620 1621 // Word. 1622 case Hexagon::POST_STwri_cPt: 1623 return Hexagon::POST_STwri_cNotPt; 1624 case Hexagon::POST_STwri_cNotPt: 1625 return Hexagon::POST_STwri_cPt; 1626 1627 case Hexagon::STriw_cPt: 1628 return Hexagon::STriw_cNotPt; 1629 case Hexagon::STriw_cNotPt: 1630 return Hexagon::STriw_cPt; 1631 1632 case Hexagon::STriw_indexed_cPt: 1633 return Hexagon::STriw_indexed_cNotPt; 1634 case Hexagon::STriw_indexed_cNotPt: 1635 return Hexagon::STriw_indexed_cPt; 1636 1637 case Hexagon::STriw_indexed_shl_cPt_V4: 1638 return Hexagon::STriw_indexed_shl_cNotPt_V4; 1639 case Hexagon::STriw_indexed_shl_cNotPt_V4: 1640 return Hexagon::STriw_indexed_shl_cPt_V4; 1641 1642 case Hexagon::STriw_imm_cPt_V4: 1643 return Hexagon::STriw_imm_cNotPt_V4; 1644 case Hexagon::STriw_imm_cNotPt_V4: 1645 return Hexagon::STriw_imm_cPt_V4; 1646 1647 // Double word. 1648 case Hexagon::POST_STdri_cPt: 1649 return Hexagon::POST_STdri_cNotPt; 1650 case Hexagon::POST_STdri_cNotPt: 1651 return Hexagon::POST_STdri_cPt; 1652 1653 case Hexagon::STrid_cPt: 1654 return Hexagon::STrid_cNotPt; 1655 case Hexagon::STrid_cNotPt: 1656 return Hexagon::STrid_cPt; 1657 1658 case Hexagon::STrid_indexed_cPt: 1659 return Hexagon::STrid_indexed_cNotPt; 1660 case Hexagon::STrid_indexed_cNotPt: 1661 return Hexagon::STrid_indexed_cPt; 1662 1663 case Hexagon::STrid_indexed_shl_cPt_V4: 1664 return Hexagon::STrid_indexed_shl_cNotPt_V4; 1665 case Hexagon::STrid_indexed_shl_cNotPt_V4: 1666 return Hexagon::STrid_indexed_shl_cPt_V4; 1667 1668 // V4 Store to global address. 1669 case Hexagon::STd_GP_cPt_V4: 1670 return Hexagon::STd_GP_cNotPt_V4; 1671 case Hexagon::STd_GP_cNotPt_V4: 1672 return Hexagon::STd_GP_cPt_V4; 1673 1674 case Hexagon::STb_GP_cPt_V4: 1675 return Hexagon::STb_GP_cNotPt_V4; 1676 case Hexagon::STb_GP_cNotPt_V4: 1677 return Hexagon::STb_GP_cPt_V4; 1678 1679 case Hexagon::STh_GP_cPt_V4: 1680 return Hexagon::STh_GP_cNotPt_V4; 1681 case Hexagon::STh_GP_cNotPt_V4: 1682 return Hexagon::STh_GP_cPt_V4; 1683 1684 case Hexagon::STw_GP_cPt_V4: 1685 return Hexagon::STw_GP_cNotPt_V4; 1686 case Hexagon::STw_GP_cNotPt_V4: 1687 return Hexagon::STw_GP_cPt_V4; 1688 1689 case Hexagon::STrid_GP_cPt_V4: 1690 return Hexagon::STrid_GP_cNotPt_V4; 1691 case Hexagon::STrid_GP_cNotPt_V4: 1692 return Hexagon::STrid_GP_cPt_V4; 1693 1694 case Hexagon::STrib_GP_cPt_V4: 1695 return Hexagon::STrib_GP_cNotPt_V4; 1696 case Hexagon::STrib_GP_cNotPt_V4: 1697 return Hexagon::STrib_GP_cPt_V4; 1698 1699 case Hexagon::STrih_GP_cPt_V4: 1700 return Hexagon::STrih_GP_cNotPt_V4; 1701 case Hexagon::STrih_GP_cNotPt_V4: 1702 return Hexagon::STrih_GP_cPt_V4; 1703 1704 case Hexagon::STriw_GP_cPt_V4: 1705 return Hexagon::STriw_GP_cNotPt_V4; 1706 case Hexagon::STriw_GP_cNotPt_V4: 1707 return Hexagon::STriw_GP_cPt_V4; 1708 1709 // Load. 1710 case Hexagon::LDrid_cPt: 1711 return Hexagon::LDrid_cNotPt; 1712 case Hexagon::LDrid_cNotPt: 1713 return Hexagon::LDrid_cPt; 1714 1715 case Hexagon::LDriw_cPt: 1716 return Hexagon::LDriw_cNotPt; 1717 case Hexagon::LDriw_cNotPt: 1718 return Hexagon::LDriw_cPt; 1719 1720 case Hexagon::LDrih_cPt: 1721 return Hexagon::LDrih_cNotPt; 1722 case Hexagon::LDrih_cNotPt: 1723 return Hexagon::LDrih_cPt; 1724 1725 case Hexagon::LDriuh_cPt: 1726 return Hexagon::LDriuh_cNotPt; 1727 case Hexagon::LDriuh_cNotPt: 1728 return Hexagon::LDriuh_cPt; 1729 1730 case Hexagon::LDrib_cPt: 1731 return Hexagon::LDrib_cNotPt; 1732 case Hexagon::LDrib_cNotPt: 1733 return Hexagon::LDrib_cPt; 1734 1735 case Hexagon::LDriub_cPt: 1736 return Hexagon::LDriub_cNotPt; 1737 case Hexagon::LDriub_cNotPt: 1738 return Hexagon::LDriub_cPt; 1739 1740 // Load Indexed. 1741 case Hexagon::LDrid_indexed_cPt: 1742 return Hexagon::LDrid_indexed_cNotPt; 1743 case Hexagon::LDrid_indexed_cNotPt: 1744 return Hexagon::LDrid_indexed_cPt; 1745 1746 case Hexagon::LDriw_indexed_cPt: 1747 return Hexagon::LDriw_indexed_cNotPt; 1748 case Hexagon::LDriw_indexed_cNotPt: 1749 return Hexagon::LDriw_indexed_cPt; 1750 1751 case Hexagon::LDrih_indexed_cPt: 1752 return Hexagon::LDrih_indexed_cNotPt; 1753 case Hexagon::LDrih_indexed_cNotPt: 1754 return Hexagon::LDrih_indexed_cPt; 1755 1756 case Hexagon::LDriuh_indexed_cPt: 1757 return Hexagon::LDriuh_indexed_cNotPt; 1758 case Hexagon::LDriuh_indexed_cNotPt: 1759 return Hexagon::LDriuh_indexed_cPt; 1760 1761 case Hexagon::LDrib_indexed_cPt: 1762 return Hexagon::LDrib_indexed_cNotPt; 1763 case Hexagon::LDrib_indexed_cNotPt: 1764 return Hexagon::LDrib_indexed_cPt; 1765 1766 case Hexagon::LDriub_indexed_cPt: 1767 return Hexagon::LDriub_indexed_cNotPt; 1768 case Hexagon::LDriub_indexed_cNotPt: 1769 return Hexagon::LDriub_indexed_cPt; 1770 1771 // Post Inc Load. 1772 case Hexagon::POST_LDrid_cPt: 1773 return Hexagon::POST_LDrid_cNotPt; 1774 case Hexagon::POST_LDriw_cNotPt: 1775 return Hexagon::POST_LDriw_cPt; 1776 1777 case Hexagon::POST_LDrih_cPt: 1778 return Hexagon::POST_LDrih_cNotPt; 1779 case Hexagon::POST_LDrih_cNotPt: 1780 return Hexagon::POST_LDrih_cPt; 1781 1782 case Hexagon::POST_LDriuh_cPt: 1783 return Hexagon::POST_LDriuh_cNotPt; 1784 case Hexagon::POST_LDriuh_cNotPt: 1785 return Hexagon::POST_LDriuh_cPt; 1786 1787 case Hexagon::POST_LDrib_cPt: 1788 return Hexagon::POST_LDrib_cNotPt; 1789 case Hexagon::POST_LDrib_cNotPt: 1790 return Hexagon::POST_LDrib_cPt; 1791 1792 case Hexagon::POST_LDriub_cPt: 1793 return Hexagon::POST_LDriub_cNotPt; 1794 case Hexagon::POST_LDriub_cNotPt: 1795 return Hexagon::POST_LDriub_cPt; 1796 1797 // Dealloc_return. 1798 case Hexagon::DEALLOC_RET_cPt_V4: 1799 return Hexagon::DEALLOC_RET_cNotPt_V4; 1800 case Hexagon::DEALLOC_RET_cNotPt_V4: 1801 return Hexagon::DEALLOC_RET_cPt_V4; 1802 1803 // New Value Jump. 1804 // JMPEQ_ri - with -1. 1805 case Hexagon::JMP_EQriPtneg_nv_V4: 1806 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1807 case Hexagon::JMP_EQriNotPtneg_nv_V4: 1808 return Hexagon::JMP_EQriPtneg_nv_V4; 1809 1810 case Hexagon::JMP_EQriPntneg_nv_V4: 1811 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1812 case Hexagon::JMP_EQriNotPntneg_nv_V4: 1813 return Hexagon::JMP_EQriPntneg_nv_V4; 1814 1815 // JMPEQ_ri. 1816 case Hexagon::JMP_EQriPt_nv_V4: 1817 return Hexagon::JMP_EQriNotPt_nv_V4; 1818 case Hexagon::JMP_EQriNotPt_nv_V4: 1819 return Hexagon::JMP_EQriPt_nv_V4; 1820 1821 case Hexagon::JMP_EQriPnt_nv_V4: 1822 return Hexagon::JMP_EQriNotPnt_nv_V4; 1823 case Hexagon::JMP_EQriNotPnt_nv_V4: 1824 return Hexagon::JMP_EQriPnt_nv_V4; 1825 1826 // JMPEQ_rr. 1827 case Hexagon::JMP_EQrrPt_nv_V4: 1828 return Hexagon::JMP_EQrrNotPt_nv_V4; 1829 case Hexagon::JMP_EQrrNotPt_nv_V4: 1830 return Hexagon::JMP_EQrrPt_nv_V4; 1831 1832 case Hexagon::JMP_EQrrPnt_nv_V4: 1833 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1834 case Hexagon::JMP_EQrrNotPnt_nv_V4: 1835 return Hexagon::JMP_EQrrPnt_nv_V4; 1836 1837 // JMPGT_ri - with -1. 1838 case Hexagon::JMP_GTriPtneg_nv_V4: 1839 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1840 case Hexagon::JMP_GTriNotPtneg_nv_V4: 1841 return Hexagon::JMP_GTriPtneg_nv_V4; 1842 1843 case Hexagon::JMP_GTriPntneg_nv_V4: 1844 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1845 case Hexagon::JMP_GTriNotPntneg_nv_V4: 1846 return Hexagon::JMP_GTriPntneg_nv_V4; 1847 1848 // JMPGT_ri. 1849 case Hexagon::JMP_GTriPt_nv_V4: 1850 return Hexagon::JMP_GTriNotPt_nv_V4; 1851 case Hexagon::JMP_GTriNotPt_nv_V4: 1852 return Hexagon::JMP_GTriPt_nv_V4; 1853 1854 case Hexagon::JMP_GTriPnt_nv_V4: 1855 return Hexagon::JMP_GTriNotPnt_nv_V4; 1856 case Hexagon::JMP_GTriNotPnt_nv_V4: 1857 return Hexagon::JMP_GTriPnt_nv_V4; 1858 1859 // JMPGT_rr. 1860 case Hexagon::JMP_GTrrPt_nv_V4: 1861 return Hexagon::JMP_GTrrNotPt_nv_V4; 1862 case Hexagon::JMP_GTrrNotPt_nv_V4: 1863 return Hexagon::JMP_GTrrPt_nv_V4; 1864 1865 case Hexagon::JMP_GTrrPnt_nv_V4: 1866 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1867 case Hexagon::JMP_GTrrNotPnt_nv_V4: 1868 return Hexagon::JMP_GTrrPnt_nv_V4; 1869 1870 // JMPGT_rrdn. 1871 case Hexagon::JMP_GTrrdnPt_nv_V4: 1872 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1873 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 1874 return Hexagon::JMP_GTrrdnPt_nv_V4; 1875 1876 case Hexagon::JMP_GTrrdnPnt_nv_V4: 1877 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1878 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 1879 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1880 1881 // JMPGTU_ri. 1882 case Hexagon::JMP_GTUriPt_nv_V4: 1883 return Hexagon::JMP_GTUriNotPt_nv_V4; 1884 case Hexagon::JMP_GTUriNotPt_nv_V4: 1885 return Hexagon::JMP_GTUriPt_nv_V4; 1886 1887 case Hexagon::JMP_GTUriPnt_nv_V4: 1888 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1889 case Hexagon::JMP_GTUriNotPnt_nv_V4: 1890 return Hexagon::JMP_GTUriPnt_nv_V4; 1891 1892 // JMPGTU_rr. 1893 case Hexagon::JMP_GTUrrPt_nv_V4: 1894 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1895 case Hexagon::JMP_GTUrrNotPt_nv_V4: 1896 return Hexagon::JMP_GTUrrPt_nv_V4; 1897 1898 case Hexagon::JMP_GTUrrPnt_nv_V4: 1899 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1900 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 1901 return Hexagon::JMP_GTUrrPnt_nv_V4; 1902 1903 // JMPGTU_rrdn. 1904 case Hexagon::JMP_GTUrrdnPt_nv_V4: 1905 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1906 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 1907 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1908 1909 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 1910 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1911 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 1912 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1913 } 1914} 1915 1916 1917int HexagonInstrInfo:: 1918getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { 1919 enum Hexagon::PredSense inPredSense; 1920 inPredSense = invertPredicate ? Hexagon::PredSense_false : 1921 Hexagon::PredSense_true; 1922 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); 1923 if (CondOpcode >= 0) // Valid Conditional opcode/instruction 1924 return CondOpcode; 1925 1926 // This switch case will be removed once all the instructions have been 1927 // modified to use relation maps. 1928 switch(Opc) { 1929 case Hexagon::TFR: 1930 return !invertPredicate ? Hexagon::TFR_cPt : 1931 Hexagon::TFR_cNotPt; 1932 case Hexagon::TFRI_f: 1933 return !invertPredicate ? Hexagon::TFRI_cPt_f : 1934 Hexagon::TFRI_cNotPt_f; 1935 case Hexagon::TFRI: 1936 return !invertPredicate ? Hexagon::TFRI_cPt : 1937 Hexagon::TFRI_cNotPt; 1938 case Hexagon::JMP: 1939 return !invertPredicate ? Hexagon::JMP_c : 1940 Hexagon::JMP_cNot; 1941 case Hexagon::JMP_EQrrPt_nv_V4: 1942 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : 1943 Hexagon::JMP_EQrrNotPt_nv_V4; 1944 case Hexagon::JMP_EQriPt_nv_V4: 1945 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : 1946 Hexagon::JMP_EQriNotPt_nv_V4; 1947 case Hexagon::COMBINE_rr: 1948 return !invertPredicate ? Hexagon::COMBINE_rr_cPt : 1949 Hexagon::COMBINE_rr_cNotPt; 1950 case Hexagon::ASLH: 1951 return !invertPredicate ? Hexagon::ASLH_cPt_V4 : 1952 Hexagon::ASLH_cNotPt_V4; 1953 case Hexagon::ASRH: 1954 return !invertPredicate ? Hexagon::ASRH_cPt_V4 : 1955 Hexagon::ASRH_cNotPt_V4; 1956 case Hexagon::SXTB: 1957 return !invertPredicate ? Hexagon::SXTB_cPt_V4 : 1958 Hexagon::SXTB_cNotPt_V4; 1959 case Hexagon::SXTH: 1960 return !invertPredicate ? Hexagon::SXTH_cPt_V4 : 1961 Hexagon::SXTH_cNotPt_V4; 1962 case Hexagon::ZXTB: 1963 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 : 1964 Hexagon::ZXTB_cNotPt_V4; 1965 case Hexagon::ZXTH: 1966 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 : 1967 Hexagon::ZXTH_cNotPt_V4; 1968 1969 case Hexagon::JMPR: 1970 return !invertPredicate ? Hexagon::JMPR_cPt : 1971 Hexagon::JMPR_cNotPt; 1972 1973 // V4 indexed+scaled load. 1974 case Hexagon::LDrid_indexed_V4: 1975 return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 : 1976 Hexagon::LDrid_indexed_cNotPt_V4; 1977 case Hexagon::LDrid_indexed_shl_V4: 1978 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 : 1979 Hexagon::LDrid_indexed_shl_cNotPt_V4; 1980 case Hexagon::LDrib_indexed_V4: 1981 return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 : 1982 Hexagon::LDrib_indexed_cNotPt_V4; 1983 case Hexagon::LDriub_indexed_V4: 1984 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1985 Hexagon::LDriub_indexed_cNotPt_V4; 1986 case Hexagon::LDriub_ae_indexed_V4: 1987 return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 : 1988 Hexagon::LDriub_indexed_cNotPt_V4; 1989 case Hexagon::LDrib_indexed_shl_V4: 1990 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 : 1991 Hexagon::LDrib_indexed_shl_cNotPt_V4; 1992 case Hexagon::LDriub_indexed_shl_V4: 1993 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1994 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1995 case Hexagon::LDriub_ae_indexed_shl_V4: 1996 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1997 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1998 case Hexagon::LDrih_indexed_V4: 1999 return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 : 2000 Hexagon::LDrih_indexed_cNotPt_V4; 2001 case Hexagon::LDriuh_indexed_V4: 2002 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 2003 Hexagon::LDriuh_indexed_cNotPt_V4; 2004 case Hexagon::LDriuh_ae_indexed_V4: 2005 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 : 2006 Hexagon::LDriuh_indexed_cNotPt_V4; 2007 case Hexagon::LDrih_indexed_shl_V4: 2008 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 : 2009 Hexagon::LDrih_indexed_shl_cNotPt_V4; 2010 case Hexagon::LDriuh_indexed_shl_V4: 2011 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2012 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2013 case Hexagon::LDriuh_ae_indexed_shl_V4: 2014 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 2015 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 2016 case Hexagon::LDriw_indexed_V4: 2017 return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 : 2018 Hexagon::LDriw_indexed_cNotPt_V4; 2019 case Hexagon::LDriw_indexed_shl_V4: 2020 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : 2021 Hexagon::LDriw_indexed_shl_cNotPt_V4; 2022 2023 // V4 Load from global address 2024 case Hexagon::LDrid_GP_V4: 2025 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 : 2026 Hexagon::LDrid_GP_cNotPt_V4; 2027 case Hexagon::LDrib_GP_V4: 2028 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 : 2029 Hexagon::LDrib_GP_cNotPt_V4; 2030 case Hexagon::LDriub_GP_V4: 2031 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 : 2032 Hexagon::LDriub_GP_cNotPt_V4; 2033 case Hexagon::LDrih_GP_V4: 2034 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 : 2035 Hexagon::LDrih_GP_cNotPt_V4; 2036 case Hexagon::LDriuh_GP_V4: 2037 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 : 2038 Hexagon::LDriuh_GP_cNotPt_V4; 2039 case Hexagon::LDriw_GP_V4: 2040 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 : 2041 Hexagon::LDriw_GP_cNotPt_V4; 2042 2043 case Hexagon::LDd_GP_V4: 2044 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : 2045 Hexagon::LDd_GP_cNotPt_V4; 2046 case Hexagon::LDb_GP_V4: 2047 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : 2048 Hexagon::LDb_GP_cNotPt_V4; 2049 case Hexagon::LDub_GP_V4: 2050 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : 2051 Hexagon::LDub_GP_cNotPt_V4; 2052 case Hexagon::LDh_GP_V4: 2053 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : 2054 Hexagon::LDh_GP_cNotPt_V4; 2055 case Hexagon::LDuh_GP_V4: 2056 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : 2057 Hexagon::LDuh_GP_cNotPt_V4; 2058 case Hexagon::LDw_GP_V4: 2059 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : 2060 Hexagon::LDw_GP_cNotPt_V4; 2061 2062 // Byte. 2063 case Hexagon::POST_STbri: 2064 return !invertPredicate ? Hexagon::POST_STbri_cPt : 2065 Hexagon::POST_STbri_cNotPt; 2066 case Hexagon::STrib: 2067 return !invertPredicate ? Hexagon::STrib_cPt : 2068 Hexagon::STrib_cNotPt; 2069 case Hexagon::STrib_indexed: 2070 return !invertPredicate ? Hexagon::STrib_indexed_cPt : 2071 Hexagon::STrib_indexed_cNotPt; 2072 case Hexagon::STrib_imm_V4: 2073 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 : 2074 Hexagon::STrib_imm_cNotPt_V4; 2075 case Hexagon::STrib_indexed_shl_V4: 2076 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 : 2077 Hexagon::STrib_indexed_shl_cNotPt_V4; 2078 // Halfword. 2079 case Hexagon::POST_SThri: 2080 return !invertPredicate ? Hexagon::POST_SThri_cPt : 2081 Hexagon::POST_SThri_cNotPt; 2082 case Hexagon::STrih: 2083 return !invertPredicate ? Hexagon::STrih_cPt : 2084 Hexagon::STrih_cNotPt; 2085 case Hexagon::STrih_indexed: 2086 return !invertPredicate ? Hexagon::STrih_indexed_cPt : 2087 Hexagon::STrih_indexed_cNotPt; 2088 case Hexagon::STrih_imm_V4: 2089 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 : 2090 Hexagon::STrih_imm_cNotPt_V4; 2091 case Hexagon::STrih_indexed_shl_V4: 2092 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 : 2093 Hexagon::STrih_indexed_shl_cNotPt_V4; 2094 // Word. 2095 case Hexagon::POST_STwri: 2096 return !invertPredicate ? Hexagon::POST_STwri_cPt : 2097 Hexagon::POST_STwri_cNotPt; 2098 case Hexagon::STriw: 2099 return !invertPredicate ? Hexagon::STriw_cPt : 2100 Hexagon::STriw_cNotPt; 2101 case Hexagon::STriw_indexed: 2102 return !invertPredicate ? Hexagon::STriw_indexed_cPt : 2103 Hexagon::STriw_indexed_cNotPt; 2104 case Hexagon::STriw_indexed_shl_V4: 2105 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 : 2106 Hexagon::STriw_indexed_shl_cNotPt_V4; 2107 case Hexagon::STriw_imm_V4: 2108 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 : 2109 Hexagon::STriw_imm_cNotPt_V4; 2110 // Double word. 2111 case Hexagon::POST_STdri: 2112 return !invertPredicate ? Hexagon::POST_STdri_cPt : 2113 Hexagon::POST_STdri_cNotPt; 2114 case Hexagon::STrid: 2115 return !invertPredicate ? Hexagon::STrid_cPt : 2116 Hexagon::STrid_cNotPt; 2117 case Hexagon::STrid_indexed: 2118 return !invertPredicate ? Hexagon::STrid_indexed_cPt : 2119 Hexagon::STrid_indexed_cNotPt; 2120 case Hexagon::STrid_indexed_shl_V4: 2121 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : 2122 Hexagon::STrid_indexed_shl_cNotPt_V4; 2123 2124 // V4 Store to global address 2125 case Hexagon::STrid_GP_V4: 2126 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 : 2127 Hexagon::STrid_GP_cNotPt_V4; 2128 case Hexagon::STrib_GP_V4: 2129 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 : 2130 Hexagon::STrib_GP_cNotPt_V4; 2131 case Hexagon::STrih_GP_V4: 2132 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 : 2133 Hexagon::STrih_GP_cNotPt_V4; 2134 case Hexagon::STriw_GP_V4: 2135 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 : 2136 Hexagon::STriw_GP_cNotPt_V4; 2137 2138 case Hexagon::STd_GP_V4: 2139 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : 2140 Hexagon::STd_GP_cNotPt_V4; 2141 case Hexagon::STb_GP_V4: 2142 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : 2143 Hexagon::STb_GP_cNotPt_V4; 2144 case Hexagon::STh_GP_V4: 2145 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : 2146 Hexagon::STh_GP_cNotPt_V4; 2147 case Hexagon::STw_GP_V4: 2148 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : 2149 Hexagon::STw_GP_cNotPt_V4; 2150 2151 // Load. 2152 case Hexagon::LDrid: 2153 return !invertPredicate ? Hexagon::LDrid_cPt : 2154 Hexagon::LDrid_cNotPt; 2155 case Hexagon::LDriw: 2156 return !invertPredicate ? Hexagon::LDriw_cPt : 2157 Hexagon::LDriw_cNotPt; 2158 case Hexagon::LDrih: 2159 return !invertPredicate ? Hexagon::LDrih_cPt : 2160 Hexagon::LDrih_cNotPt; 2161 case Hexagon::LDriuh: 2162 return !invertPredicate ? Hexagon::LDriuh_cPt : 2163 Hexagon::LDriuh_cNotPt; 2164 case Hexagon::LDrib: 2165 return !invertPredicate ? Hexagon::LDrib_cPt : 2166 Hexagon::LDrib_cNotPt; 2167 case Hexagon::LDriub: 2168 return !invertPredicate ? Hexagon::LDriub_cPt : 2169 Hexagon::LDriub_cNotPt; 2170 // Load Indexed. 2171 case Hexagon::LDrid_indexed: 2172 return !invertPredicate ? Hexagon::LDrid_indexed_cPt : 2173 Hexagon::LDrid_indexed_cNotPt; 2174 case Hexagon::LDriw_indexed: 2175 return !invertPredicate ? Hexagon::LDriw_indexed_cPt : 2176 Hexagon::LDriw_indexed_cNotPt; 2177 case Hexagon::LDrih_indexed: 2178 return !invertPredicate ? Hexagon::LDrih_indexed_cPt : 2179 Hexagon::LDrih_indexed_cNotPt; 2180 case Hexagon::LDriuh_indexed: 2181 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt : 2182 Hexagon::LDriuh_indexed_cNotPt; 2183 case Hexagon::LDrib_indexed: 2184 return !invertPredicate ? Hexagon::LDrib_indexed_cPt : 2185 Hexagon::LDrib_indexed_cNotPt; 2186 case Hexagon::LDriub_indexed: 2187 return !invertPredicate ? Hexagon::LDriub_indexed_cPt : 2188 Hexagon::LDriub_indexed_cNotPt; 2189 // Post Increment Load. 2190 case Hexagon::POST_LDrid: 2191 return !invertPredicate ? Hexagon::POST_LDrid_cPt : 2192 Hexagon::POST_LDrid_cNotPt; 2193 case Hexagon::POST_LDriw: 2194 return !invertPredicate ? Hexagon::POST_LDriw_cPt : 2195 Hexagon::POST_LDriw_cNotPt; 2196 case Hexagon::POST_LDrih: 2197 return !invertPredicate ? Hexagon::POST_LDrih_cPt : 2198 Hexagon::POST_LDrih_cNotPt; 2199 case Hexagon::POST_LDriuh: 2200 return !invertPredicate ? Hexagon::POST_LDriuh_cPt : 2201 Hexagon::POST_LDriuh_cNotPt; 2202 case Hexagon::POST_LDrib: 2203 return !invertPredicate ? Hexagon::POST_LDrib_cPt : 2204 Hexagon::POST_LDrib_cNotPt; 2205 case Hexagon::POST_LDriub: 2206 return !invertPredicate ? Hexagon::POST_LDriub_cPt : 2207 Hexagon::POST_LDriub_cNotPt; 2208 // DEALLOC_RETURN. 2209 case Hexagon::DEALLOC_RET_V4: 2210 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : 2211 Hexagon::DEALLOC_RET_cNotPt_V4; 2212 } 2213 llvm_unreachable("Unexpected predicable instruction"); 2214} 2215 2216 2217bool HexagonInstrInfo:: 2218PredicateInstruction(MachineInstr *MI, 2219 const SmallVectorImpl<MachineOperand> &Cond) const { 2220 int Opc = MI->getOpcode(); 2221 assert (isPredicable(MI) && "Expected predicable instruction"); 2222 bool invertJump = (!Cond.empty() && Cond[0].isImm() && 2223 (Cond[0].getImm() == 0)); 2224 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); 2225 // 2226 // This assumes that the predicate is always the first operand 2227 // in the set of inputs. 2228 // 2229 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 2230 int oper; 2231 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) { 2232 MachineOperand MO = MI->getOperand(oper); 2233 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) { 2234 break; 2235 } 2236 2237 if (MO.isReg()) { 2238 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 2239 MO.isImplicit(), MO.isKill(), 2240 MO.isDead(), MO.isUndef(), 2241 MO.isDebug()); 2242 } else if (MO.isImm()) { 2243 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); 2244 } else { 2245 llvm_unreachable("Unexpected operand type"); 2246 } 2247 } 2248 2249 int regPos = invertJump ? 1 : 0; 2250 MachineOperand PredMO = Cond[regPos]; 2251 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(), 2252 PredMO.isImplicit(), PredMO.isKill(), 2253 PredMO.isDead(), PredMO.isUndef(), 2254 PredMO.isDebug()); 2255 2256 return true; 2257} 2258 2259 2260bool 2261HexagonInstrInfo:: 2262isProfitableToIfCvt(MachineBasicBlock &MBB, 2263 unsigned NumCycles, 2264 unsigned ExtraPredCycles, 2265 const BranchProbability &Probability) const { 2266 return true; 2267} 2268 2269 2270bool 2271HexagonInstrInfo:: 2272isProfitableToIfCvt(MachineBasicBlock &TMBB, 2273 unsigned NumTCycles, 2274 unsigned ExtraTCycles, 2275 MachineBasicBlock &FMBB, 2276 unsigned NumFCycles, 2277 unsigned ExtraFCycles, 2278 const BranchProbability &Probability) const { 2279 return true; 2280} 2281 2282 2283bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { 2284 const uint64_t F = MI->getDesc().TSFlags; 2285 2286 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); 2287} 2288 2289bool 2290HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, 2291 std::vector<MachineOperand> &Pred) const { 2292 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) { 2293 MachineOperand MO = MI->getOperand(oper); 2294 if (MO.isReg() && MO.isDef()) { 2295 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); 2296 if (RC == &Hexagon::PredRegsRegClass) { 2297 Pred.push_back(MO); 2298 return true; 2299 } 2300 } 2301 } 2302 return false; 2303} 2304 2305 2306bool 2307HexagonInstrInfo:: 2308SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 2309 const SmallVectorImpl<MachineOperand> &Pred2) const { 2310 // TODO: Fix this 2311 return false; 2312} 2313 2314 2315// 2316// We indicate that we want to reverse the branch by 2317// inserting a 0 at the beginning of the Cond vector. 2318// 2319bool HexagonInstrInfo:: 2320ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2321 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 2322 Cond.erase(Cond.begin()); 2323 } else { 2324 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0)); 2325 } 2326 return false; 2327} 2328 2329 2330bool HexagonInstrInfo:: 2331isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, 2332 const BranchProbability &Probability) const { 2333 return (NumInstrs <= 4); 2334} 2335 2336bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { 2337 switch (MI->getOpcode()) { 2338 default: return false; 2339 case Hexagon::DEALLOC_RET_V4 : 2340 case Hexagon::DEALLOC_RET_cPt_V4 : 2341 case Hexagon::DEALLOC_RET_cNotPt_V4 : 2342 case Hexagon::DEALLOC_RET_cdnPnt_V4 : 2343 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 : 2344 case Hexagon::DEALLOC_RET_cdnPt_V4 : 2345 case Hexagon::DEALLOC_RET_cNotdnPt_V4 : 2346 return true; 2347 } 2348} 2349 2350 2351bool HexagonInstrInfo:: 2352isValidOffset(const int Opcode, const int Offset) const { 2353 // This function is to check whether the "Offset" is in the correct range of 2354 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is 2355 // inserted to calculate the final address. Due to this reason, the function 2356 // assumes that the "Offset" has correct alignment. 2357 2358 switch(Opcode) { 2359 2360 case Hexagon::LDriw: 2361 case Hexagon::LDriw_f: 2362 case Hexagon::STriw: 2363 case Hexagon::STriw_f: 2364 assert((Offset % 4 == 0) && "Offset has incorrect alignment"); 2365 return (Offset >= Hexagon_MEMW_OFFSET_MIN) && 2366 (Offset <= Hexagon_MEMW_OFFSET_MAX); 2367 2368 case Hexagon::LDrid: 2369 case Hexagon::LDrid_f: 2370 case Hexagon::STrid: 2371 case Hexagon::STrid_f: 2372 assert((Offset % 8 == 0) && "Offset has incorrect alignment"); 2373 return (Offset >= Hexagon_MEMD_OFFSET_MIN) && 2374 (Offset <= Hexagon_MEMD_OFFSET_MAX); 2375 2376 case Hexagon::LDrih: 2377 case Hexagon::LDriuh: 2378 case Hexagon::STrih: 2379 assert((Offset % 2 == 0) && "Offset has incorrect alignment"); 2380 return (Offset >= Hexagon_MEMH_OFFSET_MIN) && 2381 (Offset <= Hexagon_MEMH_OFFSET_MAX); 2382 2383 case Hexagon::LDrib: 2384 case Hexagon::STrib: 2385 case Hexagon::LDriub: 2386 return (Offset >= Hexagon_MEMB_OFFSET_MIN) && 2387 (Offset <= Hexagon_MEMB_OFFSET_MAX); 2388 2389 case Hexagon::ADD_ri: 2390 case Hexagon::TFR_FI: 2391 return (Offset >= Hexagon_ADDI_OFFSET_MIN) && 2392 (Offset <= Hexagon_ADDI_OFFSET_MAX); 2393 2394 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2395 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2396 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2397 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2398 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2399 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2400 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2401 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2402 case Hexagon::MEMw_ADDi_MEM_V4 : 2403 case Hexagon::MEMw_SUBi_MEM_V4 : 2404 case Hexagon::MEMw_ADDr_MEM_V4 : 2405 case Hexagon::MEMw_SUBr_MEM_V4 : 2406 case Hexagon::MEMw_ANDr_MEM_V4 : 2407 case Hexagon::MEMw_ORr_MEM_V4 : 2408 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." ); 2409 return (0 <= Offset && Offset <= 255); 2410 2411 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2412 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2413 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2414 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2415 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2416 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2417 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2418 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2419 case Hexagon::MEMh_ADDi_MEM_V4 : 2420 case Hexagon::MEMh_SUBi_MEM_V4 : 2421 case Hexagon::MEMh_ADDr_MEM_V4 : 2422 case Hexagon::MEMh_SUBr_MEM_V4 : 2423 case Hexagon::MEMh_ANDr_MEM_V4 : 2424 case Hexagon::MEMh_ORr_MEM_V4 : 2425 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." ); 2426 return (0 <= Offset && Offset <= 127); 2427 2428 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2429 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2430 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2431 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2432 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2433 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2434 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2435 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2436 case Hexagon::MEMb_ADDi_MEM_V4 : 2437 case Hexagon::MEMb_SUBi_MEM_V4 : 2438 case Hexagon::MEMb_ADDr_MEM_V4 : 2439 case Hexagon::MEMb_SUBr_MEM_V4 : 2440 case Hexagon::MEMb_ANDr_MEM_V4 : 2441 case Hexagon::MEMb_ORr_MEM_V4 : 2442 return (0 <= Offset && Offset <= 63); 2443 2444 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of 2445 // any size. Later pass knows how to handle it. 2446 case Hexagon::STriw_pred: 2447 case Hexagon::LDriw_pred: 2448 return true; 2449 2450 // INLINEASM is very special. 2451 case Hexagon::INLINEASM: 2452 return true; 2453 } 2454 2455 llvm_unreachable("No offset range is defined for this opcode. " 2456 "Please define it in the above switch statement!"); 2457} 2458 2459 2460// 2461// Check if the Offset is a valid auto-inc imm by Load/Store Type. 2462// 2463bool HexagonInstrInfo:: 2464isValidAutoIncImm(const EVT VT, const int Offset) const { 2465 2466 if (VT == MVT::i64) { 2467 return (Offset >= Hexagon_MEMD_AUTOINC_MIN && 2468 Offset <= Hexagon_MEMD_AUTOINC_MAX && 2469 (Offset & 0x7) == 0); 2470 } 2471 if (VT == MVT::i32) { 2472 return (Offset >= Hexagon_MEMW_AUTOINC_MIN && 2473 Offset <= Hexagon_MEMW_AUTOINC_MAX && 2474 (Offset & 0x3) == 0); 2475 } 2476 if (VT == MVT::i16) { 2477 return (Offset >= Hexagon_MEMH_AUTOINC_MIN && 2478 Offset <= Hexagon_MEMH_AUTOINC_MAX && 2479 (Offset & 0x1) == 0); 2480 } 2481 if (VT == MVT::i8) { 2482 return (Offset >= Hexagon_MEMB_AUTOINC_MIN && 2483 Offset <= Hexagon_MEMB_AUTOINC_MAX); 2484 } 2485 llvm_unreachable("Not an auto-inc opc!"); 2486} 2487 2488 2489bool HexagonInstrInfo:: 2490isMemOp(const MachineInstr *MI) const { 2491 switch (MI->getOpcode()) 2492 { 2493 default: return false; 2494 case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : 2495 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2496 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2497 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2498 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2499 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2500 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2501 case Hexagon::MEMw_ADDSUBi_MEM_V4 : 2502 case Hexagon::MEMw_ADDi_MEM_V4 : 2503 case Hexagon::MEMw_SUBi_MEM_V4 : 2504 case Hexagon::MEMw_ADDr_MEM_V4 : 2505 case Hexagon::MEMw_SUBr_MEM_V4 : 2506 case Hexagon::MEMw_ANDr_MEM_V4 : 2507 case Hexagon::MEMw_ORr_MEM_V4 : 2508 case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : 2509 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2510 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2511 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2512 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2513 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2514 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2515 case Hexagon::MEMh_ADDSUBi_MEM_V4 : 2516 case Hexagon::MEMh_ADDi_MEM_V4 : 2517 case Hexagon::MEMh_SUBi_MEM_V4 : 2518 case Hexagon::MEMh_ADDr_MEM_V4 : 2519 case Hexagon::MEMh_SUBr_MEM_V4 : 2520 case Hexagon::MEMh_ANDr_MEM_V4 : 2521 case Hexagon::MEMh_ORr_MEM_V4 : 2522 case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : 2523 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2524 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2525 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2526 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2527 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2528 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2529 case Hexagon::MEMb_ADDSUBi_MEM_V4 : 2530 case Hexagon::MEMb_ADDi_MEM_V4 : 2531 case Hexagon::MEMb_SUBi_MEM_V4 : 2532 case Hexagon::MEMb_ADDr_MEM_V4 : 2533 case Hexagon::MEMb_SUBr_MEM_V4 : 2534 case Hexagon::MEMb_ANDr_MEM_V4 : 2535 case Hexagon::MEMb_ORr_MEM_V4 : 2536 return true; 2537 } 2538} 2539 2540 2541bool HexagonInstrInfo:: 2542isSpillPredRegOp(const MachineInstr *MI) const { 2543 switch (MI->getOpcode()) { 2544 default: return false; 2545 case Hexagon::STriw_pred : 2546 case Hexagon::LDriw_pred : 2547 return true; 2548 } 2549} 2550 2551bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { 2552 switch (MI->getOpcode()) { 2553 default: return false; 2554 case Hexagon::CMPEQrr: 2555 case Hexagon::CMPEQri: 2556 case Hexagon::CMPLTrr: 2557 case Hexagon::CMPGTrr: 2558 case Hexagon::CMPGTri: 2559 case Hexagon::CMPLTUrr: 2560 case Hexagon::CMPGTUrr: 2561 case Hexagon::CMPGTUri: 2562 case Hexagon::CMPGEri: 2563 case Hexagon::CMPGEUri: 2564 return true; 2565 } 2566} 2567 2568bool HexagonInstrInfo:: 2569isConditionalTransfer (const MachineInstr *MI) const { 2570 switch (MI->getOpcode()) { 2571 default: return false; 2572 case Hexagon::TFR_cPt: 2573 case Hexagon::TFR_cNotPt: 2574 case Hexagon::TFRI_cPt: 2575 case Hexagon::TFRI_cNotPt: 2576 case Hexagon::TFR_cdnPt: 2577 case Hexagon::TFR_cdnNotPt: 2578 case Hexagon::TFRI_cdnPt: 2579 case Hexagon::TFRI_cdnNotPt: 2580 return true; 2581 } 2582} 2583 2584bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { 2585 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2586 switch (MI->getOpcode()) 2587 { 2588 default: return false; 2589 case Hexagon::ADD_ri_cPt: 2590 case Hexagon::ADD_ri_cNotPt: 2591 case Hexagon::ADD_rr_cPt: 2592 case Hexagon::ADD_rr_cNotPt: 2593 case Hexagon::XOR_rr_cPt: 2594 case Hexagon::XOR_rr_cNotPt: 2595 case Hexagon::AND_rr_cPt: 2596 case Hexagon::AND_rr_cNotPt: 2597 case Hexagon::OR_rr_cPt: 2598 case Hexagon::OR_rr_cNotPt: 2599 case Hexagon::SUB_rr_cPt: 2600 case Hexagon::SUB_rr_cNotPt: 2601 case Hexagon::COMBINE_rr_cPt: 2602 case Hexagon::COMBINE_rr_cNotPt: 2603 return true; 2604 case Hexagon::ASLH_cPt_V4: 2605 case Hexagon::ASLH_cNotPt_V4: 2606 case Hexagon::ASRH_cPt_V4: 2607 case Hexagon::ASRH_cNotPt_V4: 2608 case Hexagon::SXTB_cPt_V4: 2609 case Hexagon::SXTB_cNotPt_V4: 2610 case Hexagon::SXTH_cPt_V4: 2611 case Hexagon::SXTH_cNotPt_V4: 2612 case Hexagon::ZXTB_cPt_V4: 2613 case Hexagon::ZXTB_cNotPt_V4: 2614 case Hexagon::ZXTH_cPt_V4: 2615 case Hexagon::ZXTH_cNotPt_V4: 2616 return QRI.Subtarget.hasV4TOps(); 2617 } 2618} 2619 2620bool HexagonInstrInfo:: 2621isConditionalLoad (const MachineInstr* MI) const { 2622 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2623 switch (MI->getOpcode()) 2624 { 2625 default: return false; 2626 case Hexagon::LDrid_cPt : 2627 case Hexagon::LDrid_cNotPt : 2628 case Hexagon::LDrid_indexed_cPt : 2629 case Hexagon::LDrid_indexed_cNotPt : 2630 case Hexagon::LDriw_cPt : 2631 case Hexagon::LDriw_cNotPt : 2632 case Hexagon::LDriw_indexed_cPt : 2633 case Hexagon::LDriw_indexed_cNotPt : 2634 case Hexagon::LDrih_cPt : 2635 case Hexagon::LDrih_cNotPt : 2636 case Hexagon::LDrih_indexed_cPt : 2637 case Hexagon::LDrih_indexed_cNotPt : 2638 case Hexagon::LDrib_cPt : 2639 case Hexagon::LDrib_cNotPt : 2640 case Hexagon::LDrib_indexed_cPt : 2641 case Hexagon::LDrib_indexed_cNotPt : 2642 case Hexagon::LDriuh_cPt : 2643 case Hexagon::LDriuh_cNotPt : 2644 case Hexagon::LDriuh_indexed_cPt : 2645 case Hexagon::LDriuh_indexed_cNotPt : 2646 case Hexagon::LDriub_cPt : 2647 case Hexagon::LDriub_cNotPt : 2648 case Hexagon::LDriub_indexed_cPt : 2649 case Hexagon::LDriub_indexed_cNotPt : 2650 return true; 2651 case Hexagon::POST_LDrid_cPt : 2652 case Hexagon::POST_LDrid_cNotPt : 2653 case Hexagon::POST_LDriw_cPt : 2654 case Hexagon::POST_LDriw_cNotPt : 2655 case Hexagon::POST_LDrih_cPt : 2656 case Hexagon::POST_LDrih_cNotPt : 2657 case Hexagon::POST_LDrib_cPt : 2658 case Hexagon::POST_LDrib_cNotPt : 2659 case Hexagon::POST_LDriuh_cPt : 2660 case Hexagon::POST_LDriuh_cNotPt : 2661 case Hexagon::POST_LDriub_cPt : 2662 case Hexagon::POST_LDriub_cNotPt : 2663 return QRI.Subtarget.hasV4TOps(); 2664 case Hexagon::LDrid_indexed_cPt_V4 : 2665 case Hexagon::LDrid_indexed_cNotPt_V4 : 2666 case Hexagon::LDrid_indexed_shl_cPt_V4 : 2667 case Hexagon::LDrid_indexed_shl_cNotPt_V4 : 2668 case Hexagon::LDrib_indexed_cPt_V4 : 2669 case Hexagon::LDrib_indexed_cNotPt_V4 : 2670 case Hexagon::LDrib_indexed_shl_cPt_V4 : 2671 case Hexagon::LDrib_indexed_shl_cNotPt_V4 : 2672 case Hexagon::LDriub_indexed_cPt_V4 : 2673 case Hexagon::LDriub_indexed_cNotPt_V4 : 2674 case Hexagon::LDriub_indexed_shl_cPt_V4 : 2675 case Hexagon::LDriub_indexed_shl_cNotPt_V4 : 2676 case Hexagon::LDrih_indexed_cPt_V4 : 2677 case Hexagon::LDrih_indexed_cNotPt_V4 : 2678 case Hexagon::LDrih_indexed_shl_cPt_V4 : 2679 case Hexagon::LDrih_indexed_shl_cNotPt_V4 : 2680 case Hexagon::LDriuh_indexed_cPt_V4 : 2681 case Hexagon::LDriuh_indexed_cNotPt_V4 : 2682 case Hexagon::LDriuh_indexed_shl_cPt_V4 : 2683 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : 2684 case Hexagon::LDriw_indexed_cPt_V4 : 2685 case Hexagon::LDriw_indexed_cNotPt_V4 : 2686 case Hexagon::LDriw_indexed_shl_cPt_V4 : 2687 case Hexagon::LDriw_indexed_shl_cNotPt_V4 : 2688 return QRI.Subtarget.hasV4TOps(); 2689 } 2690} 2691 2692// Returns true if an instruction is a conditional store. 2693// 2694// Note: It doesn't include conditional new-value stores as they can't be 2695// converted to .new predicate. 2696// 2697// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] 2698// ^ ^ 2699// / \ (not OK. it will cause new-value store to be 2700// / X conditional on p0.new while R2 producer is 2701// / \ on p0) 2702// / \. 2703// p.new store p.old NV store 2704// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] 2705// ^ ^ 2706// \ / 2707// \ / 2708// \ / 2709// p.old store 2710// [if (p0)memw(R0+#0)=R2] 2711// 2712// The above diagram shows the steps involoved in the conversion of a predicated 2713// store instruction to its .new predicated new-value form. 2714// 2715// The following set of instructions further explains the scenario where 2716// conditional new-value store becomes invalid when promoted to .new predicate 2717// form. 2718// 2719// { 1) if (p0) r0 = add(r1, r2) 2720// 2) p0 = cmp.eq(r3, #0) } 2721// 2722// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with 2723// the first two instructions because in instr 1, r0 is conditional on old value 2724// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which 2725// is not valid for new-value stores. 2726bool HexagonInstrInfo:: 2727isConditionalStore (const MachineInstr* MI) const { 2728 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2729 switch (MI->getOpcode()) 2730 { 2731 default: return false; 2732 case Hexagon::STrib_imm_cPt_V4 : 2733 case Hexagon::STrib_imm_cNotPt_V4 : 2734 case Hexagon::STrib_indexed_shl_cPt_V4 : 2735 case Hexagon::STrib_indexed_shl_cNotPt_V4 : 2736 case Hexagon::STrib_cPt : 2737 case Hexagon::STrib_cNotPt : 2738 case Hexagon::POST_STbri_cPt : 2739 case Hexagon::POST_STbri_cNotPt : 2740 case Hexagon::STrid_indexed_cPt : 2741 case Hexagon::STrid_indexed_cNotPt : 2742 case Hexagon::STrid_indexed_shl_cPt_V4 : 2743 case Hexagon::POST_STdri_cPt : 2744 case Hexagon::POST_STdri_cNotPt : 2745 case Hexagon::STrih_cPt : 2746 case Hexagon::STrih_cNotPt : 2747 case Hexagon::STrih_indexed_cPt : 2748 case Hexagon::STrih_indexed_cNotPt : 2749 case Hexagon::STrih_imm_cPt_V4 : 2750 case Hexagon::STrih_imm_cNotPt_V4 : 2751 case Hexagon::STrih_indexed_shl_cPt_V4 : 2752 case Hexagon::STrih_indexed_shl_cNotPt_V4 : 2753 case Hexagon::POST_SThri_cPt : 2754 case Hexagon::POST_SThri_cNotPt : 2755 case Hexagon::STriw_cPt : 2756 case Hexagon::STriw_cNotPt : 2757 case Hexagon::STriw_indexed_cPt : 2758 case Hexagon::STriw_indexed_cNotPt : 2759 case Hexagon::STriw_imm_cPt_V4 : 2760 case Hexagon::STriw_imm_cNotPt_V4 : 2761 case Hexagon::STriw_indexed_shl_cPt_V4 : 2762 case Hexagon::STriw_indexed_shl_cNotPt_V4 : 2763 case Hexagon::POST_STwri_cPt : 2764 case Hexagon::POST_STwri_cNotPt : 2765 return QRI.Subtarget.hasV4TOps(); 2766 2767 // V4 global address store before promoting to dot new. 2768 case Hexagon::STrid_GP_cPt_V4 : 2769 case Hexagon::STrid_GP_cNotPt_V4 : 2770 case Hexagon::STrib_GP_cPt_V4 : 2771 case Hexagon::STrib_GP_cNotPt_V4 : 2772 case Hexagon::STrih_GP_cPt_V4 : 2773 case Hexagon::STrih_GP_cNotPt_V4 : 2774 case Hexagon::STriw_GP_cPt_V4 : 2775 case Hexagon::STriw_GP_cNotPt_V4 : 2776 case Hexagon::STd_GP_cPt_V4 : 2777 case Hexagon::STd_GP_cNotPt_V4 : 2778 case Hexagon::STb_GP_cPt_V4 : 2779 case Hexagon::STb_GP_cNotPt_V4 : 2780 case Hexagon::STh_GP_cPt_V4 : 2781 case Hexagon::STh_GP_cNotPt_V4 : 2782 case Hexagon::STw_GP_cPt_V4 : 2783 case Hexagon::STw_GP_cNotPt_V4 : 2784 return QRI.Subtarget.hasV4TOps(); 2785 2786 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded 2787 // from the "Conditional Store" list. Because a predicated new value store 2788 // would NOT be promoted to a double dot new store. See diagram below: 2789 // This function returns yes for those stores that are predicated but not 2790 // yet promoted to predicate dot new instructions. 2791 // 2792 // +---------------------+ 2793 // /-----| if (p0) memw(..)=r0 |---------\~ 2794 // || +---------------------+ || 2795 // promote || /\ /\ || promote 2796 // || /||\ /||\ || 2797 // \||/ demote || \||/ 2798 // \/ || || \/ 2799 // +-------------------------+ || +-------------------------+ 2800 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | 2801 // +-------------------------+ || +-------------------------+ 2802 // || || || 2803 // || demote \||/ 2804 // promote || \/ NOT possible 2805 // || || /\~ 2806 // \||/ || /||\~ 2807 // \/ || || 2808 // +-----------------------------+ 2809 // | if (p0.new) memw(..)=r0.new | 2810 // +-----------------------------+ 2811 // Double Dot New Store 2812 // 2813 } 2814} 2815 2816 2817 2818DFAPacketizer *HexagonInstrInfo:: 2819CreateTargetScheduleState(const TargetMachine *TM, 2820 const ScheduleDAG *DAG) const { 2821 const InstrItineraryData *II = TM->getInstrItineraryData(); 2822 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); 2823} 2824 2825bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 2826 const MachineBasicBlock *MBB, 2827 const MachineFunction &MF) const { 2828 // Debug info is never a scheduling boundary. It's necessary to be explicit 2829 // due to the special treatment of IT instructions below, otherwise a 2830 // dbg_value followed by an IT will result in the IT instruction being 2831 // considered a scheduling hazard, which is wrong. It should be the actual 2832 // instruction preceding the dbg_value instruction(s), just like it is 2833 // when debug info is not present. 2834 if (MI->isDebugValue()) 2835 return false; 2836 2837 // Terminators and labels can't be scheduled around. 2838 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) 2839 return true; 2840 2841 return false; 2842} 2843