HexagonInstrInfo.cpp revision 924223c9aba54736c86bed74ffe0ceb01467a23d
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Hexagon implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "HexagonInstrInfo.h" 15#include "Hexagon.h" 16#include "HexagonRegisterInfo.h" 17#include "HexagonSubtarget.h" 18#include "llvm/ADT/STLExtras.h" 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/CodeGen/DFAPacketizer.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineMemOperand.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Support/MathExtras.h" 27#define GET_INSTRINFO_CTOR 28#define GET_INSTRMAP_INFO 29#include "HexagonGenInstrInfo.inc" 30#include "HexagonGenDFAPacketizer.inc" 31 32using namespace llvm; 33 34/// 35/// Constants for Hexagon instructions. 36/// 37const int Hexagon_MEMW_OFFSET_MAX = 4095; 38const int Hexagon_MEMW_OFFSET_MIN = -4096; 39const int Hexagon_MEMD_OFFSET_MAX = 8191; 40const int Hexagon_MEMD_OFFSET_MIN = -8192; 41const int Hexagon_MEMH_OFFSET_MAX = 2047; 42const int Hexagon_MEMH_OFFSET_MIN = -2048; 43const int Hexagon_MEMB_OFFSET_MAX = 1023; 44const int Hexagon_MEMB_OFFSET_MIN = -1024; 45const int Hexagon_ADDI_OFFSET_MAX = 32767; 46const int Hexagon_ADDI_OFFSET_MIN = -32768; 47const int Hexagon_MEMD_AUTOINC_MAX = 56; 48const int Hexagon_MEMD_AUTOINC_MIN = -64; 49const int Hexagon_MEMW_AUTOINC_MAX = 28; 50const int Hexagon_MEMW_AUTOINC_MIN = -32; 51const int Hexagon_MEMH_AUTOINC_MAX = 14; 52const int Hexagon_MEMH_AUTOINC_MIN = -16; 53const int Hexagon_MEMB_AUTOINC_MAX = 7; 54const int Hexagon_MEMB_AUTOINC_MIN = -8; 55 56 57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) 58 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), 59 RI(ST, *this), Subtarget(ST) { 60} 61 62 63/// isLoadFromStackSlot - If the specified machine instruction is a direct 64/// load from a stack slot, return the virtual or physical register number of 65/// the destination along with the FrameIndex of the loaded stack slot. If 66/// not, return 0. This predicate must return 0 if the instruction has 67/// any side effects other than loading from the stack slot. 68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 69 int &FrameIndex) const { 70 71 72 switch (MI->getOpcode()) { 73 default: break; 74 case Hexagon::LDriw: 75 case Hexagon::LDrid: 76 case Hexagon::LDrih: 77 case Hexagon::LDrib: 78 case Hexagon::LDriub: 79 if (MI->getOperand(2).isFI() && 80 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 81 FrameIndex = MI->getOperand(2).getIndex(); 82 return MI->getOperand(0).getReg(); 83 } 84 break; 85 } 86 return 0; 87} 88 89 90/// isStoreToStackSlot - If the specified machine instruction is a direct 91/// store to a stack slot, return the virtual or physical register number of 92/// the source reg along with the FrameIndex of the loaded stack slot. If 93/// not, return 0. This predicate must return 0 if the instruction has 94/// any side effects other than storing to the stack slot. 95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 96 int &FrameIndex) const { 97 switch (MI->getOpcode()) { 98 default: break; 99 case Hexagon::STriw: 100 case Hexagon::STrid: 101 case Hexagon::STrih: 102 case Hexagon::STrib: 103 if (MI->getOperand(2).isFI() && 104 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { 105 FrameIndex = MI->getOperand(0).getIndex(); 106 return MI->getOperand(2).getReg(); 107 } 108 break; 109 } 110 return 0; 111} 112 113 114unsigned 115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 116 MachineBasicBlock *FBB, 117 const SmallVectorImpl<MachineOperand> &Cond, 118 DebugLoc DL) const{ 119 120 int BOpc = Hexagon::JMP; 121 int BccOpc = Hexagon::JMP_c; 122 123 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 124 125 int regPos = 0; 126 // Check if ReverseBranchCondition has asked to reverse this branch 127 // If we want to reverse the branch an odd number of times, we want 128 // JMP_cNot. 129 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 130 BccOpc = Hexagon::JMP_cNot; 131 regPos = 1; 132 } 133 134 if (FBB == 0) { 135 if (Cond.empty()) { 136 // Due to a bug in TailMerging/CFG Optimization, we need to add a 137 // special case handling of a predicated jump followed by an 138 // unconditional jump. If not, Tail Merging and CFG Optimization go 139 // into an infinite loop. 140 MachineBasicBlock *NewTBB, *NewFBB; 141 SmallVector<MachineOperand, 4> Cond; 142 MachineInstr *Term = MBB.getFirstTerminator(); 143 if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, 144 false)) { 145 MachineBasicBlock *NextBB = 146 llvm::next(MachineFunction::iterator(&MBB)); 147 if (NewTBB == NextBB) { 148 ReverseBranchCondition(Cond); 149 RemoveBranch(MBB); 150 return InsertBranch(MBB, TBB, 0, Cond, DL); 151 } 152 } 153 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB); 154 } else { 155 BuildMI(&MBB, DL, 156 get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 157 } 158 return 1; 159 } 160 161 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB); 162 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB); 163 164 return 2; 165} 166 167 168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 169 MachineBasicBlock *&TBB, 170 MachineBasicBlock *&FBB, 171 SmallVectorImpl<MachineOperand> &Cond, 172 bool AllowModify) const { 173 TBB = NULL; 174 FBB = NULL; 175 176 // If the block has no terminators, it just falls into the block after it. 177 MachineBasicBlock::iterator I = MBB.end(); 178 if (I == MBB.begin()) 179 return false; 180 181 // A basic block may looks like this: 182 // 183 // [ insn 184 // EH_LABEL 185 // insn 186 // insn 187 // insn 188 // EH_LABEL 189 // insn ] 190 // 191 // It has two succs but does not have a terminator 192 // Don't know how to handle it. 193 do { 194 --I; 195 if (I->isEHLabel()) 196 return true; 197 } while (I != MBB.begin()); 198 199 I = MBB.end(); 200 --I; 201 202 while (I->isDebugValue()) { 203 if (I == MBB.begin()) 204 return false; 205 --I; 206 } 207 if (!isUnpredicatedTerminator(I)) 208 return false; 209 210 // Get the last instruction in the block. 211 MachineInstr *LastInst = I; 212 213 // If there is only one terminator instruction, process it. 214 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { 215 if (LastInst->getOpcode() == Hexagon::JMP) { 216 TBB = LastInst->getOperand(0).getMBB(); 217 return false; 218 } 219 if (LastInst->getOpcode() == Hexagon::JMP_c) { 220 // Block ends with fall-through true condbranch. 221 TBB = LastInst->getOperand(1).getMBB(); 222 Cond.push_back(LastInst->getOperand(0)); 223 return false; 224 } 225 if (LastInst->getOpcode() == Hexagon::JMP_cNot) { 226 // Block ends with fall-through false condbranch. 227 TBB = LastInst->getOperand(1).getMBB(); 228 Cond.push_back(MachineOperand::CreateImm(0)); 229 Cond.push_back(LastInst->getOperand(0)); 230 return false; 231 } 232 // Otherwise, don't know what this is. 233 return true; 234 } 235 236 // Get the instruction before it if it's a terminator. 237 MachineInstr *SecondLastInst = I; 238 239 // If there are three terminators, we don't know what sort of block this is. 240 if (SecondLastInst && I != MBB.begin() && 241 isUnpredicatedTerminator(--I)) 242 return true; 243 244 // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. 245 if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || 246 (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && 247 LastInst->getOpcode() == Hexagon::JMP) { 248 TBB = SecondLastInst->getOperand(1).getMBB(); 249 Cond.push_back(SecondLastInst->getOperand(0)); 250 FBB = LastInst->getOperand(0).getMBB(); 251 return false; 252 } 253 254 // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. 255 if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && 256 LastInst->getOpcode() == Hexagon::JMP) { 257 TBB = SecondLastInst->getOperand(1).getMBB(); 258 Cond.push_back(MachineOperand::CreateImm(0)); 259 Cond.push_back(SecondLastInst->getOperand(0)); 260 FBB = LastInst->getOperand(0).getMBB(); 261 return false; 262 } 263 264 // If the block ends with two Hexagon:JMPs, handle it. The second one is not 265 // executed, so remove it. 266 if (SecondLastInst->getOpcode() == Hexagon::JMP && 267 LastInst->getOpcode() == Hexagon::JMP) { 268 TBB = SecondLastInst->getOperand(0).getMBB(); 269 I = LastInst; 270 if (AllowModify) 271 I->eraseFromParent(); 272 return false; 273 } 274 275 // Otherwise, can't handle this. 276 return true; 277} 278 279 280unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 281 int BOpc = Hexagon::JMP; 282 int BccOpc = Hexagon::JMP_c; 283 int BccOpcNot = Hexagon::JMP_cNot; 284 285 MachineBasicBlock::iterator I = MBB.end(); 286 if (I == MBB.begin()) return 0; 287 --I; 288 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc && 289 I->getOpcode() != BccOpcNot) 290 return 0; 291 292 // Remove the branch. 293 I->eraseFromParent(); 294 295 I = MBB.end(); 296 297 if (I == MBB.begin()) return 1; 298 --I; 299 if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot) 300 return 1; 301 302 // Remove the branch. 303 I->eraseFromParent(); 304 return 2; 305} 306 307 308void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 309 MachineBasicBlock::iterator I, DebugLoc DL, 310 unsigned DestReg, unsigned SrcReg, 311 bool KillSrc) const { 312 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { 313 BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg); 314 return; 315 } 316 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { 317 BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg); 318 return; 319 } 320 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { 321 // Map Pd = Ps to Pd = or(Ps, Ps). 322 BuildMI(MBB, I, DL, get(Hexagon::OR_pp), 323 DestReg).addReg(SrcReg).addReg(SrcReg); 324 return; 325 } 326 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && 327 Hexagon::IntRegsRegClass.contains(SrcReg)) { 328 // We can have an overlap between single and double reg: r1:0 = r0. 329 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { 330 // r1:0 = r0 331 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 332 Hexagon::subreg_hireg))).addImm(0); 333 } else { 334 // r1:0 = r1 or no overlap. 335 BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg, 336 Hexagon::subreg_loreg))).addReg(SrcReg); 337 BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg, 338 Hexagon::subreg_hireg))).addImm(0); 339 } 340 return; 341 } 342 if (Hexagon::CRRegsRegClass.contains(DestReg) && 343 Hexagon::IntRegsRegClass.contains(SrcReg)) { 344 BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); 345 return; 346 } 347 348 llvm_unreachable("Unimplemented"); 349} 350 351 352void HexagonInstrInfo:: 353storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 354 unsigned SrcReg, bool isKill, int FI, 355 const TargetRegisterClass *RC, 356 const TargetRegisterInfo *TRI) const { 357 358 DebugLoc DL = MBB.findDebugLoc(I); 359 MachineFunction &MF = *MBB.getParent(); 360 MachineFrameInfo &MFI = *MF.getFrameInfo(); 361 unsigned Align = MFI.getObjectAlignment(FI); 362 363 MachineMemOperand *MMO = 364 MF.getMachineMemOperand( 365 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 366 MachineMemOperand::MOStore, 367 MFI.getObjectSize(FI), 368 Align); 369 370 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 371 BuildMI(MBB, I, DL, get(Hexagon::STriw)) 372 .addFrameIndex(FI).addImm(0) 373 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 374 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 375 BuildMI(MBB, I, DL, get(Hexagon::STrid)) 376 .addFrameIndex(FI).addImm(0) 377 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 378 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 379 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) 380 .addFrameIndex(FI).addImm(0) 381 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 382 } else { 383 llvm_unreachable("Unimplemented"); 384 } 385} 386 387 388void HexagonInstrInfo::storeRegToAddr( 389 MachineFunction &MF, unsigned SrcReg, 390 bool isKill, 391 SmallVectorImpl<MachineOperand> &Addr, 392 const TargetRegisterClass *RC, 393 SmallVectorImpl<MachineInstr*> &NewMIs) const 394{ 395 llvm_unreachable("Unimplemented"); 396} 397 398 399void HexagonInstrInfo:: 400loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 401 unsigned DestReg, int FI, 402 const TargetRegisterClass *RC, 403 const TargetRegisterInfo *TRI) const { 404 DebugLoc DL = MBB.findDebugLoc(I); 405 MachineFunction &MF = *MBB.getParent(); 406 MachineFrameInfo &MFI = *MF.getFrameInfo(); 407 unsigned Align = MFI.getObjectAlignment(FI); 408 409 MachineMemOperand *MMO = 410 MF.getMachineMemOperand( 411 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 412 MachineMemOperand::MOLoad, 413 MFI.getObjectSize(FI), 414 Align); 415 if (RC == &Hexagon::IntRegsRegClass) { 416 BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) 417 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 418 } else if (RC == &Hexagon::DoubleRegsRegClass) { 419 BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) 420 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 421 } else if (RC == &Hexagon::PredRegsRegClass) { 422 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) 423 .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 424 } else { 425 llvm_unreachable("Can't store this register to stack slot"); 426 } 427} 428 429 430void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 431 SmallVectorImpl<MachineOperand> &Addr, 432 const TargetRegisterClass *RC, 433 SmallVectorImpl<MachineInstr*> &NewMIs) const { 434 llvm_unreachable("Unimplemented"); 435} 436 437 438MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 439 MachineInstr* MI, 440 const SmallVectorImpl<unsigned> &Ops, 441 int FI) const { 442 // Hexagon_TODO: Implement. 443 return(0); 444} 445 446 447unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { 448 449 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 450 const TargetRegisterClass *TRC; 451 if (VT == MVT::i1) { 452 TRC = &Hexagon::PredRegsRegClass; 453 } else if (VT == MVT::i32 || VT == MVT::f32) { 454 TRC = &Hexagon::IntRegsRegClass; 455 } else if (VT == MVT::i64 || VT == MVT::f64) { 456 TRC = &Hexagon::DoubleRegsRegClass; 457 } else { 458 llvm_unreachable("Cannot handle this register class"); 459 } 460 461 unsigned NewReg = RegInfo.createVirtualRegister(TRC); 462 return NewReg; 463} 464 465bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { 466 switch(MI->getOpcode()) { 467 default: return false; 468 // JMP_EQri 469 case Hexagon::JMP_EQriPt_nv_V4: 470 case Hexagon::JMP_EQriPnt_nv_V4: 471 case Hexagon::JMP_EQriNotPt_nv_V4: 472 case Hexagon::JMP_EQriNotPnt_nv_V4: 473 474 // JMP_EQri - with -1 475 case Hexagon::JMP_EQriPtneg_nv_V4: 476 case Hexagon::JMP_EQriPntneg_nv_V4: 477 case Hexagon::JMP_EQriNotPtneg_nv_V4: 478 case Hexagon::JMP_EQriNotPntneg_nv_V4: 479 480 // JMP_EQrr 481 case Hexagon::JMP_EQrrPt_nv_V4: 482 case Hexagon::JMP_EQrrPnt_nv_V4: 483 case Hexagon::JMP_EQrrNotPt_nv_V4: 484 case Hexagon::JMP_EQrrNotPnt_nv_V4: 485 486 // JMP_GTri 487 case Hexagon::JMP_GTriPt_nv_V4: 488 case Hexagon::JMP_GTriPnt_nv_V4: 489 case Hexagon::JMP_GTriNotPt_nv_V4: 490 case Hexagon::JMP_GTriNotPnt_nv_V4: 491 492 // JMP_GTri - with -1 493 case Hexagon::JMP_GTriPtneg_nv_V4: 494 case Hexagon::JMP_GTriPntneg_nv_V4: 495 case Hexagon::JMP_GTriNotPtneg_nv_V4: 496 case Hexagon::JMP_GTriNotPntneg_nv_V4: 497 498 // JMP_GTrr 499 case Hexagon::JMP_GTrrPt_nv_V4: 500 case Hexagon::JMP_GTrrPnt_nv_V4: 501 case Hexagon::JMP_GTrrNotPt_nv_V4: 502 case Hexagon::JMP_GTrrNotPnt_nv_V4: 503 504 // JMP_GTrrdn 505 case Hexagon::JMP_GTrrdnPt_nv_V4: 506 case Hexagon::JMP_GTrrdnPnt_nv_V4: 507 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 508 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 509 510 // JMP_GTUri 511 case Hexagon::JMP_GTUriPt_nv_V4: 512 case Hexagon::JMP_GTUriPnt_nv_V4: 513 case Hexagon::JMP_GTUriNotPt_nv_V4: 514 case Hexagon::JMP_GTUriNotPnt_nv_V4: 515 516 // JMP_GTUrr 517 case Hexagon::JMP_GTUrrPt_nv_V4: 518 case Hexagon::JMP_GTUrrPnt_nv_V4: 519 case Hexagon::JMP_GTUrrNotPt_nv_V4: 520 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 521 522 // JMP_GTUrrdn 523 case Hexagon::JMP_GTUrrdnPt_nv_V4: 524 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 525 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 526 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 527 528 // TFR_FI 529 case Hexagon::TFR_FI: 530 return true; 531 } 532} 533 534bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { 535 switch(MI->getOpcode()) { 536 default: return false; 537 // JMP_EQri 538 case Hexagon::JMP_EQriPt_ie_nv_V4: 539 case Hexagon::JMP_EQriPnt_ie_nv_V4: 540 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 541 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 542 543 // JMP_EQri - with -1 544 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 545 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 546 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 547 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 548 549 // JMP_EQrr 550 case Hexagon::JMP_EQrrPt_ie_nv_V4: 551 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 552 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 553 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 554 555 // JMP_GTri 556 case Hexagon::JMP_GTriPt_ie_nv_V4: 557 case Hexagon::JMP_GTriPnt_ie_nv_V4: 558 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 559 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 560 561 // JMP_GTri - with -1 562 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 563 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 564 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 565 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 566 567 // JMP_GTrr 568 case Hexagon::JMP_GTrrPt_ie_nv_V4: 569 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 570 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 571 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 572 573 // JMP_GTrrdn 574 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 575 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 576 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 577 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 578 579 // JMP_GTUri 580 case Hexagon::JMP_GTUriPt_ie_nv_V4: 581 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 582 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 583 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 584 585 // JMP_GTUrr 586 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 587 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 588 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 589 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 590 591 // JMP_GTUrrdn 592 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 593 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 594 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 595 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 596 597 // V4 absolute set addressing. 598 case Hexagon::LDrid_abs_setimm_V4: 599 case Hexagon::LDriw_abs_setimm_V4: 600 case Hexagon::LDrih_abs_setimm_V4: 601 case Hexagon::LDrib_abs_setimm_V4: 602 case Hexagon::LDriuh_abs_setimm_V4: 603 case Hexagon::LDriub_abs_setimm_V4: 604 605 case Hexagon::STrid_abs_setimm_V4: 606 case Hexagon::STrib_abs_setimm_V4: 607 case Hexagon::STrih_abs_setimm_V4: 608 case Hexagon::STriw_abs_setimm_V4: 609 610 // V4 global address load. 611 case Hexagon::LDrid_GP_cPt_V4 : 612 case Hexagon::LDrid_GP_cNotPt_V4 : 613 case Hexagon::LDrid_GP_cdnPt_V4 : 614 case Hexagon::LDrid_GP_cdnNotPt_V4 : 615 case Hexagon::LDrib_GP_cPt_V4 : 616 case Hexagon::LDrib_GP_cNotPt_V4 : 617 case Hexagon::LDrib_GP_cdnPt_V4 : 618 case Hexagon::LDrib_GP_cdnNotPt_V4 : 619 case Hexagon::LDriub_GP_cPt_V4 : 620 case Hexagon::LDriub_GP_cNotPt_V4 : 621 case Hexagon::LDriub_GP_cdnPt_V4 : 622 case Hexagon::LDriub_GP_cdnNotPt_V4 : 623 case Hexagon::LDrih_GP_cPt_V4 : 624 case Hexagon::LDrih_GP_cNotPt_V4 : 625 case Hexagon::LDrih_GP_cdnPt_V4 : 626 case Hexagon::LDrih_GP_cdnNotPt_V4 : 627 case Hexagon::LDriuh_GP_cPt_V4 : 628 case Hexagon::LDriuh_GP_cNotPt_V4 : 629 case Hexagon::LDriuh_GP_cdnPt_V4 : 630 case Hexagon::LDriuh_GP_cdnNotPt_V4 : 631 case Hexagon::LDriw_GP_cPt_V4 : 632 case Hexagon::LDriw_GP_cNotPt_V4 : 633 case Hexagon::LDriw_GP_cdnPt_V4 : 634 case Hexagon::LDriw_GP_cdnNotPt_V4 : 635 case Hexagon::LDd_GP_cPt_V4 : 636 case Hexagon::LDd_GP_cNotPt_V4 : 637 case Hexagon::LDd_GP_cdnPt_V4 : 638 case Hexagon::LDd_GP_cdnNotPt_V4 : 639 case Hexagon::LDb_GP_cPt_V4 : 640 case Hexagon::LDb_GP_cNotPt_V4 : 641 case Hexagon::LDb_GP_cdnPt_V4 : 642 case Hexagon::LDb_GP_cdnNotPt_V4 : 643 case Hexagon::LDub_GP_cPt_V4 : 644 case Hexagon::LDub_GP_cNotPt_V4 : 645 case Hexagon::LDub_GP_cdnPt_V4 : 646 case Hexagon::LDub_GP_cdnNotPt_V4 : 647 case Hexagon::LDh_GP_cPt_V4 : 648 case Hexagon::LDh_GP_cNotPt_V4 : 649 case Hexagon::LDh_GP_cdnPt_V4 : 650 case Hexagon::LDh_GP_cdnNotPt_V4 : 651 case Hexagon::LDuh_GP_cPt_V4 : 652 case Hexagon::LDuh_GP_cNotPt_V4 : 653 case Hexagon::LDuh_GP_cdnPt_V4 : 654 case Hexagon::LDuh_GP_cdnNotPt_V4 : 655 case Hexagon::LDw_GP_cPt_V4 : 656 case Hexagon::LDw_GP_cNotPt_V4 : 657 case Hexagon::LDw_GP_cdnPt_V4 : 658 case Hexagon::LDw_GP_cdnNotPt_V4 : 659 660 // V4 global address store. 661 case Hexagon::STrid_GP_cPt_V4 : 662 case Hexagon::STrid_GP_cNotPt_V4 : 663 case Hexagon::STrid_GP_cdnPt_V4 : 664 case Hexagon::STrid_GP_cdnNotPt_V4 : 665 case Hexagon::STrib_GP_cPt_V4 : 666 case Hexagon::STrib_GP_cNotPt_V4 : 667 case Hexagon::STrib_GP_cdnPt_V4 : 668 case Hexagon::STrib_GP_cdnNotPt_V4 : 669 case Hexagon::STrih_GP_cPt_V4 : 670 case Hexagon::STrih_GP_cNotPt_V4 : 671 case Hexagon::STrih_GP_cdnPt_V4 : 672 case Hexagon::STrih_GP_cdnNotPt_V4 : 673 case Hexagon::STriw_GP_cPt_V4 : 674 case Hexagon::STriw_GP_cNotPt_V4 : 675 case Hexagon::STriw_GP_cdnPt_V4 : 676 case Hexagon::STriw_GP_cdnNotPt_V4 : 677 case Hexagon::STd_GP_cPt_V4 : 678 case Hexagon::STd_GP_cNotPt_V4 : 679 case Hexagon::STd_GP_cdnPt_V4 : 680 case Hexagon::STd_GP_cdnNotPt_V4 : 681 case Hexagon::STb_GP_cPt_V4 : 682 case Hexagon::STb_GP_cNotPt_V4 : 683 case Hexagon::STb_GP_cdnPt_V4 : 684 case Hexagon::STb_GP_cdnNotPt_V4 : 685 case Hexagon::STh_GP_cPt_V4 : 686 case Hexagon::STh_GP_cNotPt_V4 : 687 case Hexagon::STh_GP_cdnPt_V4 : 688 case Hexagon::STh_GP_cdnNotPt_V4 : 689 case Hexagon::STw_GP_cPt_V4 : 690 case Hexagon::STw_GP_cNotPt_V4 : 691 case Hexagon::STw_GP_cdnPt_V4 : 692 case Hexagon::STw_GP_cdnNotPt_V4 : 693 694 // V4 predicated global address new value store. 695 case Hexagon::STrib_GP_cPt_nv_V4 : 696 case Hexagon::STrib_GP_cNotPt_nv_V4 : 697 case Hexagon::STrib_GP_cdnPt_nv_V4 : 698 case Hexagon::STrib_GP_cdnNotPt_nv_V4 : 699 case Hexagon::STrih_GP_cPt_nv_V4 : 700 case Hexagon::STrih_GP_cNotPt_nv_V4 : 701 case Hexagon::STrih_GP_cdnPt_nv_V4 : 702 case Hexagon::STrih_GP_cdnNotPt_nv_V4 : 703 case Hexagon::STriw_GP_cPt_nv_V4 : 704 case Hexagon::STriw_GP_cNotPt_nv_V4 : 705 case Hexagon::STriw_GP_cdnPt_nv_V4 : 706 case Hexagon::STriw_GP_cdnNotPt_nv_V4 : 707 case Hexagon::STb_GP_cPt_nv_V4 : 708 case Hexagon::STb_GP_cNotPt_nv_V4 : 709 case Hexagon::STb_GP_cdnPt_nv_V4 : 710 case Hexagon::STb_GP_cdnNotPt_nv_V4 : 711 case Hexagon::STh_GP_cPt_nv_V4 : 712 case Hexagon::STh_GP_cNotPt_nv_V4 : 713 case Hexagon::STh_GP_cdnPt_nv_V4 : 714 case Hexagon::STh_GP_cdnNotPt_nv_V4 : 715 case Hexagon::STw_GP_cPt_nv_V4 : 716 case Hexagon::STw_GP_cNotPt_nv_V4 : 717 case Hexagon::STw_GP_cdnPt_nv_V4 : 718 case Hexagon::STw_GP_cdnNotPt_nv_V4 : 719 720 // TFR_FI 721 case Hexagon::TFR_FI_immext_V4: 722 723 // TFRI_F 724 case Hexagon::TFRI_f: 725 case Hexagon::TFRI_cPt_f: 726 case Hexagon::TFRI_cNotPt_f: 727 case Hexagon::CONST64_Float_Real: 728 return true; 729 } 730} 731 732bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { 733 switch (MI->getOpcode()) { 734 default: return false; 735 // JMP_EQri 736 case Hexagon::JMP_EQriPt_nv_V4: 737 case Hexagon::JMP_EQriPnt_nv_V4: 738 case Hexagon::JMP_EQriNotPt_nv_V4: 739 case Hexagon::JMP_EQriNotPnt_nv_V4: 740 case Hexagon::JMP_EQriPt_ie_nv_V4: 741 case Hexagon::JMP_EQriPnt_ie_nv_V4: 742 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 743 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 744 745 // JMP_EQri - with -1 746 case Hexagon::JMP_EQriPtneg_nv_V4: 747 case Hexagon::JMP_EQriPntneg_nv_V4: 748 case Hexagon::JMP_EQriNotPtneg_nv_V4: 749 case Hexagon::JMP_EQriNotPntneg_nv_V4: 750 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 751 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 752 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 753 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 754 755 // JMP_EQrr 756 case Hexagon::JMP_EQrrPt_nv_V4: 757 case Hexagon::JMP_EQrrPnt_nv_V4: 758 case Hexagon::JMP_EQrrNotPt_nv_V4: 759 case Hexagon::JMP_EQrrNotPnt_nv_V4: 760 case Hexagon::JMP_EQrrPt_ie_nv_V4: 761 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 762 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 763 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 764 765 // JMP_GTri 766 case Hexagon::JMP_GTriPt_nv_V4: 767 case Hexagon::JMP_GTriPnt_nv_V4: 768 case Hexagon::JMP_GTriNotPt_nv_V4: 769 case Hexagon::JMP_GTriNotPnt_nv_V4: 770 case Hexagon::JMP_GTriPt_ie_nv_V4: 771 case Hexagon::JMP_GTriPnt_ie_nv_V4: 772 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 773 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 774 775 // JMP_GTri - with -1 776 case Hexagon::JMP_GTriPtneg_nv_V4: 777 case Hexagon::JMP_GTriPntneg_nv_V4: 778 case Hexagon::JMP_GTriNotPtneg_nv_V4: 779 case Hexagon::JMP_GTriNotPntneg_nv_V4: 780 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 781 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 782 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 783 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 784 785 // JMP_GTrr 786 case Hexagon::JMP_GTrrPt_nv_V4: 787 case Hexagon::JMP_GTrrPnt_nv_V4: 788 case Hexagon::JMP_GTrrNotPt_nv_V4: 789 case Hexagon::JMP_GTrrNotPnt_nv_V4: 790 case Hexagon::JMP_GTrrPt_ie_nv_V4: 791 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 792 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 793 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 794 795 // JMP_GTrrdn 796 case Hexagon::JMP_GTrrdnPt_nv_V4: 797 case Hexagon::JMP_GTrrdnPnt_nv_V4: 798 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 799 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 800 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 801 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 802 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 803 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 804 805 // JMP_GTUri 806 case Hexagon::JMP_GTUriPt_nv_V4: 807 case Hexagon::JMP_GTUriPnt_nv_V4: 808 case Hexagon::JMP_GTUriNotPt_nv_V4: 809 case Hexagon::JMP_GTUriNotPnt_nv_V4: 810 case Hexagon::JMP_GTUriPt_ie_nv_V4: 811 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 812 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 813 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 814 815 // JMP_GTUrr 816 case Hexagon::JMP_GTUrrPt_nv_V4: 817 case Hexagon::JMP_GTUrrPnt_nv_V4: 818 case Hexagon::JMP_GTUrrNotPt_nv_V4: 819 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 820 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 821 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 822 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 823 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 824 825 // JMP_GTUrrdn 826 case Hexagon::JMP_GTUrrdnPt_nv_V4: 827 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 828 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 829 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 830 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 831 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 832 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 833 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 834 return true; 835 } 836} 837 838unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const { 839 switch(MI->getOpcode()) { 840 default: llvm_unreachable("Unknown type of instruction."); 841 // JMP_EQri 842 case Hexagon::JMP_EQriPt_nv_V4: 843 return Hexagon::JMP_EQriPt_ie_nv_V4; 844 case Hexagon::JMP_EQriNotPt_nv_V4: 845 return Hexagon::JMP_EQriNotPt_ie_nv_V4; 846 case Hexagon::JMP_EQriPnt_nv_V4: 847 return Hexagon::JMP_EQriPnt_ie_nv_V4; 848 case Hexagon::JMP_EQriNotPnt_nv_V4: 849 return Hexagon::JMP_EQriNotPnt_ie_nv_V4; 850 851 // JMP_EQri -- with -1 852 case Hexagon::JMP_EQriPtneg_nv_V4: 853 return Hexagon::JMP_EQriPtneg_ie_nv_V4; 854 case Hexagon::JMP_EQriNotPtneg_nv_V4: 855 return Hexagon::JMP_EQriNotPtneg_ie_nv_V4; 856 case Hexagon::JMP_EQriPntneg_nv_V4: 857 return Hexagon::JMP_EQriPntneg_ie_nv_V4; 858 case Hexagon::JMP_EQriNotPntneg_nv_V4: 859 return Hexagon::JMP_EQriNotPntneg_ie_nv_V4; 860 861 // JMP_EQrr 862 case Hexagon::JMP_EQrrPt_nv_V4: 863 return Hexagon::JMP_EQrrPt_ie_nv_V4; 864 case Hexagon::JMP_EQrrNotPt_nv_V4: 865 return Hexagon::JMP_EQrrNotPt_ie_nv_V4; 866 case Hexagon::JMP_EQrrPnt_nv_V4: 867 return Hexagon::JMP_EQrrPnt_ie_nv_V4; 868 case Hexagon::JMP_EQrrNotPnt_nv_V4: 869 return Hexagon::JMP_EQrrNotPnt_ie_nv_V4; 870 871 // JMP_GTri 872 case Hexagon::JMP_GTriPt_nv_V4: 873 return Hexagon::JMP_GTriPt_ie_nv_V4; 874 case Hexagon::JMP_GTriNotPt_nv_V4: 875 return Hexagon::JMP_GTriNotPt_ie_nv_V4; 876 case Hexagon::JMP_GTriPnt_nv_V4: 877 return Hexagon::JMP_GTriPnt_ie_nv_V4; 878 case Hexagon::JMP_GTriNotPnt_nv_V4: 879 return Hexagon::JMP_GTriNotPnt_ie_nv_V4; 880 881 // JMP_GTri -- with -1 882 case Hexagon::JMP_GTriPtneg_nv_V4: 883 return Hexagon::JMP_GTriPtneg_ie_nv_V4; 884 case Hexagon::JMP_GTriNotPtneg_nv_V4: 885 return Hexagon::JMP_GTriNotPtneg_ie_nv_V4; 886 case Hexagon::JMP_GTriPntneg_nv_V4: 887 return Hexagon::JMP_GTriPntneg_ie_nv_V4; 888 case Hexagon::JMP_GTriNotPntneg_nv_V4: 889 return Hexagon::JMP_GTriNotPntneg_ie_nv_V4; 890 891 // JMP_GTrr 892 case Hexagon::JMP_GTrrPt_nv_V4: 893 return Hexagon::JMP_GTrrPt_ie_nv_V4; 894 case Hexagon::JMP_GTrrNotPt_nv_V4: 895 return Hexagon::JMP_GTrrNotPt_ie_nv_V4; 896 case Hexagon::JMP_GTrrPnt_nv_V4: 897 return Hexagon::JMP_GTrrPnt_ie_nv_V4; 898 case Hexagon::JMP_GTrrNotPnt_nv_V4: 899 return Hexagon::JMP_GTrrNotPnt_ie_nv_V4; 900 901 // JMP_GTrrdn 902 case Hexagon::JMP_GTrrdnPt_nv_V4: 903 return Hexagon::JMP_GTrrdnPt_ie_nv_V4; 904 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 905 return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4; 906 case Hexagon::JMP_GTrrdnPnt_nv_V4: 907 return Hexagon::JMP_GTrrdnPnt_ie_nv_V4; 908 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 909 return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4; 910 911 // JMP_GTUri 912 case Hexagon::JMP_GTUriPt_nv_V4: 913 return Hexagon::JMP_GTUriPt_ie_nv_V4; 914 case Hexagon::JMP_GTUriNotPt_nv_V4: 915 return Hexagon::JMP_GTUriNotPt_ie_nv_V4; 916 case Hexagon::JMP_GTUriPnt_nv_V4: 917 return Hexagon::JMP_GTUriPnt_ie_nv_V4; 918 case Hexagon::JMP_GTUriNotPnt_nv_V4: 919 return Hexagon::JMP_GTUriNotPnt_ie_nv_V4; 920 921 // JMP_GTUrr 922 case Hexagon::JMP_GTUrrPt_nv_V4: 923 return Hexagon::JMP_GTUrrPt_ie_nv_V4; 924 case Hexagon::JMP_GTUrrNotPt_nv_V4: 925 return Hexagon::JMP_GTUrrNotPt_ie_nv_V4; 926 case Hexagon::JMP_GTUrrPnt_nv_V4: 927 return Hexagon::JMP_GTUrrPnt_ie_nv_V4; 928 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 929 return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4; 930 931 // JMP_GTUrrdn 932 case Hexagon::JMP_GTUrrdnPt_nv_V4: 933 return Hexagon::JMP_GTUrrdnPt_ie_nv_V4; 934 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 935 return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4; 936 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 937 return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4; 938 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 939 return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4; 940 941 case Hexagon::TFR_FI: 942 return Hexagon::TFR_FI_immext_V4; 943 944 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 945 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 946 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 947 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 948 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 949 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 950 case Hexagon::MEMw_ADDi_MEM_V4 : 951 case Hexagon::MEMw_SUBi_MEM_V4 : 952 case Hexagon::MEMw_ADDr_MEM_V4 : 953 case Hexagon::MEMw_SUBr_MEM_V4 : 954 case Hexagon::MEMw_ANDr_MEM_V4 : 955 case Hexagon::MEMw_ORr_MEM_V4 : 956 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 957 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 958 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 959 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 960 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 961 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 962 case Hexagon::MEMh_ADDi_MEM_V4 : 963 case Hexagon::MEMh_SUBi_MEM_V4 : 964 case Hexagon::MEMh_ADDr_MEM_V4 : 965 case Hexagon::MEMh_SUBr_MEM_V4 : 966 case Hexagon::MEMh_ANDr_MEM_V4 : 967 case Hexagon::MEMh_ORr_MEM_V4 : 968 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 969 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 970 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 971 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 972 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 973 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 974 case Hexagon::MEMb_ADDi_MEM_V4 : 975 case Hexagon::MEMb_SUBi_MEM_V4 : 976 case Hexagon::MEMb_ADDr_MEM_V4 : 977 case Hexagon::MEMb_SUBr_MEM_V4 : 978 case Hexagon::MEMb_ANDr_MEM_V4 : 979 case Hexagon::MEMb_ORr_MEM_V4 : 980 llvm_unreachable("Needs implementing."); 981 } 982} 983 984unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const { 985 switch(MI->getOpcode()) { 986 default: llvm_unreachable("Unknown type of jump instruction."); 987 // JMP_EQri 988 case Hexagon::JMP_EQriPt_ie_nv_V4: 989 return Hexagon::JMP_EQriPt_nv_V4; 990 case Hexagon::JMP_EQriNotPt_ie_nv_V4: 991 return Hexagon::JMP_EQriNotPt_nv_V4; 992 case Hexagon::JMP_EQriPnt_ie_nv_V4: 993 return Hexagon::JMP_EQriPnt_nv_V4; 994 case Hexagon::JMP_EQriNotPnt_ie_nv_V4: 995 return Hexagon::JMP_EQriNotPnt_nv_V4; 996 997 // JMP_EQri -- with -1 998 case Hexagon::JMP_EQriPtneg_ie_nv_V4: 999 return Hexagon::JMP_EQriPtneg_nv_V4; 1000 case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: 1001 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1002 case Hexagon::JMP_EQriPntneg_ie_nv_V4: 1003 return Hexagon::JMP_EQriPntneg_nv_V4; 1004 case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: 1005 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1006 1007 // JMP_EQrr 1008 case Hexagon::JMP_EQrrPt_ie_nv_V4: 1009 return Hexagon::JMP_EQrrPt_nv_V4; 1010 case Hexagon::JMP_EQrrNotPt_ie_nv_V4: 1011 return Hexagon::JMP_EQrrNotPt_nv_V4; 1012 case Hexagon::JMP_EQrrPnt_ie_nv_V4: 1013 return Hexagon::JMP_EQrrPnt_nv_V4; 1014 case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: 1015 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1016 1017 // JMP_GTri 1018 case Hexagon::JMP_GTriPt_ie_nv_V4: 1019 return Hexagon::JMP_GTriPt_nv_V4; 1020 case Hexagon::JMP_GTriNotPt_ie_nv_V4: 1021 return Hexagon::JMP_GTriNotPt_nv_V4; 1022 case Hexagon::JMP_GTriPnt_ie_nv_V4: 1023 return Hexagon::JMP_GTriPnt_nv_V4; 1024 case Hexagon::JMP_GTriNotPnt_ie_nv_V4: 1025 return Hexagon::JMP_GTriNotPnt_nv_V4; 1026 1027 // JMP_GTri -- with -1 1028 case Hexagon::JMP_GTriPtneg_ie_nv_V4: 1029 return Hexagon::JMP_GTriPtneg_nv_V4; 1030 case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: 1031 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1032 case Hexagon::JMP_GTriPntneg_ie_nv_V4: 1033 return Hexagon::JMP_GTriPntneg_nv_V4; 1034 case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: 1035 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1036 1037 // JMP_GTrr 1038 case Hexagon::JMP_GTrrPt_ie_nv_V4: 1039 return Hexagon::JMP_GTrrPt_nv_V4; 1040 case Hexagon::JMP_GTrrNotPt_ie_nv_V4: 1041 return Hexagon::JMP_GTrrNotPt_nv_V4; 1042 case Hexagon::JMP_GTrrPnt_ie_nv_V4: 1043 return Hexagon::JMP_GTrrPnt_nv_V4; 1044 case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: 1045 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1046 1047 // JMP_GTrrdn 1048 case Hexagon::JMP_GTrrdnPt_ie_nv_V4: 1049 return Hexagon::JMP_GTrrdnPt_nv_V4; 1050 case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: 1051 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1052 case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: 1053 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1054 case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: 1055 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1056 1057 // JMP_GTUri 1058 case Hexagon::JMP_GTUriPt_ie_nv_V4: 1059 return Hexagon::JMP_GTUriPt_nv_V4; 1060 case Hexagon::JMP_GTUriNotPt_ie_nv_V4: 1061 return Hexagon::JMP_GTUriNotPt_nv_V4; 1062 case Hexagon::JMP_GTUriPnt_ie_nv_V4: 1063 return Hexagon::JMP_GTUriPnt_nv_V4; 1064 case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: 1065 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1066 1067 // JMP_GTUrr 1068 case Hexagon::JMP_GTUrrPt_ie_nv_V4: 1069 return Hexagon::JMP_GTUrrPt_nv_V4; 1070 case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: 1071 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1072 case Hexagon::JMP_GTUrrPnt_ie_nv_V4: 1073 return Hexagon::JMP_GTUrrPnt_nv_V4; 1074 case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: 1075 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1076 1077 // JMP_GTUrrdn 1078 case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: 1079 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1080 case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: 1081 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1082 case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: 1083 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1084 case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: 1085 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1086 } 1087} 1088 1089 1090bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { 1091 switch (MI->getOpcode()) { 1092 default: return false; 1093 // Store Byte 1094 case Hexagon::STrib_nv_V4: 1095 case Hexagon::STrib_indexed_nv_V4: 1096 case Hexagon::STrib_indexed_shl_nv_V4: 1097 case Hexagon::STrib_shl_nv_V4: 1098 case Hexagon::STrib_GP_nv_V4: 1099 case Hexagon::STb_GP_nv_V4: 1100 case Hexagon::POST_STbri_nv_V4: 1101 case Hexagon::STrib_cPt_nv_V4: 1102 case Hexagon::STrib_cdnPt_nv_V4: 1103 case Hexagon::STrib_cNotPt_nv_V4: 1104 case Hexagon::STrib_cdnNotPt_nv_V4: 1105 case Hexagon::STrib_indexed_cPt_nv_V4: 1106 case Hexagon::STrib_indexed_cdnPt_nv_V4: 1107 case Hexagon::STrib_indexed_cNotPt_nv_V4: 1108 case Hexagon::STrib_indexed_cdnNotPt_nv_V4: 1109 case Hexagon::STrib_indexed_shl_cPt_nv_V4: 1110 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: 1111 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: 1112 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: 1113 case Hexagon::POST_STbri_cPt_nv_V4: 1114 case Hexagon::POST_STbri_cdnPt_nv_V4: 1115 case Hexagon::POST_STbri_cNotPt_nv_V4: 1116 case Hexagon::POST_STbri_cdnNotPt_nv_V4: 1117 case Hexagon::STb_GP_cPt_nv_V4: 1118 case Hexagon::STb_GP_cNotPt_nv_V4: 1119 case Hexagon::STb_GP_cdnPt_nv_V4: 1120 case Hexagon::STb_GP_cdnNotPt_nv_V4: 1121 case Hexagon::STrib_GP_cPt_nv_V4: 1122 case Hexagon::STrib_GP_cNotPt_nv_V4: 1123 case Hexagon::STrib_GP_cdnPt_nv_V4: 1124 case Hexagon::STrib_GP_cdnNotPt_nv_V4: 1125 case Hexagon::STrib_abs_nv_V4: 1126 case Hexagon::STrib_abs_cPt_nv_V4: 1127 case Hexagon::STrib_abs_cdnPt_nv_V4: 1128 case Hexagon::STrib_abs_cNotPt_nv_V4: 1129 case Hexagon::STrib_abs_cdnNotPt_nv_V4: 1130 case Hexagon::STrib_imm_abs_nv_V4: 1131 case Hexagon::STrib_imm_abs_cPt_nv_V4: 1132 case Hexagon::STrib_imm_abs_cdnPt_nv_V4: 1133 case Hexagon::STrib_imm_abs_cNotPt_nv_V4: 1134 case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: 1135 1136 // Store Halfword 1137 case Hexagon::STrih_nv_V4: 1138 case Hexagon::STrih_indexed_nv_V4: 1139 case Hexagon::STrih_indexed_shl_nv_V4: 1140 case Hexagon::STrih_shl_nv_V4: 1141 case Hexagon::STrih_GP_nv_V4: 1142 case Hexagon::STh_GP_nv_V4: 1143 case Hexagon::POST_SThri_nv_V4: 1144 case Hexagon::STrih_cPt_nv_V4: 1145 case Hexagon::STrih_cdnPt_nv_V4: 1146 case Hexagon::STrih_cNotPt_nv_V4: 1147 case Hexagon::STrih_cdnNotPt_nv_V4: 1148 case Hexagon::STrih_indexed_cPt_nv_V4: 1149 case Hexagon::STrih_indexed_cdnPt_nv_V4: 1150 case Hexagon::STrih_indexed_cNotPt_nv_V4: 1151 case Hexagon::STrih_indexed_cdnNotPt_nv_V4: 1152 case Hexagon::STrih_indexed_shl_cPt_nv_V4: 1153 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: 1154 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: 1155 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: 1156 case Hexagon::POST_SThri_cPt_nv_V4: 1157 case Hexagon::POST_SThri_cdnPt_nv_V4: 1158 case Hexagon::POST_SThri_cNotPt_nv_V4: 1159 case Hexagon::POST_SThri_cdnNotPt_nv_V4: 1160 case Hexagon::STh_GP_cPt_nv_V4: 1161 case Hexagon::STh_GP_cNotPt_nv_V4: 1162 case Hexagon::STh_GP_cdnPt_nv_V4: 1163 case Hexagon::STh_GP_cdnNotPt_nv_V4: 1164 case Hexagon::STrih_GP_cPt_nv_V4: 1165 case Hexagon::STrih_GP_cNotPt_nv_V4: 1166 case Hexagon::STrih_GP_cdnPt_nv_V4: 1167 case Hexagon::STrih_GP_cdnNotPt_nv_V4: 1168 case Hexagon::STrih_abs_nv_V4: 1169 case Hexagon::STrih_abs_cPt_nv_V4: 1170 case Hexagon::STrih_abs_cdnPt_nv_V4: 1171 case Hexagon::STrih_abs_cNotPt_nv_V4: 1172 case Hexagon::STrih_abs_cdnNotPt_nv_V4: 1173 case Hexagon::STrih_imm_abs_nv_V4: 1174 case Hexagon::STrih_imm_abs_cPt_nv_V4: 1175 case Hexagon::STrih_imm_abs_cdnPt_nv_V4: 1176 case Hexagon::STrih_imm_abs_cNotPt_nv_V4: 1177 case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: 1178 1179 // Store Word 1180 case Hexagon::STriw_nv_V4: 1181 case Hexagon::STriw_indexed_nv_V4: 1182 case Hexagon::STriw_indexed_shl_nv_V4: 1183 case Hexagon::STriw_shl_nv_V4: 1184 case Hexagon::STriw_GP_nv_V4: 1185 case Hexagon::STw_GP_nv_V4: 1186 case Hexagon::POST_STwri_nv_V4: 1187 case Hexagon::STriw_cPt_nv_V4: 1188 case Hexagon::STriw_cdnPt_nv_V4: 1189 case Hexagon::STriw_cNotPt_nv_V4: 1190 case Hexagon::STriw_cdnNotPt_nv_V4: 1191 case Hexagon::STriw_indexed_cPt_nv_V4: 1192 case Hexagon::STriw_indexed_cdnPt_nv_V4: 1193 case Hexagon::STriw_indexed_cNotPt_nv_V4: 1194 case Hexagon::STriw_indexed_cdnNotPt_nv_V4: 1195 case Hexagon::STriw_indexed_shl_cPt_nv_V4: 1196 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: 1197 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: 1198 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: 1199 case Hexagon::POST_STwri_cPt_nv_V4: 1200 case Hexagon::POST_STwri_cdnPt_nv_V4: 1201 case Hexagon::POST_STwri_cNotPt_nv_V4: 1202 case Hexagon::POST_STwri_cdnNotPt_nv_V4: 1203 case Hexagon::STw_GP_cPt_nv_V4: 1204 case Hexagon::STw_GP_cNotPt_nv_V4: 1205 case Hexagon::STw_GP_cdnPt_nv_V4: 1206 case Hexagon::STw_GP_cdnNotPt_nv_V4: 1207 case Hexagon::STriw_GP_cPt_nv_V4: 1208 case Hexagon::STriw_GP_cNotPt_nv_V4: 1209 case Hexagon::STriw_GP_cdnPt_nv_V4: 1210 case Hexagon::STriw_GP_cdnNotPt_nv_V4: 1211 case Hexagon::STriw_abs_nv_V4: 1212 case Hexagon::STriw_abs_cPt_nv_V4: 1213 case Hexagon::STriw_abs_cdnPt_nv_V4: 1214 case Hexagon::STriw_abs_cNotPt_nv_V4: 1215 case Hexagon::STriw_abs_cdnNotPt_nv_V4: 1216 case Hexagon::STriw_imm_abs_nv_V4: 1217 case Hexagon::STriw_imm_abs_cPt_nv_V4: 1218 case Hexagon::STriw_imm_abs_cdnPt_nv_V4: 1219 case Hexagon::STriw_imm_abs_cNotPt_nv_V4: 1220 case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: 1221 return true; 1222 } 1223} 1224 1225bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { 1226 switch (MI->getOpcode()) 1227 { 1228 default: return false; 1229 // Load Byte 1230 case Hexagon::POST_LDrib: 1231 case Hexagon::POST_LDrib_cPt: 1232 case Hexagon::POST_LDrib_cNotPt: 1233 case Hexagon::POST_LDrib_cdnPt_V4: 1234 case Hexagon::POST_LDrib_cdnNotPt_V4: 1235 1236 // Load unsigned byte 1237 case Hexagon::POST_LDriub: 1238 case Hexagon::POST_LDriub_cPt: 1239 case Hexagon::POST_LDriub_cNotPt: 1240 case Hexagon::POST_LDriub_cdnPt_V4: 1241 case Hexagon::POST_LDriub_cdnNotPt_V4: 1242 1243 // Load halfword 1244 case Hexagon::POST_LDrih: 1245 case Hexagon::POST_LDrih_cPt: 1246 case Hexagon::POST_LDrih_cNotPt: 1247 case Hexagon::POST_LDrih_cdnPt_V4: 1248 case Hexagon::POST_LDrih_cdnNotPt_V4: 1249 1250 // Load unsigned halfword 1251 case Hexagon::POST_LDriuh: 1252 case Hexagon::POST_LDriuh_cPt: 1253 case Hexagon::POST_LDriuh_cNotPt: 1254 case Hexagon::POST_LDriuh_cdnPt_V4: 1255 case Hexagon::POST_LDriuh_cdnNotPt_V4: 1256 1257 // Load word 1258 case Hexagon::POST_LDriw: 1259 case Hexagon::POST_LDriw_cPt: 1260 case Hexagon::POST_LDriw_cNotPt: 1261 case Hexagon::POST_LDriw_cdnPt_V4: 1262 case Hexagon::POST_LDriw_cdnNotPt_V4: 1263 1264 // Load double word 1265 case Hexagon::POST_LDrid: 1266 case Hexagon::POST_LDrid_cPt: 1267 case Hexagon::POST_LDrid_cNotPt: 1268 case Hexagon::POST_LDrid_cdnPt_V4: 1269 case Hexagon::POST_LDrid_cdnNotPt_V4: 1270 1271 // Store byte 1272 case Hexagon::POST_STbri: 1273 case Hexagon::POST_STbri_cPt: 1274 case Hexagon::POST_STbri_cNotPt: 1275 case Hexagon::POST_STbri_cdnPt_V4: 1276 case Hexagon::POST_STbri_cdnNotPt_V4: 1277 1278 // Store halfword 1279 case Hexagon::POST_SThri: 1280 case Hexagon::POST_SThri_cPt: 1281 case Hexagon::POST_SThri_cNotPt: 1282 case Hexagon::POST_SThri_cdnPt_V4: 1283 case Hexagon::POST_SThri_cdnNotPt_V4: 1284 1285 // Store word 1286 case Hexagon::POST_STwri: 1287 case Hexagon::POST_STwri_cPt: 1288 case Hexagon::POST_STwri_cNotPt: 1289 case Hexagon::POST_STwri_cdnPt_V4: 1290 case Hexagon::POST_STwri_cdnNotPt_V4: 1291 1292 // Store double word 1293 case Hexagon::POST_STdri: 1294 case Hexagon::POST_STdri_cPt: 1295 case Hexagon::POST_STdri_cNotPt: 1296 case Hexagon::POST_STdri_cdnPt_V4: 1297 case Hexagon::POST_STdri_cdnNotPt_V4: 1298 return true; 1299 } 1300} 1301 1302bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { 1303 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; 1304} 1305 1306bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { 1307 bool isPred = MI->getDesc().isPredicable(); 1308 1309 if (!isPred) 1310 return false; 1311 1312 const int Opc = MI->getOpcode(); 1313 1314 switch(Opc) { 1315 case Hexagon::TFRI: 1316 return isInt<12>(MI->getOperand(1).getImm()); 1317 1318 case Hexagon::STrid: 1319 case Hexagon::STrid_indexed: 1320 return isShiftedUInt<6,3>(MI->getOperand(1).getImm()); 1321 1322 case Hexagon::STriw: 1323 case Hexagon::STriw_indexed: 1324 case Hexagon::STriw_nv_V4: 1325 return isShiftedUInt<6,2>(MI->getOperand(1).getImm()); 1326 1327 case Hexagon::STrih: 1328 case Hexagon::STrih_indexed: 1329 case Hexagon::STrih_nv_V4: 1330 return isShiftedUInt<6,1>(MI->getOperand(1).getImm()); 1331 1332 case Hexagon::STrib: 1333 case Hexagon::STrib_indexed: 1334 case Hexagon::STrib_nv_V4: 1335 return isUInt<6>(MI->getOperand(1).getImm()); 1336 1337 case Hexagon::LDrid: 1338 case Hexagon::LDrid_indexed: 1339 return isShiftedUInt<6,3>(MI->getOperand(2).getImm()); 1340 1341 case Hexagon::LDriw: 1342 case Hexagon::LDriw_indexed: 1343 return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); 1344 1345 case Hexagon::LDrih: 1346 case Hexagon::LDriuh: 1347 case Hexagon::LDrih_indexed: 1348 case Hexagon::LDriuh_indexed: 1349 return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); 1350 1351 case Hexagon::LDrib: 1352 case Hexagon::LDriub: 1353 case Hexagon::LDrib_indexed: 1354 case Hexagon::LDriub_indexed: 1355 return isUInt<6>(MI->getOperand(2).getImm()); 1356 1357 case Hexagon::POST_LDrid: 1358 return isShiftedInt<4,3>(MI->getOperand(3).getImm()); 1359 1360 case Hexagon::POST_LDriw: 1361 return isShiftedInt<4,2>(MI->getOperand(3).getImm()); 1362 1363 case Hexagon::POST_LDrih: 1364 case Hexagon::POST_LDriuh: 1365 return isShiftedInt<4,1>(MI->getOperand(3).getImm()); 1366 1367 case Hexagon::POST_LDrib: 1368 case Hexagon::POST_LDriub: 1369 return isInt<4>(MI->getOperand(3).getImm()); 1370 1371 case Hexagon::STrib_imm_V4: 1372 case Hexagon::STrih_imm_V4: 1373 case Hexagon::STriw_imm_V4: 1374 return (isUInt<6>(MI->getOperand(1).getImm()) && 1375 isInt<6>(MI->getOperand(2).getImm())); 1376 1377 case Hexagon::ADD_ri: 1378 return isInt<8>(MI->getOperand(2).getImm()); 1379 1380 case Hexagon::ASLH: 1381 case Hexagon::ASRH: 1382 case Hexagon::SXTB: 1383 case Hexagon::SXTH: 1384 case Hexagon::ZXTB: 1385 case Hexagon::ZXTH: 1386 return Subtarget.hasV4TOps(); 1387 1388 case Hexagon::JMPR: 1389 return false; 1390 } 1391 1392 return true; 1393} 1394 1395// This function performs the following inversiones: 1396// 1397// cPt ---> cNotPt 1398// cNotPt ---> cPt 1399// 1400// however, these inversiones are NOT included: 1401// 1402// cdnPt -X-> cdnNotPt 1403// cdnNotPt -X-> cdnPt 1404// cPt_nv -X-> cNotPt_nv (new value stores) 1405// cNotPt_nv -X-> cPt_nv (new value stores) 1406// 1407// because only the following transformations are allowed: 1408// 1409// cNotPt ---> cdnNotPt 1410// cPt ---> cdnPt 1411// cNotPt ---> cNotPt_nv 1412// cPt ---> cPt_nv 1413unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { 1414 switch(Opc) { 1415 default: llvm_unreachable("Unexpected predicated instruction"); 1416 case Hexagon::TFR_cPt: 1417 return Hexagon::TFR_cNotPt; 1418 case Hexagon::TFR_cNotPt: 1419 return Hexagon::TFR_cPt; 1420 1421 case Hexagon::TFRI_cPt: 1422 return Hexagon::TFRI_cNotPt; 1423 case Hexagon::TFRI_cNotPt: 1424 return Hexagon::TFRI_cPt; 1425 1426 case Hexagon::JMP_c: 1427 return Hexagon::JMP_cNot; 1428 case Hexagon::JMP_cNot: 1429 return Hexagon::JMP_c; 1430 1431 case Hexagon::ADD_ri_cPt: 1432 return Hexagon::ADD_ri_cNotPt; 1433 case Hexagon::ADD_ri_cNotPt: 1434 return Hexagon::ADD_ri_cPt; 1435 1436 case Hexagon::ADD_rr_cPt: 1437 return Hexagon::ADD_rr_cNotPt; 1438 case Hexagon::ADD_rr_cNotPt: 1439 return Hexagon::ADD_rr_cPt; 1440 1441 case Hexagon::XOR_rr_cPt: 1442 return Hexagon::XOR_rr_cNotPt; 1443 case Hexagon::XOR_rr_cNotPt: 1444 return Hexagon::XOR_rr_cPt; 1445 1446 case Hexagon::AND_rr_cPt: 1447 return Hexagon::AND_rr_cNotPt; 1448 case Hexagon::AND_rr_cNotPt: 1449 return Hexagon::AND_rr_cPt; 1450 1451 case Hexagon::OR_rr_cPt: 1452 return Hexagon::OR_rr_cNotPt; 1453 case Hexagon::OR_rr_cNotPt: 1454 return Hexagon::OR_rr_cPt; 1455 1456 case Hexagon::SUB_rr_cPt: 1457 return Hexagon::SUB_rr_cNotPt; 1458 case Hexagon::SUB_rr_cNotPt: 1459 return Hexagon::SUB_rr_cPt; 1460 1461 case Hexagon::COMBINE_rr_cPt: 1462 return Hexagon::COMBINE_rr_cNotPt; 1463 case Hexagon::COMBINE_rr_cNotPt: 1464 return Hexagon::COMBINE_rr_cPt; 1465 1466 case Hexagon::ASLH_cPt_V4: 1467 return Hexagon::ASLH_cNotPt_V4; 1468 case Hexagon::ASLH_cNotPt_V4: 1469 return Hexagon::ASLH_cPt_V4; 1470 1471 case Hexagon::ASRH_cPt_V4: 1472 return Hexagon::ASRH_cNotPt_V4; 1473 case Hexagon::ASRH_cNotPt_V4: 1474 return Hexagon::ASRH_cPt_V4; 1475 1476 case Hexagon::SXTB_cPt_V4: 1477 return Hexagon::SXTB_cNotPt_V4; 1478 case Hexagon::SXTB_cNotPt_V4: 1479 return Hexagon::SXTB_cPt_V4; 1480 1481 case Hexagon::SXTH_cPt_V4: 1482 return Hexagon::SXTH_cNotPt_V4; 1483 case Hexagon::SXTH_cNotPt_V4: 1484 return Hexagon::SXTH_cPt_V4; 1485 1486 case Hexagon::ZXTB_cPt_V4: 1487 return Hexagon::ZXTB_cNotPt_V4; 1488 case Hexagon::ZXTB_cNotPt_V4: 1489 return Hexagon::ZXTB_cPt_V4; 1490 1491 case Hexagon::ZXTH_cPt_V4: 1492 return Hexagon::ZXTH_cNotPt_V4; 1493 case Hexagon::ZXTH_cNotPt_V4: 1494 return Hexagon::ZXTH_cPt_V4; 1495 1496 1497 case Hexagon::JMPR_cPt: 1498 return Hexagon::JMPR_cNotPt; 1499 case Hexagon::JMPR_cNotPt: 1500 return Hexagon::JMPR_cPt; 1501 1502 // V4 indexed+scaled load. 1503 case Hexagon::LDrid_indexed_shl_cPt_V4: 1504 return Hexagon::LDrid_indexed_shl_cNotPt_V4; 1505 case Hexagon::LDrid_indexed_shl_cNotPt_V4: 1506 return Hexagon::LDrid_indexed_shl_cPt_V4; 1507 1508 case Hexagon::LDrib_indexed_shl_cPt_V4: 1509 return Hexagon::LDrib_indexed_shl_cNotPt_V4; 1510 case Hexagon::LDrib_indexed_shl_cNotPt_V4: 1511 return Hexagon::LDrib_indexed_shl_cPt_V4; 1512 1513 case Hexagon::LDriub_indexed_shl_cPt_V4: 1514 return Hexagon::LDriub_indexed_shl_cNotPt_V4; 1515 case Hexagon::LDriub_indexed_shl_cNotPt_V4: 1516 return Hexagon::LDriub_indexed_shl_cPt_V4; 1517 1518 case Hexagon::LDrih_indexed_shl_cPt_V4: 1519 return Hexagon::LDrih_indexed_shl_cNotPt_V4; 1520 case Hexagon::LDrih_indexed_shl_cNotPt_V4: 1521 return Hexagon::LDrih_indexed_shl_cPt_V4; 1522 1523 case Hexagon::LDriuh_indexed_shl_cPt_V4: 1524 return Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1525 case Hexagon::LDriuh_indexed_shl_cNotPt_V4: 1526 return Hexagon::LDriuh_indexed_shl_cPt_V4; 1527 1528 case Hexagon::LDriw_indexed_shl_cPt_V4: 1529 return Hexagon::LDriw_indexed_shl_cNotPt_V4; 1530 case Hexagon::LDriw_indexed_shl_cNotPt_V4: 1531 return Hexagon::LDriw_indexed_shl_cPt_V4; 1532 1533 // Byte. 1534 case Hexagon::POST_STbri_cPt: 1535 return Hexagon::POST_STbri_cNotPt; 1536 case Hexagon::POST_STbri_cNotPt: 1537 return Hexagon::POST_STbri_cPt; 1538 1539 case Hexagon::STrib_cPt: 1540 return Hexagon::STrib_cNotPt; 1541 case Hexagon::STrib_cNotPt: 1542 return Hexagon::STrib_cPt; 1543 1544 case Hexagon::STrib_indexed_cPt: 1545 return Hexagon::STrib_indexed_cNotPt; 1546 case Hexagon::STrib_indexed_cNotPt: 1547 return Hexagon::STrib_indexed_cPt; 1548 1549 case Hexagon::STrib_imm_cPt_V4: 1550 return Hexagon::STrib_imm_cNotPt_V4; 1551 case Hexagon::STrib_imm_cNotPt_V4: 1552 return Hexagon::STrib_imm_cPt_V4; 1553 1554 case Hexagon::STrib_indexed_shl_cPt_V4: 1555 return Hexagon::STrib_indexed_shl_cNotPt_V4; 1556 case Hexagon::STrib_indexed_shl_cNotPt_V4: 1557 return Hexagon::STrib_indexed_shl_cPt_V4; 1558 1559 // Halfword. 1560 case Hexagon::POST_SThri_cPt: 1561 return Hexagon::POST_SThri_cNotPt; 1562 case Hexagon::POST_SThri_cNotPt: 1563 return Hexagon::POST_SThri_cPt; 1564 1565 case Hexagon::STrih_cPt: 1566 return Hexagon::STrih_cNotPt; 1567 case Hexagon::STrih_cNotPt: 1568 return Hexagon::STrih_cPt; 1569 1570 case Hexagon::STrih_indexed_cPt: 1571 return Hexagon::STrih_indexed_cNotPt; 1572 case Hexagon::STrih_indexed_cNotPt: 1573 return Hexagon::STrih_indexed_cPt; 1574 1575 case Hexagon::STrih_imm_cPt_V4: 1576 return Hexagon::STrih_imm_cNotPt_V4; 1577 case Hexagon::STrih_imm_cNotPt_V4: 1578 return Hexagon::STrih_imm_cPt_V4; 1579 1580 case Hexagon::STrih_indexed_shl_cPt_V4: 1581 return Hexagon::STrih_indexed_shl_cNotPt_V4; 1582 case Hexagon::STrih_indexed_shl_cNotPt_V4: 1583 return Hexagon::STrih_indexed_shl_cPt_V4; 1584 1585 // Word. 1586 case Hexagon::POST_STwri_cPt: 1587 return Hexagon::POST_STwri_cNotPt; 1588 case Hexagon::POST_STwri_cNotPt: 1589 return Hexagon::POST_STwri_cPt; 1590 1591 case Hexagon::STriw_cPt: 1592 return Hexagon::STriw_cNotPt; 1593 case Hexagon::STriw_cNotPt: 1594 return Hexagon::STriw_cPt; 1595 1596 case Hexagon::STriw_indexed_cPt: 1597 return Hexagon::STriw_indexed_cNotPt; 1598 case Hexagon::STriw_indexed_cNotPt: 1599 return Hexagon::STriw_indexed_cPt; 1600 1601 case Hexagon::STriw_indexed_shl_cPt_V4: 1602 return Hexagon::STriw_indexed_shl_cNotPt_V4; 1603 case Hexagon::STriw_indexed_shl_cNotPt_V4: 1604 return Hexagon::STriw_indexed_shl_cPt_V4; 1605 1606 case Hexagon::STriw_imm_cPt_V4: 1607 return Hexagon::STriw_imm_cNotPt_V4; 1608 case Hexagon::STriw_imm_cNotPt_V4: 1609 return Hexagon::STriw_imm_cPt_V4; 1610 1611 // Double word. 1612 case Hexagon::POST_STdri_cPt: 1613 return Hexagon::POST_STdri_cNotPt; 1614 case Hexagon::POST_STdri_cNotPt: 1615 return Hexagon::POST_STdri_cPt; 1616 1617 case Hexagon::STrid_cPt: 1618 return Hexagon::STrid_cNotPt; 1619 case Hexagon::STrid_cNotPt: 1620 return Hexagon::STrid_cPt; 1621 1622 case Hexagon::STrid_indexed_cPt: 1623 return Hexagon::STrid_indexed_cNotPt; 1624 case Hexagon::STrid_indexed_cNotPt: 1625 return Hexagon::STrid_indexed_cPt; 1626 1627 case Hexagon::STrid_indexed_shl_cPt_V4: 1628 return Hexagon::STrid_indexed_shl_cNotPt_V4; 1629 case Hexagon::STrid_indexed_shl_cNotPt_V4: 1630 return Hexagon::STrid_indexed_shl_cPt_V4; 1631 1632 // V4 Store to global address. 1633 case Hexagon::STd_GP_cPt_V4: 1634 return Hexagon::STd_GP_cNotPt_V4; 1635 case Hexagon::STd_GP_cNotPt_V4: 1636 return Hexagon::STd_GP_cPt_V4; 1637 1638 case Hexagon::STb_GP_cPt_V4: 1639 return Hexagon::STb_GP_cNotPt_V4; 1640 case Hexagon::STb_GP_cNotPt_V4: 1641 return Hexagon::STb_GP_cPt_V4; 1642 1643 case Hexagon::STh_GP_cPt_V4: 1644 return Hexagon::STh_GP_cNotPt_V4; 1645 case Hexagon::STh_GP_cNotPt_V4: 1646 return Hexagon::STh_GP_cPt_V4; 1647 1648 case Hexagon::STw_GP_cPt_V4: 1649 return Hexagon::STw_GP_cNotPt_V4; 1650 case Hexagon::STw_GP_cNotPt_V4: 1651 return Hexagon::STw_GP_cPt_V4; 1652 1653 case Hexagon::STrid_GP_cPt_V4: 1654 return Hexagon::STrid_GP_cNotPt_V4; 1655 case Hexagon::STrid_GP_cNotPt_V4: 1656 return Hexagon::STrid_GP_cPt_V4; 1657 1658 case Hexagon::STrib_GP_cPt_V4: 1659 return Hexagon::STrib_GP_cNotPt_V4; 1660 case Hexagon::STrib_GP_cNotPt_V4: 1661 return Hexagon::STrib_GP_cPt_V4; 1662 1663 case Hexagon::STrih_GP_cPt_V4: 1664 return Hexagon::STrih_GP_cNotPt_V4; 1665 case Hexagon::STrih_GP_cNotPt_V4: 1666 return Hexagon::STrih_GP_cPt_V4; 1667 1668 case Hexagon::STriw_GP_cPt_V4: 1669 return Hexagon::STriw_GP_cNotPt_V4; 1670 case Hexagon::STriw_GP_cNotPt_V4: 1671 return Hexagon::STriw_GP_cPt_V4; 1672 1673 // Load. 1674 case Hexagon::LDrid_cPt: 1675 return Hexagon::LDrid_cNotPt; 1676 case Hexagon::LDrid_cNotPt: 1677 return Hexagon::LDrid_cPt; 1678 1679 case Hexagon::LDriw_cPt: 1680 return Hexagon::LDriw_cNotPt; 1681 case Hexagon::LDriw_cNotPt: 1682 return Hexagon::LDriw_cPt; 1683 1684 case Hexagon::LDrih_cPt: 1685 return Hexagon::LDrih_cNotPt; 1686 case Hexagon::LDrih_cNotPt: 1687 return Hexagon::LDrih_cPt; 1688 1689 case Hexagon::LDriuh_cPt: 1690 return Hexagon::LDriuh_cNotPt; 1691 case Hexagon::LDriuh_cNotPt: 1692 return Hexagon::LDriuh_cPt; 1693 1694 case Hexagon::LDrib_cPt: 1695 return Hexagon::LDrib_cNotPt; 1696 case Hexagon::LDrib_cNotPt: 1697 return Hexagon::LDrib_cPt; 1698 1699 case Hexagon::LDriub_cPt: 1700 return Hexagon::LDriub_cNotPt; 1701 case Hexagon::LDriub_cNotPt: 1702 return Hexagon::LDriub_cPt; 1703 1704 // Load Indexed. 1705 case Hexagon::LDrid_indexed_cPt: 1706 return Hexagon::LDrid_indexed_cNotPt; 1707 case Hexagon::LDrid_indexed_cNotPt: 1708 return Hexagon::LDrid_indexed_cPt; 1709 1710 case Hexagon::LDriw_indexed_cPt: 1711 return Hexagon::LDriw_indexed_cNotPt; 1712 case Hexagon::LDriw_indexed_cNotPt: 1713 return Hexagon::LDriw_indexed_cPt; 1714 1715 case Hexagon::LDrih_indexed_cPt: 1716 return Hexagon::LDrih_indexed_cNotPt; 1717 case Hexagon::LDrih_indexed_cNotPt: 1718 return Hexagon::LDrih_indexed_cPt; 1719 1720 case Hexagon::LDriuh_indexed_cPt: 1721 return Hexagon::LDriuh_indexed_cNotPt; 1722 case Hexagon::LDriuh_indexed_cNotPt: 1723 return Hexagon::LDriuh_indexed_cPt; 1724 1725 case Hexagon::LDrib_indexed_cPt: 1726 return Hexagon::LDrib_indexed_cNotPt; 1727 case Hexagon::LDrib_indexed_cNotPt: 1728 return Hexagon::LDrib_indexed_cPt; 1729 1730 case Hexagon::LDriub_indexed_cPt: 1731 return Hexagon::LDriub_indexed_cNotPt; 1732 case Hexagon::LDriub_indexed_cNotPt: 1733 return Hexagon::LDriub_indexed_cPt; 1734 1735 // Post Inc Load. 1736 case Hexagon::POST_LDrid_cPt: 1737 return Hexagon::POST_LDrid_cNotPt; 1738 case Hexagon::POST_LDriw_cNotPt: 1739 return Hexagon::POST_LDriw_cPt; 1740 1741 case Hexagon::POST_LDrih_cPt: 1742 return Hexagon::POST_LDrih_cNotPt; 1743 case Hexagon::POST_LDrih_cNotPt: 1744 return Hexagon::POST_LDrih_cPt; 1745 1746 case Hexagon::POST_LDriuh_cPt: 1747 return Hexagon::POST_LDriuh_cNotPt; 1748 case Hexagon::POST_LDriuh_cNotPt: 1749 return Hexagon::POST_LDriuh_cPt; 1750 1751 case Hexagon::POST_LDrib_cPt: 1752 return Hexagon::POST_LDrib_cNotPt; 1753 case Hexagon::POST_LDrib_cNotPt: 1754 return Hexagon::POST_LDrib_cPt; 1755 1756 case Hexagon::POST_LDriub_cPt: 1757 return Hexagon::POST_LDriub_cNotPt; 1758 case Hexagon::POST_LDriub_cNotPt: 1759 return Hexagon::POST_LDriub_cPt; 1760 1761 // Dealloc_return. 1762 case Hexagon::DEALLOC_RET_cPt_V4: 1763 return Hexagon::DEALLOC_RET_cNotPt_V4; 1764 case Hexagon::DEALLOC_RET_cNotPt_V4: 1765 return Hexagon::DEALLOC_RET_cPt_V4; 1766 1767 // New Value Jump. 1768 // JMPEQ_ri - with -1. 1769 case Hexagon::JMP_EQriPtneg_nv_V4: 1770 return Hexagon::JMP_EQriNotPtneg_nv_V4; 1771 case Hexagon::JMP_EQriNotPtneg_nv_V4: 1772 return Hexagon::JMP_EQriPtneg_nv_V4; 1773 1774 case Hexagon::JMP_EQriPntneg_nv_V4: 1775 return Hexagon::JMP_EQriNotPntneg_nv_V4; 1776 case Hexagon::JMP_EQriNotPntneg_nv_V4: 1777 return Hexagon::JMP_EQriPntneg_nv_V4; 1778 1779 // JMPEQ_ri. 1780 case Hexagon::JMP_EQriPt_nv_V4: 1781 return Hexagon::JMP_EQriNotPt_nv_V4; 1782 case Hexagon::JMP_EQriNotPt_nv_V4: 1783 return Hexagon::JMP_EQriPt_nv_V4; 1784 1785 case Hexagon::JMP_EQriPnt_nv_V4: 1786 return Hexagon::JMP_EQriNotPnt_nv_V4; 1787 case Hexagon::JMP_EQriNotPnt_nv_V4: 1788 return Hexagon::JMP_EQriPnt_nv_V4; 1789 1790 // JMPEQ_rr. 1791 case Hexagon::JMP_EQrrPt_nv_V4: 1792 return Hexagon::JMP_EQrrNotPt_nv_V4; 1793 case Hexagon::JMP_EQrrNotPt_nv_V4: 1794 return Hexagon::JMP_EQrrPt_nv_V4; 1795 1796 case Hexagon::JMP_EQrrPnt_nv_V4: 1797 return Hexagon::JMP_EQrrNotPnt_nv_V4; 1798 case Hexagon::JMP_EQrrNotPnt_nv_V4: 1799 return Hexagon::JMP_EQrrPnt_nv_V4; 1800 1801 // JMPGT_ri - with -1. 1802 case Hexagon::JMP_GTriPtneg_nv_V4: 1803 return Hexagon::JMP_GTriNotPtneg_nv_V4; 1804 case Hexagon::JMP_GTriNotPtneg_nv_V4: 1805 return Hexagon::JMP_GTriPtneg_nv_V4; 1806 1807 case Hexagon::JMP_GTriPntneg_nv_V4: 1808 return Hexagon::JMP_GTriNotPntneg_nv_V4; 1809 case Hexagon::JMP_GTriNotPntneg_nv_V4: 1810 return Hexagon::JMP_GTriPntneg_nv_V4; 1811 1812 // JMPGT_ri. 1813 case Hexagon::JMP_GTriPt_nv_V4: 1814 return Hexagon::JMP_GTriNotPt_nv_V4; 1815 case Hexagon::JMP_GTriNotPt_nv_V4: 1816 return Hexagon::JMP_GTriPt_nv_V4; 1817 1818 case Hexagon::JMP_GTriPnt_nv_V4: 1819 return Hexagon::JMP_GTriNotPnt_nv_V4; 1820 case Hexagon::JMP_GTriNotPnt_nv_V4: 1821 return Hexagon::JMP_GTriPnt_nv_V4; 1822 1823 // JMPGT_rr. 1824 case Hexagon::JMP_GTrrPt_nv_V4: 1825 return Hexagon::JMP_GTrrNotPt_nv_V4; 1826 case Hexagon::JMP_GTrrNotPt_nv_V4: 1827 return Hexagon::JMP_GTrrPt_nv_V4; 1828 1829 case Hexagon::JMP_GTrrPnt_nv_V4: 1830 return Hexagon::JMP_GTrrNotPnt_nv_V4; 1831 case Hexagon::JMP_GTrrNotPnt_nv_V4: 1832 return Hexagon::JMP_GTrrPnt_nv_V4; 1833 1834 // JMPGT_rrdn. 1835 case Hexagon::JMP_GTrrdnPt_nv_V4: 1836 return Hexagon::JMP_GTrrdnNotPt_nv_V4; 1837 case Hexagon::JMP_GTrrdnNotPt_nv_V4: 1838 return Hexagon::JMP_GTrrdnPt_nv_V4; 1839 1840 case Hexagon::JMP_GTrrdnPnt_nv_V4: 1841 return Hexagon::JMP_GTrrdnNotPnt_nv_V4; 1842 case Hexagon::JMP_GTrrdnNotPnt_nv_V4: 1843 return Hexagon::JMP_GTrrdnPnt_nv_V4; 1844 1845 // JMPGTU_ri. 1846 case Hexagon::JMP_GTUriPt_nv_V4: 1847 return Hexagon::JMP_GTUriNotPt_nv_V4; 1848 case Hexagon::JMP_GTUriNotPt_nv_V4: 1849 return Hexagon::JMP_GTUriPt_nv_V4; 1850 1851 case Hexagon::JMP_GTUriPnt_nv_V4: 1852 return Hexagon::JMP_GTUriNotPnt_nv_V4; 1853 case Hexagon::JMP_GTUriNotPnt_nv_V4: 1854 return Hexagon::JMP_GTUriPnt_nv_V4; 1855 1856 // JMPGTU_rr. 1857 case Hexagon::JMP_GTUrrPt_nv_V4: 1858 return Hexagon::JMP_GTUrrNotPt_nv_V4; 1859 case Hexagon::JMP_GTUrrNotPt_nv_V4: 1860 return Hexagon::JMP_GTUrrPt_nv_V4; 1861 1862 case Hexagon::JMP_GTUrrPnt_nv_V4: 1863 return Hexagon::JMP_GTUrrNotPnt_nv_V4; 1864 case Hexagon::JMP_GTUrrNotPnt_nv_V4: 1865 return Hexagon::JMP_GTUrrPnt_nv_V4; 1866 1867 // JMPGTU_rrdn. 1868 case Hexagon::JMP_GTUrrdnPt_nv_V4: 1869 return Hexagon::JMP_GTUrrdnNotPt_nv_V4; 1870 case Hexagon::JMP_GTUrrdnNotPt_nv_V4: 1871 return Hexagon::JMP_GTUrrdnPt_nv_V4; 1872 1873 case Hexagon::JMP_GTUrrdnPnt_nv_V4: 1874 return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; 1875 case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: 1876 return Hexagon::JMP_GTUrrdnPnt_nv_V4; 1877 } 1878} 1879 1880 1881int HexagonInstrInfo:: 1882getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { 1883 enum Hexagon::PredSense inPredSense; 1884 inPredSense = invertPredicate ? Hexagon::PredSense_false : 1885 Hexagon::PredSense_true; 1886 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); 1887 if (CondOpcode >= 0) // Valid Conditional opcode/instruction 1888 return CondOpcode; 1889 1890 // This switch case will be removed once all the instructions have been 1891 // modified to use relation maps. 1892 switch(Opc) { 1893 case Hexagon::TFR: 1894 return !invertPredicate ? Hexagon::TFR_cPt : 1895 Hexagon::TFR_cNotPt; 1896 case Hexagon::TFRI_f: 1897 return !invertPredicate ? Hexagon::TFRI_cPt_f : 1898 Hexagon::TFRI_cNotPt_f; 1899 case Hexagon::TFRI: 1900 return !invertPredicate ? Hexagon::TFRI_cPt : 1901 Hexagon::TFRI_cNotPt; 1902 case Hexagon::JMP: 1903 return !invertPredicate ? Hexagon::JMP_c : 1904 Hexagon::JMP_cNot; 1905 case Hexagon::JMP_EQrrPt_nv_V4: 1906 return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : 1907 Hexagon::JMP_EQrrNotPt_nv_V4; 1908 case Hexagon::JMP_EQriPt_nv_V4: 1909 return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : 1910 Hexagon::JMP_EQriNotPt_nv_V4; 1911 case Hexagon::COMBINE_rr: 1912 return !invertPredicate ? Hexagon::COMBINE_rr_cPt : 1913 Hexagon::COMBINE_rr_cNotPt; 1914 case Hexagon::ASLH: 1915 return !invertPredicate ? Hexagon::ASLH_cPt_V4 : 1916 Hexagon::ASLH_cNotPt_V4; 1917 case Hexagon::ASRH: 1918 return !invertPredicate ? Hexagon::ASRH_cPt_V4 : 1919 Hexagon::ASRH_cNotPt_V4; 1920 case Hexagon::SXTB: 1921 return !invertPredicate ? Hexagon::SXTB_cPt_V4 : 1922 Hexagon::SXTB_cNotPt_V4; 1923 case Hexagon::SXTH: 1924 return !invertPredicate ? Hexagon::SXTH_cPt_V4 : 1925 Hexagon::SXTH_cNotPt_V4; 1926 case Hexagon::ZXTB: 1927 return !invertPredicate ? Hexagon::ZXTB_cPt_V4 : 1928 Hexagon::ZXTB_cNotPt_V4; 1929 case Hexagon::ZXTH: 1930 return !invertPredicate ? Hexagon::ZXTH_cPt_V4 : 1931 Hexagon::ZXTH_cNotPt_V4; 1932 1933 case Hexagon::JMPR: 1934 return !invertPredicate ? Hexagon::JMPR_cPt : 1935 Hexagon::JMPR_cNotPt; 1936 1937 // V4 indexed+scaled load. 1938 case Hexagon::LDrid_indexed_shl_V4: 1939 return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 : 1940 Hexagon::LDrid_indexed_shl_cNotPt_V4; 1941 case Hexagon::LDrib_indexed_shl_V4: 1942 return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 : 1943 Hexagon::LDrib_indexed_shl_cNotPt_V4; 1944 case Hexagon::LDriub_indexed_shl_V4: 1945 return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 : 1946 Hexagon::LDriub_indexed_shl_cNotPt_V4; 1947 case Hexagon::LDrih_indexed_shl_V4: 1948 return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 : 1949 Hexagon::LDrih_indexed_shl_cNotPt_V4; 1950 case Hexagon::LDriuh_indexed_shl_V4: 1951 return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 : 1952 Hexagon::LDriuh_indexed_shl_cNotPt_V4; 1953 case Hexagon::LDriw_indexed_shl_V4: 1954 return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : 1955 Hexagon::LDriw_indexed_shl_cNotPt_V4; 1956 1957 // V4 Load from global address 1958 case Hexagon::LDrid_GP_V4: 1959 return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 : 1960 Hexagon::LDrid_GP_cNotPt_V4; 1961 case Hexagon::LDrib_GP_V4: 1962 return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 : 1963 Hexagon::LDrib_GP_cNotPt_V4; 1964 case Hexagon::LDriub_GP_V4: 1965 return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 : 1966 Hexagon::LDriub_GP_cNotPt_V4; 1967 case Hexagon::LDrih_GP_V4: 1968 return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 : 1969 Hexagon::LDrih_GP_cNotPt_V4; 1970 case Hexagon::LDriuh_GP_V4: 1971 return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 : 1972 Hexagon::LDriuh_GP_cNotPt_V4; 1973 case Hexagon::LDriw_GP_V4: 1974 return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 : 1975 Hexagon::LDriw_GP_cNotPt_V4; 1976 1977 case Hexagon::LDd_GP_V4: 1978 return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : 1979 Hexagon::LDd_GP_cNotPt_V4; 1980 case Hexagon::LDb_GP_V4: 1981 return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : 1982 Hexagon::LDb_GP_cNotPt_V4; 1983 case Hexagon::LDub_GP_V4: 1984 return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : 1985 Hexagon::LDub_GP_cNotPt_V4; 1986 case Hexagon::LDh_GP_V4: 1987 return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : 1988 Hexagon::LDh_GP_cNotPt_V4; 1989 case Hexagon::LDuh_GP_V4: 1990 return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : 1991 Hexagon::LDuh_GP_cNotPt_V4; 1992 case Hexagon::LDw_GP_V4: 1993 return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : 1994 Hexagon::LDw_GP_cNotPt_V4; 1995 1996 // Byte. 1997 case Hexagon::POST_STbri: 1998 return !invertPredicate ? Hexagon::POST_STbri_cPt : 1999 Hexagon::POST_STbri_cNotPt; 2000 case Hexagon::STrib: 2001 return !invertPredicate ? Hexagon::STrib_cPt : 2002 Hexagon::STrib_cNotPt; 2003 case Hexagon::STrib_indexed: 2004 return !invertPredicate ? Hexagon::STrib_indexed_cPt : 2005 Hexagon::STrib_indexed_cNotPt; 2006 case Hexagon::STrib_imm_V4: 2007 return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 : 2008 Hexagon::STrib_imm_cNotPt_V4; 2009 case Hexagon::STrib_indexed_shl_V4: 2010 return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 : 2011 Hexagon::STrib_indexed_shl_cNotPt_V4; 2012 // Halfword. 2013 case Hexagon::POST_SThri: 2014 return !invertPredicate ? Hexagon::POST_SThri_cPt : 2015 Hexagon::POST_SThri_cNotPt; 2016 case Hexagon::STrih: 2017 return !invertPredicate ? Hexagon::STrih_cPt : 2018 Hexagon::STrih_cNotPt; 2019 case Hexagon::STrih_indexed: 2020 return !invertPredicate ? Hexagon::STrih_indexed_cPt : 2021 Hexagon::STrih_indexed_cNotPt; 2022 case Hexagon::STrih_imm_V4: 2023 return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 : 2024 Hexagon::STrih_imm_cNotPt_V4; 2025 case Hexagon::STrih_indexed_shl_V4: 2026 return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 : 2027 Hexagon::STrih_indexed_shl_cNotPt_V4; 2028 // Word. 2029 case Hexagon::POST_STwri: 2030 return !invertPredicate ? Hexagon::POST_STwri_cPt : 2031 Hexagon::POST_STwri_cNotPt; 2032 case Hexagon::STriw: 2033 return !invertPredicate ? Hexagon::STriw_cPt : 2034 Hexagon::STriw_cNotPt; 2035 case Hexagon::STriw_indexed: 2036 return !invertPredicate ? Hexagon::STriw_indexed_cPt : 2037 Hexagon::STriw_indexed_cNotPt; 2038 case Hexagon::STriw_indexed_shl_V4: 2039 return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 : 2040 Hexagon::STriw_indexed_shl_cNotPt_V4; 2041 case Hexagon::STriw_imm_V4: 2042 return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 : 2043 Hexagon::STriw_imm_cNotPt_V4; 2044 // Double word. 2045 case Hexagon::POST_STdri: 2046 return !invertPredicate ? Hexagon::POST_STdri_cPt : 2047 Hexagon::POST_STdri_cNotPt; 2048 case Hexagon::STrid: 2049 return !invertPredicate ? Hexagon::STrid_cPt : 2050 Hexagon::STrid_cNotPt; 2051 case Hexagon::STrid_indexed: 2052 return !invertPredicate ? Hexagon::STrid_indexed_cPt : 2053 Hexagon::STrid_indexed_cNotPt; 2054 case Hexagon::STrid_indexed_shl_V4: 2055 return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : 2056 Hexagon::STrid_indexed_shl_cNotPt_V4; 2057 2058 // V4 Store to global address 2059 case Hexagon::STrid_GP_V4: 2060 return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 : 2061 Hexagon::STrid_GP_cNotPt_V4; 2062 case Hexagon::STrib_GP_V4: 2063 return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 : 2064 Hexagon::STrib_GP_cNotPt_V4; 2065 case Hexagon::STrih_GP_V4: 2066 return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 : 2067 Hexagon::STrih_GP_cNotPt_V4; 2068 case Hexagon::STriw_GP_V4: 2069 return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 : 2070 Hexagon::STriw_GP_cNotPt_V4; 2071 2072 case Hexagon::STd_GP_V4: 2073 return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : 2074 Hexagon::STd_GP_cNotPt_V4; 2075 case Hexagon::STb_GP_V4: 2076 return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : 2077 Hexagon::STb_GP_cNotPt_V4; 2078 case Hexagon::STh_GP_V4: 2079 return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : 2080 Hexagon::STh_GP_cNotPt_V4; 2081 case Hexagon::STw_GP_V4: 2082 return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : 2083 Hexagon::STw_GP_cNotPt_V4; 2084 2085 // Load. 2086 case Hexagon::LDrid: 2087 return !invertPredicate ? Hexagon::LDrid_cPt : 2088 Hexagon::LDrid_cNotPt; 2089 case Hexagon::LDriw: 2090 return !invertPredicate ? Hexagon::LDriw_cPt : 2091 Hexagon::LDriw_cNotPt; 2092 case Hexagon::LDrih: 2093 return !invertPredicate ? Hexagon::LDrih_cPt : 2094 Hexagon::LDrih_cNotPt; 2095 case Hexagon::LDriuh: 2096 return !invertPredicate ? Hexagon::LDriuh_cPt : 2097 Hexagon::LDriuh_cNotPt; 2098 case Hexagon::LDrib: 2099 return !invertPredicate ? Hexagon::LDrib_cPt : 2100 Hexagon::LDrib_cNotPt; 2101 case Hexagon::LDriub: 2102 return !invertPredicate ? Hexagon::LDriub_cPt : 2103 Hexagon::LDriub_cNotPt; 2104 // Load Indexed. 2105 case Hexagon::LDrid_indexed: 2106 return !invertPredicate ? Hexagon::LDrid_indexed_cPt : 2107 Hexagon::LDrid_indexed_cNotPt; 2108 case Hexagon::LDriw_indexed: 2109 return !invertPredicate ? Hexagon::LDriw_indexed_cPt : 2110 Hexagon::LDriw_indexed_cNotPt; 2111 case Hexagon::LDrih_indexed: 2112 return !invertPredicate ? Hexagon::LDrih_indexed_cPt : 2113 Hexagon::LDrih_indexed_cNotPt; 2114 case Hexagon::LDriuh_indexed: 2115 return !invertPredicate ? Hexagon::LDriuh_indexed_cPt : 2116 Hexagon::LDriuh_indexed_cNotPt; 2117 case Hexagon::LDrib_indexed: 2118 return !invertPredicate ? Hexagon::LDrib_indexed_cPt : 2119 Hexagon::LDrib_indexed_cNotPt; 2120 case Hexagon::LDriub_indexed: 2121 return !invertPredicate ? Hexagon::LDriub_indexed_cPt : 2122 Hexagon::LDriub_indexed_cNotPt; 2123 // Post Increment Load. 2124 case Hexagon::POST_LDrid: 2125 return !invertPredicate ? Hexagon::POST_LDrid_cPt : 2126 Hexagon::POST_LDrid_cNotPt; 2127 case Hexagon::POST_LDriw: 2128 return !invertPredicate ? Hexagon::POST_LDriw_cPt : 2129 Hexagon::POST_LDriw_cNotPt; 2130 case Hexagon::POST_LDrih: 2131 return !invertPredicate ? Hexagon::POST_LDrih_cPt : 2132 Hexagon::POST_LDrih_cNotPt; 2133 case Hexagon::POST_LDriuh: 2134 return !invertPredicate ? Hexagon::POST_LDriuh_cPt : 2135 Hexagon::POST_LDriuh_cNotPt; 2136 case Hexagon::POST_LDrib: 2137 return !invertPredicate ? Hexagon::POST_LDrib_cPt : 2138 Hexagon::POST_LDrib_cNotPt; 2139 case Hexagon::POST_LDriub: 2140 return !invertPredicate ? Hexagon::POST_LDriub_cPt : 2141 Hexagon::POST_LDriub_cNotPt; 2142 // DEALLOC_RETURN. 2143 case Hexagon::DEALLOC_RET_V4: 2144 return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : 2145 Hexagon::DEALLOC_RET_cNotPt_V4; 2146 } 2147 llvm_unreachable("Unexpected predicable instruction"); 2148} 2149 2150 2151bool HexagonInstrInfo:: 2152PredicateInstruction(MachineInstr *MI, 2153 const SmallVectorImpl<MachineOperand> &Cond) const { 2154 int Opc = MI->getOpcode(); 2155 assert (isPredicable(MI) && "Expected predicable instruction"); 2156 bool invertJump = (!Cond.empty() && Cond[0].isImm() && 2157 (Cond[0].getImm() == 0)); 2158 MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump))); 2159 // 2160 // This assumes that the predicate is always the first operand 2161 // in the set of inputs. 2162 // 2163 MI->addOperand(MI->getOperand(MI->getNumOperands()-1)); 2164 int oper; 2165 for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) { 2166 MachineOperand MO = MI->getOperand(oper); 2167 if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) { 2168 break; 2169 } 2170 2171 if (MO.isReg()) { 2172 MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(), 2173 MO.isImplicit(), MO.isKill(), 2174 MO.isDead(), MO.isUndef(), 2175 MO.isDebug()); 2176 } else if (MO.isImm()) { 2177 MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); 2178 } else { 2179 llvm_unreachable("Unexpected operand type"); 2180 } 2181 } 2182 2183 int regPos = invertJump ? 1 : 0; 2184 MachineOperand PredMO = Cond[regPos]; 2185 MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(), 2186 PredMO.isImplicit(), PredMO.isKill(), 2187 PredMO.isDead(), PredMO.isUndef(), 2188 PredMO.isDebug()); 2189 2190 return true; 2191} 2192 2193 2194bool 2195HexagonInstrInfo:: 2196isProfitableToIfCvt(MachineBasicBlock &MBB, 2197 unsigned NumCycles, 2198 unsigned ExtraPredCycles, 2199 const BranchProbability &Probability) const { 2200 return true; 2201} 2202 2203 2204bool 2205HexagonInstrInfo:: 2206isProfitableToIfCvt(MachineBasicBlock &TMBB, 2207 unsigned NumTCycles, 2208 unsigned ExtraTCycles, 2209 MachineBasicBlock &FMBB, 2210 unsigned NumFCycles, 2211 unsigned ExtraFCycles, 2212 const BranchProbability &Probability) const { 2213 return true; 2214} 2215 2216 2217bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { 2218 const uint64_t F = MI->getDesc().TSFlags; 2219 2220 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); 2221} 2222 2223bool 2224HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, 2225 std::vector<MachineOperand> &Pred) const { 2226 for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) { 2227 MachineOperand MO = MI->getOperand(oper); 2228 if (MO.isReg() && MO.isDef()) { 2229 const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); 2230 if (RC == &Hexagon::PredRegsRegClass) { 2231 Pred.push_back(MO); 2232 return true; 2233 } 2234 } 2235 } 2236 return false; 2237} 2238 2239 2240bool 2241HexagonInstrInfo:: 2242SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 2243 const SmallVectorImpl<MachineOperand> &Pred2) const { 2244 // TODO: Fix this 2245 return false; 2246} 2247 2248 2249// 2250// We indicate that we want to reverse the branch by 2251// inserting a 0 at the beginning of the Cond vector. 2252// 2253bool HexagonInstrInfo:: 2254ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2255 if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { 2256 Cond.erase(Cond.begin()); 2257 } else { 2258 Cond.insert(Cond.begin(), MachineOperand::CreateImm(0)); 2259 } 2260 return false; 2261} 2262 2263 2264bool HexagonInstrInfo:: 2265isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, 2266 const BranchProbability &Probability) const { 2267 return (NumInstrs <= 4); 2268} 2269 2270bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { 2271 switch (MI->getOpcode()) { 2272 default: return false; 2273 case Hexagon::DEALLOC_RET_V4 : 2274 case Hexagon::DEALLOC_RET_cPt_V4 : 2275 case Hexagon::DEALLOC_RET_cNotPt_V4 : 2276 case Hexagon::DEALLOC_RET_cdnPnt_V4 : 2277 case Hexagon::DEALLOC_RET_cNotdnPnt_V4 : 2278 case Hexagon::DEALLOC_RET_cdnPt_V4 : 2279 case Hexagon::DEALLOC_RET_cNotdnPt_V4 : 2280 return true; 2281 } 2282} 2283 2284 2285bool HexagonInstrInfo:: 2286isValidOffset(const int Opcode, const int Offset) const { 2287 // This function is to check whether the "Offset" is in the correct range of 2288 // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is 2289 // inserted to calculate the final address. Due to this reason, the function 2290 // assumes that the "Offset" has correct alignment. 2291 2292 switch(Opcode) { 2293 2294 case Hexagon::LDriw: 2295 case Hexagon::LDriw_indexed: 2296 case Hexagon::LDriw_f: 2297 case Hexagon::STriw_indexed: 2298 case Hexagon::STriw: 2299 case Hexagon::STriw_f: 2300 assert((Offset % 4 == 0) && "Offset has incorrect alignment"); 2301 return (Offset >= Hexagon_MEMW_OFFSET_MIN) && 2302 (Offset <= Hexagon_MEMW_OFFSET_MAX); 2303 2304 case Hexagon::LDrid: 2305 case Hexagon::LDrid_indexed: 2306 case Hexagon::LDrid_f: 2307 case Hexagon::STrid: 2308 case Hexagon::STrid_indexed: 2309 case Hexagon::STrid_f: 2310 assert((Offset % 8 == 0) && "Offset has incorrect alignment"); 2311 return (Offset >= Hexagon_MEMD_OFFSET_MIN) && 2312 (Offset <= Hexagon_MEMD_OFFSET_MAX); 2313 2314 case Hexagon::LDrih: 2315 case Hexagon::LDriuh: 2316 case Hexagon::STrih: 2317 assert((Offset % 2 == 0) && "Offset has incorrect alignment"); 2318 return (Offset >= Hexagon_MEMH_OFFSET_MIN) && 2319 (Offset <= Hexagon_MEMH_OFFSET_MAX); 2320 2321 case Hexagon::LDrib: 2322 case Hexagon::STrib: 2323 case Hexagon::LDriub: 2324 return (Offset >= Hexagon_MEMB_OFFSET_MIN) && 2325 (Offset <= Hexagon_MEMB_OFFSET_MAX); 2326 2327 case Hexagon::ADD_ri: 2328 case Hexagon::TFR_FI: 2329 return (Offset >= Hexagon_ADDI_OFFSET_MIN) && 2330 (Offset <= Hexagon_ADDI_OFFSET_MAX); 2331 2332 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2333 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2334 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2335 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2336 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2337 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2338 case Hexagon::MEMw_ADDi_MEM_V4 : 2339 case Hexagon::MEMw_SUBi_MEM_V4 : 2340 case Hexagon::MEMw_ADDr_MEM_V4 : 2341 case Hexagon::MEMw_SUBr_MEM_V4 : 2342 case Hexagon::MEMw_ANDr_MEM_V4 : 2343 case Hexagon::MEMw_ORr_MEM_V4 : 2344 assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." ); 2345 return (0 <= Offset && Offset <= 255); 2346 2347 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2348 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2349 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2350 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2351 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2352 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2353 case Hexagon::MEMh_ADDi_MEM_V4 : 2354 case Hexagon::MEMh_SUBi_MEM_V4 : 2355 case Hexagon::MEMh_ADDr_MEM_V4 : 2356 case Hexagon::MEMh_SUBr_MEM_V4 : 2357 case Hexagon::MEMh_ANDr_MEM_V4 : 2358 case Hexagon::MEMh_ORr_MEM_V4 : 2359 assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." ); 2360 return (0 <= Offset && Offset <= 127); 2361 2362 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2363 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2364 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2365 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2366 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2367 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2368 case Hexagon::MEMb_ADDi_MEM_V4 : 2369 case Hexagon::MEMb_SUBi_MEM_V4 : 2370 case Hexagon::MEMb_ADDr_MEM_V4 : 2371 case Hexagon::MEMb_SUBr_MEM_V4 : 2372 case Hexagon::MEMb_ANDr_MEM_V4 : 2373 case Hexagon::MEMb_ORr_MEM_V4 : 2374 return (0 <= Offset && Offset <= 63); 2375 2376 // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of 2377 // any size. Later pass knows how to handle it. 2378 case Hexagon::STriw_pred: 2379 case Hexagon::LDriw_pred: 2380 return true; 2381 2382 // INLINEASM is very special. 2383 case Hexagon::INLINEASM: 2384 return true; 2385 } 2386 2387 llvm_unreachable("No offset range is defined for this opcode. " 2388 "Please define it in the above switch statement!"); 2389} 2390 2391 2392// 2393// Check if the Offset is a valid auto-inc imm by Load/Store Type. 2394// 2395bool HexagonInstrInfo:: 2396isValidAutoIncImm(const EVT VT, const int Offset) const { 2397 2398 if (VT == MVT::i64) { 2399 return (Offset >= Hexagon_MEMD_AUTOINC_MIN && 2400 Offset <= Hexagon_MEMD_AUTOINC_MAX && 2401 (Offset & 0x7) == 0); 2402 } 2403 if (VT == MVT::i32) { 2404 return (Offset >= Hexagon_MEMW_AUTOINC_MIN && 2405 Offset <= Hexagon_MEMW_AUTOINC_MAX && 2406 (Offset & 0x3) == 0); 2407 } 2408 if (VT == MVT::i16) { 2409 return (Offset >= Hexagon_MEMH_AUTOINC_MIN && 2410 Offset <= Hexagon_MEMH_AUTOINC_MAX && 2411 (Offset & 0x1) == 0); 2412 } 2413 if (VT == MVT::i8) { 2414 return (Offset >= Hexagon_MEMB_AUTOINC_MIN && 2415 Offset <= Hexagon_MEMB_AUTOINC_MAX); 2416 } 2417 llvm_unreachable("Not an auto-inc opc!"); 2418} 2419 2420 2421bool HexagonInstrInfo:: 2422isMemOp(const MachineInstr *MI) const { 2423 switch (MI->getOpcode()) 2424 { 2425 default: return false; 2426 case Hexagon::MEMw_ADDi_indexed_MEM_V4 : 2427 case Hexagon::MEMw_SUBi_indexed_MEM_V4 : 2428 case Hexagon::MEMw_ADDr_indexed_MEM_V4 : 2429 case Hexagon::MEMw_SUBr_indexed_MEM_V4 : 2430 case Hexagon::MEMw_ANDr_indexed_MEM_V4 : 2431 case Hexagon::MEMw_ORr_indexed_MEM_V4 : 2432 case Hexagon::MEMw_ADDi_MEM_V4 : 2433 case Hexagon::MEMw_SUBi_MEM_V4 : 2434 case Hexagon::MEMw_ADDr_MEM_V4 : 2435 case Hexagon::MEMw_SUBr_MEM_V4 : 2436 case Hexagon::MEMw_ANDr_MEM_V4 : 2437 case Hexagon::MEMw_ORr_MEM_V4 : 2438 case Hexagon::MEMh_ADDi_indexed_MEM_V4 : 2439 case Hexagon::MEMh_SUBi_indexed_MEM_V4 : 2440 case Hexagon::MEMh_ADDr_indexed_MEM_V4 : 2441 case Hexagon::MEMh_SUBr_indexed_MEM_V4 : 2442 case Hexagon::MEMh_ANDr_indexed_MEM_V4 : 2443 case Hexagon::MEMh_ORr_indexed_MEM_V4 : 2444 case Hexagon::MEMh_ADDi_MEM_V4 : 2445 case Hexagon::MEMh_SUBi_MEM_V4 : 2446 case Hexagon::MEMh_ADDr_MEM_V4 : 2447 case Hexagon::MEMh_SUBr_MEM_V4 : 2448 case Hexagon::MEMh_ANDr_MEM_V4 : 2449 case Hexagon::MEMh_ORr_MEM_V4 : 2450 case Hexagon::MEMb_ADDi_indexed_MEM_V4 : 2451 case Hexagon::MEMb_SUBi_indexed_MEM_V4 : 2452 case Hexagon::MEMb_ADDr_indexed_MEM_V4 : 2453 case Hexagon::MEMb_SUBr_indexed_MEM_V4 : 2454 case Hexagon::MEMb_ANDr_indexed_MEM_V4 : 2455 case Hexagon::MEMb_ORr_indexed_MEM_V4 : 2456 case Hexagon::MEMb_ADDi_MEM_V4 : 2457 case Hexagon::MEMb_SUBi_MEM_V4 : 2458 case Hexagon::MEMb_ADDr_MEM_V4 : 2459 case Hexagon::MEMb_SUBr_MEM_V4 : 2460 case Hexagon::MEMb_ANDr_MEM_V4 : 2461 case Hexagon::MEMb_ORr_MEM_V4 : 2462 return true; 2463 } 2464} 2465 2466 2467bool HexagonInstrInfo:: 2468isSpillPredRegOp(const MachineInstr *MI) const { 2469 switch (MI->getOpcode()) { 2470 default: return false; 2471 case Hexagon::STriw_pred : 2472 case Hexagon::LDriw_pred : 2473 return true; 2474 } 2475} 2476 2477bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { 2478 switch (MI->getOpcode()) { 2479 default: return false; 2480 case Hexagon::CMPEQrr: 2481 case Hexagon::CMPEQri: 2482 case Hexagon::CMPLTrr: 2483 case Hexagon::CMPGTrr: 2484 case Hexagon::CMPGTri: 2485 case Hexagon::CMPLTUrr: 2486 case Hexagon::CMPGTUrr: 2487 case Hexagon::CMPGTUri: 2488 case Hexagon::CMPGEri: 2489 case Hexagon::CMPGEUri: 2490 return true; 2491 } 2492} 2493 2494bool HexagonInstrInfo:: 2495isConditionalTransfer (const MachineInstr *MI) const { 2496 switch (MI->getOpcode()) { 2497 default: return false; 2498 case Hexagon::TFR_cPt: 2499 case Hexagon::TFR_cNotPt: 2500 case Hexagon::TFRI_cPt: 2501 case Hexagon::TFRI_cNotPt: 2502 case Hexagon::TFR_cdnPt: 2503 case Hexagon::TFR_cdnNotPt: 2504 case Hexagon::TFRI_cdnPt: 2505 case Hexagon::TFRI_cdnNotPt: 2506 return true; 2507 } 2508} 2509 2510bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { 2511 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2512 switch (MI->getOpcode()) 2513 { 2514 default: return false; 2515 case Hexagon::ADD_ri_cPt: 2516 case Hexagon::ADD_ri_cNotPt: 2517 case Hexagon::ADD_rr_cPt: 2518 case Hexagon::ADD_rr_cNotPt: 2519 case Hexagon::XOR_rr_cPt: 2520 case Hexagon::XOR_rr_cNotPt: 2521 case Hexagon::AND_rr_cPt: 2522 case Hexagon::AND_rr_cNotPt: 2523 case Hexagon::OR_rr_cPt: 2524 case Hexagon::OR_rr_cNotPt: 2525 case Hexagon::SUB_rr_cPt: 2526 case Hexagon::SUB_rr_cNotPt: 2527 case Hexagon::COMBINE_rr_cPt: 2528 case Hexagon::COMBINE_rr_cNotPt: 2529 return true; 2530 case Hexagon::ASLH_cPt_V4: 2531 case Hexagon::ASLH_cNotPt_V4: 2532 case Hexagon::ASRH_cPt_V4: 2533 case Hexagon::ASRH_cNotPt_V4: 2534 case Hexagon::SXTB_cPt_V4: 2535 case Hexagon::SXTB_cNotPt_V4: 2536 case Hexagon::SXTH_cPt_V4: 2537 case Hexagon::SXTH_cNotPt_V4: 2538 case Hexagon::ZXTB_cPt_V4: 2539 case Hexagon::ZXTB_cNotPt_V4: 2540 case Hexagon::ZXTH_cPt_V4: 2541 case Hexagon::ZXTH_cNotPt_V4: 2542 return QRI.Subtarget.hasV4TOps(); 2543 } 2544} 2545 2546bool HexagonInstrInfo:: 2547isConditionalLoad (const MachineInstr* MI) const { 2548 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2549 switch (MI->getOpcode()) 2550 { 2551 default: return false; 2552 case Hexagon::LDrid_cPt : 2553 case Hexagon::LDrid_cNotPt : 2554 case Hexagon::LDrid_indexed_cPt : 2555 case Hexagon::LDrid_indexed_cNotPt : 2556 case Hexagon::LDriw_cPt : 2557 case Hexagon::LDriw_cNotPt : 2558 case Hexagon::LDriw_indexed_cPt : 2559 case Hexagon::LDriw_indexed_cNotPt : 2560 case Hexagon::LDrih_cPt : 2561 case Hexagon::LDrih_cNotPt : 2562 case Hexagon::LDrih_indexed_cPt : 2563 case Hexagon::LDrih_indexed_cNotPt : 2564 case Hexagon::LDrib_cPt : 2565 case Hexagon::LDrib_cNotPt : 2566 case Hexagon::LDrib_indexed_cPt : 2567 case Hexagon::LDrib_indexed_cNotPt : 2568 case Hexagon::LDriuh_cPt : 2569 case Hexagon::LDriuh_cNotPt : 2570 case Hexagon::LDriuh_indexed_cPt : 2571 case Hexagon::LDriuh_indexed_cNotPt : 2572 case Hexagon::LDriub_cPt : 2573 case Hexagon::LDriub_cNotPt : 2574 case Hexagon::LDriub_indexed_cPt : 2575 case Hexagon::LDriub_indexed_cNotPt : 2576 return true; 2577 case Hexagon::POST_LDrid_cPt : 2578 case Hexagon::POST_LDrid_cNotPt : 2579 case Hexagon::POST_LDriw_cPt : 2580 case Hexagon::POST_LDriw_cNotPt : 2581 case Hexagon::POST_LDrih_cPt : 2582 case Hexagon::POST_LDrih_cNotPt : 2583 case Hexagon::POST_LDrib_cPt : 2584 case Hexagon::POST_LDrib_cNotPt : 2585 case Hexagon::POST_LDriuh_cPt : 2586 case Hexagon::POST_LDriuh_cNotPt : 2587 case Hexagon::POST_LDriub_cPt : 2588 case Hexagon::POST_LDriub_cNotPt : 2589 return QRI.Subtarget.hasV4TOps(); 2590 case Hexagon::LDrid_indexed_shl_cPt_V4 : 2591 case Hexagon::LDrid_indexed_shl_cNotPt_V4 : 2592 case Hexagon::LDrib_indexed_shl_cPt_V4 : 2593 case Hexagon::LDrib_indexed_shl_cNotPt_V4 : 2594 case Hexagon::LDriub_indexed_shl_cPt_V4 : 2595 case Hexagon::LDriub_indexed_shl_cNotPt_V4 : 2596 case Hexagon::LDrih_indexed_shl_cPt_V4 : 2597 case Hexagon::LDrih_indexed_shl_cNotPt_V4 : 2598 case Hexagon::LDriuh_indexed_shl_cPt_V4 : 2599 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : 2600 case Hexagon::LDriw_indexed_shl_cPt_V4 : 2601 case Hexagon::LDriw_indexed_shl_cNotPt_V4 : 2602 return QRI.Subtarget.hasV4TOps(); 2603 } 2604} 2605 2606// Returns true if an instruction is a conditional store. 2607// 2608// Note: It doesn't include conditional new-value stores as they can't be 2609// converted to .new predicate. 2610// 2611// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] 2612// ^ ^ 2613// / \ (not OK. it will cause new-value store to be 2614// / X conditional on p0.new while R2 producer is 2615// / \ on p0) 2616// / \. 2617// p.new store p.old NV store 2618// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] 2619// ^ ^ 2620// \ / 2621// \ / 2622// \ / 2623// p.old store 2624// [if (p0)memw(R0+#0)=R2] 2625// 2626// The above diagram shows the steps involoved in the conversion of a predicated 2627// store instruction to its .new predicated new-value form. 2628// 2629// The following set of instructions further explains the scenario where 2630// conditional new-value store becomes invalid when promoted to .new predicate 2631// form. 2632// 2633// { 1) if (p0) r0 = add(r1, r2) 2634// 2) p0 = cmp.eq(r3, #0) } 2635// 2636// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with 2637// the first two instructions because in instr 1, r0 is conditional on old value 2638// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which 2639// is not valid for new-value stores. 2640bool HexagonInstrInfo:: 2641isConditionalStore (const MachineInstr* MI) const { 2642 const HexagonRegisterInfo& QRI = getRegisterInfo(); 2643 switch (MI->getOpcode()) 2644 { 2645 default: return false; 2646 case Hexagon::STrib_imm_cPt_V4 : 2647 case Hexagon::STrib_imm_cNotPt_V4 : 2648 case Hexagon::STrib_indexed_shl_cPt_V4 : 2649 case Hexagon::STrib_indexed_shl_cNotPt_V4 : 2650 case Hexagon::STrib_cPt : 2651 case Hexagon::STrib_cNotPt : 2652 case Hexagon::POST_STbri_cPt : 2653 case Hexagon::POST_STbri_cNotPt : 2654 case Hexagon::STrid_indexed_cPt : 2655 case Hexagon::STrid_indexed_cNotPt : 2656 case Hexagon::STrid_indexed_shl_cPt_V4 : 2657 case Hexagon::POST_STdri_cPt : 2658 case Hexagon::POST_STdri_cNotPt : 2659 case Hexagon::STrih_cPt : 2660 case Hexagon::STrih_cNotPt : 2661 case Hexagon::STrih_indexed_cPt : 2662 case Hexagon::STrih_indexed_cNotPt : 2663 case Hexagon::STrih_imm_cPt_V4 : 2664 case Hexagon::STrih_imm_cNotPt_V4 : 2665 case Hexagon::STrih_indexed_shl_cPt_V4 : 2666 case Hexagon::STrih_indexed_shl_cNotPt_V4 : 2667 case Hexagon::POST_SThri_cPt : 2668 case Hexagon::POST_SThri_cNotPt : 2669 case Hexagon::STriw_cPt : 2670 case Hexagon::STriw_cNotPt : 2671 case Hexagon::STriw_indexed_cPt : 2672 case Hexagon::STriw_indexed_cNotPt : 2673 case Hexagon::STriw_imm_cPt_V4 : 2674 case Hexagon::STriw_imm_cNotPt_V4 : 2675 case Hexagon::STriw_indexed_shl_cPt_V4 : 2676 case Hexagon::STriw_indexed_shl_cNotPt_V4 : 2677 case Hexagon::POST_STwri_cPt : 2678 case Hexagon::POST_STwri_cNotPt : 2679 return QRI.Subtarget.hasV4TOps(); 2680 2681 // V4 global address store before promoting to dot new. 2682 case Hexagon::STrid_GP_cPt_V4 : 2683 case Hexagon::STrid_GP_cNotPt_V4 : 2684 case Hexagon::STrib_GP_cPt_V4 : 2685 case Hexagon::STrib_GP_cNotPt_V4 : 2686 case Hexagon::STrih_GP_cPt_V4 : 2687 case Hexagon::STrih_GP_cNotPt_V4 : 2688 case Hexagon::STriw_GP_cPt_V4 : 2689 case Hexagon::STriw_GP_cNotPt_V4 : 2690 case Hexagon::STd_GP_cPt_V4 : 2691 case Hexagon::STd_GP_cNotPt_V4 : 2692 case Hexagon::STb_GP_cPt_V4 : 2693 case Hexagon::STb_GP_cNotPt_V4 : 2694 case Hexagon::STh_GP_cPt_V4 : 2695 case Hexagon::STh_GP_cNotPt_V4 : 2696 case Hexagon::STw_GP_cPt_V4 : 2697 case Hexagon::STw_GP_cNotPt_V4 : 2698 return QRI.Subtarget.hasV4TOps(); 2699 2700 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded 2701 // from the "Conditional Store" list. Because a predicated new value store 2702 // would NOT be promoted to a double dot new store. See diagram below: 2703 // This function returns yes for those stores that are predicated but not 2704 // yet promoted to predicate dot new instructions. 2705 // 2706 // +---------------------+ 2707 // /-----| if (p0) memw(..)=r0 |---------\~ 2708 // || +---------------------+ || 2709 // promote || /\ /\ || promote 2710 // || /||\ /||\ || 2711 // \||/ demote || \||/ 2712 // \/ || || \/ 2713 // +-------------------------+ || +-------------------------+ 2714 // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | 2715 // +-------------------------+ || +-------------------------+ 2716 // || || || 2717 // || demote \||/ 2718 // promote || \/ NOT possible 2719 // || || /\~ 2720 // \||/ || /||\~ 2721 // \/ || || 2722 // +-----------------------------+ 2723 // | if (p0.new) memw(..)=r0.new | 2724 // +-----------------------------+ 2725 // Double Dot New Store 2726 // 2727 } 2728} 2729 2730 2731 2732DFAPacketizer *HexagonInstrInfo:: 2733CreateTargetScheduleState(const TargetMachine *TM, 2734 const ScheduleDAG *DAG) const { 2735 const InstrItineraryData *II = TM->getInstrItineraryData(); 2736 return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); 2737} 2738 2739bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, 2740 const MachineBasicBlock *MBB, 2741 const MachineFunction &MF) const { 2742 // Debug info is never a scheduling boundary. It's necessary to be explicit 2743 // due to the special treatment of IT instructions below, otherwise a 2744 // dbg_value followed by an IT will result in the IT instruction being 2745 // considered a scheduling hazard, which is wrong. It should be the actual 2746 // instruction preceding the dbg_value instruction(s), just like it is 2747 // when debug info is not present. 2748 if (MI->isDebugValue()) 2749 return false; 2750 2751 // Terminators and labels can't be scheduled around. 2752 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) 2753 return true; 2754 2755 return false; 2756} 2757