HexagonInstrInfo.cpp revision d1a87a68064e0b9af3b71b681286954f861bb1b3 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "HexagonRegisterInfo.h"
16#include "HexagonSubtarget.h"
17#include "Hexagon.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#include "HexagonGenInstrInfo.inc"
29#include "HexagonGenDFAPacketizer.inc"
30
31using namespace llvm;
32
33///
34/// Constants for Hexagon instructions.
35///
36const int Hexagon_MEMW_OFFSET_MAX = 4095;
37const int Hexagon_MEMW_OFFSET_MIN = 4096;
38const int Hexagon_MEMD_OFFSET_MAX = 8191;
39const int Hexagon_MEMD_OFFSET_MIN = 8192;
40const int Hexagon_MEMH_OFFSET_MAX = 2047;
41const int Hexagon_MEMH_OFFSET_MIN = 2048;
42const int Hexagon_MEMB_OFFSET_MAX = 1023;
43const int Hexagon_MEMB_OFFSET_MIN = 1024;
44const int Hexagon_ADDI_OFFSET_MAX = 32767;
45const int Hexagon_ADDI_OFFSET_MIN = 32768;
46const int Hexagon_MEMD_AUTOINC_MAX = 56;
47const int Hexagon_MEMD_AUTOINC_MIN = 64;
48const int Hexagon_MEMW_AUTOINC_MAX = 28;
49const int Hexagon_MEMW_AUTOINC_MIN = 32;
50const int Hexagon_MEMH_AUTOINC_MAX = 14;
51const int Hexagon_MEMH_AUTOINC_MIN = 16;
52const int Hexagon_MEMB_AUTOINC_MAX = 7;
53const int Hexagon_MEMB_AUTOINC_MIN = 8;
54
55
56
57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59    RI(ST, *this), Subtarget(ST) {
60}
61
62
63/// isLoadFromStackSlot - If the specified machine instruction is a direct
64/// load from a stack slot, return the virtual or physical register number of
65/// the destination along with the FrameIndex of the loaded stack slot.  If
66/// not, return 0.  This predicate must return 0 if the instruction has
67/// any side effects other than loading from the stack slot.
68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69                                             int &FrameIndex) const {
70
71
72  switch (MI->getOpcode()) {
73  case Hexagon::LDriw:
74  case Hexagon::LDrid:
75  case Hexagon::LDrih:
76  case Hexagon::LDrib:
77  case Hexagon::LDriub:
78    if (MI->getOperand(2).isFI() &&
79        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
80      FrameIndex = MI->getOperand(2).getIndex();
81      return MI->getOperand(0).getReg();
82    }
83    break;
84
85  default:
86    break;
87  }
88
89  return 0;
90}
91
92
93/// isStoreToStackSlot - If the specified machine instruction is a direct
94/// store to a stack slot, return the virtual or physical register number of
95/// the source reg along with the FrameIndex of the loaded stack slot.  If
96/// not, return 0.  This predicate must return 0 if the instruction has
97/// any side effects other than storing to the stack slot.
98unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99                                            int &FrameIndex) const {
100  switch (MI->getOpcode()) {
101  case Hexagon::STriw:
102  case Hexagon::STrid:
103  case Hexagon::STrih:
104  case Hexagon::STrib:
105    if (MI->getOperand(2).isFI() &&
106        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
107      FrameIndex = MI->getOperand(2).getIndex();
108      return MI->getOperand(0).getReg();
109    }
110    break;
111
112  default:
113    break;
114  }
115
116  return 0;
117}
118
119
120unsigned
121HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
122                             MachineBasicBlock *FBB,
123                             const SmallVectorImpl<MachineOperand> &Cond,
124                             DebugLoc DL) const{
125
126    int BOpc   = Hexagon::JMP;
127    int BccOpc = Hexagon::JMP_c;
128
129    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
130
131    int regPos = 0;
132    // Check if ReverseBranchCondition has asked to reverse this branch
133    // If we want to reverse the branch an odd number of times, we want
134    // JMP_cNot.
135    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
136      BccOpc = Hexagon::JMP_cNot;
137      regPos = 1;
138    }
139
140    if (FBB == 0) {
141      if (Cond.empty()) {
142        // Due to a bug in TailMerging/CFG Optimization, we need to add a
143        // special case handling of a predicated jump followed by an
144        // unconditional jump. If not, Tail Merging and CFG Optimization go
145        // into an infinite loop.
146        MachineBasicBlock *NewTBB, *NewFBB;
147        SmallVector<MachineOperand, 4> Cond;
148        MachineInstr *Term = MBB.getFirstTerminator();
149        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
150                                                 false)) {
151          MachineBasicBlock *NextBB =
152            llvm::next(MachineFunction::iterator(&MBB));
153          if (NewTBB == NextBB) {
154            ReverseBranchCondition(Cond);
155            RemoveBranch(MBB);
156            return InsertBranch(MBB, TBB, 0, Cond, DL);
157          }
158        }
159        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
160      } else {
161        BuildMI(&MBB, DL,
162                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
163      }
164      return 1;
165    }
166
167    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
168    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
169
170    return 2;
171}
172
173
174bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
175                                     MachineBasicBlock *&TBB,
176                                 MachineBasicBlock *&FBB,
177                                 SmallVectorImpl<MachineOperand> &Cond,
178                                 bool AllowModify) const {
179  FBB = NULL;
180
181  // If the block has no terminators, it just falls into the block after it.
182  MachineBasicBlock::iterator I = MBB.end();
183  if (I == MBB.begin())
184    return false;
185
186  // A basic block may looks like this:
187  //
188  //  [   insn
189  //     EH_LABEL
190  //      insn
191  //      insn
192  //      insn
193  //     EH_LABEL
194  //      insn     ]
195  //
196  // It has two succs but does not have a terminator
197  // Don't know how to handle it.
198  do {
199    --I;
200    if (I->isEHLabel())
201      return true;
202  } while (I != MBB.begin());
203
204  I = MBB.end();
205  --I;
206
207  while (I->isDebugValue()) {
208    if (I == MBB.begin())
209      return false;
210    --I;
211  }
212  if (!isUnpredicatedTerminator(I))
213    return false;
214
215  // Get the last instruction in the block.
216  MachineInstr *LastInst = I;
217
218  // If there is only one terminator instruction, process it.
219  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
220    if (LastInst->getOpcode() == Hexagon::JMP) {
221      TBB = LastInst->getOperand(0).getMBB();
222      return false;
223    }
224    if (LastInst->getOpcode() == Hexagon::JMP_c) {
225      // Block ends with fall-through true condbranch.
226      TBB = LastInst->getOperand(1).getMBB();
227      Cond.push_back(LastInst->getOperand(0));
228      return false;
229    }
230    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
231      // Block ends with fall-through false condbranch.
232      TBB = LastInst->getOperand(1).getMBB();
233      Cond.push_back(MachineOperand::CreateImm(0));
234      Cond.push_back(LastInst->getOperand(0));
235      return false;
236    }
237    // Otherwise, don't know what this is.
238    return true;
239  }
240
241  // Get the instruction before it if it's a terminator.
242  MachineInstr *SecondLastInst = I;
243
244  // If there are three terminators, we don't know what sort of block this is.
245  if (SecondLastInst && I != MBB.begin() &&
246      isUnpredicatedTerminator(--I))
247    return true;
248
249  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
250  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
251      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
252      LastInst->getOpcode() == Hexagon::JMP) {
253    TBB =  SecondLastInst->getOperand(1).getMBB();
254    Cond.push_back(SecondLastInst->getOperand(0));
255    FBB = LastInst->getOperand(0).getMBB();
256    return false;
257  }
258
259  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
260  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
261      LastInst->getOpcode() == Hexagon::JMP) {
262    TBB =  SecondLastInst->getOperand(1).getMBB();
263    Cond.push_back(MachineOperand::CreateImm(0));
264    Cond.push_back(SecondLastInst->getOperand(0));
265    FBB = LastInst->getOperand(0).getMBB();
266    return false;
267  }
268
269  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
270  // executed, so remove it.
271  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
272      LastInst->getOpcode() == Hexagon::JMP) {
273    TBB = SecondLastInst->getOperand(0).getMBB();
274    I = LastInst;
275    if (AllowModify)
276      I->eraseFromParent();
277    return false;
278  }
279
280  // Otherwise, can't handle this.
281  return true;
282}
283
284
285unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
286  int BOpc   = Hexagon::JMP;
287  int BccOpc = Hexagon::JMP_c;
288  int BccOpcNot = Hexagon::JMP_cNot;
289
290  MachineBasicBlock::iterator I = MBB.end();
291  if (I == MBB.begin()) return 0;
292  --I;
293  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
294      I->getOpcode() != BccOpcNot)
295    return 0;
296
297  // Remove the branch.
298  I->eraseFromParent();
299
300  I = MBB.end();
301
302  if (I == MBB.begin()) return 1;
303  --I;
304  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
305    return 1;
306
307  // Remove the branch.
308  I->eraseFromParent();
309  return 2;
310}
311
312
313void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
314                                 MachineBasicBlock::iterator I, DebugLoc DL,
315                                 unsigned DestReg, unsigned SrcReg,
316                                 bool KillSrc) const {
317  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
318    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
319    return;
320  }
321  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
322    BuildMI(MBB, I, DL, get(Hexagon::TFR_64), DestReg).addReg(SrcReg);
323    return;
324  }
325  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
326    // Map Pd = Ps to Pd = or(Ps, Ps).
327    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
328            DestReg).addReg(SrcReg).addReg(SrcReg);
329    return;
330  }
331  if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) {
332    // We can have an overlap between single and double reg: r1:0 = r0.
333    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
334        // r1:0 = r0
335        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
336                Hexagon::subreg_hireg))).addImm(0);
337    } else {
338        // r1:0 = r1 or no overlap.
339        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
340                Hexagon::subreg_loreg))).addReg(SrcReg);
341        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
342                Hexagon::subreg_hireg))).addImm(0);
343    }
344    return;
345  }
346  if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) {
347    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
348    return;
349  }
350
351  llvm_unreachable("Unimplemented");
352}
353
354
355void HexagonInstrInfo::
356storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
357                    unsigned SrcReg, bool isKill, int FI,
358                    const TargetRegisterClass *RC,
359                    const TargetRegisterInfo *TRI) const {
360
361  DebugLoc DL = MBB.findDebugLoc(I);
362  MachineFunction &MF = *MBB.getParent();
363  MachineFrameInfo &MFI = *MF.getFrameInfo();
364  unsigned Align = MFI.getObjectAlignment(FI);
365
366  MachineMemOperand *MMO =
367      MF.getMachineMemOperand(
368                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
369                      MachineMemOperand::MOStore,
370                      MFI.getObjectSize(FI),
371                      Align);
372
373  if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) {
374    BuildMI(MBB, I, DL, get(Hexagon::STriw))
375          .addFrameIndex(FI).addImm(0)
376          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
377  } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) {
378    BuildMI(MBB, I, DL, get(Hexagon::STrid))
379          .addFrameIndex(FI).addImm(0)
380          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
381  } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) {
382    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
383          .addFrameIndex(FI).addImm(0)
384          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
385  } else {
386    llvm_unreachable("Unimplemented");
387  }
388}
389
390
391void HexagonInstrInfo::storeRegToAddr(
392                                 MachineFunction &MF, unsigned SrcReg,
393                                 bool isKill,
394                                 SmallVectorImpl<MachineOperand> &Addr,
395                                 const TargetRegisterClass *RC,
396                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
397{
398  llvm_unreachable("Unimplemented");
399}
400
401
402void HexagonInstrInfo::
403loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
404                     unsigned DestReg, int FI,
405                     const TargetRegisterClass *RC,
406                     const TargetRegisterInfo *TRI) const {
407  DebugLoc DL = MBB.findDebugLoc(I);
408  MachineFunction &MF = *MBB.getParent();
409  MachineFrameInfo &MFI = *MF.getFrameInfo();
410  unsigned Align = MFI.getObjectAlignment(FI);
411
412  MachineMemOperand *MMO =
413      MF.getMachineMemOperand(
414                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
415                      MachineMemOperand::MOLoad,
416                      MFI.getObjectSize(FI),
417                      Align);
418
419  if (RC == Hexagon::IntRegsRegisterClass) {
420    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
421          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
422  } else if (RC == Hexagon::DoubleRegsRegisterClass) {
423    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
424          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
425  } else if (RC == Hexagon::PredRegsRegisterClass) {
426    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
427          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
428  } else {
429    llvm_unreachable("Can't store this register to stack slot");
430  }
431}
432
433
434void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
435                                        SmallVectorImpl<MachineOperand> &Addr,
436                                        const TargetRegisterClass *RC,
437                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
438  llvm_unreachable("Unimplemented");
439}
440
441
442MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
443                                                    MachineInstr* MI,
444                                          const SmallVectorImpl<unsigned> &Ops,
445                                                    int FI) const {
446  // Hexagon_TODO: Implement.
447  return(0);
448}
449
450
451unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
452
453  MachineRegisterInfo &RegInfo = MF->getRegInfo();
454  const TargetRegisterClass *TRC;
455  if (VT == MVT::i1) {
456    TRC =  Hexagon::PredRegsRegisterClass;
457  } else if (VT == MVT::i32) {
458    TRC =  Hexagon::IntRegsRegisterClass;
459  } else if (VT == MVT::i64) {
460    TRC =  Hexagon::DoubleRegsRegisterClass;
461  } else {
462    llvm_unreachable("Cannot handle this register class");
463  }
464
465  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
466  return NewReg;
467}
468
469bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
470  switch(MI->getOpcode()) {
471    // JMP_EQri
472    case Hexagon::JMP_EQriPt_nv_V4:
473    case Hexagon::JMP_EQriPnt_nv_V4:
474    case Hexagon::JMP_EQriNotPt_nv_V4:
475    case Hexagon::JMP_EQriNotPnt_nv_V4:
476
477    // JMP_EQri - with -1
478    case Hexagon::JMP_EQriPtneg_nv_V4:
479    case Hexagon::JMP_EQriPntneg_nv_V4:
480    case Hexagon::JMP_EQriNotPtneg_nv_V4:
481    case Hexagon::JMP_EQriNotPntneg_nv_V4:
482
483    // JMP_EQrr
484    case Hexagon::JMP_EQrrPt_nv_V4:
485    case Hexagon::JMP_EQrrPnt_nv_V4:
486    case Hexagon::JMP_EQrrNotPt_nv_V4:
487    case Hexagon::JMP_EQrrNotPnt_nv_V4:
488
489    // JMP_GTri
490    case Hexagon::JMP_GTriPt_nv_V4:
491    case Hexagon::JMP_GTriPnt_nv_V4:
492    case Hexagon::JMP_GTriNotPt_nv_V4:
493    case Hexagon::JMP_GTriNotPnt_nv_V4:
494
495    // JMP_GTri - with -1
496    case Hexagon::JMP_GTriPtneg_nv_V4:
497    case Hexagon::JMP_GTriPntneg_nv_V4:
498    case Hexagon::JMP_GTriNotPtneg_nv_V4:
499    case Hexagon::JMP_GTriNotPntneg_nv_V4:
500
501    // JMP_GTrr
502    case Hexagon::JMP_GTrrPt_nv_V4:
503    case Hexagon::JMP_GTrrPnt_nv_V4:
504    case Hexagon::JMP_GTrrNotPt_nv_V4:
505    case Hexagon::JMP_GTrrNotPnt_nv_V4:
506
507    // JMP_GTrrdn
508    case Hexagon::JMP_GTrrdnPt_nv_V4:
509    case Hexagon::JMP_GTrrdnPnt_nv_V4:
510    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
511    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
512
513    // JMP_GTUri
514    case Hexagon::JMP_GTUriPt_nv_V4:
515    case Hexagon::JMP_GTUriPnt_nv_V4:
516    case Hexagon::JMP_GTUriNotPt_nv_V4:
517    case Hexagon::JMP_GTUriNotPnt_nv_V4:
518
519    // JMP_GTUrr
520    case Hexagon::JMP_GTUrrPt_nv_V4:
521    case Hexagon::JMP_GTUrrPnt_nv_V4:
522    case Hexagon::JMP_GTUrrNotPt_nv_V4:
523    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
524
525    // JMP_GTUrrdn
526    case Hexagon::JMP_GTUrrdnPt_nv_V4:
527    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
528    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
529    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
530      return true;
531
532    // TFR_FI
533    case Hexagon::TFR_FI:
534      return true;
535
536
537    default:
538      return false;
539  }
540  return  false;
541}
542
543bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
544  switch(MI->getOpcode()) {
545    // JMP_EQri
546    case Hexagon::JMP_EQriPt_ie_nv_V4:
547    case Hexagon::JMP_EQriPnt_ie_nv_V4:
548    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
549    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
550
551    // JMP_EQri - with -1
552    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
553    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
554    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
555    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
556
557    // JMP_EQrr
558    case Hexagon::JMP_EQrrPt_ie_nv_V4:
559    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
560    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
561    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
562
563    // JMP_GTri
564    case Hexagon::JMP_GTriPt_ie_nv_V4:
565    case Hexagon::JMP_GTriPnt_ie_nv_V4:
566    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
567    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
568
569    // JMP_GTri - with -1
570    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
571    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
572    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
573    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
574
575    // JMP_GTrr
576    case Hexagon::JMP_GTrrPt_ie_nv_V4:
577    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
578    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
579    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
580
581    // JMP_GTrrdn
582    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
583    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
584    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
585    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
586
587    // JMP_GTUri
588    case Hexagon::JMP_GTUriPt_ie_nv_V4:
589    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
590    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
591    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
592
593    // JMP_GTUrr
594    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
595    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
596    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
597    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
598
599    // JMP_GTUrrdn
600    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
601    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
602    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
603    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
604
605    // V4 absolute set addressing.
606    case Hexagon::LDrid_abs_setimm_V4:
607    case Hexagon::LDriw_abs_setimm_V4:
608    case Hexagon::LDrih_abs_setimm_V4:
609    case Hexagon::LDrib_abs_setimm_V4:
610    case Hexagon::LDriuh_abs_setimm_V4:
611    case Hexagon::LDriub_abs_setimm_V4:
612
613    case Hexagon::STrid_abs_setimm_V4:
614    case Hexagon::STrib_abs_setimm_V4:
615    case Hexagon::STrih_abs_setimm_V4:
616    case Hexagon::STriw_abs_setimm_V4:
617
618    // V4 global address load.
619    case Hexagon::LDrid_GP_cPt_V4 :
620    case Hexagon::LDrid_GP_cNotPt_V4 :
621    case Hexagon::LDrid_GP_cdnPt_V4 :
622    case Hexagon::LDrid_GP_cdnNotPt_V4 :
623    case Hexagon::LDrib_GP_cPt_V4 :
624    case Hexagon::LDrib_GP_cNotPt_V4 :
625    case Hexagon::LDrib_GP_cdnPt_V4 :
626    case Hexagon::LDrib_GP_cdnNotPt_V4 :
627    case Hexagon::LDriub_GP_cPt_V4 :
628    case Hexagon::LDriub_GP_cNotPt_V4 :
629    case Hexagon::LDriub_GP_cdnPt_V4 :
630    case Hexagon::LDriub_GP_cdnNotPt_V4 :
631    case Hexagon::LDrih_GP_cPt_V4 :
632    case Hexagon::LDrih_GP_cNotPt_V4 :
633    case Hexagon::LDrih_GP_cdnPt_V4 :
634    case Hexagon::LDrih_GP_cdnNotPt_V4 :
635    case Hexagon::LDriuh_GP_cPt_V4 :
636    case Hexagon::LDriuh_GP_cNotPt_V4 :
637    case Hexagon::LDriuh_GP_cdnPt_V4 :
638    case Hexagon::LDriuh_GP_cdnNotPt_V4 :
639    case Hexagon::LDriw_GP_cPt_V4 :
640    case Hexagon::LDriw_GP_cNotPt_V4 :
641    case Hexagon::LDriw_GP_cdnPt_V4 :
642    case Hexagon::LDriw_GP_cdnNotPt_V4 :
643    case Hexagon::LDd_GP_cPt_V4 :
644    case Hexagon::LDd_GP_cNotPt_V4 :
645    case Hexagon::LDd_GP_cdnPt_V4 :
646    case Hexagon::LDd_GP_cdnNotPt_V4 :
647    case Hexagon::LDb_GP_cPt_V4 :
648    case Hexagon::LDb_GP_cNotPt_V4 :
649    case Hexagon::LDb_GP_cdnPt_V4 :
650    case Hexagon::LDb_GP_cdnNotPt_V4 :
651    case Hexagon::LDub_GP_cPt_V4 :
652    case Hexagon::LDub_GP_cNotPt_V4 :
653    case Hexagon::LDub_GP_cdnPt_V4 :
654    case Hexagon::LDub_GP_cdnNotPt_V4 :
655    case Hexagon::LDh_GP_cPt_V4 :
656    case Hexagon::LDh_GP_cNotPt_V4 :
657    case Hexagon::LDh_GP_cdnPt_V4 :
658    case Hexagon::LDh_GP_cdnNotPt_V4 :
659    case Hexagon::LDuh_GP_cPt_V4 :
660    case Hexagon::LDuh_GP_cNotPt_V4 :
661    case Hexagon::LDuh_GP_cdnPt_V4 :
662    case Hexagon::LDuh_GP_cdnNotPt_V4 :
663    case Hexagon::LDw_GP_cPt_V4 :
664    case Hexagon::LDw_GP_cNotPt_V4 :
665    case Hexagon::LDw_GP_cdnPt_V4 :
666    case Hexagon::LDw_GP_cdnNotPt_V4 :
667
668    // V4 global address store.
669    case Hexagon::STrid_GP_cPt_V4 :
670    case Hexagon::STrid_GP_cNotPt_V4 :
671    case Hexagon::STrid_GP_cdnPt_V4 :
672    case Hexagon::STrid_GP_cdnNotPt_V4 :
673    case Hexagon::STrib_GP_cPt_V4 :
674    case Hexagon::STrib_GP_cNotPt_V4 :
675    case Hexagon::STrib_GP_cdnPt_V4 :
676    case Hexagon::STrib_GP_cdnNotPt_V4 :
677    case Hexagon::STrih_GP_cPt_V4 :
678    case Hexagon::STrih_GP_cNotPt_V4 :
679    case Hexagon::STrih_GP_cdnPt_V4 :
680    case Hexagon::STrih_GP_cdnNotPt_V4 :
681    case Hexagon::STriw_GP_cPt_V4 :
682    case Hexagon::STriw_GP_cNotPt_V4 :
683    case Hexagon::STriw_GP_cdnPt_V4 :
684    case Hexagon::STriw_GP_cdnNotPt_V4 :
685    case Hexagon::STd_GP_cPt_V4 :
686    case Hexagon::STd_GP_cNotPt_V4 :
687    case Hexagon::STd_GP_cdnPt_V4 :
688    case Hexagon::STd_GP_cdnNotPt_V4 :
689    case Hexagon::STb_GP_cPt_V4 :
690    case Hexagon::STb_GP_cNotPt_V4 :
691    case Hexagon::STb_GP_cdnPt_V4 :
692    case Hexagon::STb_GP_cdnNotPt_V4 :
693    case Hexagon::STh_GP_cPt_V4 :
694    case Hexagon::STh_GP_cNotPt_V4 :
695    case Hexagon::STh_GP_cdnPt_V4 :
696    case Hexagon::STh_GP_cdnNotPt_V4 :
697    case Hexagon::STw_GP_cPt_V4 :
698    case Hexagon::STw_GP_cNotPt_V4 :
699    case Hexagon::STw_GP_cdnPt_V4 :
700    case Hexagon::STw_GP_cdnNotPt_V4 :
701
702    // V4 predicated global address new value store.
703    case Hexagon::STrib_GP_cPt_nv_V4 :
704    case Hexagon::STrib_GP_cNotPt_nv_V4 :
705    case Hexagon::STrib_GP_cdnPt_nv_V4 :
706    case Hexagon::STrib_GP_cdnNotPt_nv_V4 :
707    case Hexagon::STrih_GP_cPt_nv_V4 :
708    case Hexagon::STrih_GP_cNotPt_nv_V4 :
709    case Hexagon::STrih_GP_cdnPt_nv_V4 :
710    case Hexagon::STrih_GP_cdnNotPt_nv_V4 :
711    case Hexagon::STriw_GP_cPt_nv_V4 :
712    case Hexagon::STriw_GP_cNotPt_nv_V4 :
713    case Hexagon::STriw_GP_cdnPt_nv_V4 :
714    case Hexagon::STriw_GP_cdnNotPt_nv_V4 :
715    case Hexagon::STb_GP_cPt_nv_V4 :
716    case Hexagon::STb_GP_cNotPt_nv_V4 :
717    case Hexagon::STb_GP_cdnPt_nv_V4 :
718    case Hexagon::STb_GP_cdnNotPt_nv_V4 :
719    case Hexagon::STh_GP_cPt_nv_V4 :
720    case Hexagon::STh_GP_cNotPt_nv_V4 :
721    case Hexagon::STh_GP_cdnPt_nv_V4 :
722    case Hexagon::STh_GP_cdnNotPt_nv_V4 :
723    case Hexagon::STw_GP_cPt_nv_V4 :
724    case Hexagon::STw_GP_cNotPt_nv_V4 :
725    case Hexagon::STw_GP_cdnPt_nv_V4 :
726    case Hexagon::STw_GP_cdnNotPt_nv_V4 :
727
728    // TFR_FI
729    case Hexagon::TFR_FI_immext_V4:
730      return true;
731
732    default:
733      return false;
734  }
735  return  false;
736}
737
738bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
739  switch (MI->getOpcode()) {
740    // JMP_EQri
741    case Hexagon::JMP_EQriPt_nv_V4:
742    case Hexagon::JMP_EQriPnt_nv_V4:
743    case Hexagon::JMP_EQriNotPt_nv_V4:
744    case Hexagon::JMP_EQriNotPnt_nv_V4:
745    case Hexagon::JMP_EQriPt_ie_nv_V4:
746    case Hexagon::JMP_EQriPnt_ie_nv_V4:
747    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
748    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
749
750    // JMP_EQri - with -1
751    case Hexagon::JMP_EQriPtneg_nv_V4:
752    case Hexagon::JMP_EQriPntneg_nv_V4:
753    case Hexagon::JMP_EQriNotPtneg_nv_V4:
754    case Hexagon::JMP_EQriNotPntneg_nv_V4:
755    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
756    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
757    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
758    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
759
760    // JMP_EQrr
761    case Hexagon::JMP_EQrrPt_nv_V4:
762    case Hexagon::JMP_EQrrPnt_nv_V4:
763    case Hexagon::JMP_EQrrNotPt_nv_V4:
764    case Hexagon::JMP_EQrrNotPnt_nv_V4:
765    case Hexagon::JMP_EQrrPt_ie_nv_V4:
766    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
767    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
768    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
769
770    // JMP_GTri
771    case Hexagon::JMP_GTriPt_nv_V4:
772    case Hexagon::JMP_GTriPnt_nv_V4:
773    case Hexagon::JMP_GTriNotPt_nv_V4:
774    case Hexagon::JMP_GTriNotPnt_nv_V4:
775    case Hexagon::JMP_GTriPt_ie_nv_V4:
776    case Hexagon::JMP_GTriPnt_ie_nv_V4:
777    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
778    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
779
780    // JMP_GTri - with -1
781    case Hexagon::JMP_GTriPtneg_nv_V4:
782    case Hexagon::JMP_GTriPntneg_nv_V4:
783    case Hexagon::JMP_GTriNotPtneg_nv_V4:
784    case Hexagon::JMP_GTriNotPntneg_nv_V4:
785    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
786    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
787    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
788    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
789
790    // JMP_GTrr
791    case Hexagon::JMP_GTrrPt_nv_V4:
792    case Hexagon::JMP_GTrrPnt_nv_V4:
793    case Hexagon::JMP_GTrrNotPt_nv_V4:
794    case Hexagon::JMP_GTrrNotPnt_nv_V4:
795    case Hexagon::JMP_GTrrPt_ie_nv_V4:
796    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
797    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
798    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
799
800    // JMP_GTrrdn
801    case Hexagon::JMP_GTrrdnPt_nv_V4:
802    case Hexagon::JMP_GTrrdnPnt_nv_V4:
803    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
804    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
805    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
806    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
807    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
808    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
809
810    // JMP_GTUri
811    case Hexagon::JMP_GTUriPt_nv_V4:
812    case Hexagon::JMP_GTUriPnt_nv_V4:
813    case Hexagon::JMP_GTUriNotPt_nv_V4:
814    case Hexagon::JMP_GTUriNotPnt_nv_V4:
815    case Hexagon::JMP_GTUriPt_ie_nv_V4:
816    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
817    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
818    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
819
820    // JMP_GTUrr
821    case Hexagon::JMP_GTUrrPt_nv_V4:
822    case Hexagon::JMP_GTUrrPnt_nv_V4:
823    case Hexagon::JMP_GTUrrNotPt_nv_V4:
824    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
825    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
826    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
827    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
828    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
829
830    // JMP_GTUrrdn
831    case Hexagon::JMP_GTUrrdnPt_nv_V4:
832    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
833    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
834    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
835    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
836    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
837    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
838    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
839      return true;
840
841    default:
842      return false;
843  }
844  return false;
845}
846
847unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
848  switch(MI->getOpcode()) {
849    // JMP_EQri
850    case Hexagon::JMP_EQriPt_nv_V4:
851      return Hexagon::JMP_EQriPt_ie_nv_V4;
852    case Hexagon::JMP_EQriNotPt_nv_V4:
853      return Hexagon::JMP_EQriNotPt_ie_nv_V4;
854    case Hexagon::JMP_EQriPnt_nv_V4:
855      return Hexagon::JMP_EQriPnt_ie_nv_V4;
856    case Hexagon::JMP_EQriNotPnt_nv_V4:
857      return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
858
859    // JMP_EQri -- with -1
860    case Hexagon::JMP_EQriPtneg_nv_V4:
861      return Hexagon::JMP_EQriPtneg_ie_nv_V4;
862    case Hexagon::JMP_EQriNotPtneg_nv_V4:
863      return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
864    case Hexagon::JMP_EQriPntneg_nv_V4:
865      return Hexagon::JMP_EQriPntneg_ie_nv_V4;
866    case Hexagon::JMP_EQriNotPntneg_nv_V4:
867      return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
868
869    // JMP_EQrr
870    case Hexagon::JMP_EQrrPt_nv_V4:
871      return Hexagon::JMP_EQrrPt_ie_nv_V4;
872    case Hexagon::JMP_EQrrNotPt_nv_V4:
873      return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
874    case Hexagon::JMP_EQrrPnt_nv_V4:
875      return Hexagon::JMP_EQrrPnt_ie_nv_V4;
876    case Hexagon::JMP_EQrrNotPnt_nv_V4:
877      return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
878
879    // JMP_GTri
880    case Hexagon::JMP_GTriPt_nv_V4:
881      return Hexagon::JMP_GTriPt_ie_nv_V4;
882    case Hexagon::JMP_GTriNotPt_nv_V4:
883      return Hexagon::JMP_GTriNotPt_ie_nv_V4;
884    case Hexagon::JMP_GTriPnt_nv_V4:
885      return Hexagon::JMP_GTriPnt_ie_nv_V4;
886    case Hexagon::JMP_GTriNotPnt_nv_V4:
887      return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
888
889    // JMP_GTri -- with -1
890    case Hexagon::JMP_GTriPtneg_nv_V4:
891      return Hexagon::JMP_GTriPtneg_ie_nv_V4;
892    case Hexagon::JMP_GTriNotPtneg_nv_V4:
893      return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
894    case Hexagon::JMP_GTriPntneg_nv_V4:
895      return Hexagon::JMP_GTriPntneg_ie_nv_V4;
896    case Hexagon::JMP_GTriNotPntneg_nv_V4:
897      return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
898
899    // JMP_GTrr
900    case Hexagon::JMP_GTrrPt_nv_V4:
901      return Hexagon::JMP_GTrrPt_ie_nv_V4;
902    case Hexagon::JMP_GTrrNotPt_nv_V4:
903      return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
904    case Hexagon::JMP_GTrrPnt_nv_V4:
905      return Hexagon::JMP_GTrrPnt_ie_nv_V4;
906    case Hexagon::JMP_GTrrNotPnt_nv_V4:
907      return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
908
909    // JMP_GTrrdn
910    case Hexagon::JMP_GTrrdnPt_nv_V4:
911      return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
912    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
913      return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
914    case Hexagon::JMP_GTrrdnPnt_nv_V4:
915      return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
916    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
917      return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
918
919    // JMP_GTUri
920    case Hexagon::JMP_GTUriPt_nv_V4:
921      return Hexagon::JMP_GTUriPt_ie_nv_V4;
922    case Hexagon::JMP_GTUriNotPt_nv_V4:
923      return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
924    case Hexagon::JMP_GTUriPnt_nv_V4:
925      return Hexagon::JMP_GTUriPnt_ie_nv_V4;
926    case Hexagon::JMP_GTUriNotPnt_nv_V4:
927      return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
928
929    // JMP_GTUrr
930    case Hexagon::JMP_GTUrrPt_nv_V4:
931      return Hexagon::JMP_GTUrrPt_ie_nv_V4;
932    case Hexagon::JMP_GTUrrNotPt_nv_V4:
933      return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
934    case Hexagon::JMP_GTUrrPnt_nv_V4:
935      return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
936    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
937      return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
938
939    // JMP_GTUrrdn
940    case Hexagon::JMP_GTUrrdnPt_nv_V4:
941      return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
942    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
943      return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
944    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
945      return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
946    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
947      return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
948
949  case Hexagon::TFR_FI:
950      return Hexagon::TFR_FI_immext_V4;
951
952  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
953  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
954  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
955  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
956  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
957  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
958  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
959  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
960  case Hexagon::MEMw_ADDi_MEM_V4 :
961  case Hexagon::MEMw_SUBi_MEM_V4 :
962  case Hexagon::MEMw_ADDr_MEM_V4 :
963  case Hexagon::MEMw_SUBr_MEM_V4 :
964  case Hexagon::MEMw_ANDr_MEM_V4 :
965  case Hexagon::MEMw_ORr_MEM_V4 :
966  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
967  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
968  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
969  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
970  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
971  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
972  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
973  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
974  case Hexagon::MEMh_ADDi_MEM_V4 :
975  case Hexagon::MEMh_SUBi_MEM_V4 :
976  case Hexagon::MEMh_ADDr_MEM_V4 :
977  case Hexagon::MEMh_SUBr_MEM_V4 :
978  case Hexagon::MEMh_ANDr_MEM_V4 :
979  case Hexagon::MEMh_ORr_MEM_V4 :
980  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
981  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
982  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
983  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
984  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
985  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
986  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
987  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
988  case Hexagon::MEMb_ADDi_MEM_V4 :
989  case Hexagon::MEMb_SUBi_MEM_V4 :
990  case Hexagon::MEMb_ADDr_MEM_V4 :
991  case Hexagon::MEMb_SUBr_MEM_V4 :
992  case Hexagon::MEMb_ANDr_MEM_V4 :
993  case Hexagon::MEMb_ORr_MEM_V4 :
994    assert(0 && "Needs implementing");
995
996  default:
997    assert(0 && "Unknown type of instruction");
998  }
999  assert(0 && "Unknown type of instruction");
1000}
1001
1002unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
1003  switch(MI->getOpcode()) {
1004    // JMP_EQri
1005    case Hexagon::JMP_EQriPt_ie_nv_V4:
1006      return Hexagon::JMP_EQriPt_nv_V4;
1007    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
1008      return Hexagon::JMP_EQriNotPt_nv_V4;
1009    case Hexagon::JMP_EQriPnt_ie_nv_V4:
1010      return Hexagon::JMP_EQriPnt_nv_V4;
1011    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
1012      return Hexagon::JMP_EQriNotPnt_nv_V4;
1013
1014    // JMP_EQri -- with -1
1015    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
1016      return Hexagon::JMP_EQriPtneg_nv_V4;
1017    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
1018      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1019    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
1020      return Hexagon::JMP_EQriPntneg_nv_V4;
1021    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
1022      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1023
1024    // JMP_EQrr
1025    case Hexagon::JMP_EQrrPt_ie_nv_V4:
1026      return Hexagon::JMP_EQrrPt_nv_V4;
1027    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
1028      return Hexagon::JMP_EQrrNotPt_nv_V4;
1029    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
1030      return Hexagon::JMP_EQrrPnt_nv_V4;
1031    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
1032      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1033
1034    // JMP_GTri
1035    case Hexagon::JMP_GTriPt_ie_nv_V4:
1036      return Hexagon::JMP_GTriPt_nv_V4;
1037    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
1038      return Hexagon::JMP_GTriNotPt_nv_V4;
1039    case Hexagon::JMP_GTriPnt_ie_nv_V4:
1040      return Hexagon::JMP_GTriPnt_nv_V4;
1041    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
1042      return Hexagon::JMP_GTriNotPnt_nv_V4;
1043
1044    // JMP_GTri -- with -1
1045    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
1046      return Hexagon::JMP_GTriPtneg_nv_V4;
1047    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
1048      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1049    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
1050      return Hexagon::JMP_GTriPntneg_nv_V4;
1051    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
1052      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1053
1054    // JMP_GTrr
1055    case Hexagon::JMP_GTrrPt_ie_nv_V4:
1056      return Hexagon::JMP_GTrrPt_nv_V4;
1057    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
1058      return Hexagon::JMP_GTrrNotPt_nv_V4;
1059    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
1060      return Hexagon::JMP_GTrrPnt_nv_V4;
1061    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
1062      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1063
1064    // JMP_GTrrdn
1065    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
1066      return Hexagon::JMP_GTrrdnPt_nv_V4;
1067    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
1068      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1069    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
1070      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1071    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
1072      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1073
1074    // JMP_GTUri
1075    case Hexagon::JMP_GTUriPt_ie_nv_V4:
1076      return Hexagon::JMP_GTUriPt_nv_V4;
1077    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
1078      return Hexagon::JMP_GTUriNotPt_nv_V4;
1079    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
1080      return Hexagon::JMP_GTUriPnt_nv_V4;
1081    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
1082      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1083
1084    // JMP_GTUrr
1085    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
1086      return Hexagon::JMP_GTUrrPt_nv_V4;
1087    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
1088      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1089    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
1090      return Hexagon::JMP_GTUrrPnt_nv_V4;
1091    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
1092      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1093
1094    // JMP_GTUrrdn
1095    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
1096      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1097    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
1098      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1099    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
1100      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1101    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
1102      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1103
1104    default:
1105      assert(0 && "Unknown type of jump instruction");
1106  }
1107  assert(0 && "Unknown type of jump instruction");
1108}
1109
1110
1111bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
1112  switch (MI->getOpcode()) {
1113
1114    // Store Byte
1115    case Hexagon::STrib_nv_V4:
1116    case Hexagon::STrib_indexed_nv_V4:
1117    case Hexagon::STrib_indexed_shl_nv_V4:
1118    case Hexagon::STrib_shl_nv_V4:
1119    case Hexagon::STrib_GP_nv_V4:
1120    case Hexagon::STb_GP_nv_V4:
1121    case Hexagon::POST_STbri_nv_V4:
1122    case Hexagon::STrib_cPt_nv_V4:
1123    case Hexagon::STrib_cdnPt_nv_V4:
1124    case Hexagon::STrib_cNotPt_nv_V4:
1125    case Hexagon::STrib_cdnNotPt_nv_V4:
1126    case Hexagon::STrib_indexed_cPt_nv_V4:
1127    case Hexagon::STrib_indexed_cdnPt_nv_V4:
1128    case Hexagon::STrib_indexed_cNotPt_nv_V4:
1129    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
1130    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
1131    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1132    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
1133    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1134    case Hexagon::POST_STbri_cPt_nv_V4:
1135    case Hexagon::POST_STbri_cdnPt_nv_V4:
1136    case Hexagon::POST_STbri_cNotPt_nv_V4:
1137    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
1138    case Hexagon::STb_GP_cPt_nv_V4:
1139    case Hexagon::STb_GP_cNotPt_nv_V4:
1140    case Hexagon::STb_GP_cdnPt_nv_V4:
1141    case Hexagon::STb_GP_cdnNotPt_nv_V4:
1142    case Hexagon::STrib_GP_cPt_nv_V4:
1143    case Hexagon::STrib_GP_cNotPt_nv_V4:
1144    case Hexagon::STrib_GP_cdnPt_nv_V4:
1145    case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1146    case Hexagon::STrib_abs_nv_V4:
1147    case Hexagon::STrib_abs_cPt_nv_V4:
1148    case Hexagon::STrib_abs_cdnPt_nv_V4:
1149    case Hexagon::STrib_abs_cNotPt_nv_V4:
1150    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
1151    case Hexagon::STrib_imm_abs_nv_V4:
1152    case Hexagon::STrib_imm_abs_cPt_nv_V4:
1153    case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
1154    case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
1155    case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
1156
1157    // Store Halfword
1158    case Hexagon::STrih_nv_V4:
1159    case Hexagon::STrih_indexed_nv_V4:
1160    case Hexagon::STrih_indexed_shl_nv_V4:
1161    case Hexagon::STrih_shl_nv_V4:
1162    case Hexagon::STrih_GP_nv_V4:
1163    case Hexagon::STh_GP_nv_V4:
1164    case Hexagon::POST_SThri_nv_V4:
1165    case Hexagon::STrih_cPt_nv_V4:
1166    case Hexagon::STrih_cdnPt_nv_V4:
1167    case Hexagon::STrih_cNotPt_nv_V4:
1168    case Hexagon::STrih_cdnNotPt_nv_V4:
1169    case Hexagon::STrih_indexed_cPt_nv_V4:
1170    case Hexagon::STrih_indexed_cdnPt_nv_V4:
1171    case Hexagon::STrih_indexed_cNotPt_nv_V4:
1172    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1173    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
1174    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
1175    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
1176    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
1177    case Hexagon::POST_SThri_cPt_nv_V4:
1178    case Hexagon::POST_SThri_cdnPt_nv_V4:
1179    case Hexagon::POST_SThri_cNotPt_nv_V4:
1180    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
1181    case Hexagon::STh_GP_cPt_nv_V4:
1182    case Hexagon::STh_GP_cNotPt_nv_V4:
1183    case Hexagon::STh_GP_cdnPt_nv_V4:
1184    case Hexagon::STh_GP_cdnNotPt_nv_V4:
1185    case Hexagon::STrih_GP_cPt_nv_V4:
1186    case Hexagon::STrih_GP_cNotPt_nv_V4:
1187    case Hexagon::STrih_GP_cdnPt_nv_V4:
1188    case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1189    case Hexagon::STrih_abs_nv_V4:
1190    case Hexagon::STrih_abs_cPt_nv_V4:
1191    case Hexagon::STrih_abs_cdnPt_nv_V4:
1192    case Hexagon::STrih_abs_cNotPt_nv_V4:
1193    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
1194    case Hexagon::STrih_imm_abs_nv_V4:
1195    case Hexagon::STrih_imm_abs_cPt_nv_V4:
1196    case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
1197    case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
1198    case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
1199
1200    // Store Word
1201    case Hexagon::STriw_nv_V4:
1202    case Hexagon::STriw_indexed_nv_V4:
1203    case Hexagon::STriw_indexed_shl_nv_V4:
1204    case Hexagon::STriw_shl_nv_V4:
1205    case Hexagon::STriw_GP_nv_V4:
1206    case Hexagon::STw_GP_nv_V4:
1207    case Hexagon::POST_STwri_nv_V4:
1208    case Hexagon::STriw_cPt_nv_V4:
1209    case Hexagon::STriw_cdnPt_nv_V4:
1210    case Hexagon::STriw_cNotPt_nv_V4:
1211    case Hexagon::STriw_cdnNotPt_nv_V4:
1212    case Hexagon::STriw_indexed_cPt_nv_V4:
1213    case Hexagon::STriw_indexed_cdnPt_nv_V4:
1214    case Hexagon::STriw_indexed_cNotPt_nv_V4:
1215    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
1216    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
1217    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
1218    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
1219    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
1220    case Hexagon::POST_STwri_cPt_nv_V4:
1221    case Hexagon::POST_STwri_cdnPt_nv_V4:
1222    case Hexagon::POST_STwri_cNotPt_nv_V4:
1223    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
1224    case Hexagon::STw_GP_cPt_nv_V4:
1225    case Hexagon::STw_GP_cNotPt_nv_V4:
1226    case Hexagon::STw_GP_cdnPt_nv_V4:
1227    case Hexagon::STw_GP_cdnNotPt_nv_V4:
1228    case Hexagon::STriw_GP_cPt_nv_V4:
1229    case Hexagon::STriw_GP_cNotPt_nv_V4:
1230    case Hexagon::STriw_GP_cdnPt_nv_V4:
1231    case Hexagon::STriw_GP_cdnNotPt_nv_V4:
1232    case Hexagon::STriw_abs_nv_V4:
1233    case Hexagon::STriw_abs_cPt_nv_V4:
1234    case Hexagon::STriw_abs_cdnPt_nv_V4:
1235    case Hexagon::STriw_abs_cNotPt_nv_V4:
1236    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
1237    case Hexagon::STriw_imm_abs_nv_V4:
1238    case Hexagon::STriw_imm_abs_cPt_nv_V4:
1239    case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
1240    case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
1241    case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
1242      return true;
1243
1244    default:
1245      return false;
1246  }
1247  return false;
1248}
1249
1250bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
1251  switch (MI->getOpcode())
1252  {
1253    // Load Byte
1254    case Hexagon::POST_LDrib:
1255    case Hexagon::POST_LDrib_cPt:
1256    case Hexagon::POST_LDrib_cNotPt:
1257    case Hexagon::POST_LDrib_cdnPt_V4:
1258    case Hexagon::POST_LDrib_cdnNotPt_V4:
1259
1260    // Load unsigned byte
1261    case Hexagon::POST_LDriub:
1262    case Hexagon::POST_LDriub_cPt:
1263    case Hexagon::POST_LDriub_cNotPt:
1264    case Hexagon::POST_LDriub_cdnPt_V4:
1265    case Hexagon::POST_LDriub_cdnNotPt_V4:
1266
1267    // Load halfword
1268    case Hexagon::POST_LDrih:
1269    case Hexagon::POST_LDrih_cPt:
1270    case Hexagon::POST_LDrih_cNotPt:
1271    case Hexagon::POST_LDrih_cdnPt_V4:
1272    case Hexagon::POST_LDrih_cdnNotPt_V4:
1273
1274    // Load unsigned halfword
1275    case Hexagon::POST_LDriuh:
1276    case Hexagon::POST_LDriuh_cPt:
1277    case Hexagon::POST_LDriuh_cNotPt:
1278    case Hexagon::POST_LDriuh_cdnPt_V4:
1279    case Hexagon::POST_LDriuh_cdnNotPt_V4:
1280
1281    // Load word
1282    case Hexagon::POST_LDriw:
1283    case Hexagon::POST_LDriw_cPt:
1284    case Hexagon::POST_LDriw_cNotPt:
1285    case Hexagon::POST_LDriw_cdnPt_V4:
1286    case Hexagon::POST_LDriw_cdnNotPt_V4:
1287
1288    // Load double word
1289    case Hexagon::POST_LDrid:
1290    case Hexagon::POST_LDrid_cPt:
1291    case Hexagon::POST_LDrid_cNotPt:
1292    case Hexagon::POST_LDrid_cdnPt_V4:
1293    case Hexagon::POST_LDrid_cdnNotPt_V4:
1294
1295    // Store byte
1296    case Hexagon::POST_STbri:
1297    case Hexagon::POST_STbri_cPt:
1298    case Hexagon::POST_STbri_cNotPt:
1299    case Hexagon::POST_STbri_cdnPt_V4:
1300    case Hexagon::POST_STbri_cdnNotPt_V4:
1301
1302    // Store halfword
1303    case Hexagon::POST_SThri:
1304    case Hexagon::POST_SThri_cPt:
1305    case Hexagon::POST_SThri_cNotPt:
1306    case Hexagon::POST_SThri_cdnPt_V4:
1307    case Hexagon::POST_SThri_cdnNotPt_V4:
1308
1309    // Store word
1310    case Hexagon::POST_STwri:
1311    case Hexagon::POST_STwri_cPt:
1312    case Hexagon::POST_STwri_cNotPt:
1313    case Hexagon::POST_STwri_cdnPt_V4:
1314    case Hexagon::POST_STwri_cdnNotPt_V4:
1315
1316    // Store double word
1317    case Hexagon::POST_STdri:
1318    case Hexagon::POST_STdri_cPt:
1319    case Hexagon::POST_STdri_cNotPt:
1320    case Hexagon::POST_STdri_cdnPt_V4:
1321    case Hexagon::POST_STdri_cdnNotPt_V4:
1322      return true;
1323
1324    default:
1325      return false;
1326  }
1327}
1328
1329bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
1330  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
1331}
1332
1333bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
1334  bool isPred = MI->getDesc().isPredicable();
1335
1336  if (!isPred)
1337    return false;
1338
1339  const int Opc = MI->getOpcode();
1340
1341  switch(Opc) {
1342  case Hexagon::TFRI:
1343    return isInt<12>(MI->getOperand(1).getImm());
1344
1345  case Hexagon::STrid:
1346  case Hexagon::STrid_indexed:
1347    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
1348
1349  case Hexagon::STriw:
1350  case Hexagon::STriw_indexed:
1351  case Hexagon::STriw_nv_V4:
1352    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
1353
1354  case Hexagon::STrih:
1355  case Hexagon::STrih_indexed:
1356  case Hexagon::STrih_nv_V4:
1357    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
1358
1359  case Hexagon::STrib:
1360  case Hexagon::STrib_indexed:
1361  case Hexagon::STrib_nv_V4:
1362    return isUInt<6>(MI->getOperand(1).getImm());
1363
1364  case Hexagon::LDrid:
1365  case Hexagon::LDrid_indexed:
1366    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
1367
1368  case Hexagon::LDriw:
1369  case Hexagon::LDriw_indexed:
1370    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
1371
1372  case Hexagon::LDrih:
1373  case Hexagon::LDriuh:
1374  case Hexagon::LDrih_indexed:
1375  case Hexagon::LDriuh_indexed:
1376    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
1377
1378  case Hexagon::LDrib:
1379  case Hexagon::LDriub:
1380  case Hexagon::LDrib_indexed:
1381  case Hexagon::LDriub_indexed:
1382    return isUInt<6>(MI->getOperand(2).getImm());
1383
1384  case Hexagon::POST_LDrid:
1385    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
1386
1387  case Hexagon::POST_LDriw:
1388    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
1389
1390  case Hexagon::POST_LDrih:
1391  case Hexagon::POST_LDriuh:
1392    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
1393
1394  case Hexagon::POST_LDrib:
1395  case Hexagon::POST_LDriub:
1396    return isInt<4>(MI->getOperand(3).getImm());
1397
1398  case Hexagon::STrib_imm_V4:
1399  case Hexagon::STrih_imm_V4:
1400  case Hexagon::STriw_imm_V4:
1401    return (isUInt<6>(MI->getOperand(1).getImm()) &&
1402            isInt<6>(MI->getOperand(2).getImm()));
1403
1404  case Hexagon::ADD_ri:
1405    return isInt<8>(MI->getOperand(2).getImm());
1406
1407  case Hexagon::ASLH:
1408  case Hexagon::ASRH:
1409  case Hexagon::SXTB:
1410  case Hexagon::SXTH:
1411  case Hexagon::ZXTB:
1412  case Hexagon::ZXTH:
1413    return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
1414
1415  case Hexagon::JMPR:
1416    return false;
1417  }
1418
1419  return true;
1420}
1421
1422unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1423  switch(Opc) {
1424    case Hexagon::TFR_cPt:
1425      return Hexagon::TFR_cNotPt;
1426    case Hexagon::TFR_cNotPt:
1427      return Hexagon::TFR_cPt;
1428
1429    case Hexagon::TFRI_cPt:
1430      return Hexagon::TFRI_cNotPt;
1431    case Hexagon::TFRI_cNotPt:
1432      return Hexagon::TFRI_cPt;
1433
1434    case Hexagon::JMP_c:
1435      return Hexagon::JMP_cNot;
1436    case Hexagon::JMP_cNot:
1437      return Hexagon::JMP_c;
1438
1439    case Hexagon::ADD_ri_cPt:
1440      return Hexagon::ADD_ri_cNotPt;
1441    case Hexagon::ADD_ri_cNotPt:
1442      return Hexagon::ADD_ri_cPt;
1443
1444    case Hexagon::ADD_rr_cPt:
1445      return Hexagon::ADD_rr_cNotPt;
1446    case Hexagon::ADD_rr_cNotPt:
1447      return Hexagon::ADD_rr_cPt;
1448
1449    case Hexagon::XOR_rr_cPt:
1450      return Hexagon::XOR_rr_cNotPt;
1451    case Hexagon::XOR_rr_cNotPt:
1452      return Hexagon::XOR_rr_cPt;
1453
1454    case Hexagon::AND_rr_cPt:
1455      return Hexagon::AND_rr_cNotPt;
1456    case Hexagon::AND_rr_cNotPt:
1457      return Hexagon::AND_rr_cPt;
1458
1459    case Hexagon::OR_rr_cPt:
1460      return Hexagon::OR_rr_cNotPt;
1461    case Hexagon::OR_rr_cNotPt:
1462      return Hexagon::OR_rr_cPt;
1463
1464    case Hexagon::SUB_rr_cPt:
1465      return Hexagon::SUB_rr_cNotPt;
1466    case Hexagon::SUB_rr_cNotPt:
1467      return Hexagon::SUB_rr_cPt;
1468
1469    case Hexagon::COMBINE_rr_cPt:
1470      return Hexagon::COMBINE_rr_cNotPt;
1471    case Hexagon::COMBINE_rr_cNotPt:
1472      return Hexagon::COMBINE_rr_cPt;
1473
1474    case Hexagon::ASLH_cPt_V4:
1475      return Hexagon::ASLH_cNotPt_V4;
1476    case Hexagon::ASLH_cNotPt_V4:
1477      return Hexagon::ASLH_cPt_V4;
1478
1479    case Hexagon::ASRH_cPt_V4:
1480      return Hexagon::ASRH_cNotPt_V4;
1481    case Hexagon::ASRH_cNotPt_V4:
1482      return Hexagon::ASRH_cPt_V4;
1483
1484    case Hexagon::SXTB_cPt_V4:
1485      return Hexagon::SXTB_cNotPt_V4;
1486    case Hexagon::SXTB_cNotPt_V4:
1487      return Hexagon::SXTB_cPt_V4;
1488
1489    case Hexagon::SXTH_cPt_V4:
1490      return Hexagon::SXTH_cNotPt_V4;
1491    case Hexagon::SXTH_cNotPt_V4:
1492      return Hexagon::SXTH_cPt_V4;
1493
1494    case Hexagon::ZXTB_cPt_V4:
1495      return Hexagon::ZXTB_cNotPt_V4;
1496    case Hexagon::ZXTB_cNotPt_V4:
1497      return Hexagon::ZXTB_cPt_V4;
1498
1499    case Hexagon::ZXTH_cPt_V4:
1500      return Hexagon::ZXTH_cNotPt_V4;
1501    case Hexagon::ZXTH_cNotPt_V4:
1502      return Hexagon::ZXTH_cPt_V4;
1503
1504
1505    case Hexagon::JMPR_cPt:
1506      return Hexagon::JMPR_cNotPt;
1507    case Hexagon::JMPR_cNotPt:
1508      return Hexagon::JMPR_cPt;
1509
1510  // V4 indexed+scaled load.
1511    case Hexagon::LDrid_indexed_cPt_V4:
1512      return Hexagon::LDrid_indexed_cNotPt_V4;
1513    case Hexagon::LDrid_indexed_cNotPt_V4:
1514      return Hexagon::LDrid_indexed_cPt_V4;
1515
1516    case Hexagon::LDrid_indexed_shl_cPt_V4:
1517      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1518    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1519      return Hexagon::LDrid_indexed_shl_cPt_V4;
1520
1521    case Hexagon::LDrib_indexed_cPt_V4:
1522      return Hexagon::LDrib_indexed_cNotPt_V4;
1523    case Hexagon::LDrib_indexed_cNotPt_V4:
1524      return Hexagon::LDrib_indexed_cPt_V4;
1525
1526    case Hexagon::LDriub_indexed_cPt_V4:
1527      return Hexagon::LDriub_indexed_cNotPt_V4;
1528    case Hexagon::LDriub_indexed_cNotPt_V4:
1529      return Hexagon::LDriub_indexed_cPt_V4;
1530
1531    case Hexagon::LDrib_indexed_shl_cPt_V4:
1532      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1533    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1534      return Hexagon::LDrib_indexed_shl_cPt_V4;
1535
1536    case Hexagon::LDriub_indexed_shl_cPt_V4:
1537      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1538    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1539      return Hexagon::LDriub_indexed_shl_cPt_V4;
1540
1541    case Hexagon::LDrih_indexed_cPt_V4:
1542      return Hexagon::LDrih_indexed_cNotPt_V4;
1543    case Hexagon::LDrih_indexed_cNotPt_V4:
1544      return Hexagon::LDrih_indexed_cPt_V4;
1545
1546    case Hexagon::LDriuh_indexed_cPt_V4:
1547      return Hexagon::LDriuh_indexed_cNotPt_V4;
1548    case Hexagon::LDriuh_indexed_cNotPt_V4:
1549      return Hexagon::LDriuh_indexed_cPt_V4;
1550
1551    case Hexagon::LDrih_indexed_shl_cPt_V4:
1552      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1553    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1554      return Hexagon::LDrih_indexed_shl_cPt_V4;
1555
1556    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1557      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1558    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1559      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1560
1561    case Hexagon::LDriw_indexed_cPt_V4:
1562      return Hexagon::LDriw_indexed_cNotPt_V4;
1563    case Hexagon::LDriw_indexed_cNotPt_V4:
1564      return Hexagon::LDriw_indexed_cPt_V4;
1565
1566    case Hexagon::LDriw_indexed_shl_cPt_V4:
1567      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1568    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1569      return Hexagon::LDriw_indexed_shl_cPt_V4;
1570
1571    // Byte.
1572    case Hexagon::POST_STbri_cPt:
1573      return Hexagon::POST_STbri_cNotPt;
1574    case Hexagon::POST_STbri_cNotPt:
1575      return Hexagon::POST_STbri_cPt;
1576
1577    case Hexagon::STrib_cPt:
1578      return Hexagon::STrib_cNotPt;
1579    case Hexagon::STrib_cNotPt:
1580      return Hexagon::STrib_cPt;
1581
1582    case Hexagon::STrib_indexed_cPt:
1583      return Hexagon::STrib_indexed_cNotPt;
1584    case Hexagon::STrib_indexed_cNotPt:
1585      return Hexagon::STrib_indexed_cPt;
1586
1587    case Hexagon::STrib_imm_cPt_V4:
1588      return Hexagon::STrib_imm_cNotPt_V4;
1589    case Hexagon::STrib_imm_cNotPt_V4:
1590      return Hexagon::STrib_imm_cPt_V4;
1591
1592    case Hexagon::STrib_indexed_shl_cPt_V4:
1593      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1594    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1595      return Hexagon::STrib_indexed_shl_cPt_V4;
1596
1597  // Halfword.
1598    case Hexagon::POST_SThri_cPt:
1599      return Hexagon::POST_SThri_cNotPt;
1600    case Hexagon::POST_SThri_cNotPt:
1601      return Hexagon::POST_SThri_cPt;
1602
1603    case Hexagon::STrih_cPt:
1604      return Hexagon::STrih_cNotPt;
1605    case Hexagon::STrih_cNotPt:
1606      return Hexagon::STrih_cPt;
1607
1608    case Hexagon::STrih_indexed_cPt:
1609      return Hexagon::STrih_indexed_cNotPt;
1610    case Hexagon::STrih_indexed_cNotPt:
1611      return Hexagon::STrih_indexed_cPt;
1612
1613    case Hexagon::STrih_imm_cPt_V4:
1614      return Hexagon::STrih_imm_cNotPt_V4;
1615    case Hexagon::STrih_imm_cNotPt_V4:
1616      return Hexagon::STrih_imm_cPt_V4;
1617
1618    case Hexagon::STrih_indexed_shl_cPt_V4:
1619      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1620    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1621      return Hexagon::STrih_indexed_shl_cPt_V4;
1622
1623  // Word.
1624    case Hexagon::POST_STwri_cPt:
1625      return Hexagon::POST_STwri_cNotPt;
1626    case Hexagon::POST_STwri_cNotPt:
1627      return Hexagon::POST_STwri_cPt;
1628
1629    case Hexagon::STriw_cPt:
1630      return Hexagon::STriw_cNotPt;
1631    case Hexagon::STriw_cNotPt:
1632      return Hexagon::STriw_cPt;
1633
1634    case Hexagon::STriw_indexed_cPt:
1635      return Hexagon::STriw_indexed_cNotPt;
1636    case Hexagon::STriw_indexed_cNotPt:
1637      return Hexagon::STriw_indexed_cPt;
1638
1639    case Hexagon::STriw_indexed_shl_cPt_V4:
1640      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1641    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1642      return Hexagon::STriw_indexed_shl_cPt_V4;
1643
1644    case Hexagon::STriw_imm_cPt_V4:
1645      return Hexagon::STriw_imm_cNotPt_V4;
1646    case Hexagon::STriw_imm_cNotPt_V4:
1647      return Hexagon::STriw_imm_cPt_V4;
1648
1649  // Double word.
1650    case Hexagon::POST_STdri_cPt:
1651      return Hexagon::POST_STdri_cNotPt;
1652    case Hexagon::POST_STdri_cNotPt:
1653      return Hexagon::POST_STdri_cPt;
1654
1655    case Hexagon::STrid_cPt:
1656      return Hexagon::STrid_cNotPt;
1657    case Hexagon::STrid_cNotPt:
1658      return Hexagon::STrid_cPt;
1659
1660    case Hexagon::STrid_indexed_cPt:
1661      return Hexagon::STrid_indexed_cNotPt;
1662    case Hexagon::STrid_indexed_cNotPt:
1663      return Hexagon::STrid_indexed_cPt;
1664
1665    case Hexagon::STrid_indexed_shl_cPt_V4:
1666      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1667    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1668      return Hexagon::STrid_indexed_shl_cPt_V4;
1669
1670  // Load.
1671    case Hexagon::LDrid_cPt:
1672      return Hexagon::LDrid_cNotPt;
1673    case Hexagon::LDrid_cNotPt:
1674      return Hexagon::LDrid_cPt;
1675
1676    case Hexagon::LDriw_cPt:
1677      return Hexagon::LDriw_cNotPt;
1678    case Hexagon::LDriw_cNotPt:
1679      return Hexagon::LDriw_cPt;
1680
1681    case Hexagon::LDrih_cPt:
1682      return Hexagon::LDrih_cNotPt;
1683    case Hexagon::LDrih_cNotPt:
1684      return Hexagon::LDrih_cPt;
1685
1686    case Hexagon::LDriuh_cPt:
1687      return Hexagon::LDriuh_cNotPt;
1688    case Hexagon::LDriuh_cNotPt:
1689      return Hexagon::LDriuh_cPt;
1690
1691    case Hexagon::LDrib_cPt:
1692      return Hexagon::LDrib_cNotPt;
1693    case Hexagon::LDrib_cNotPt:
1694      return Hexagon::LDrib_cPt;
1695
1696    case Hexagon::LDriub_cPt:
1697      return Hexagon::LDriub_cNotPt;
1698    case Hexagon::LDriub_cNotPt:
1699      return Hexagon::LDriub_cPt;
1700
1701 // Load Indexed.
1702    case Hexagon::LDrid_indexed_cPt:
1703      return Hexagon::LDrid_indexed_cNotPt;
1704    case Hexagon::LDrid_indexed_cNotPt:
1705      return Hexagon::LDrid_indexed_cPt;
1706
1707    case Hexagon::LDriw_indexed_cPt:
1708      return Hexagon::LDriw_indexed_cNotPt;
1709    case Hexagon::LDriw_indexed_cNotPt:
1710      return Hexagon::LDriw_indexed_cPt;
1711
1712    case Hexagon::LDrih_indexed_cPt:
1713      return Hexagon::LDrih_indexed_cNotPt;
1714    case Hexagon::LDrih_indexed_cNotPt:
1715      return Hexagon::LDrih_indexed_cPt;
1716
1717    case Hexagon::LDriuh_indexed_cPt:
1718      return Hexagon::LDriuh_indexed_cNotPt;
1719    case Hexagon::LDriuh_indexed_cNotPt:
1720      return Hexagon::LDriuh_indexed_cPt;
1721
1722    case Hexagon::LDrib_indexed_cPt:
1723      return Hexagon::LDrib_indexed_cNotPt;
1724    case Hexagon::LDrib_indexed_cNotPt:
1725      return Hexagon::LDrib_indexed_cPt;
1726
1727    case Hexagon::LDriub_indexed_cPt:
1728      return Hexagon::LDriub_indexed_cNotPt;
1729    case Hexagon::LDriub_indexed_cNotPt:
1730      return Hexagon::LDriub_indexed_cPt;
1731
1732  // Post Inc Load.
1733    case Hexagon::POST_LDrid_cPt:
1734      return Hexagon::POST_LDrid_cNotPt;
1735    case Hexagon::POST_LDriw_cNotPt:
1736      return Hexagon::POST_LDriw_cPt;
1737
1738    case Hexagon::POST_LDrih_cPt:
1739      return Hexagon::POST_LDrih_cNotPt;
1740    case Hexagon::POST_LDrih_cNotPt:
1741      return Hexagon::POST_LDrih_cPt;
1742
1743    case Hexagon::POST_LDriuh_cPt:
1744      return Hexagon::POST_LDriuh_cNotPt;
1745    case Hexagon::POST_LDriuh_cNotPt:
1746      return Hexagon::POST_LDriuh_cPt;
1747
1748    case Hexagon::POST_LDrib_cPt:
1749      return Hexagon::POST_LDrib_cNotPt;
1750    case Hexagon::POST_LDrib_cNotPt:
1751      return Hexagon::POST_LDrib_cPt;
1752
1753    case Hexagon::POST_LDriub_cPt:
1754      return Hexagon::POST_LDriub_cNotPt;
1755    case Hexagon::POST_LDriub_cNotPt:
1756      return Hexagon::POST_LDriub_cPt;
1757
1758  // Dealloc_return.
1759    case Hexagon::DEALLOC_RET_cPt_V4:
1760      return Hexagon::DEALLOC_RET_cNotPt_V4;
1761    case Hexagon::DEALLOC_RET_cNotPt_V4:
1762      return Hexagon::DEALLOC_RET_cPt_V4;
1763
1764   // New Value Jump.
1765   // JMPEQ_ri - with -1.
1766    case Hexagon::JMP_EQriPtneg_nv_V4:
1767      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1768    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1769      return Hexagon::JMP_EQriPtneg_nv_V4;
1770
1771    case Hexagon::JMP_EQriPntneg_nv_V4:
1772      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1773    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1774      return Hexagon::JMP_EQriPntneg_nv_V4;
1775
1776   // JMPEQ_ri.
1777     case Hexagon::JMP_EQriPt_nv_V4:
1778      return Hexagon::JMP_EQriNotPt_nv_V4;
1779    case Hexagon::JMP_EQriNotPt_nv_V4:
1780      return Hexagon::JMP_EQriPt_nv_V4;
1781
1782     case Hexagon::JMP_EQriPnt_nv_V4:
1783      return Hexagon::JMP_EQriNotPnt_nv_V4;
1784    case Hexagon::JMP_EQriNotPnt_nv_V4:
1785      return Hexagon::JMP_EQriPnt_nv_V4;
1786
1787   // JMPEQ_rr.
1788     case Hexagon::JMP_EQrrPt_nv_V4:
1789      return Hexagon::JMP_EQrrNotPt_nv_V4;
1790    case Hexagon::JMP_EQrrNotPt_nv_V4:
1791      return Hexagon::JMP_EQrrPt_nv_V4;
1792
1793     case Hexagon::JMP_EQrrPnt_nv_V4:
1794      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1795    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1796      return Hexagon::JMP_EQrrPnt_nv_V4;
1797
1798   // JMPGT_ri - with -1.
1799    case Hexagon::JMP_GTriPtneg_nv_V4:
1800      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1801    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1802      return Hexagon::JMP_GTriPtneg_nv_V4;
1803
1804    case Hexagon::JMP_GTriPntneg_nv_V4:
1805      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1806    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1807      return Hexagon::JMP_GTriPntneg_nv_V4;
1808
1809   // JMPGT_ri.
1810     case Hexagon::JMP_GTriPt_nv_V4:
1811      return Hexagon::JMP_GTriNotPt_nv_V4;
1812    case Hexagon::JMP_GTriNotPt_nv_V4:
1813      return Hexagon::JMP_GTriPt_nv_V4;
1814
1815     case Hexagon::JMP_GTriPnt_nv_V4:
1816      return Hexagon::JMP_GTriNotPnt_nv_V4;
1817    case Hexagon::JMP_GTriNotPnt_nv_V4:
1818      return Hexagon::JMP_GTriPnt_nv_V4;
1819
1820   // JMPGT_rr.
1821     case Hexagon::JMP_GTrrPt_nv_V4:
1822      return Hexagon::JMP_GTrrNotPt_nv_V4;
1823    case Hexagon::JMP_GTrrNotPt_nv_V4:
1824      return Hexagon::JMP_GTrrPt_nv_V4;
1825
1826     case Hexagon::JMP_GTrrPnt_nv_V4:
1827      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1828    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1829      return Hexagon::JMP_GTrrPnt_nv_V4;
1830
1831   // JMPGT_rrdn.
1832     case Hexagon::JMP_GTrrdnPt_nv_V4:
1833      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1834    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1835      return Hexagon::JMP_GTrrdnPt_nv_V4;
1836
1837     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1838      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1839    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1840      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1841
1842   // JMPGTU_ri.
1843     case Hexagon::JMP_GTUriPt_nv_V4:
1844      return Hexagon::JMP_GTUriNotPt_nv_V4;
1845    case Hexagon::JMP_GTUriNotPt_nv_V4:
1846      return Hexagon::JMP_GTUriPt_nv_V4;
1847
1848     case Hexagon::JMP_GTUriPnt_nv_V4:
1849      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1850    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1851      return Hexagon::JMP_GTUriPnt_nv_V4;
1852
1853   // JMPGTU_rr.
1854     case Hexagon::JMP_GTUrrPt_nv_V4:
1855      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1856    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1857      return Hexagon::JMP_GTUrrPt_nv_V4;
1858
1859     case Hexagon::JMP_GTUrrPnt_nv_V4:
1860      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1861    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1862      return Hexagon::JMP_GTUrrPnt_nv_V4;
1863
1864   // JMPGTU_rrdn.
1865     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1866      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1867    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1868      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1869
1870     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1871      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1872    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1873      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1874
1875  default:
1876    llvm_unreachable("Unexpected predicated instruction");
1877  }
1878}
1879
1880
1881int HexagonInstrInfo::
1882getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1883  switch(Opc) {
1884  case Hexagon::TFR:
1885    return !invertPredicate ? Hexagon::TFR_cPt :
1886                              Hexagon::TFR_cNotPt;
1887  case Hexagon::TFRI:
1888    return !invertPredicate ? Hexagon::TFRI_cPt :
1889                              Hexagon::TFRI_cNotPt;
1890  case Hexagon::JMP:
1891    return !invertPredicate ? Hexagon::JMP_c :
1892                              Hexagon::JMP_cNot;
1893  case Hexagon::ADD_ri:
1894    return !invertPredicate ? Hexagon::ADD_ri_cPt :
1895                              Hexagon::ADD_ri_cNotPt;
1896  case Hexagon::ADD_rr:
1897    return !invertPredicate ? Hexagon::ADD_rr_cPt :
1898                              Hexagon::ADD_rr_cNotPt;
1899  case Hexagon::XOR_rr:
1900    return !invertPredicate ? Hexagon::XOR_rr_cPt :
1901                              Hexagon::XOR_rr_cNotPt;
1902  case Hexagon::AND_rr:
1903    return !invertPredicate ? Hexagon::AND_rr_cPt :
1904                              Hexagon::AND_rr_cNotPt;
1905  case Hexagon::OR_rr:
1906    return !invertPredicate ? Hexagon::OR_rr_cPt :
1907                              Hexagon::OR_rr_cNotPt;
1908  case Hexagon::SUB_rr:
1909    return !invertPredicate ? Hexagon::SUB_rr_cPt :
1910                              Hexagon::SUB_rr_cNotPt;
1911  case Hexagon::COMBINE_rr:
1912    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1913                              Hexagon::COMBINE_rr_cNotPt;
1914  case Hexagon::ASLH:
1915    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1916                              Hexagon::ASLH_cNotPt_V4;
1917  case Hexagon::ASRH:
1918    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1919                              Hexagon::ASRH_cNotPt_V4;
1920  case Hexagon::SXTB:
1921    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1922                              Hexagon::SXTB_cNotPt_V4;
1923  case Hexagon::SXTH:
1924    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1925                              Hexagon::SXTH_cNotPt_V4;
1926  case Hexagon::ZXTB:
1927    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1928                              Hexagon::ZXTB_cNotPt_V4;
1929  case Hexagon::ZXTH:
1930    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1931                              Hexagon::ZXTH_cNotPt_V4;
1932
1933  case Hexagon::JMPR:
1934    return !invertPredicate ? Hexagon::JMPR_cPt :
1935                              Hexagon::JMPR_cNotPt;
1936
1937  // V4 indexed+scaled load.
1938  case Hexagon::LDrid_indexed_V4:
1939    return !invertPredicate ? Hexagon::LDrid_indexed_cPt_V4 :
1940                              Hexagon::LDrid_indexed_cNotPt_V4;
1941  case Hexagon::LDrid_indexed_shl_V4:
1942    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1943                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1944  case Hexagon::LDrib_indexed_V4:
1945    return !invertPredicate ? Hexagon::LDrib_indexed_cPt_V4 :
1946                              Hexagon::LDrib_indexed_cNotPt_V4;
1947  case Hexagon::LDriub_indexed_V4:
1948    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1949                              Hexagon::LDriub_indexed_cNotPt_V4;
1950  case Hexagon::LDriub_ae_indexed_V4:
1951    return !invertPredicate ? Hexagon::LDriub_indexed_cPt_V4 :
1952                              Hexagon::LDriub_indexed_cNotPt_V4;
1953  case Hexagon::LDrib_indexed_shl_V4:
1954    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1955                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1956  case Hexagon::LDriub_indexed_shl_V4:
1957    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1958                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1959  case Hexagon::LDriub_ae_indexed_shl_V4:
1960    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1961                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1962  case Hexagon::LDrih_indexed_V4:
1963    return !invertPredicate ? Hexagon::LDrih_indexed_cPt_V4 :
1964                              Hexagon::LDrih_indexed_cNotPt_V4;
1965  case Hexagon::LDriuh_indexed_V4:
1966    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1967                              Hexagon::LDriuh_indexed_cNotPt_V4;
1968  case Hexagon::LDriuh_ae_indexed_V4:
1969    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt_V4 :
1970                              Hexagon::LDriuh_indexed_cNotPt_V4;
1971  case Hexagon::LDrih_indexed_shl_V4:
1972    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1973                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1974  case Hexagon::LDriuh_indexed_shl_V4:
1975    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1976                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1977  case Hexagon::LDriuh_ae_indexed_shl_V4:
1978    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1979                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1980  case Hexagon::LDriw_indexed_V4:
1981    return !invertPredicate ? Hexagon::LDriw_indexed_cPt_V4 :
1982                              Hexagon::LDriw_indexed_cNotPt_V4;
1983  case Hexagon::LDriw_indexed_shl_V4:
1984    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1985                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1986    // Byte.
1987  case Hexagon::POST_STbri:
1988    return !invertPredicate ? Hexagon::POST_STbri_cPt :
1989                              Hexagon::POST_STbri_cNotPt;
1990  case Hexagon::STrib:
1991    return !invertPredicate ? Hexagon::STrib_cPt :
1992                              Hexagon::STrib_cNotPt;
1993  case Hexagon::STrib_indexed:
1994    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1995                              Hexagon::STrib_indexed_cNotPt;
1996  case Hexagon::STrib_imm_V4:
1997    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1998                              Hexagon::STrib_imm_cNotPt_V4;
1999  case Hexagon::STrib_indexed_shl_V4:
2000    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
2001                              Hexagon::STrib_indexed_shl_cNotPt_V4;
2002  // Halfword.
2003  case Hexagon::POST_SThri:
2004    return !invertPredicate ? Hexagon::POST_SThri_cPt :
2005                              Hexagon::POST_SThri_cNotPt;
2006  case Hexagon::STrih:
2007    return !invertPredicate ? Hexagon::STrih_cPt :
2008                              Hexagon::STrih_cNotPt;
2009  case Hexagon::STrih_indexed:
2010    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
2011                              Hexagon::STrih_indexed_cNotPt;
2012  case Hexagon::STrih_imm_V4:
2013    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
2014                              Hexagon::STrih_imm_cNotPt_V4;
2015  case Hexagon::STrih_indexed_shl_V4:
2016    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
2017                              Hexagon::STrih_indexed_shl_cNotPt_V4;
2018  // Word.
2019  case Hexagon::POST_STwri:
2020    return !invertPredicate ? Hexagon::POST_STwri_cPt :
2021                              Hexagon::POST_STwri_cNotPt;
2022  case Hexagon::STriw:
2023    return !invertPredicate ? Hexagon::STriw_cPt :
2024                              Hexagon::STriw_cNotPt;
2025  case Hexagon::STriw_indexed:
2026    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
2027                              Hexagon::STriw_indexed_cNotPt;
2028  case Hexagon::STriw_indexed_shl_V4:
2029    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
2030                              Hexagon::STriw_indexed_shl_cNotPt_V4;
2031  case Hexagon::STriw_imm_V4:
2032    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
2033                              Hexagon::STriw_imm_cNotPt_V4;
2034  // Double word.
2035  case Hexagon::POST_STdri:
2036    return !invertPredicate ? Hexagon::POST_STdri_cPt :
2037                              Hexagon::POST_STdri_cNotPt;
2038  case Hexagon::STrid:
2039    return !invertPredicate ? Hexagon::STrid_cPt :
2040                              Hexagon::STrid_cNotPt;
2041  case Hexagon::STrid_indexed:
2042    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
2043                              Hexagon::STrid_indexed_cNotPt;
2044  case Hexagon::STrid_indexed_shl_V4:
2045    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
2046                              Hexagon::STrid_indexed_shl_cNotPt_V4;
2047  // Load.
2048  case Hexagon::LDrid:
2049    return !invertPredicate ? Hexagon::LDrid_cPt :
2050                              Hexagon::LDrid_cNotPt;
2051  case Hexagon::LDriw:
2052    return !invertPredicate ? Hexagon::LDriw_cPt :
2053                              Hexagon::LDriw_cNotPt;
2054  case Hexagon::LDrih:
2055    return !invertPredicate ? Hexagon::LDrih_cPt :
2056                              Hexagon::LDrih_cNotPt;
2057  case Hexagon::LDriuh:
2058    return !invertPredicate ? Hexagon::LDriuh_cPt :
2059                              Hexagon::LDriuh_cNotPt;
2060  case Hexagon::LDrib:
2061    return !invertPredicate ? Hexagon::LDrib_cPt :
2062                              Hexagon::LDrib_cNotPt;
2063  case Hexagon::LDriub:
2064    return !invertPredicate ? Hexagon::LDriub_cPt :
2065                              Hexagon::LDriub_cNotPt;
2066  case Hexagon::LDriubit:
2067    return !invertPredicate ? Hexagon::LDriub_cPt :
2068                              Hexagon::LDriub_cNotPt;
2069 // Load Indexed.
2070  case Hexagon::LDrid_indexed:
2071    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
2072                              Hexagon::LDrid_indexed_cNotPt;
2073  case Hexagon::LDriw_indexed:
2074    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
2075                              Hexagon::LDriw_indexed_cNotPt;
2076  case Hexagon::LDrih_indexed:
2077    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
2078                              Hexagon::LDrih_indexed_cNotPt;
2079  case Hexagon::LDriuh_indexed:
2080    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
2081                              Hexagon::LDriuh_indexed_cNotPt;
2082  case Hexagon::LDrib_indexed:
2083    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
2084                              Hexagon::LDrib_indexed_cNotPt;
2085  case Hexagon::LDriub_indexed:
2086    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
2087                              Hexagon::LDriub_indexed_cNotPt;
2088  // Post Increment Load.
2089  case Hexagon::POST_LDrid:
2090    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
2091                              Hexagon::POST_LDrid_cNotPt;
2092  case Hexagon::POST_LDriw:
2093    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
2094                              Hexagon::POST_LDriw_cNotPt;
2095  case Hexagon::POST_LDrih:
2096    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
2097                              Hexagon::POST_LDrih_cNotPt;
2098  case Hexagon::POST_LDriuh:
2099    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
2100                              Hexagon::POST_LDriuh_cNotPt;
2101  case Hexagon::POST_LDrib:
2102    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
2103                              Hexagon::POST_LDrib_cNotPt;
2104  case Hexagon::POST_LDriub:
2105    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
2106                              Hexagon::POST_LDriub_cNotPt;
2107  // DEALLOC_RETURN.
2108  case Hexagon::DEALLOC_RET_V4:
2109    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
2110                              Hexagon::DEALLOC_RET_cNotPt_V4;
2111  }
2112  llvm_unreachable("Unexpected predicable instruction");
2113}
2114
2115
2116bool HexagonInstrInfo::
2117PredicateInstruction(MachineInstr *MI,
2118                     const SmallVectorImpl<MachineOperand> &Cond) const {
2119  int Opc = MI->getOpcode();
2120  assert (isPredicable(MI) && "Expected predicable instruction");
2121  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
2122                     (Cond[0].getImm() == 0));
2123  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
2124  //
2125  // This assumes that the predicate is always the first operand
2126  // in the set of inputs.
2127  //
2128  MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
2129  int oper;
2130  for (oper = MI->getNumOperands() - 3; oper >= 0; --oper) {
2131    MachineOperand MO = MI->getOperand(oper);
2132    if ((MO.isReg() && !MO.isUse() && !MO.isImplicit())) {
2133      break;
2134    }
2135
2136    if (MO.isReg()) {
2137      MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
2138                                              MO.isImplicit(), MO.isKill(),
2139                                              MO.isDead(), MO.isUndef(),
2140                                              MO.isDebug());
2141    } else if (MO.isImm()) {
2142      MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
2143    } else {
2144      llvm_unreachable("Unexpected operand type");
2145    }
2146  }
2147
2148  int regPos = invertJump ? 1 : 0;
2149  MachineOperand PredMO = Cond[regPos];
2150  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
2151                                          PredMO.isImplicit(), PredMO.isKill(),
2152                                          PredMO.isDead(), PredMO.isUndef(),
2153                                          PredMO.isDebug());
2154
2155  return true;
2156}
2157
2158
2159bool
2160HexagonInstrInfo::
2161isProfitableToIfCvt(MachineBasicBlock &MBB,
2162                    unsigned NumCyles,
2163                    unsigned ExtraPredCycles,
2164                    const BranchProbability &Probability) const {
2165  return true;
2166}
2167
2168
2169bool
2170HexagonInstrInfo::
2171isProfitableToIfCvt(MachineBasicBlock &TMBB,
2172                    unsigned NumTCycles,
2173                    unsigned ExtraTCycles,
2174                    MachineBasicBlock &FMBB,
2175                    unsigned NumFCycles,
2176                    unsigned ExtraFCycles,
2177                    const BranchProbability &Probability) const {
2178  return true;
2179}
2180
2181
2182bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
2183  const uint64_t F = MI->getDesc().TSFlags;
2184
2185  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2186}
2187
2188
2189bool
2190HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
2191                                   std::vector<MachineOperand> &Pred) const {
2192  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
2193    MachineOperand MO = MI->getOperand(oper);
2194    if (MO.isReg() && MO.isDef()) {
2195      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
2196      if (RC == Hexagon::PredRegsRegisterClass) {
2197        Pred.push_back(MO);
2198        return true;
2199      }
2200    }
2201  }
2202  return false;
2203}
2204
2205
2206bool
2207HexagonInstrInfo::
2208SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
2209                  const SmallVectorImpl<MachineOperand> &Pred2) const {
2210  // TODO: Fix this
2211  return false;
2212}
2213
2214
2215//
2216// We indicate that we want to reverse the branch by
2217// inserting a 0 at the beginning of the Cond vector.
2218//
2219bool HexagonInstrInfo::
2220ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2221  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
2222    Cond.erase(Cond.begin());
2223  } else {
2224    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
2225  }
2226  return false;
2227}
2228
2229
2230bool HexagonInstrInfo::
2231isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
2232                          const BranchProbability &Probability) const {
2233  return (NumInstrs <= 4);
2234}
2235
2236bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
2237  switch (MI->getOpcode()) {
2238  case Hexagon::DEALLOC_RET_V4 :
2239  case Hexagon::DEALLOC_RET_cPt_V4 :
2240  case Hexagon::DEALLOC_RET_cNotPt_V4 :
2241  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
2242  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
2243  case Hexagon::DEALLOC_RET_cdnPt_V4 :
2244  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
2245   return true;
2246  }
2247  return false;
2248}
2249
2250
2251bool HexagonInstrInfo::
2252isValidOffset(const int Opcode, const int Offset) const {
2253  // This function is to check whether the "Offset" is in the correct range of
2254  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
2255  // inserted to calculate the final address. Due to this reason, the function
2256  // assumes that the "Offset" has correct alignment.
2257
2258  switch(Opcode) {
2259
2260  case Hexagon::LDriw:
2261  case Hexagon::STriw:
2262    assert((Offset % 4 == 0) && "Offset has incorrect alignment");
2263    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2264      (Offset <= Hexagon_MEMW_OFFSET_MAX);
2265
2266  case Hexagon::LDrid:
2267  case Hexagon::STrid:
2268    assert((Offset % 8 == 0) && "Offset has incorrect alignment");
2269    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2270      (Offset <= Hexagon_MEMD_OFFSET_MAX);
2271
2272  case Hexagon::LDrih:
2273  case Hexagon::LDriuh:
2274  case Hexagon::STrih:
2275  case Hexagon::LDrih_ae:
2276    assert((Offset % 2 == 0) && "Offset has incorrect alignment");
2277    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2278      (Offset <= Hexagon_MEMH_OFFSET_MAX);
2279
2280  case Hexagon::LDrib:
2281  case Hexagon::STrib:
2282  case Hexagon::LDriub:
2283  case Hexagon::LDriubit:
2284  case Hexagon::LDrib_ae:
2285  case Hexagon::LDriub_ae:
2286    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2287      (Offset <= Hexagon_MEMB_OFFSET_MAX);
2288
2289  case Hexagon::ADD_ri:
2290  case Hexagon::TFR_FI:
2291    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2292      (Offset <= Hexagon_ADDI_OFFSET_MAX);
2293
2294  case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2295  case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2296  case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2297  case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2298  case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2299  case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2300  case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2301  case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2302  case Hexagon::MEMw_ADDi_MEM_V4 :
2303  case Hexagon::MEMw_SUBi_MEM_V4 :
2304  case Hexagon::MEMw_ADDr_MEM_V4 :
2305  case Hexagon::MEMw_SUBr_MEM_V4 :
2306  case Hexagon::MEMw_ANDr_MEM_V4 :
2307  case Hexagon::MEMw_ORr_MEM_V4 :
2308    assert ((Offset % 4) == 0 && "MEMOPw offset is not aligned correctly." );
2309    return (0 <= Offset && Offset <= 255);
2310
2311  case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2312  case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2313  case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2314  case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2315  case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2316  case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2317  case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2318  case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2319  case Hexagon::MEMh_ADDi_MEM_V4 :
2320  case Hexagon::MEMh_SUBi_MEM_V4 :
2321  case Hexagon::MEMh_ADDr_MEM_V4 :
2322  case Hexagon::MEMh_SUBr_MEM_V4 :
2323  case Hexagon::MEMh_ANDr_MEM_V4 :
2324  case Hexagon::MEMh_ORr_MEM_V4 :
2325    assert ((Offset % 2) == 0 && "MEMOPh offset is not aligned correctly." );
2326    return (0 <= Offset && Offset <= 127);
2327
2328  case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2329  case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2330  case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2331  case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2332  case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2333  case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2334  case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2335  case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2336  case Hexagon::MEMb_ADDi_MEM_V4 :
2337  case Hexagon::MEMb_SUBi_MEM_V4 :
2338  case Hexagon::MEMb_ADDr_MEM_V4 :
2339  case Hexagon::MEMb_SUBr_MEM_V4 :
2340  case Hexagon::MEMb_ANDr_MEM_V4 :
2341  case Hexagon::MEMb_ORr_MEM_V4 :
2342    return (0 <= Offset && Offset <= 63);
2343
2344  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2345  // any size. Later pass knows how to handle it.
2346  case Hexagon::STriw_pred:
2347  case Hexagon::LDriw_pred:
2348    return true;
2349
2350  // INLINEASM is very special.
2351  case Hexagon::INLINEASM:
2352    return true;
2353  }
2354
2355  llvm_unreachable("No offset range is defined for this opcode. "
2356                   "Please define it in the above switch statement!");
2357}
2358
2359
2360//
2361// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2362//
2363bool HexagonInstrInfo::
2364isValidAutoIncImm(const EVT VT, const int Offset) const {
2365
2366  if (VT == MVT::i64) {
2367      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2368              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2369              (Offset & 0x7) == 0);
2370  }
2371  if (VT == MVT::i32) {
2372      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2373              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2374              (Offset & 0x3) == 0);
2375  }
2376  if (VT == MVT::i16) {
2377      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2378              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2379              (Offset & 0x1) == 0);
2380  }
2381  if (VT == MVT::i8) {
2382      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2383              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2384  }
2385  llvm_unreachable("Not an auto-inc opc!");
2386}
2387
2388
2389bool HexagonInstrInfo::
2390isMemOp(const MachineInstr *MI) const {
2391  switch (MI->getOpcode())
2392  {
2393    case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 :
2394    case Hexagon::MEMw_ADDi_indexed_MEM_V4 :
2395    case Hexagon::MEMw_SUBi_indexed_MEM_V4 :
2396    case Hexagon::MEMw_ADDr_indexed_MEM_V4 :
2397    case Hexagon::MEMw_SUBr_indexed_MEM_V4 :
2398    case Hexagon::MEMw_ANDr_indexed_MEM_V4 :
2399    case Hexagon::MEMw_ORr_indexed_MEM_V4 :
2400    case Hexagon::MEMw_ADDSUBi_MEM_V4 :
2401    case Hexagon::MEMw_ADDi_MEM_V4 :
2402    case Hexagon::MEMw_SUBi_MEM_V4 :
2403    case Hexagon::MEMw_ADDr_MEM_V4 :
2404    case Hexagon::MEMw_SUBr_MEM_V4 :
2405    case Hexagon::MEMw_ANDr_MEM_V4 :
2406    case Hexagon::MEMw_ORr_MEM_V4 :
2407    case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 :
2408    case Hexagon::MEMh_ADDi_indexed_MEM_V4 :
2409    case Hexagon::MEMh_SUBi_indexed_MEM_V4 :
2410    case Hexagon::MEMh_ADDr_indexed_MEM_V4 :
2411    case Hexagon::MEMh_SUBr_indexed_MEM_V4 :
2412    case Hexagon::MEMh_ANDr_indexed_MEM_V4 :
2413    case Hexagon::MEMh_ORr_indexed_MEM_V4 :
2414    case Hexagon::MEMh_ADDSUBi_MEM_V4 :
2415    case Hexagon::MEMh_ADDi_MEM_V4 :
2416    case Hexagon::MEMh_SUBi_MEM_V4 :
2417    case Hexagon::MEMh_ADDr_MEM_V4 :
2418    case Hexagon::MEMh_SUBr_MEM_V4 :
2419    case Hexagon::MEMh_ANDr_MEM_V4 :
2420    case Hexagon::MEMh_ORr_MEM_V4 :
2421    case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 :
2422    case Hexagon::MEMb_ADDi_indexed_MEM_V4 :
2423    case Hexagon::MEMb_SUBi_indexed_MEM_V4 :
2424    case Hexagon::MEMb_ADDr_indexed_MEM_V4 :
2425    case Hexagon::MEMb_SUBr_indexed_MEM_V4 :
2426    case Hexagon::MEMb_ANDr_indexed_MEM_V4 :
2427    case Hexagon::MEMb_ORr_indexed_MEM_V4 :
2428    case Hexagon::MEMb_ADDSUBi_MEM_V4 :
2429    case Hexagon::MEMb_ADDi_MEM_V4 :
2430    case Hexagon::MEMb_SUBi_MEM_V4 :
2431    case Hexagon::MEMb_ADDr_MEM_V4 :
2432    case Hexagon::MEMb_SUBr_MEM_V4 :
2433    case Hexagon::MEMb_ANDr_MEM_V4 :
2434    case Hexagon::MEMb_ORr_MEM_V4 :
2435    return true;
2436  }
2437  return false;
2438}
2439
2440
2441bool HexagonInstrInfo::
2442isSpillPredRegOp(const MachineInstr *MI) const {
2443  switch (MI->getOpcode())
2444  {
2445    case Hexagon::STriw_pred :
2446    case Hexagon::LDriw_pred :
2447    return true;
2448  }
2449  return false;
2450}
2451
2452bool HexagonInstrInfo::
2453isConditionalTransfer (const MachineInstr *MI) const {
2454  switch (MI->getOpcode()) {
2455    case Hexagon::TFR_cPt:
2456    case Hexagon::TFR_cNotPt:
2457    case Hexagon::TFRI_cPt:
2458    case Hexagon::TFRI_cNotPt:
2459    case Hexagon::TFR_cdnPt:
2460    case Hexagon::TFR_cdnNotPt:
2461    case Hexagon::TFRI_cdnPt:
2462    case Hexagon::TFRI_cdnNotPt:
2463      return true;
2464
2465    default:
2466      return false;
2467  }
2468  return false;
2469}
2470
2471bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2472  const HexagonRegisterInfo& QRI = getRegisterInfo();
2473  switch (MI->getOpcode())
2474  {
2475    case Hexagon::ADD_ri_cPt:
2476    case Hexagon::ADD_ri_cNotPt:
2477    case Hexagon::ADD_rr_cPt:
2478    case Hexagon::ADD_rr_cNotPt:
2479    case Hexagon::XOR_rr_cPt:
2480    case Hexagon::XOR_rr_cNotPt:
2481    case Hexagon::AND_rr_cPt:
2482    case Hexagon::AND_rr_cNotPt:
2483    case Hexagon::OR_rr_cPt:
2484    case Hexagon::OR_rr_cNotPt:
2485    case Hexagon::SUB_rr_cPt:
2486    case Hexagon::SUB_rr_cNotPt:
2487    case Hexagon::COMBINE_rr_cPt:
2488    case Hexagon::COMBINE_rr_cNotPt:
2489      return true;
2490    case Hexagon::ASLH_cPt_V4:
2491    case Hexagon::ASLH_cNotPt_V4:
2492    case Hexagon::ASRH_cPt_V4:
2493    case Hexagon::ASRH_cNotPt_V4:
2494    case Hexagon::SXTB_cPt_V4:
2495    case Hexagon::SXTB_cNotPt_V4:
2496    case Hexagon::SXTH_cPt_V4:
2497    case Hexagon::SXTH_cNotPt_V4:
2498    case Hexagon::ZXTB_cPt_V4:
2499    case Hexagon::ZXTB_cNotPt_V4:
2500    case Hexagon::ZXTH_cPt_V4:
2501    case Hexagon::ZXTH_cNotPt_V4:
2502      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2503
2504    default:
2505      return false;
2506  }
2507}
2508
2509bool HexagonInstrInfo::
2510isConditionalLoad (const MachineInstr* MI) const {
2511  const HexagonRegisterInfo& QRI = getRegisterInfo();
2512  switch (MI->getOpcode())
2513  {
2514    case Hexagon::LDrid_cPt :
2515    case Hexagon::LDrid_cNotPt :
2516    case Hexagon::LDrid_indexed_cPt :
2517    case Hexagon::LDrid_indexed_cNotPt :
2518    case Hexagon::LDriw_cPt :
2519    case Hexagon::LDriw_cNotPt :
2520    case Hexagon::LDriw_indexed_cPt :
2521    case Hexagon::LDriw_indexed_cNotPt :
2522    case Hexagon::LDrih_cPt :
2523    case Hexagon::LDrih_cNotPt :
2524    case Hexagon::LDrih_indexed_cPt :
2525    case Hexagon::LDrih_indexed_cNotPt :
2526    case Hexagon::LDrib_cPt :
2527    case Hexagon::LDrib_cNotPt :
2528    case Hexagon::LDrib_indexed_cPt :
2529    case Hexagon::LDrib_indexed_cNotPt :
2530    case Hexagon::LDriuh_cPt :
2531    case Hexagon::LDriuh_cNotPt :
2532    case Hexagon::LDriuh_indexed_cPt :
2533    case Hexagon::LDriuh_indexed_cNotPt :
2534    case Hexagon::LDriub_cPt :
2535    case Hexagon::LDriub_cNotPt :
2536    case Hexagon::LDriub_indexed_cPt :
2537    case Hexagon::LDriub_indexed_cNotPt :
2538      return true;
2539    case Hexagon::POST_LDrid_cPt :
2540    case Hexagon::POST_LDrid_cNotPt :
2541    case Hexagon::POST_LDriw_cPt :
2542    case Hexagon::POST_LDriw_cNotPt :
2543    case Hexagon::POST_LDrih_cPt :
2544    case Hexagon::POST_LDrih_cNotPt :
2545    case Hexagon::POST_LDrib_cPt :
2546    case Hexagon::POST_LDrib_cNotPt :
2547    case Hexagon::POST_LDriuh_cPt :
2548    case Hexagon::POST_LDriuh_cNotPt :
2549    case Hexagon::POST_LDriub_cPt :
2550    case Hexagon::POST_LDriub_cNotPt :
2551      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2552    case Hexagon::LDrid_indexed_cPt_V4 :
2553    case Hexagon::LDrid_indexed_cNotPt_V4 :
2554    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2555    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2556    case Hexagon::LDrib_indexed_cPt_V4 :
2557    case Hexagon::LDrib_indexed_cNotPt_V4 :
2558    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2559    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2560    case Hexagon::LDriub_indexed_cPt_V4 :
2561    case Hexagon::LDriub_indexed_cNotPt_V4 :
2562    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2563    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2564    case Hexagon::LDrih_indexed_cPt_V4 :
2565    case Hexagon::LDrih_indexed_cNotPt_V4 :
2566    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2567    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2568    case Hexagon::LDriuh_indexed_cPt_V4 :
2569    case Hexagon::LDriuh_indexed_cNotPt_V4 :
2570    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2571    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2572    case Hexagon::LDriw_indexed_cPt_V4 :
2573    case Hexagon::LDriw_indexed_cNotPt_V4 :
2574    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2575    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2576      return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4;
2577    default:
2578      return false;
2579  }
2580}
2581
2582// Returns true if an instruction is a conditional store.
2583//
2584// Note: It doesn't include conditional new-value stores as they can't be
2585// converted to .new predicate.
2586//
2587//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2588//                ^           ^
2589//               /             \ (not OK. it will cause new-value store to be
2590//              /               X conditional on p0.new while R2 producer is
2591//             /                 \ on p0)
2592//            /                   \.
2593//     p.new store                 p.old NV store
2594// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2595//            ^                  ^
2596//             \                /
2597//              \              /
2598//               \            /
2599//                 p.old store
2600//             [if (p0)memw(R0+#0)=R2]
2601//
2602// The above diagram shows the steps involoved in the conversion of a predicated
2603// store instruction to its .new predicated new-value form.
2604//
2605// The following set of instructions further explains the scenario where
2606// conditional new-value store becomes invalid when promoted to .new predicate
2607// form.
2608//
2609// { 1) if (p0) r0 = add(r1, r2)
2610//   2) p0 = cmp.eq(r3, #0) }
2611//
2612//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2613// the first two instructions because in instr 1, r0 is conditional on old value
2614// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2615// is not valid for new-value stores.
2616bool HexagonInstrInfo::
2617isConditionalStore (const MachineInstr* MI) const {
2618  const HexagonRegisterInfo& QRI = getRegisterInfo();
2619  switch (MI->getOpcode())
2620  {
2621    case Hexagon::STrib_imm_cPt_V4 :
2622    case Hexagon::STrib_imm_cNotPt_V4 :
2623    case Hexagon::STrib_indexed_shl_cPt_V4 :
2624    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2625    case Hexagon::STrib_cPt :
2626    case Hexagon::STrib_cNotPt :
2627    case Hexagon::POST_STbri_cPt :
2628    case Hexagon::POST_STbri_cNotPt :
2629    case Hexagon::STrid_indexed_cPt :
2630    case Hexagon::STrid_indexed_cNotPt :
2631    case Hexagon::STrid_indexed_shl_cPt_V4 :
2632    case Hexagon::POST_STdri_cPt :
2633    case Hexagon::POST_STdri_cNotPt :
2634    case Hexagon::STrih_cPt :
2635    case Hexagon::STrih_cNotPt :
2636    case Hexagon::STrih_indexed_cPt :
2637    case Hexagon::STrih_indexed_cNotPt :
2638    case Hexagon::STrih_imm_cPt_V4 :
2639    case Hexagon::STrih_imm_cNotPt_V4 :
2640    case Hexagon::STrih_indexed_shl_cPt_V4 :
2641    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2642    case Hexagon::POST_SThri_cPt :
2643    case Hexagon::POST_SThri_cNotPt :
2644    case Hexagon::STriw_cPt :
2645    case Hexagon::STriw_cNotPt :
2646    case Hexagon::STriw_indexed_cPt :
2647    case Hexagon::STriw_indexed_cNotPt :
2648    case Hexagon::STriw_imm_cPt_V4 :
2649    case Hexagon::STriw_imm_cNotPt_V4 :
2650    case Hexagon::STriw_indexed_shl_cPt_V4 :
2651    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2652    case Hexagon::POST_STwri_cPt :
2653    case Hexagon::POST_STwri_cNotPt :
2654      return QRI.Subtarget.hasV4TOps();
2655
2656    // V4 global address store before promoting to dot new.
2657    case Hexagon::STrid_GP_cPt_V4 :
2658    case Hexagon::STrid_GP_cNotPt_V4 :
2659    case Hexagon::STrib_GP_cPt_V4 :
2660    case Hexagon::STrib_GP_cNotPt_V4 :
2661    case Hexagon::STrih_GP_cPt_V4 :
2662    case Hexagon::STrih_GP_cNotPt_V4 :
2663    case Hexagon::STriw_GP_cPt_V4 :
2664    case Hexagon::STriw_GP_cNotPt_V4 :
2665    case Hexagon::STd_GP_cPt_V4 :
2666    case Hexagon::STd_GP_cNotPt_V4 :
2667    case Hexagon::STb_GP_cPt_V4 :
2668    case Hexagon::STb_GP_cNotPt_V4 :
2669    case Hexagon::STh_GP_cPt_V4 :
2670    case Hexagon::STh_GP_cNotPt_V4 :
2671    case Hexagon::STw_GP_cPt_V4 :
2672    case Hexagon::STw_GP_cNotPt_V4 :
2673      return QRI.Subtarget.hasV4TOps();
2674
2675    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2676    // from the "Conditional Store" list. Because a predicated new value store
2677    // would NOT be promoted to a double dot new store. See diagram below:
2678    // This function returns yes for those stores that are predicated but not
2679    // yet promoted to predicate dot new instructions.
2680    //
2681    //                          +---------------------+
2682    //                    /-----| if (p0) memw(..)=r0 |---------\~
2683    //                   ||     +---------------------+         ||
2684    //          promote  ||       /\       /\                   ||  promote
2685    //                   ||      /||\     /||\                  ||
2686    //                  \||/    demote     ||                  \||/
2687    //                   \/       ||       ||                   \/
2688    //       +-------------------------+   ||   +-------------------------+
2689    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2690    //       +-------------------------+   ||   +-------------------------+
2691    //                        ||           ||         ||
2692    //                        ||         demote      \||/
2693    //                      promote        ||         \/ NOT possible
2694    //                        ||           ||         /\~
2695    //                       \||/          ||        /||\~
2696    //                        \/           ||         ||
2697    //                      +-----------------------------+
2698    //                      | if (p0.new) memw(..)=r0.new |
2699    //                      +-----------------------------+
2700    //                           Double Dot New Store
2701    //
2702
2703    default:
2704      return false;
2705
2706  }
2707  return false;
2708}
2709
2710
2711
2712DFAPacketizer *HexagonInstrInfo::
2713CreateTargetScheduleState(const TargetMachine *TM,
2714                           const ScheduleDAG *DAG) const {
2715  const InstrItineraryData *II = TM->getInstrItineraryData();
2716  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2717}
2718
2719bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2720                                            const MachineBasicBlock *MBB,
2721                                            const MachineFunction &MF) const {
2722  // Debug info is never a scheduling boundary. It's necessary to be explicit
2723  // due to the special treatment of IT instructions below, otherwise a
2724  // dbg_value followed by an IT will result in the IT instruction being
2725  // considered a scheduling hazard, which is wrong. It should be the actual
2726  // instruction preceding the dbg_value instruction(s), just like it is
2727  // when debug info is not present.
2728  if (MI->isDebugValue())
2729    return false;
2730
2731  // Terminators and labels can't be scheduled around.
2732  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2733    return true;
2734
2735  return false;
2736}
2737