HexagonInstrInfo.cpp revision f9759c9f08af056ca6a496d846dd06656b6f1d9b 
1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "Hexagon.h"
16#include "HexagonRegisterInfo.h"
17#include "HexagonSubtarget.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#define GET_INSTRMAP_INFO
29#include "HexagonGenInstrInfo.inc"
30#include "HexagonGenDFAPacketizer.inc"
31
32using namespace llvm;
33
34///
35/// Constants for Hexagon instructions.
36///
37const int Hexagon_MEMW_OFFSET_MAX = 4095;
38const int Hexagon_MEMW_OFFSET_MIN = -4096;
39const int Hexagon_MEMD_OFFSET_MAX = 8191;
40const int Hexagon_MEMD_OFFSET_MIN = -8192;
41const int Hexagon_MEMH_OFFSET_MAX = 2047;
42const int Hexagon_MEMH_OFFSET_MIN = -2048;
43const int Hexagon_MEMB_OFFSET_MAX = 1023;
44const int Hexagon_MEMB_OFFSET_MIN = -1024;
45const int Hexagon_ADDI_OFFSET_MAX = 32767;
46const int Hexagon_ADDI_OFFSET_MIN = -32768;
47const int Hexagon_MEMD_AUTOINC_MAX = 56;
48const int Hexagon_MEMD_AUTOINC_MIN = -64;
49const int Hexagon_MEMW_AUTOINC_MAX = 28;
50const int Hexagon_MEMW_AUTOINC_MIN = -32;
51const int Hexagon_MEMH_AUTOINC_MAX = 14;
52const int Hexagon_MEMH_AUTOINC_MIN = -16;
53const int Hexagon_MEMB_AUTOINC_MAX = 7;
54const int Hexagon_MEMB_AUTOINC_MIN = -8;
55
56
57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59    RI(ST, *this), Subtarget(ST) {
60}
61
62
63/// isLoadFromStackSlot - If the specified machine instruction is a direct
64/// load from a stack slot, return the virtual or physical register number of
65/// the destination along with the FrameIndex of the loaded stack slot.  If
66/// not, return 0.  This predicate must return 0 if the instruction has
67/// any side effects other than loading from the stack slot.
68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69                                             int &FrameIndex) const {
70
71
72  switch (MI->getOpcode()) {
73  default: break;
74  case Hexagon::LDriw:
75  case Hexagon::LDrid:
76  case Hexagon::LDrih:
77  case Hexagon::LDrib:
78  case Hexagon::LDriub:
79    if (MI->getOperand(2).isFI() &&
80        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81      FrameIndex = MI->getOperand(2).getIndex();
82      return MI->getOperand(0).getReg();
83    }
84    break;
85  }
86  return 0;
87}
88
89
90/// isStoreToStackSlot - If the specified machine instruction is a direct
91/// store to a stack slot, return the virtual or physical register number of
92/// the source reg along with the FrameIndex of the loaded stack slot.  If
93/// not, return 0.  This predicate must return 0 if the instruction has
94/// any side effects other than storing to the stack slot.
95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96                                            int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case Hexagon::STriw:
100  case Hexagon::STrid:
101  case Hexagon::STrih:
102  case Hexagon::STrib:
103    if (MI->getOperand(2).isFI() &&
104        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105      FrameIndex = MI->getOperand(0).getIndex();
106      return MI->getOperand(2).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113
114unsigned
115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
116                             MachineBasicBlock *FBB,
117                             const SmallVectorImpl<MachineOperand> &Cond,
118                             DebugLoc DL) const{
119
120    int BOpc   = Hexagon::JMP;
121    int BccOpc = Hexagon::JMP_c;
122
123    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
124
125    int regPos = 0;
126    // Check if ReverseBranchCondition has asked to reverse this branch
127    // If we want to reverse the branch an odd number of times, we want
128    // JMP_cNot.
129    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
130      BccOpc = Hexagon::JMP_cNot;
131      regPos = 1;
132    }
133
134    if (FBB == 0) {
135      if (Cond.empty()) {
136        // Due to a bug in TailMerging/CFG Optimization, we need to add a
137        // special case handling of a predicated jump followed by an
138        // unconditional jump. If not, Tail Merging and CFG Optimization go
139        // into an infinite loop.
140        MachineBasicBlock *NewTBB, *NewFBB;
141        SmallVector<MachineOperand, 4> Cond;
142        MachineInstr *Term = MBB.getFirstTerminator();
143        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
144                                                 false)) {
145          MachineBasicBlock *NextBB =
146            llvm::next(MachineFunction::iterator(&MBB));
147          if (NewTBB == NextBB) {
148            ReverseBranchCondition(Cond);
149            RemoveBranch(MBB);
150            return InsertBranch(MBB, TBB, 0, Cond, DL);
151          }
152        }
153        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
154      } else {
155        BuildMI(&MBB, DL,
156                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
157      }
158      return 1;
159    }
160
161    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
163
164    return 2;
165}
166
167
168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
169                                     MachineBasicBlock *&TBB,
170                                 MachineBasicBlock *&FBB,
171                                 SmallVectorImpl<MachineOperand> &Cond,
172                                 bool AllowModify) const {
173  TBB = NULL;
174  FBB = NULL;
175
176  // If the block has no terminators, it just falls into the block after it.
177  MachineBasicBlock::iterator I = MBB.end();
178  if (I == MBB.begin())
179    return false;
180
181  // A basic block may looks like this:
182  //
183  //  [   insn
184  //     EH_LABEL
185  //      insn
186  //      insn
187  //      insn
188  //     EH_LABEL
189  //      insn     ]
190  //
191  // It has two succs but does not have a terminator
192  // Don't know how to handle it.
193  do {
194    --I;
195    if (I->isEHLabel())
196      return true;
197  } while (I != MBB.begin());
198
199  I = MBB.end();
200  --I;
201
202  while (I->isDebugValue()) {
203    if (I == MBB.begin())
204      return false;
205    --I;
206  }
207  if (!isUnpredicatedTerminator(I))
208    return false;
209
210  // Get the last instruction in the block.
211  MachineInstr *LastInst = I;
212
213  // If there is only one terminator instruction, process it.
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215    if (LastInst->getOpcode() == Hexagon::JMP) {
216      TBB = LastInst->getOperand(0).getMBB();
217      return false;
218    }
219    if (LastInst->getOpcode() == Hexagon::JMP_c) {
220      // Block ends with fall-through true condbranch.
221      TBB = LastInst->getOperand(1).getMBB();
222      Cond.push_back(LastInst->getOperand(0));
223      return false;
224    }
225    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
226      // Block ends with fall-through false condbranch.
227      TBB = LastInst->getOperand(1).getMBB();
228      Cond.push_back(MachineOperand::CreateImm(0));
229      Cond.push_back(LastInst->getOperand(0));
230      return false;
231    }
232    // Otherwise, don't know what this is.
233    return true;
234  }
235
236  // Get the instruction before it if it's a terminator.
237  MachineInstr *SecondLastInst = I;
238
239  // If there are three terminators, we don't know what sort of block this is.
240  if (SecondLastInst && I != MBB.begin() &&
241      isUnpredicatedTerminator(--I))
242    return true;
243
244  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
245  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247      LastInst->getOpcode() == Hexagon::JMP) {
248    TBB =  SecondLastInst->getOperand(1).getMBB();
249    Cond.push_back(SecondLastInst->getOperand(0));
250    FBB = LastInst->getOperand(0).getMBB();
251    return false;
252  }
253
254  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
255  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256      LastInst->getOpcode() == Hexagon::JMP) {
257    TBB =  SecondLastInst->getOperand(1).getMBB();
258    Cond.push_back(MachineOperand::CreateImm(0));
259    Cond.push_back(SecondLastInst->getOperand(0));
260    FBB = LastInst->getOperand(0).getMBB();
261    return false;
262  }
263
264  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
265  // executed, so remove it.
266  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267      LastInst->getOpcode() == Hexagon::JMP) {
268    TBB = SecondLastInst->getOperand(0).getMBB();
269    I = LastInst;
270    if (AllowModify)
271      I->eraseFromParent();
272    return false;
273  }
274
275  // Otherwise, can't handle this.
276  return true;
277}
278
279
280unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281  int BOpc   = Hexagon::JMP;
282  int BccOpc = Hexagon::JMP_c;
283  int BccOpcNot = Hexagon::JMP_cNot;
284
285  MachineBasicBlock::iterator I = MBB.end();
286  if (I == MBB.begin()) return 0;
287  --I;
288  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289      I->getOpcode() != BccOpcNot)
290    return 0;
291
292  // Remove the branch.
293  I->eraseFromParent();
294
295  I = MBB.end();
296
297  if (I == MBB.begin()) return 1;
298  --I;
299  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
300    return 1;
301
302  // Remove the branch.
303  I->eraseFromParent();
304  return 2;
305}
306
307
308/// \brief For a comparison instruction, return the source registers in
309/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
310/// compares against in CmpValue. Return true if the comparison instruction
311/// can be analyzed.
312bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
313                                      unsigned &SrcReg, unsigned &SrcReg2,
314                                      int &Mask, int &Value) const {
315  unsigned Opc = MI->getOpcode();
316
317  // Set mask and the first source register.
318  switch (Opc) {
319    case Hexagon::CMPEHexagon4rr:
320    case Hexagon::CMPEQri:
321    case Hexagon::CMPEQrr:
322    case Hexagon::CMPGT64rr:
323    case Hexagon::CMPGTU64rr:
324    case Hexagon::CMPGTUri:
325    case Hexagon::CMPGTUrr:
326    case Hexagon::CMPGTri:
327    case Hexagon::CMPGTrr:
328      SrcReg = MI->getOperand(1).getReg();
329      Mask = ~0;
330      break;
331    case Hexagon::CMPbEQri_V4:
332    case Hexagon::CMPbEQrr_sbsb_V4:
333    case Hexagon::CMPbEQrr_ubub_V4:
334    case Hexagon::CMPbGTUri_V4:
335    case Hexagon::CMPbGTUrr_V4:
336    case Hexagon::CMPbGTrr_V4:
337      SrcReg = MI->getOperand(1).getReg();
338      Mask = 0xFF;
339      break;
340    case Hexagon::CMPhEQri_V4:
341    case Hexagon::CMPhEQrr_shl_V4:
342    case Hexagon::CMPhEQrr_xor_V4:
343    case Hexagon::CMPhGTUri_V4:
344    case Hexagon::CMPhGTUrr_V4:
345    case Hexagon::CMPhGTrr_shl_V4:
346      SrcReg = MI->getOperand(1).getReg();
347      Mask = 0xFFFF;
348      break;
349  }
350
351  // Set the value/second source register.
352  switch (Opc) {
353    case Hexagon::CMPEHexagon4rr:
354    case Hexagon::CMPEQrr:
355    case Hexagon::CMPGT64rr:
356    case Hexagon::CMPGTU64rr:
357    case Hexagon::CMPGTUrr:
358    case Hexagon::CMPGTrr:
359    case Hexagon::CMPbEQrr_sbsb_V4:
360    case Hexagon::CMPbEQrr_ubub_V4:
361    case Hexagon::CMPbGTUrr_V4:
362    case Hexagon::CMPbGTrr_V4:
363    case Hexagon::CMPhEQrr_shl_V4:
364    case Hexagon::CMPhEQrr_xor_V4:
365    case Hexagon::CMPhGTUrr_V4:
366    case Hexagon::CMPhGTrr_shl_V4:
367      SrcReg2 = MI->getOperand(2).getReg();
368      return true;
369
370    case Hexagon::CMPEQri:
371    case Hexagon::CMPGTUri:
372    case Hexagon::CMPGTri:
373    case Hexagon::CMPbEQri_V4:
374    case Hexagon::CMPbGTUri_V4:
375    case Hexagon::CMPhEQri_V4:
376    case Hexagon::CMPhGTUri_V4:
377      SrcReg2 = 0;
378      Value = MI->getOperand(2).getImm();
379      return true;
380  }
381
382  return false;
383}
384
385
386void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
387                                 MachineBasicBlock::iterator I, DebugLoc DL,
388                                 unsigned DestReg, unsigned SrcReg,
389                                 bool KillSrc) const {
390  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
391    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
392    return;
393  }
394  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
395    BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
396    return;
397  }
398  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
399    // Map Pd = Ps to Pd = or(Ps, Ps).
400    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
401            DestReg).addReg(SrcReg).addReg(SrcReg);
402    return;
403  }
404  if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
405      Hexagon::IntRegsRegClass.contains(SrcReg)) {
406    // We can have an overlap between single and double reg: r1:0 = r0.
407    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
408        // r1:0 = r0
409        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
410                Hexagon::subreg_hireg))).addImm(0);
411    } else {
412        // r1:0 = r1 or no overlap.
413        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
414                Hexagon::subreg_loreg))).addReg(SrcReg);
415        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
416                Hexagon::subreg_hireg))).addImm(0);
417    }
418    return;
419  }
420  if (Hexagon::CRRegsRegClass.contains(DestReg) &&
421      Hexagon::IntRegsRegClass.contains(SrcReg)) {
422    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
423    return;
424  }
425  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
426      Hexagon::IntRegsRegClass.contains(DestReg)) {
427    BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
428      addReg(SrcReg, getKillRegState(KillSrc));
429    return;
430  }
431  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
432      Hexagon::PredRegsRegClass.contains(DestReg)) {
433    BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
434      addReg(SrcReg, getKillRegState(KillSrc));
435    return;
436  }
437
438  llvm_unreachable("Unimplemented");
439}
440
441
442void HexagonInstrInfo::
443storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
444                    unsigned SrcReg, bool isKill, int FI,
445                    const TargetRegisterClass *RC,
446                    const TargetRegisterInfo *TRI) const {
447
448  DebugLoc DL = MBB.findDebugLoc(I);
449  MachineFunction &MF = *MBB.getParent();
450  MachineFrameInfo &MFI = *MF.getFrameInfo();
451  unsigned Align = MFI.getObjectAlignment(FI);
452
453  MachineMemOperand *MMO =
454      MF.getMachineMemOperand(
455                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
456                      MachineMemOperand::MOStore,
457                      MFI.getObjectSize(FI),
458                      Align);
459
460  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
461    BuildMI(MBB, I, DL, get(Hexagon::STriw))
462          .addFrameIndex(FI).addImm(0)
463          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
464  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
465    BuildMI(MBB, I, DL, get(Hexagon::STrid))
466          .addFrameIndex(FI).addImm(0)
467          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
468  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
469    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
470          .addFrameIndex(FI).addImm(0)
471          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
472  } else {
473    llvm_unreachable("Unimplemented");
474  }
475}
476
477
478void HexagonInstrInfo::storeRegToAddr(
479                                 MachineFunction &MF, unsigned SrcReg,
480                                 bool isKill,
481                                 SmallVectorImpl<MachineOperand> &Addr,
482                                 const TargetRegisterClass *RC,
483                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
484{
485  llvm_unreachable("Unimplemented");
486}
487
488
489void HexagonInstrInfo::
490loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
491                     unsigned DestReg, int FI,
492                     const TargetRegisterClass *RC,
493                     const TargetRegisterInfo *TRI) const {
494  DebugLoc DL = MBB.findDebugLoc(I);
495  MachineFunction &MF = *MBB.getParent();
496  MachineFrameInfo &MFI = *MF.getFrameInfo();
497  unsigned Align = MFI.getObjectAlignment(FI);
498
499  MachineMemOperand *MMO =
500      MF.getMachineMemOperand(
501                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
502                      MachineMemOperand::MOLoad,
503                      MFI.getObjectSize(FI),
504                      Align);
505  if (RC == &Hexagon::IntRegsRegClass) {
506    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
507          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
508  } else if (RC == &Hexagon::DoubleRegsRegClass) {
509    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
510          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
511  } else if (RC == &Hexagon::PredRegsRegClass) {
512    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
513          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
514  } else {
515    llvm_unreachable("Can't store this register to stack slot");
516  }
517}
518
519
520void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
521                                        SmallVectorImpl<MachineOperand> &Addr,
522                                        const TargetRegisterClass *RC,
523                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
524  llvm_unreachable("Unimplemented");
525}
526
527
528MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
529                                                    MachineInstr* MI,
530                                          const SmallVectorImpl<unsigned> &Ops,
531                                                    int FI) const {
532  // Hexagon_TODO: Implement.
533  return(0);
534}
535
536MachineInstr*
537HexagonInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
538                                           int FrameIx, uint64_t Offset,
539                                           const MDNode *MDPtr,
540                                           DebugLoc DL) const {
541  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Hexagon::DBG_VALUE))
542    .addImm(0).addImm(Offset).addMetadata(MDPtr);
543  return &*MIB;
544}
545
546unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
547
548  MachineRegisterInfo &RegInfo = MF->getRegInfo();
549  const TargetRegisterClass *TRC;
550  if (VT == MVT::i1) {
551    TRC = &Hexagon::PredRegsRegClass;
552  } else if (VT == MVT::i32 || VT == MVT::f32) {
553    TRC = &Hexagon::IntRegsRegClass;
554  } else if (VT == MVT::i64 || VT == MVT::f64) {
555    TRC = &Hexagon::DoubleRegsRegClass;
556  } else {
557    llvm_unreachable("Cannot handle this register class");
558  }
559
560  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
561  return NewReg;
562}
563
564bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
565  // Constant extenders are allowed only for V4 and above.
566  if (!Subtarget.hasV4TOps())
567    return false;
568
569  const MCInstrDesc &MID = MI->getDesc();
570  const uint64_t F = MID.TSFlags;
571  if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
572    return true;
573
574  // TODO: This is largely obsolete now. Will need to be removed
575  // in consecutive patches.
576  switch(MI->getOpcode()) {
577    // TFR_FI Remains a special case.
578    case Hexagon::TFR_FI:
579      return true;
580    default:
581      return false;
582  }
583  return  false;
584}
585
586// This returns true in two cases:
587// - The OP code itself indicates that this is an extended instruction.
588// - One of MOs has been marked with HMOTF_ConstExtended flag.
589bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
590  // First check if this is permanently extended op code.
591  const uint64_t F = MI->getDesc().TSFlags;
592  if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
593    return true;
594  // Use MO operand flags to determine if one of MI's operands
595  // has HMOTF_ConstExtended flag set.
596  for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
597       E = MI->operands_end(); I != E; ++I) {
598    if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
599      return true;
600  }
601  return  false;
602}
603
604bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
605  switch (MI->getOpcode()) {
606    default: return false;
607    // JMP_EQri
608    case Hexagon::JMP_EQriPt_nv_V4:
609    case Hexagon::JMP_EQriPnt_nv_V4:
610    case Hexagon::JMP_EQriNotPt_nv_V4:
611    case Hexagon::JMP_EQriNotPnt_nv_V4:
612    case Hexagon::JMP_EQriPt_ie_nv_V4:
613    case Hexagon::JMP_EQriPnt_ie_nv_V4:
614    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
615    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
616
617    // JMP_EQri - with -1
618    case Hexagon::JMP_EQriPtneg_nv_V4:
619    case Hexagon::JMP_EQriPntneg_nv_V4:
620    case Hexagon::JMP_EQriNotPtneg_nv_V4:
621    case Hexagon::JMP_EQriNotPntneg_nv_V4:
622    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
623    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
624    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
625    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
626
627    // JMP_EQrr
628    case Hexagon::JMP_EQrrPt_nv_V4:
629    case Hexagon::JMP_EQrrPnt_nv_V4:
630    case Hexagon::JMP_EQrrNotPt_nv_V4:
631    case Hexagon::JMP_EQrrNotPnt_nv_V4:
632    case Hexagon::JMP_EQrrPt_ie_nv_V4:
633    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
634    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
635    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
636
637    // JMP_GTri
638    case Hexagon::JMP_GTriPt_nv_V4:
639    case Hexagon::JMP_GTriPnt_nv_V4:
640    case Hexagon::JMP_GTriNotPt_nv_V4:
641    case Hexagon::JMP_GTriNotPnt_nv_V4:
642    case Hexagon::JMP_GTriPt_ie_nv_V4:
643    case Hexagon::JMP_GTriPnt_ie_nv_V4:
644    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
645    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
646
647    // JMP_GTri - with -1
648    case Hexagon::JMP_GTriPtneg_nv_V4:
649    case Hexagon::JMP_GTriPntneg_nv_V4:
650    case Hexagon::JMP_GTriNotPtneg_nv_V4:
651    case Hexagon::JMP_GTriNotPntneg_nv_V4:
652    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
653    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
654    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
655    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
656
657    // JMP_GTrr
658    case Hexagon::JMP_GTrrPt_nv_V4:
659    case Hexagon::JMP_GTrrPnt_nv_V4:
660    case Hexagon::JMP_GTrrNotPt_nv_V4:
661    case Hexagon::JMP_GTrrNotPnt_nv_V4:
662    case Hexagon::JMP_GTrrPt_ie_nv_V4:
663    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
664    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
665    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
666
667    // JMP_GTrrdn
668    case Hexagon::JMP_GTrrdnPt_nv_V4:
669    case Hexagon::JMP_GTrrdnPnt_nv_V4:
670    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
671    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
672    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
673    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
674    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
675    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
676
677    // JMP_GTUri
678    case Hexagon::JMP_GTUriPt_nv_V4:
679    case Hexagon::JMP_GTUriPnt_nv_V4:
680    case Hexagon::JMP_GTUriNotPt_nv_V4:
681    case Hexagon::JMP_GTUriNotPnt_nv_V4:
682    case Hexagon::JMP_GTUriPt_ie_nv_V4:
683    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
684    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
685    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
686
687    // JMP_GTUrr
688    case Hexagon::JMP_GTUrrPt_nv_V4:
689    case Hexagon::JMP_GTUrrPnt_nv_V4:
690    case Hexagon::JMP_GTUrrNotPt_nv_V4:
691    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
692    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
693    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
694    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
695    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
696
697    // JMP_GTUrrdn
698    case Hexagon::JMP_GTUrrdnPt_nv_V4:
699    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
700    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
701    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
702    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
703    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
704    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
705    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
706      return true;
707  }
708}
709
710bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
711  switch (MI->getOpcode()) {
712    default: return false;
713    // Store Byte
714    case Hexagon::STrib_nv_V4:
715    case Hexagon::STrib_indexed_nv_V4:
716    case Hexagon::STrib_indexed_shl_nv_V4:
717    case Hexagon::STrib_shl_nv_V4:
718    case Hexagon::STb_GP_nv_V4:
719    case Hexagon::POST_STbri_nv_V4:
720    case Hexagon::STrib_cPt_nv_V4:
721    case Hexagon::STrib_cdnPt_nv_V4:
722    case Hexagon::STrib_cNotPt_nv_V4:
723    case Hexagon::STrib_cdnNotPt_nv_V4:
724    case Hexagon::STrib_indexed_cPt_nv_V4:
725    case Hexagon::STrib_indexed_cdnPt_nv_V4:
726    case Hexagon::STrib_indexed_cNotPt_nv_V4:
727    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
728    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
729    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
730    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
731    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
732    case Hexagon::POST_STbri_cPt_nv_V4:
733    case Hexagon::POST_STbri_cdnPt_nv_V4:
734    case Hexagon::POST_STbri_cNotPt_nv_V4:
735    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
736    case Hexagon::STb_GP_cPt_nv_V4:
737    case Hexagon::STb_GP_cNotPt_nv_V4:
738    case Hexagon::STb_GP_cdnPt_nv_V4:
739    case Hexagon::STb_GP_cdnNotPt_nv_V4:
740    case Hexagon::STrib_abs_nv_V4:
741    case Hexagon::STrib_abs_cPt_nv_V4:
742    case Hexagon::STrib_abs_cdnPt_nv_V4:
743    case Hexagon::STrib_abs_cNotPt_nv_V4:
744    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
745
746    // Store Halfword
747    case Hexagon::STrih_nv_V4:
748    case Hexagon::STrih_indexed_nv_V4:
749    case Hexagon::STrih_indexed_shl_nv_V4:
750    case Hexagon::STrih_shl_nv_V4:
751    case Hexagon::STh_GP_nv_V4:
752    case Hexagon::POST_SThri_nv_V4:
753    case Hexagon::STrih_cPt_nv_V4:
754    case Hexagon::STrih_cdnPt_nv_V4:
755    case Hexagon::STrih_cNotPt_nv_V4:
756    case Hexagon::STrih_cdnNotPt_nv_V4:
757    case Hexagon::STrih_indexed_cPt_nv_V4:
758    case Hexagon::STrih_indexed_cdnPt_nv_V4:
759    case Hexagon::STrih_indexed_cNotPt_nv_V4:
760    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
761    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
762    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
763    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
764    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
765    case Hexagon::POST_SThri_cPt_nv_V4:
766    case Hexagon::POST_SThri_cdnPt_nv_V4:
767    case Hexagon::POST_SThri_cNotPt_nv_V4:
768    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
769    case Hexagon::STh_GP_cPt_nv_V4:
770    case Hexagon::STh_GP_cNotPt_nv_V4:
771    case Hexagon::STh_GP_cdnPt_nv_V4:
772    case Hexagon::STh_GP_cdnNotPt_nv_V4:
773    case Hexagon::STrih_abs_nv_V4:
774    case Hexagon::STrih_abs_cPt_nv_V4:
775    case Hexagon::STrih_abs_cdnPt_nv_V4:
776    case Hexagon::STrih_abs_cNotPt_nv_V4:
777    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
778
779    // Store Word
780    case Hexagon::STriw_nv_V4:
781    case Hexagon::STriw_indexed_nv_V4:
782    case Hexagon::STriw_indexed_shl_nv_V4:
783    case Hexagon::STriw_shl_nv_V4:
784    case Hexagon::STw_GP_nv_V4:
785    case Hexagon::POST_STwri_nv_V4:
786    case Hexagon::STriw_cPt_nv_V4:
787    case Hexagon::STriw_cdnPt_nv_V4:
788    case Hexagon::STriw_cNotPt_nv_V4:
789    case Hexagon::STriw_cdnNotPt_nv_V4:
790    case Hexagon::STriw_indexed_cPt_nv_V4:
791    case Hexagon::STriw_indexed_cdnPt_nv_V4:
792    case Hexagon::STriw_indexed_cNotPt_nv_V4:
793    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
794    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
795    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
796    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
797    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
798    case Hexagon::POST_STwri_cPt_nv_V4:
799    case Hexagon::POST_STwri_cdnPt_nv_V4:
800    case Hexagon::POST_STwri_cNotPt_nv_V4:
801    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
802    case Hexagon::STw_GP_cPt_nv_V4:
803    case Hexagon::STw_GP_cNotPt_nv_V4:
804    case Hexagon::STw_GP_cdnPt_nv_V4:
805    case Hexagon::STw_GP_cdnNotPt_nv_V4:
806    case Hexagon::STriw_abs_nv_V4:
807    case Hexagon::STriw_abs_cPt_nv_V4:
808    case Hexagon::STriw_abs_cdnPt_nv_V4:
809    case Hexagon::STriw_abs_cNotPt_nv_V4:
810    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
811      return true;
812  }
813}
814
815bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
816  switch (MI->getOpcode())
817  {
818    default: return false;
819    // Load Byte
820    case Hexagon::POST_LDrib:
821    case Hexagon::POST_LDrib_cPt:
822    case Hexagon::POST_LDrib_cNotPt:
823    case Hexagon::POST_LDrib_cdnPt_V4:
824    case Hexagon::POST_LDrib_cdnNotPt_V4:
825
826    // Load unsigned byte
827    case Hexagon::POST_LDriub:
828    case Hexagon::POST_LDriub_cPt:
829    case Hexagon::POST_LDriub_cNotPt:
830    case Hexagon::POST_LDriub_cdnPt_V4:
831    case Hexagon::POST_LDriub_cdnNotPt_V4:
832
833    // Load halfword
834    case Hexagon::POST_LDrih:
835    case Hexagon::POST_LDrih_cPt:
836    case Hexagon::POST_LDrih_cNotPt:
837    case Hexagon::POST_LDrih_cdnPt_V4:
838    case Hexagon::POST_LDrih_cdnNotPt_V4:
839
840    // Load unsigned halfword
841    case Hexagon::POST_LDriuh:
842    case Hexagon::POST_LDriuh_cPt:
843    case Hexagon::POST_LDriuh_cNotPt:
844    case Hexagon::POST_LDriuh_cdnPt_V4:
845    case Hexagon::POST_LDriuh_cdnNotPt_V4:
846
847    // Load word
848    case Hexagon::POST_LDriw:
849    case Hexagon::POST_LDriw_cPt:
850    case Hexagon::POST_LDriw_cNotPt:
851    case Hexagon::POST_LDriw_cdnPt_V4:
852    case Hexagon::POST_LDriw_cdnNotPt_V4:
853
854    // Load double word
855    case Hexagon::POST_LDrid:
856    case Hexagon::POST_LDrid_cPt:
857    case Hexagon::POST_LDrid_cNotPt:
858    case Hexagon::POST_LDrid_cdnPt_V4:
859    case Hexagon::POST_LDrid_cdnNotPt_V4:
860
861    // Store byte
862    case Hexagon::POST_STbri:
863    case Hexagon::POST_STbri_cPt:
864    case Hexagon::POST_STbri_cNotPt:
865    case Hexagon::POST_STbri_cdnPt_V4:
866    case Hexagon::POST_STbri_cdnNotPt_V4:
867
868    // Store halfword
869    case Hexagon::POST_SThri:
870    case Hexagon::POST_SThri_cPt:
871    case Hexagon::POST_SThri_cNotPt:
872    case Hexagon::POST_SThri_cdnPt_V4:
873    case Hexagon::POST_SThri_cdnNotPt_V4:
874
875    // Store word
876    case Hexagon::POST_STwri:
877    case Hexagon::POST_STwri_cPt:
878    case Hexagon::POST_STwri_cNotPt:
879    case Hexagon::POST_STwri_cdnPt_V4:
880    case Hexagon::POST_STwri_cdnNotPt_V4:
881
882    // Store double word
883    case Hexagon::POST_STdri:
884    case Hexagon::POST_STdri_cPt:
885    case Hexagon::POST_STdri_cNotPt:
886    case Hexagon::POST_STdri_cdnPt_V4:
887    case Hexagon::POST_STdri_cdnNotPt_V4:
888      return true;
889  }
890}
891
892bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
893  if (isNewValueJump(MI))
894    return true;
895
896  if (isNewValueStore(MI))
897    return true;
898
899  return false;
900}
901
902bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
903  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
904}
905
906bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
907  bool isPred = MI->getDesc().isPredicable();
908
909  if (!isPred)
910    return false;
911
912  const int Opc = MI->getOpcode();
913
914  switch(Opc) {
915  case Hexagon::TFRI:
916    return isInt<12>(MI->getOperand(1).getImm());
917
918  case Hexagon::STrid:
919  case Hexagon::STrid_indexed:
920    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
921
922  case Hexagon::STriw:
923  case Hexagon::STriw_indexed:
924  case Hexagon::STriw_nv_V4:
925    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
926
927  case Hexagon::STrih:
928  case Hexagon::STrih_indexed:
929  case Hexagon::STrih_nv_V4:
930    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
931
932  case Hexagon::STrib:
933  case Hexagon::STrib_indexed:
934  case Hexagon::STrib_nv_V4:
935    return isUInt<6>(MI->getOperand(1).getImm());
936
937  case Hexagon::LDrid:
938  case Hexagon::LDrid_indexed:
939    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
940
941  case Hexagon::LDriw:
942  case Hexagon::LDriw_indexed:
943    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
944
945  case Hexagon::LDrih:
946  case Hexagon::LDriuh:
947  case Hexagon::LDrih_indexed:
948  case Hexagon::LDriuh_indexed:
949    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
950
951  case Hexagon::LDrib:
952  case Hexagon::LDriub:
953  case Hexagon::LDrib_indexed:
954  case Hexagon::LDriub_indexed:
955    return isUInt<6>(MI->getOperand(2).getImm());
956
957  case Hexagon::POST_LDrid:
958    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
959
960  case Hexagon::POST_LDriw:
961    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
962
963  case Hexagon::POST_LDrih:
964  case Hexagon::POST_LDriuh:
965    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
966
967  case Hexagon::POST_LDrib:
968  case Hexagon::POST_LDriub:
969    return isInt<4>(MI->getOperand(3).getImm());
970
971  case Hexagon::STrib_imm_V4:
972  case Hexagon::STrih_imm_V4:
973  case Hexagon::STriw_imm_V4:
974    return (isUInt<6>(MI->getOperand(1).getImm()) &&
975            isInt<6>(MI->getOperand(2).getImm()));
976
977  case Hexagon::ADD_ri:
978    return isInt<8>(MI->getOperand(2).getImm());
979
980  case Hexagon::ASLH:
981  case Hexagon::ASRH:
982  case Hexagon::SXTB:
983  case Hexagon::SXTH:
984  case Hexagon::ZXTB:
985  case Hexagon::ZXTH:
986    return Subtarget.hasV4TOps();
987
988  case Hexagon::JMPR:
989    return false;
990  }
991
992  return true;
993}
994
995// This function performs the following inversiones:
996//
997//  cPt    ---> cNotPt
998//  cNotPt ---> cPt
999//
1000// however, these inversiones are NOT included:
1001//
1002//  cdnPt      -X-> cdnNotPt
1003//  cdnNotPt   -X-> cdnPt
1004//  cPt_nv     -X-> cNotPt_nv (new value stores)
1005//  cNotPt_nv  -X-> cPt_nv    (new value stores)
1006//
1007// because only the following transformations are allowed:
1008//
1009//  cNotPt  ---> cdnNotPt
1010//  cPt     ---> cdnPt
1011//  cNotPt  ---> cNotPt_nv
1012//  cPt     ---> cPt_nv
1013unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1014  switch(Opc) {
1015    default: llvm_unreachable("Unexpected predicated instruction");
1016    case Hexagon::TFR_cPt:
1017      return Hexagon::TFR_cNotPt;
1018    case Hexagon::TFR_cNotPt:
1019      return Hexagon::TFR_cPt;
1020
1021    case Hexagon::TFRI_cPt:
1022      return Hexagon::TFRI_cNotPt;
1023    case Hexagon::TFRI_cNotPt:
1024      return Hexagon::TFRI_cPt;
1025
1026    case Hexagon::JMP_c:
1027      return Hexagon::JMP_cNot;
1028    case Hexagon::JMP_cNot:
1029      return Hexagon::JMP_c;
1030
1031    case Hexagon::ADD_ri_cPt:
1032      return Hexagon::ADD_ri_cNotPt;
1033    case Hexagon::ADD_ri_cNotPt:
1034      return Hexagon::ADD_ri_cPt;
1035
1036    case Hexagon::ADD_rr_cPt:
1037      return Hexagon::ADD_rr_cNotPt;
1038    case Hexagon::ADD_rr_cNotPt:
1039      return Hexagon::ADD_rr_cPt;
1040
1041    case Hexagon::XOR_rr_cPt:
1042      return Hexagon::XOR_rr_cNotPt;
1043    case Hexagon::XOR_rr_cNotPt:
1044      return Hexagon::XOR_rr_cPt;
1045
1046    case Hexagon::AND_rr_cPt:
1047      return Hexagon::AND_rr_cNotPt;
1048    case Hexagon::AND_rr_cNotPt:
1049      return Hexagon::AND_rr_cPt;
1050
1051    case Hexagon::OR_rr_cPt:
1052      return Hexagon::OR_rr_cNotPt;
1053    case Hexagon::OR_rr_cNotPt:
1054      return Hexagon::OR_rr_cPt;
1055
1056    case Hexagon::SUB_rr_cPt:
1057      return Hexagon::SUB_rr_cNotPt;
1058    case Hexagon::SUB_rr_cNotPt:
1059      return Hexagon::SUB_rr_cPt;
1060
1061    case Hexagon::COMBINE_rr_cPt:
1062      return Hexagon::COMBINE_rr_cNotPt;
1063    case Hexagon::COMBINE_rr_cNotPt:
1064      return Hexagon::COMBINE_rr_cPt;
1065
1066    case Hexagon::ASLH_cPt_V4:
1067      return Hexagon::ASLH_cNotPt_V4;
1068    case Hexagon::ASLH_cNotPt_V4:
1069      return Hexagon::ASLH_cPt_V4;
1070
1071    case Hexagon::ASRH_cPt_V4:
1072      return Hexagon::ASRH_cNotPt_V4;
1073    case Hexagon::ASRH_cNotPt_V4:
1074      return Hexagon::ASRH_cPt_V4;
1075
1076    case Hexagon::SXTB_cPt_V4:
1077      return Hexagon::SXTB_cNotPt_V4;
1078    case Hexagon::SXTB_cNotPt_V4:
1079      return Hexagon::SXTB_cPt_V4;
1080
1081    case Hexagon::SXTH_cPt_V4:
1082      return Hexagon::SXTH_cNotPt_V4;
1083    case Hexagon::SXTH_cNotPt_V4:
1084      return Hexagon::SXTH_cPt_V4;
1085
1086    case Hexagon::ZXTB_cPt_V4:
1087      return Hexagon::ZXTB_cNotPt_V4;
1088    case Hexagon::ZXTB_cNotPt_V4:
1089      return Hexagon::ZXTB_cPt_V4;
1090
1091    case Hexagon::ZXTH_cPt_V4:
1092      return Hexagon::ZXTH_cNotPt_V4;
1093    case Hexagon::ZXTH_cNotPt_V4:
1094      return Hexagon::ZXTH_cPt_V4;
1095
1096
1097    case Hexagon::JMPR_cPt:
1098      return Hexagon::JMPR_cNotPt;
1099    case Hexagon::JMPR_cNotPt:
1100      return Hexagon::JMPR_cPt;
1101
1102  // V4 indexed+scaled load.
1103    case Hexagon::LDrid_indexed_shl_cPt_V4:
1104      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1105    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1106      return Hexagon::LDrid_indexed_shl_cPt_V4;
1107
1108    case Hexagon::LDrib_indexed_shl_cPt_V4:
1109      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1110    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1111      return Hexagon::LDrib_indexed_shl_cPt_V4;
1112
1113    case Hexagon::LDriub_indexed_shl_cPt_V4:
1114      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1115    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1116      return Hexagon::LDriub_indexed_shl_cPt_V4;
1117
1118    case Hexagon::LDrih_indexed_shl_cPt_V4:
1119      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1120    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1121      return Hexagon::LDrih_indexed_shl_cPt_V4;
1122
1123    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1124      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1125    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1126      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1127
1128    case Hexagon::LDriw_indexed_shl_cPt_V4:
1129      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1130    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1131      return Hexagon::LDriw_indexed_shl_cPt_V4;
1132
1133    // Byte.
1134    case Hexagon::POST_STbri_cPt:
1135      return Hexagon::POST_STbri_cNotPt;
1136    case Hexagon::POST_STbri_cNotPt:
1137      return Hexagon::POST_STbri_cPt;
1138
1139    case Hexagon::STrib_cPt:
1140      return Hexagon::STrib_cNotPt;
1141    case Hexagon::STrib_cNotPt:
1142      return Hexagon::STrib_cPt;
1143
1144    case Hexagon::STrib_indexed_cPt:
1145      return Hexagon::STrib_indexed_cNotPt;
1146    case Hexagon::STrib_indexed_cNotPt:
1147      return Hexagon::STrib_indexed_cPt;
1148
1149    case Hexagon::STrib_imm_cPt_V4:
1150      return Hexagon::STrib_imm_cNotPt_V4;
1151    case Hexagon::STrib_imm_cNotPt_V4:
1152      return Hexagon::STrib_imm_cPt_V4;
1153
1154    case Hexagon::STrib_indexed_shl_cPt_V4:
1155      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1156    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1157      return Hexagon::STrib_indexed_shl_cPt_V4;
1158
1159  // Halfword.
1160    case Hexagon::POST_SThri_cPt:
1161      return Hexagon::POST_SThri_cNotPt;
1162    case Hexagon::POST_SThri_cNotPt:
1163      return Hexagon::POST_SThri_cPt;
1164
1165    case Hexagon::STrih_cPt:
1166      return Hexagon::STrih_cNotPt;
1167    case Hexagon::STrih_cNotPt:
1168      return Hexagon::STrih_cPt;
1169
1170    case Hexagon::STrih_indexed_cPt:
1171      return Hexagon::STrih_indexed_cNotPt;
1172    case Hexagon::STrih_indexed_cNotPt:
1173      return Hexagon::STrih_indexed_cPt;
1174
1175    case Hexagon::STrih_imm_cPt_V4:
1176      return Hexagon::STrih_imm_cNotPt_V4;
1177    case Hexagon::STrih_imm_cNotPt_V4:
1178      return Hexagon::STrih_imm_cPt_V4;
1179
1180    case Hexagon::STrih_indexed_shl_cPt_V4:
1181      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1182    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1183      return Hexagon::STrih_indexed_shl_cPt_V4;
1184
1185  // Word.
1186    case Hexagon::POST_STwri_cPt:
1187      return Hexagon::POST_STwri_cNotPt;
1188    case Hexagon::POST_STwri_cNotPt:
1189      return Hexagon::POST_STwri_cPt;
1190
1191    case Hexagon::STriw_cPt:
1192      return Hexagon::STriw_cNotPt;
1193    case Hexagon::STriw_cNotPt:
1194      return Hexagon::STriw_cPt;
1195
1196    case Hexagon::STriw_indexed_cPt:
1197      return Hexagon::STriw_indexed_cNotPt;
1198    case Hexagon::STriw_indexed_cNotPt:
1199      return Hexagon::STriw_indexed_cPt;
1200
1201    case Hexagon::STriw_indexed_shl_cPt_V4:
1202      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1203    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1204      return Hexagon::STriw_indexed_shl_cPt_V4;
1205
1206    case Hexagon::STriw_imm_cPt_V4:
1207      return Hexagon::STriw_imm_cNotPt_V4;
1208    case Hexagon::STriw_imm_cNotPt_V4:
1209      return Hexagon::STriw_imm_cPt_V4;
1210
1211  // Double word.
1212    case Hexagon::POST_STdri_cPt:
1213      return Hexagon::POST_STdri_cNotPt;
1214    case Hexagon::POST_STdri_cNotPt:
1215      return Hexagon::POST_STdri_cPt;
1216
1217    case Hexagon::STrid_cPt:
1218      return Hexagon::STrid_cNotPt;
1219    case Hexagon::STrid_cNotPt:
1220      return Hexagon::STrid_cPt;
1221
1222    case Hexagon::STrid_indexed_cPt:
1223      return Hexagon::STrid_indexed_cNotPt;
1224    case Hexagon::STrid_indexed_cNotPt:
1225      return Hexagon::STrid_indexed_cPt;
1226
1227    case Hexagon::STrid_indexed_shl_cPt_V4:
1228      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1229    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1230      return Hexagon::STrid_indexed_shl_cPt_V4;
1231
1232    // V4 Store to global address.
1233    case Hexagon::STd_GP_cPt_V4:
1234      return Hexagon::STd_GP_cNotPt_V4;
1235    case Hexagon::STd_GP_cNotPt_V4:
1236      return Hexagon::STd_GP_cPt_V4;
1237
1238    case Hexagon::STb_GP_cPt_V4:
1239      return Hexagon::STb_GP_cNotPt_V4;
1240    case Hexagon::STb_GP_cNotPt_V4:
1241      return Hexagon::STb_GP_cPt_V4;
1242
1243    case Hexagon::STh_GP_cPt_V4:
1244      return Hexagon::STh_GP_cNotPt_V4;
1245    case Hexagon::STh_GP_cNotPt_V4:
1246      return Hexagon::STh_GP_cPt_V4;
1247
1248    case Hexagon::STw_GP_cPt_V4:
1249      return Hexagon::STw_GP_cNotPt_V4;
1250    case Hexagon::STw_GP_cNotPt_V4:
1251      return Hexagon::STw_GP_cPt_V4;
1252
1253  // Load.
1254    case Hexagon::LDrid_cPt:
1255      return Hexagon::LDrid_cNotPt;
1256    case Hexagon::LDrid_cNotPt:
1257      return Hexagon::LDrid_cPt;
1258
1259    case Hexagon::LDriw_cPt:
1260      return Hexagon::LDriw_cNotPt;
1261    case Hexagon::LDriw_cNotPt:
1262      return Hexagon::LDriw_cPt;
1263
1264    case Hexagon::LDrih_cPt:
1265      return Hexagon::LDrih_cNotPt;
1266    case Hexagon::LDrih_cNotPt:
1267      return Hexagon::LDrih_cPt;
1268
1269    case Hexagon::LDriuh_cPt:
1270      return Hexagon::LDriuh_cNotPt;
1271    case Hexagon::LDriuh_cNotPt:
1272      return Hexagon::LDriuh_cPt;
1273
1274    case Hexagon::LDrib_cPt:
1275      return Hexagon::LDrib_cNotPt;
1276    case Hexagon::LDrib_cNotPt:
1277      return Hexagon::LDrib_cPt;
1278
1279    case Hexagon::LDriub_cPt:
1280      return Hexagon::LDriub_cNotPt;
1281    case Hexagon::LDriub_cNotPt:
1282      return Hexagon::LDriub_cPt;
1283
1284 // Load Indexed.
1285    case Hexagon::LDrid_indexed_cPt:
1286      return Hexagon::LDrid_indexed_cNotPt;
1287    case Hexagon::LDrid_indexed_cNotPt:
1288      return Hexagon::LDrid_indexed_cPt;
1289
1290    case Hexagon::LDriw_indexed_cPt:
1291      return Hexagon::LDriw_indexed_cNotPt;
1292    case Hexagon::LDriw_indexed_cNotPt:
1293      return Hexagon::LDriw_indexed_cPt;
1294
1295    case Hexagon::LDrih_indexed_cPt:
1296      return Hexagon::LDrih_indexed_cNotPt;
1297    case Hexagon::LDrih_indexed_cNotPt:
1298      return Hexagon::LDrih_indexed_cPt;
1299
1300    case Hexagon::LDriuh_indexed_cPt:
1301      return Hexagon::LDriuh_indexed_cNotPt;
1302    case Hexagon::LDriuh_indexed_cNotPt:
1303      return Hexagon::LDriuh_indexed_cPt;
1304
1305    case Hexagon::LDrib_indexed_cPt:
1306      return Hexagon::LDrib_indexed_cNotPt;
1307    case Hexagon::LDrib_indexed_cNotPt:
1308      return Hexagon::LDrib_indexed_cPt;
1309
1310    case Hexagon::LDriub_indexed_cPt:
1311      return Hexagon::LDriub_indexed_cNotPt;
1312    case Hexagon::LDriub_indexed_cNotPt:
1313      return Hexagon::LDriub_indexed_cPt;
1314
1315  // Post Inc Load.
1316    case Hexagon::POST_LDrid_cPt:
1317      return Hexagon::POST_LDrid_cNotPt;
1318    case Hexagon::POST_LDriw_cNotPt:
1319      return Hexagon::POST_LDriw_cPt;
1320
1321    case Hexagon::POST_LDrih_cPt:
1322      return Hexagon::POST_LDrih_cNotPt;
1323    case Hexagon::POST_LDrih_cNotPt:
1324      return Hexagon::POST_LDrih_cPt;
1325
1326    case Hexagon::POST_LDriuh_cPt:
1327      return Hexagon::POST_LDriuh_cNotPt;
1328    case Hexagon::POST_LDriuh_cNotPt:
1329      return Hexagon::POST_LDriuh_cPt;
1330
1331    case Hexagon::POST_LDrib_cPt:
1332      return Hexagon::POST_LDrib_cNotPt;
1333    case Hexagon::POST_LDrib_cNotPt:
1334      return Hexagon::POST_LDrib_cPt;
1335
1336    case Hexagon::POST_LDriub_cPt:
1337      return Hexagon::POST_LDriub_cNotPt;
1338    case Hexagon::POST_LDriub_cNotPt:
1339      return Hexagon::POST_LDriub_cPt;
1340
1341  // Dealloc_return.
1342    case Hexagon::DEALLOC_RET_cPt_V4:
1343      return Hexagon::DEALLOC_RET_cNotPt_V4;
1344    case Hexagon::DEALLOC_RET_cNotPt_V4:
1345      return Hexagon::DEALLOC_RET_cPt_V4;
1346
1347   // New Value Jump.
1348   // JMPEQ_ri - with -1.
1349    case Hexagon::JMP_EQriPtneg_nv_V4:
1350      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1351    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1352      return Hexagon::JMP_EQriPtneg_nv_V4;
1353
1354    case Hexagon::JMP_EQriPntneg_nv_V4:
1355      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1356    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1357      return Hexagon::JMP_EQriPntneg_nv_V4;
1358
1359   // JMPEQ_ri.
1360     case Hexagon::JMP_EQriPt_nv_V4:
1361      return Hexagon::JMP_EQriNotPt_nv_V4;
1362    case Hexagon::JMP_EQriNotPt_nv_V4:
1363      return Hexagon::JMP_EQriPt_nv_V4;
1364
1365     case Hexagon::JMP_EQriPnt_nv_V4:
1366      return Hexagon::JMP_EQriNotPnt_nv_V4;
1367    case Hexagon::JMP_EQriNotPnt_nv_V4:
1368      return Hexagon::JMP_EQriPnt_nv_V4;
1369
1370   // JMPEQ_rr.
1371     case Hexagon::JMP_EQrrPt_nv_V4:
1372      return Hexagon::JMP_EQrrNotPt_nv_V4;
1373    case Hexagon::JMP_EQrrNotPt_nv_V4:
1374      return Hexagon::JMP_EQrrPt_nv_V4;
1375
1376     case Hexagon::JMP_EQrrPnt_nv_V4:
1377      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1378    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1379      return Hexagon::JMP_EQrrPnt_nv_V4;
1380
1381   // JMPGT_ri - with -1.
1382    case Hexagon::JMP_GTriPtneg_nv_V4:
1383      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1384    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1385      return Hexagon::JMP_GTriPtneg_nv_V4;
1386
1387    case Hexagon::JMP_GTriPntneg_nv_V4:
1388      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1389    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1390      return Hexagon::JMP_GTriPntneg_nv_V4;
1391
1392   // JMPGT_ri.
1393     case Hexagon::JMP_GTriPt_nv_V4:
1394      return Hexagon::JMP_GTriNotPt_nv_V4;
1395    case Hexagon::JMP_GTriNotPt_nv_V4:
1396      return Hexagon::JMP_GTriPt_nv_V4;
1397
1398     case Hexagon::JMP_GTriPnt_nv_V4:
1399      return Hexagon::JMP_GTriNotPnt_nv_V4;
1400    case Hexagon::JMP_GTriNotPnt_nv_V4:
1401      return Hexagon::JMP_GTriPnt_nv_V4;
1402
1403   // JMPGT_rr.
1404     case Hexagon::JMP_GTrrPt_nv_V4:
1405      return Hexagon::JMP_GTrrNotPt_nv_V4;
1406    case Hexagon::JMP_GTrrNotPt_nv_V4:
1407      return Hexagon::JMP_GTrrPt_nv_V4;
1408
1409     case Hexagon::JMP_GTrrPnt_nv_V4:
1410      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1411    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1412      return Hexagon::JMP_GTrrPnt_nv_V4;
1413
1414   // JMPGT_rrdn.
1415     case Hexagon::JMP_GTrrdnPt_nv_V4:
1416      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1417    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1418      return Hexagon::JMP_GTrrdnPt_nv_V4;
1419
1420     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1421      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1422    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1423      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1424
1425   // JMPGTU_ri.
1426     case Hexagon::JMP_GTUriPt_nv_V4:
1427      return Hexagon::JMP_GTUriNotPt_nv_V4;
1428    case Hexagon::JMP_GTUriNotPt_nv_V4:
1429      return Hexagon::JMP_GTUriPt_nv_V4;
1430
1431     case Hexagon::JMP_GTUriPnt_nv_V4:
1432      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1433    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1434      return Hexagon::JMP_GTUriPnt_nv_V4;
1435
1436   // JMPGTU_rr.
1437     case Hexagon::JMP_GTUrrPt_nv_V4:
1438      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1439    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1440      return Hexagon::JMP_GTUrrPt_nv_V4;
1441
1442     case Hexagon::JMP_GTUrrPnt_nv_V4:
1443      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1444    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1445      return Hexagon::JMP_GTUrrPnt_nv_V4;
1446
1447   // JMPGTU_rrdn.
1448     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1449      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1450    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1451      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1452
1453     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1454      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1455    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1456      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1457  }
1458}
1459
1460
1461int HexagonInstrInfo::
1462getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1463  enum Hexagon::PredSense inPredSense;
1464  inPredSense = invertPredicate ? Hexagon::PredSense_false :
1465                                  Hexagon::PredSense_true;
1466  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1467  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1468    return CondOpcode;
1469
1470  // This switch case will be removed once all the instructions have been
1471  // modified to use relation maps.
1472  switch(Opc) {
1473  case Hexagon::TFR:
1474    return !invertPredicate ? Hexagon::TFR_cPt :
1475                              Hexagon::TFR_cNotPt;
1476  case Hexagon::TFRI_f:
1477    return !invertPredicate ? Hexagon::TFRI_cPt_f :
1478                              Hexagon::TFRI_cNotPt_f;
1479  case Hexagon::TFRI:
1480    return !invertPredicate ? Hexagon::TFRI_cPt :
1481                              Hexagon::TFRI_cNotPt;
1482  case Hexagon::JMP:
1483    return !invertPredicate ? Hexagon::JMP_c :
1484                              Hexagon::JMP_cNot;
1485  case Hexagon::JMP_EQrrPt_nv_V4:
1486    return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1487                              Hexagon::JMP_EQrrNotPt_nv_V4;
1488  case Hexagon::JMP_EQriPt_nv_V4:
1489    return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1490                              Hexagon::JMP_EQriNotPt_nv_V4;
1491  case Hexagon::COMBINE_rr:
1492    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1493                              Hexagon::COMBINE_rr_cNotPt;
1494  case Hexagon::ASLH:
1495    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1496                              Hexagon::ASLH_cNotPt_V4;
1497  case Hexagon::ASRH:
1498    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1499                              Hexagon::ASRH_cNotPt_V4;
1500  case Hexagon::SXTB:
1501    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1502                              Hexagon::SXTB_cNotPt_V4;
1503  case Hexagon::SXTH:
1504    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1505                              Hexagon::SXTH_cNotPt_V4;
1506  case Hexagon::ZXTB:
1507    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1508                              Hexagon::ZXTB_cNotPt_V4;
1509  case Hexagon::ZXTH:
1510    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1511                              Hexagon::ZXTH_cNotPt_V4;
1512
1513  case Hexagon::JMPR:
1514    return !invertPredicate ? Hexagon::JMPR_cPt :
1515                              Hexagon::JMPR_cNotPt;
1516
1517  // V4 indexed+scaled load.
1518  case Hexagon::LDrid_indexed_shl_V4:
1519    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1520                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1521  case Hexagon::LDrib_indexed_shl_V4:
1522    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1523                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1524  case Hexagon::LDriub_indexed_shl_V4:
1525    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1526                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1527  case Hexagon::LDrih_indexed_shl_V4:
1528    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1529                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1530  case Hexagon::LDriuh_indexed_shl_V4:
1531    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1532                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1533  case Hexagon::LDriw_indexed_shl_V4:
1534    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1535                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1536
1537  // V4 Load from global address
1538  case Hexagon::LDd_GP_V4:
1539    return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
1540                              Hexagon::LDd_GP_cNotPt_V4;
1541  case Hexagon::LDb_GP_V4:
1542    return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
1543                              Hexagon::LDb_GP_cNotPt_V4;
1544  case Hexagon::LDub_GP_V4:
1545    return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
1546                              Hexagon::LDub_GP_cNotPt_V4;
1547  case Hexagon::LDh_GP_V4:
1548    return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
1549                              Hexagon::LDh_GP_cNotPt_V4;
1550  case Hexagon::LDuh_GP_V4:
1551    return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
1552                              Hexagon::LDuh_GP_cNotPt_V4;
1553  case Hexagon::LDw_GP_V4:
1554    return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
1555                              Hexagon::LDw_GP_cNotPt_V4;
1556
1557    // Byte.
1558  case Hexagon::POST_STbri:
1559    return !invertPredicate ? Hexagon::POST_STbri_cPt :
1560                              Hexagon::POST_STbri_cNotPt;
1561  case Hexagon::STrib:
1562    return !invertPredicate ? Hexagon::STrib_cPt :
1563                              Hexagon::STrib_cNotPt;
1564  case Hexagon::STrib_indexed:
1565    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1566                              Hexagon::STrib_indexed_cNotPt;
1567  case Hexagon::STrib_imm_V4:
1568    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1569                              Hexagon::STrib_imm_cNotPt_V4;
1570  case Hexagon::STrib_indexed_shl_V4:
1571    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1572                              Hexagon::STrib_indexed_shl_cNotPt_V4;
1573  // Halfword.
1574  case Hexagon::POST_SThri:
1575    return !invertPredicate ? Hexagon::POST_SThri_cPt :
1576                              Hexagon::POST_SThri_cNotPt;
1577  case Hexagon::STrih:
1578    return !invertPredicate ? Hexagon::STrih_cPt :
1579                              Hexagon::STrih_cNotPt;
1580  case Hexagon::STrih_indexed:
1581    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1582                              Hexagon::STrih_indexed_cNotPt;
1583  case Hexagon::STrih_imm_V4:
1584    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1585                              Hexagon::STrih_imm_cNotPt_V4;
1586  case Hexagon::STrih_indexed_shl_V4:
1587    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1588                              Hexagon::STrih_indexed_shl_cNotPt_V4;
1589  // Word.
1590  case Hexagon::POST_STwri:
1591    return !invertPredicate ? Hexagon::POST_STwri_cPt :
1592                              Hexagon::POST_STwri_cNotPt;
1593  case Hexagon::STriw:
1594    return !invertPredicate ? Hexagon::STriw_cPt :
1595                              Hexagon::STriw_cNotPt;
1596  case Hexagon::STriw_indexed:
1597    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1598                              Hexagon::STriw_indexed_cNotPt;
1599  case Hexagon::STriw_indexed_shl_V4:
1600    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1601                              Hexagon::STriw_indexed_shl_cNotPt_V4;
1602  case Hexagon::STriw_imm_V4:
1603    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1604                              Hexagon::STriw_imm_cNotPt_V4;
1605  // Double word.
1606  case Hexagon::POST_STdri:
1607    return !invertPredicate ? Hexagon::POST_STdri_cPt :
1608                              Hexagon::POST_STdri_cNotPt;
1609  case Hexagon::STrid:
1610    return !invertPredicate ? Hexagon::STrid_cPt :
1611                              Hexagon::STrid_cNotPt;
1612  case Hexagon::STrid_indexed:
1613    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1614                              Hexagon::STrid_indexed_cNotPt;
1615  case Hexagon::STrid_indexed_shl_V4:
1616    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1617                              Hexagon::STrid_indexed_shl_cNotPt_V4;
1618
1619  // V4 Store to global address
1620  case Hexagon::STd_GP_V4:
1621    return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
1622                              Hexagon::STd_GP_cNotPt_V4;
1623  case Hexagon::STb_GP_V4:
1624    return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
1625                              Hexagon::STb_GP_cNotPt_V4;
1626  case Hexagon::STh_GP_V4:
1627    return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
1628                              Hexagon::STh_GP_cNotPt_V4;
1629  case Hexagon::STw_GP_V4:
1630    return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
1631                              Hexagon::STw_GP_cNotPt_V4;
1632
1633  // Load.
1634  case Hexagon::LDrid:
1635    return !invertPredicate ? Hexagon::LDrid_cPt :
1636                              Hexagon::LDrid_cNotPt;
1637  case Hexagon::LDriw:
1638    return !invertPredicate ? Hexagon::LDriw_cPt :
1639                              Hexagon::LDriw_cNotPt;
1640  case Hexagon::LDrih:
1641    return !invertPredicate ? Hexagon::LDrih_cPt :
1642                              Hexagon::LDrih_cNotPt;
1643  case Hexagon::LDriuh:
1644    return !invertPredicate ? Hexagon::LDriuh_cPt :
1645                              Hexagon::LDriuh_cNotPt;
1646  case Hexagon::LDrib:
1647    return !invertPredicate ? Hexagon::LDrib_cPt :
1648                              Hexagon::LDrib_cNotPt;
1649  case Hexagon::LDriub:
1650    return !invertPredicate ? Hexagon::LDriub_cPt :
1651                              Hexagon::LDriub_cNotPt;
1652 // Load Indexed.
1653  case Hexagon::LDrid_indexed:
1654    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1655                              Hexagon::LDrid_indexed_cNotPt;
1656  case Hexagon::LDriw_indexed:
1657    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1658                              Hexagon::LDriw_indexed_cNotPt;
1659  case Hexagon::LDrih_indexed:
1660    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1661                              Hexagon::LDrih_indexed_cNotPt;
1662  case Hexagon::LDriuh_indexed:
1663    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1664                              Hexagon::LDriuh_indexed_cNotPt;
1665  case Hexagon::LDrib_indexed:
1666    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1667                              Hexagon::LDrib_indexed_cNotPt;
1668  case Hexagon::LDriub_indexed:
1669    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1670                              Hexagon::LDriub_indexed_cNotPt;
1671  // Post Increment Load.
1672  case Hexagon::POST_LDrid:
1673    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1674                              Hexagon::POST_LDrid_cNotPt;
1675  case Hexagon::POST_LDriw:
1676    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1677                              Hexagon::POST_LDriw_cNotPt;
1678  case Hexagon::POST_LDrih:
1679    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1680                              Hexagon::POST_LDrih_cNotPt;
1681  case Hexagon::POST_LDriuh:
1682    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1683                              Hexagon::POST_LDriuh_cNotPt;
1684  case Hexagon::POST_LDrib:
1685    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1686                              Hexagon::POST_LDrib_cNotPt;
1687  case Hexagon::POST_LDriub:
1688    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1689                              Hexagon::POST_LDriub_cNotPt;
1690  // DEALLOC_RETURN.
1691  case Hexagon::DEALLOC_RET_V4:
1692    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1693                              Hexagon::DEALLOC_RET_cNotPt_V4;
1694  }
1695  llvm_unreachable("Unexpected predicable instruction");
1696}
1697
1698
1699bool HexagonInstrInfo::
1700PredicateInstruction(MachineInstr *MI,
1701                     const SmallVectorImpl<MachineOperand> &Cond) const {
1702  int Opc = MI->getOpcode();
1703  assert (isPredicable(MI) && "Expected predicable instruction");
1704  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1705                     (Cond[0].getImm() == 0));
1706
1707  // This will change MI's opcode to its predicate version.
1708  // However, its operand list is still the old one, i.e. the
1709  // non-predicate one.
1710  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1711
1712  int oper = -1;
1713  unsigned int GAIdx = 0;
1714
1715  // Indicates whether the current MI has a GlobalAddress operand
1716  bool hasGAOpnd = false;
1717  std::vector<MachineOperand> tmpOpnds;
1718
1719  // Indicates whether we need to shift operands to right.
1720  bool needShift = true;
1721
1722  // The predicate is ALWAYS the FIRST input operand !!!
1723  if (MI->getNumOperands() == 0) {
1724    // The non-predicate version of MI does not take any operands,
1725    // i.e. no outs and no ins. In this condition, the predicate
1726    // operand will be directly placed at Operands[0]. No operand
1727    // shift is needed.
1728    // Example: BARRIER
1729    needShift = false;
1730    oper = -1;
1731  }
1732  else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
1733           && MI->getOperand(MI->getNumOperands()-1).isDef()
1734           && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
1735    // The non-predicate version of MI does not have any input operands.
1736    // In this condition, we extend the length of Operands[] by one and
1737    // copy the original last operand to the newly allocated slot.
1738    // At this moment, it is just a place holder. Later, we will put
1739    // predicate operand directly into it. No operand shift is needed.
1740    // Example: r0=BARRIER (this is a faked insn used here for illustration)
1741    MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1742    needShift = false;
1743    oper = MI->getNumOperands() - 2;
1744  }
1745  else {
1746    // We need to right shift all input operands by one. Duplicate the
1747    // last operand into the newly allocated slot.
1748    MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1749  }
1750
1751  if (needShift)
1752  {
1753    // Operands[ MI->getNumOperands() - 2 ] has been copied into
1754    // Operands[ MI->getNumOperands() - 1 ], so we start from
1755    // Operands[ MI->getNumOperands() - 3 ].
1756    // oper is a signed int.
1757    // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
1758    for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
1759    {
1760      MachineOperand &MO = MI->getOperand(oper);
1761
1762      // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
1763      // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
1764      //               /\~
1765      //              /||\~
1766      //               ||
1767      //        Predicate Operand here
1768      if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
1769        break;
1770      }
1771      if (MO.isReg()) {
1772        MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1773                                                MO.isImplicit(), MO.isKill(),
1774                                                MO.isDead(), MO.isUndef(),
1775                                                MO.isDebug());
1776      }
1777      else if (MO.isImm()) {
1778        MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1779      }
1780      else if (MO.isGlobal()) {
1781        // MI can not have more than one GlobalAddress operand.
1782        assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
1783
1784        // There is no member function called "ChangeToGlobalAddress" in the
1785        // MachineOperand class (not like "ChangeToRegister" and
1786        // "ChangeToImmediate"). So we have to remove them from Operands[] list
1787        // first, and then add them back after we have inserted the predicate
1788        // operand. tmpOpnds[] is to remember these operands before we remove
1789        // them.
1790        tmpOpnds.push_back(MO);
1791
1792        // Operands[oper] is a GlobalAddress operand;
1793        // Operands[oper+1] has been copied into Operands[oper+2];
1794        hasGAOpnd = true;
1795        GAIdx = oper;
1796        continue;
1797      }
1798      else {
1799        assert(false && "Unexpected operand type");
1800      }
1801    }
1802  }
1803
1804  int regPos = invertJump ? 1 : 0;
1805  MachineOperand PredMO = Cond[regPos];
1806
1807  // [oper] now points to the last explicit Def. Predicate operand must be
1808  // located at [oper+1]. See diagram above.
1809  // This assumes that the predicate is always the first operand,
1810  // i.e. Operands[0+numResults], in the set of inputs
1811  // It is better to have an assert here to check this. But I don't know how
1812  // to write this assert because findFirstPredOperandIdx() would return -1
1813  if (oper < -1) oper = -1;
1814
1815  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1816                                          PredMO.isImplicit(), false,
1817                                          PredMO.isDead(), PredMO.isUndef(),
1818                                          PredMO.isDebug());
1819
1820  MachineRegisterInfo &RegInfo = MI->getParent()->getParent()->getRegInfo();
1821  RegInfo.clearKillFlags(PredMO.getReg());
1822
1823  if (hasGAOpnd)
1824  {
1825    unsigned int i;
1826
1827    // Operands[GAIdx] is the original GlobalAddress operand, which is
1828    // already copied into tmpOpnds[0].
1829    // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1830    // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1831    // so we start from [GAIdx+2]
1832    for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1833      tmpOpnds.push_back(MI->getOperand(i));
1834
1835    // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1836    // It is very important that we always remove from the end of Operands[]
1837    // MI->getNumOperands() is at least 2 if program goes to here.
1838    for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1839      MI->RemoveOperand(i);
1840
1841    for (i = 0; i < tmpOpnds.size(); ++i)
1842      MI->addOperand(tmpOpnds[i]);
1843  }
1844
1845  return true;
1846}
1847
1848
1849bool
1850HexagonInstrInfo::
1851isProfitableToIfCvt(MachineBasicBlock &MBB,
1852                    unsigned NumCycles,
1853                    unsigned ExtraPredCycles,
1854                    const BranchProbability &Probability) const {
1855  return true;
1856}
1857
1858
1859bool
1860HexagonInstrInfo::
1861isProfitableToIfCvt(MachineBasicBlock &TMBB,
1862                    unsigned NumTCycles,
1863                    unsigned ExtraTCycles,
1864                    MachineBasicBlock &FMBB,
1865                    unsigned NumFCycles,
1866                    unsigned ExtraFCycles,
1867                    const BranchProbability &Probability) const {
1868  return true;
1869}
1870
1871
1872bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1873  const uint64_t F = MI->getDesc().TSFlags;
1874
1875  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1876}
1877
1878bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1879  const uint64_t F = MI->getDesc().TSFlags;
1880
1881  assert(isPredicated(MI));
1882  return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1883}
1884
1885bool
1886HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1887                                   std::vector<MachineOperand> &Pred) const {
1888  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1889    MachineOperand MO = MI->getOperand(oper);
1890    if (MO.isReg() && MO.isDef()) {
1891      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1892      if (RC == &Hexagon::PredRegsRegClass) {
1893        Pred.push_back(MO);
1894        return true;
1895      }
1896    }
1897  }
1898  return false;
1899}
1900
1901
1902bool
1903HexagonInstrInfo::
1904SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1905                  const SmallVectorImpl<MachineOperand> &Pred2) const {
1906  // TODO: Fix this
1907  return false;
1908}
1909
1910
1911//
1912// We indicate that we want to reverse the branch by
1913// inserting a 0 at the beginning of the Cond vector.
1914//
1915bool HexagonInstrInfo::
1916ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1917  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1918    Cond.erase(Cond.begin());
1919  } else {
1920    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1921  }
1922  return false;
1923}
1924
1925
1926bool HexagonInstrInfo::
1927isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1928                          const BranchProbability &Probability) const {
1929  return (NumInstrs <= 4);
1930}
1931
1932bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1933  switch (MI->getOpcode()) {
1934  default: return false;
1935  case Hexagon::DEALLOC_RET_V4 :
1936  case Hexagon::DEALLOC_RET_cPt_V4 :
1937  case Hexagon::DEALLOC_RET_cNotPt_V4 :
1938  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1939  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1940  case Hexagon::DEALLOC_RET_cdnPt_V4 :
1941  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1942   return true;
1943  }
1944}
1945
1946
1947bool HexagonInstrInfo::
1948isValidOffset(const int Opcode, const int Offset) const {
1949  // This function is to check whether the "Offset" is in the correct range of
1950  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1951  // inserted to calculate the final address. Due to this reason, the function
1952  // assumes that the "Offset" has correct alignment.
1953  // We used to assert if the offset was not properly aligned, however,
1954  // there are cases where a misaligned pointer recast can cause this
1955  // problem, and we need to allow for it. The front end warns of such
1956  // misaligns with respect to load size.
1957
1958  switch(Opcode) {
1959
1960  case Hexagon::LDriw:
1961  case Hexagon::LDriw_indexed:
1962  case Hexagon::LDriw_f:
1963  case Hexagon::STriw_indexed:
1964  case Hexagon::STriw:
1965  case Hexagon::STriw_f:
1966    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1967      (Offset <= Hexagon_MEMW_OFFSET_MAX);
1968
1969  case Hexagon::LDrid:
1970  case Hexagon::LDrid_indexed:
1971  case Hexagon::LDrid_f:
1972  case Hexagon::STrid:
1973  case Hexagon::STrid_indexed:
1974  case Hexagon::STrid_f:
1975    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1976      (Offset <= Hexagon_MEMD_OFFSET_MAX);
1977
1978  case Hexagon::LDrih:
1979  case Hexagon::LDriuh:
1980  case Hexagon::STrih:
1981    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1982      (Offset <= Hexagon_MEMH_OFFSET_MAX);
1983
1984  case Hexagon::LDrib:
1985  case Hexagon::STrib:
1986  case Hexagon::LDriub:
1987    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
1988      (Offset <= Hexagon_MEMB_OFFSET_MAX);
1989
1990  case Hexagon::ADD_ri:
1991  case Hexagon::TFR_FI:
1992    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
1993      (Offset <= Hexagon_ADDI_OFFSET_MAX);
1994
1995  case Hexagon::MemOPw_ADDi_V4 :
1996  case Hexagon::MemOPw_SUBi_V4 :
1997  case Hexagon::MemOPw_ADDr_V4 :
1998  case Hexagon::MemOPw_SUBr_V4 :
1999  case Hexagon::MemOPw_ANDr_V4 :
2000  case Hexagon::MemOPw_ORr_V4 :
2001    return (0 <= Offset && Offset <= 255);
2002
2003  case Hexagon::MemOPh_ADDi_V4 :
2004  case Hexagon::MemOPh_SUBi_V4 :
2005  case Hexagon::MemOPh_ADDr_V4 :
2006  case Hexagon::MemOPh_SUBr_V4 :
2007  case Hexagon::MemOPh_ANDr_V4 :
2008  case Hexagon::MemOPh_ORr_V4 :
2009    return (0 <= Offset && Offset <= 127);
2010
2011  case Hexagon::MemOPb_ADDi_V4 :
2012  case Hexagon::MemOPb_SUBi_V4 :
2013  case Hexagon::MemOPb_ADDr_V4 :
2014  case Hexagon::MemOPb_SUBr_V4 :
2015  case Hexagon::MemOPb_ANDr_V4 :
2016  case Hexagon::MemOPb_ORr_V4 :
2017    return (0 <= Offset && Offset <= 63);
2018
2019  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2020  // any size. Later pass knows how to handle it.
2021  case Hexagon::STriw_pred:
2022  case Hexagon::LDriw_pred:
2023    return true;
2024
2025  case Hexagon::LOOP0_i:
2026    return isUInt<10>(Offset);
2027
2028  // INLINEASM is very special.
2029  case Hexagon::INLINEASM:
2030    return true;
2031  }
2032
2033  llvm_unreachable("No offset range is defined for this opcode. "
2034                   "Please define it in the above switch statement!");
2035}
2036
2037
2038//
2039// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2040//
2041bool HexagonInstrInfo::
2042isValidAutoIncImm(const EVT VT, const int Offset) const {
2043
2044  if (VT == MVT::i64) {
2045      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2046              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2047              (Offset & 0x7) == 0);
2048  }
2049  if (VT == MVT::i32) {
2050      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2051              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2052              (Offset & 0x3) == 0);
2053  }
2054  if (VT == MVT::i16) {
2055      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2056              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2057              (Offset & 0x1) == 0);
2058  }
2059  if (VT == MVT::i8) {
2060      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2061              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2062  }
2063  llvm_unreachable("Not an auto-inc opc!");
2064}
2065
2066
2067bool HexagonInstrInfo::
2068isMemOp(const MachineInstr *MI) const {
2069  switch (MI->getOpcode())
2070  {
2071    default: return false;
2072    case Hexagon::MemOPw_ADDi_V4 :
2073    case Hexagon::MemOPw_SUBi_V4 :
2074    case Hexagon::MemOPw_ADDr_V4 :
2075    case Hexagon::MemOPw_SUBr_V4 :
2076    case Hexagon::MemOPw_ANDr_V4 :
2077    case Hexagon::MemOPw_ORr_V4 :
2078    case Hexagon::MemOPh_ADDi_V4 :
2079    case Hexagon::MemOPh_SUBi_V4 :
2080    case Hexagon::MemOPh_ADDr_V4 :
2081    case Hexagon::MemOPh_SUBr_V4 :
2082    case Hexagon::MemOPh_ANDr_V4 :
2083    case Hexagon::MemOPh_ORr_V4 :
2084    case Hexagon::MemOPb_ADDi_V4 :
2085    case Hexagon::MemOPb_SUBi_V4 :
2086    case Hexagon::MemOPb_ADDr_V4 :
2087    case Hexagon::MemOPb_SUBr_V4 :
2088    case Hexagon::MemOPb_ANDr_V4 :
2089    case Hexagon::MemOPb_ORr_V4 :
2090    case Hexagon::MemOPb_SETBITi_V4:
2091    case Hexagon::MemOPh_SETBITi_V4:
2092    case Hexagon::MemOPw_SETBITi_V4:
2093    case Hexagon::MemOPb_CLRBITi_V4:
2094    case Hexagon::MemOPh_CLRBITi_V4:
2095    case Hexagon::MemOPw_CLRBITi_V4:
2096    return true;
2097  }
2098  return false;
2099}
2100
2101
2102bool HexagonInstrInfo::
2103isSpillPredRegOp(const MachineInstr *MI) const {
2104  switch (MI->getOpcode()) {
2105    default: return false;
2106    case Hexagon::STriw_pred :
2107    case Hexagon::LDriw_pred :
2108      return true;
2109  }
2110}
2111
2112bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2113  switch (MI->getOpcode()) {
2114    default: return false;
2115    case Hexagon::CMPEQrr:
2116    case Hexagon::CMPEQri:
2117    case Hexagon::CMPGTrr:
2118    case Hexagon::CMPGTri:
2119    case Hexagon::CMPGTUrr:
2120    case Hexagon::CMPGTUri:
2121      return true;
2122  }
2123}
2124
2125bool HexagonInstrInfo::
2126isConditionalTransfer (const MachineInstr *MI) const {
2127  switch (MI->getOpcode()) {
2128    default: return false;
2129    case Hexagon::TFR_cPt:
2130    case Hexagon::TFR_cNotPt:
2131    case Hexagon::TFRI_cPt:
2132    case Hexagon::TFRI_cNotPt:
2133    case Hexagon::TFR_cdnPt:
2134    case Hexagon::TFR_cdnNotPt:
2135    case Hexagon::TFRI_cdnPt:
2136    case Hexagon::TFRI_cdnNotPt:
2137      return true;
2138  }
2139}
2140
2141bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2142  const HexagonRegisterInfo& QRI = getRegisterInfo();
2143  switch (MI->getOpcode())
2144  {
2145    default: return false;
2146    case Hexagon::ADD_ri_cPt:
2147    case Hexagon::ADD_ri_cNotPt:
2148    case Hexagon::ADD_rr_cPt:
2149    case Hexagon::ADD_rr_cNotPt:
2150    case Hexagon::XOR_rr_cPt:
2151    case Hexagon::XOR_rr_cNotPt:
2152    case Hexagon::AND_rr_cPt:
2153    case Hexagon::AND_rr_cNotPt:
2154    case Hexagon::OR_rr_cPt:
2155    case Hexagon::OR_rr_cNotPt:
2156    case Hexagon::SUB_rr_cPt:
2157    case Hexagon::SUB_rr_cNotPt:
2158    case Hexagon::COMBINE_rr_cPt:
2159    case Hexagon::COMBINE_rr_cNotPt:
2160      return true;
2161    case Hexagon::ASLH_cPt_V4:
2162    case Hexagon::ASLH_cNotPt_V4:
2163    case Hexagon::ASRH_cPt_V4:
2164    case Hexagon::ASRH_cNotPt_V4:
2165    case Hexagon::SXTB_cPt_V4:
2166    case Hexagon::SXTB_cNotPt_V4:
2167    case Hexagon::SXTH_cPt_V4:
2168    case Hexagon::SXTH_cNotPt_V4:
2169    case Hexagon::ZXTB_cPt_V4:
2170    case Hexagon::ZXTB_cNotPt_V4:
2171    case Hexagon::ZXTH_cPt_V4:
2172    case Hexagon::ZXTH_cNotPt_V4:
2173      return QRI.Subtarget.hasV4TOps();
2174  }
2175}
2176
2177bool HexagonInstrInfo::
2178isConditionalLoad (const MachineInstr* MI) const {
2179  const HexagonRegisterInfo& QRI = getRegisterInfo();
2180  switch (MI->getOpcode())
2181  {
2182    default: return false;
2183    case Hexagon::LDrid_cPt :
2184    case Hexagon::LDrid_cNotPt :
2185    case Hexagon::LDrid_indexed_cPt :
2186    case Hexagon::LDrid_indexed_cNotPt :
2187    case Hexagon::LDriw_cPt :
2188    case Hexagon::LDriw_cNotPt :
2189    case Hexagon::LDriw_indexed_cPt :
2190    case Hexagon::LDriw_indexed_cNotPt :
2191    case Hexagon::LDrih_cPt :
2192    case Hexagon::LDrih_cNotPt :
2193    case Hexagon::LDrih_indexed_cPt :
2194    case Hexagon::LDrih_indexed_cNotPt :
2195    case Hexagon::LDrib_cPt :
2196    case Hexagon::LDrib_cNotPt :
2197    case Hexagon::LDrib_indexed_cPt :
2198    case Hexagon::LDrib_indexed_cNotPt :
2199    case Hexagon::LDriuh_cPt :
2200    case Hexagon::LDriuh_cNotPt :
2201    case Hexagon::LDriuh_indexed_cPt :
2202    case Hexagon::LDriuh_indexed_cNotPt :
2203    case Hexagon::LDriub_cPt :
2204    case Hexagon::LDriub_cNotPt :
2205    case Hexagon::LDriub_indexed_cPt :
2206    case Hexagon::LDriub_indexed_cNotPt :
2207      return true;
2208    case Hexagon::POST_LDrid_cPt :
2209    case Hexagon::POST_LDrid_cNotPt :
2210    case Hexagon::POST_LDriw_cPt :
2211    case Hexagon::POST_LDriw_cNotPt :
2212    case Hexagon::POST_LDrih_cPt :
2213    case Hexagon::POST_LDrih_cNotPt :
2214    case Hexagon::POST_LDrib_cPt :
2215    case Hexagon::POST_LDrib_cNotPt :
2216    case Hexagon::POST_LDriuh_cPt :
2217    case Hexagon::POST_LDriuh_cNotPt :
2218    case Hexagon::POST_LDriub_cPt :
2219    case Hexagon::POST_LDriub_cNotPt :
2220      return QRI.Subtarget.hasV4TOps();
2221    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2222    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2223    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2224    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2225    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2226    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2227    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2228    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2229    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2230    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2231    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2232    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2233      return QRI.Subtarget.hasV4TOps();
2234  }
2235}
2236
2237// Returns true if an instruction is a conditional store.
2238//
2239// Note: It doesn't include conditional new-value stores as they can't be
2240// converted to .new predicate.
2241//
2242//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2243//                ^           ^
2244//               /             \ (not OK. it will cause new-value store to be
2245//              /               X conditional on p0.new while R2 producer is
2246//             /                 \ on p0)
2247//            /                   \.
2248//     p.new store                 p.old NV store
2249// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2250//            ^                  ^
2251//             \                /
2252//              \              /
2253//               \            /
2254//                 p.old store
2255//             [if (p0)memw(R0+#0)=R2]
2256//
2257// The above diagram shows the steps involoved in the conversion of a predicated
2258// store instruction to its .new predicated new-value form.
2259//
2260// The following set of instructions further explains the scenario where
2261// conditional new-value store becomes invalid when promoted to .new predicate
2262// form.
2263//
2264// { 1) if (p0) r0 = add(r1, r2)
2265//   2) p0 = cmp.eq(r3, #0) }
2266//
2267//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2268// the first two instructions because in instr 1, r0 is conditional on old value
2269// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2270// is not valid for new-value stores.
2271bool HexagonInstrInfo::
2272isConditionalStore (const MachineInstr* MI) const {
2273  const HexagonRegisterInfo& QRI = getRegisterInfo();
2274  switch (MI->getOpcode())
2275  {
2276    default: return false;
2277    case Hexagon::STrib_imm_cPt_V4 :
2278    case Hexagon::STrib_imm_cNotPt_V4 :
2279    case Hexagon::STrib_indexed_shl_cPt_V4 :
2280    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2281    case Hexagon::STrib_cPt :
2282    case Hexagon::STrib_cNotPt :
2283    case Hexagon::POST_STbri_cPt :
2284    case Hexagon::POST_STbri_cNotPt :
2285    case Hexagon::STrid_indexed_cPt :
2286    case Hexagon::STrid_indexed_cNotPt :
2287    case Hexagon::STrid_indexed_shl_cPt_V4 :
2288    case Hexagon::POST_STdri_cPt :
2289    case Hexagon::POST_STdri_cNotPt :
2290    case Hexagon::STrih_cPt :
2291    case Hexagon::STrih_cNotPt :
2292    case Hexagon::STrih_indexed_cPt :
2293    case Hexagon::STrih_indexed_cNotPt :
2294    case Hexagon::STrih_imm_cPt_V4 :
2295    case Hexagon::STrih_imm_cNotPt_V4 :
2296    case Hexagon::STrih_indexed_shl_cPt_V4 :
2297    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2298    case Hexagon::POST_SThri_cPt :
2299    case Hexagon::POST_SThri_cNotPt :
2300    case Hexagon::STriw_cPt :
2301    case Hexagon::STriw_cNotPt :
2302    case Hexagon::STriw_indexed_cPt :
2303    case Hexagon::STriw_indexed_cNotPt :
2304    case Hexagon::STriw_imm_cPt_V4 :
2305    case Hexagon::STriw_imm_cNotPt_V4 :
2306    case Hexagon::STriw_indexed_shl_cPt_V4 :
2307    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2308    case Hexagon::POST_STwri_cPt :
2309    case Hexagon::POST_STwri_cNotPt :
2310      return QRI.Subtarget.hasV4TOps();
2311
2312    // V4 global address store before promoting to dot new.
2313    case Hexagon::STd_GP_cPt_V4 :
2314    case Hexagon::STd_GP_cNotPt_V4 :
2315    case Hexagon::STb_GP_cPt_V4 :
2316    case Hexagon::STb_GP_cNotPt_V4 :
2317    case Hexagon::STh_GP_cPt_V4 :
2318    case Hexagon::STh_GP_cNotPt_V4 :
2319    case Hexagon::STw_GP_cPt_V4 :
2320    case Hexagon::STw_GP_cNotPt_V4 :
2321      return QRI.Subtarget.hasV4TOps();
2322
2323    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2324    // from the "Conditional Store" list. Because a predicated new value store
2325    // would NOT be promoted to a double dot new store. See diagram below:
2326    // This function returns yes for those stores that are predicated but not
2327    // yet promoted to predicate dot new instructions.
2328    //
2329    //                          +---------------------+
2330    //                    /-----| if (p0) memw(..)=r0 |---------\~
2331    //                   ||     +---------------------+         ||
2332    //          promote  ||       /\       /\                   ||  promote
2333    //                   ||      /||\     /||\                  ||
2334    //                  \||/    demote     ||                  \||/
2335    //                   \/       ||       ||                   \/
2336    //       +-------------------------+   ||   +-------------------------+
2337    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2338    //       +-------------------------+   ||   +-------------------------+
2339    //                        ||           ||         ||
2340    //                        ||         demote      \||/
2341    //                      promote        ||         \/ NOT possible
2342    //                        ||           ||         /\~
2343    //                       \||/          ||        /||\~
2344    //                        \/           ||         ||
2345    //                      +-----------------------------+
2346    //                      | if (p0.new) memw(..)=r0.new |
2347    //                      +-----------------------------+
2348    //                           Double Dot New Store
2349    //
2350  }
2351}
2352
2353// Returns true, if any one of the operands is a dot new
2354// insn, whether it is predicated dot new or register dot new.
2355bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
2356  return (isNewValueInst(MI) ||
2357     (isPredicated(MI) && isPredicatedNew(MI)));
2358}
2359
2360unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
2361  const uint64_t F = MI->getDesc().TSFlags;
2362
2363  return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
2364}
2365
2366/// immediateExtend - Changes the instruction in place to one using an immediate
2367/// extender.
2368void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
2369  assert((isExtendable(MI)||isConstExtended(MI)) &&
2370                               "Instruction must be extendable");
2371  // Find which operand is extendable.
2372  short ExtOpNum = getCExtOpNum(MI);
2373  MachineOperand &MO = MI->getOperand(ExtOpNum);
2374  // This needs to be something we understand.
2375  assert((MO.isMBB() || MO.isImm()) &&
2376         "Branch with unknown extendable field type");
2377  // Mark given operand as extended.
2378  MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
2379}
2380
2381DFAPacketizer *HexagonInstrInfo::
2382CreateTargetScheduleState(const TargetMachine *TM,
2383                           const ScheduleDAG *DAG) const {
2384  const InstrItineraryData *II = TM->getInstrItineraryData();
2385  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2386}
2387
2388bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2389                                            const MachineBasicBlock *MBB,
2390                                            const MachineFunction &MF) const {
2391  // Debug info is never a scheduling boundary. It's necessary to be explicit
2392  // due to the special treatment of IT instructions below, otherwise a
2393  // dbg_value followed by an IT will result in the IT instruction being
2394  // considered a scheduling hazard, which is wrong. It should be the actual
2395  // instruction preceding the dbg_value instruction(s), just like it is
2396  // when debug info is not present.
2397  if (MI->isDebugValue())
2398    return false;
2399
2400  // Terminators and labels can't be scheduled around.
2401  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2402    return true;
2403
2404  return false;
2405}
2406
2407bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
2408
2409  // Constant extenders are allowed only for V4 and above.
2410  if (!Subtarget.hasV4TOps())
2411    return false;
2412
2413  const uint64_t F = MI->getDesc().TSFlags;
2414  unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2415  if (isExtended) // Instruction must be extended.
2416    return true;
2417
2418  unsigned isExtendable = (F >> HexagonII::ExtendablePos)
2419                          & HexagonII::ExtendableMask;
2420  if (!isExtendable)
2421    return false;
2422
2423  short ExtOpNum = getCExtOpNum(MI);
2424  const MachineOperand &MO = MI->getOperand(ExtOpNum);
2425  // Use MO operand flags to determine if MO
2426  // has the HMOTF_ConstExtended flag set.
2427  if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2428    return true;
2429  // If this is a Machine BB address we are talking about, and it is
2430  // not marked as extended, say so.
2431  if (MO.isMBB())
2432    return false;
2433
2434  // We could be using an instruction with an extendable immediate and shoehorn
2435  // a global address into it. If it is a global address it will be constant
2436  // extended. We do this for COMBINE.
2437  // We currently only handle isGlobal() because it is the only kind of
2438  // object we are going to end up with here for now.
2439  // In the future we probably should add isSymbol(), etc.
2440  if (MO.isGlobal() || MO.isSymbol())
2441    return true;
2442
2443  // If the extendable operand is not 'Immediate' type, the instruction should
2444  // have 'isExtended' flag set.
2445  assert(MO.isImm() && "Extendable operand must be Immediate type");
2446
2447  int MinValue = getMinValue(MI);
2448  int MaxValue = getMaxValue(MI);
2449  int ImmValue = MO.getImm();
2450
2451  return (ImmValue < MinValue || ImmValue > MaxValue);
2452}
2453
2454// Returns true if a particular operand is extendable for an instruction.
2455bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2456                                         unsigned short OperandNum) const {
2457  // Constant extenders are allowed only for V4 and above.
2458  if (!Subtarget.hasV4TOps())
2459    return false;
2460
2461  const uint64_t F = MI->getDesc().TSFlags;
2462
2463  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2464          == OperandNum;
2465}
2466
2467// Returns Operand Index for the constant extended instruction.
2468unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
2469  const uint64_t F = MI->getDesc().TSFlags;
2470  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
2471}
2472
2473// Returns the min value that doesn't need to be extended.
2474int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
2475  const uint64_t F = MI->getDesc().TSFlags;
2476  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2477                    & HexagonII::ExtentSignedMask;
2478  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
2479                    & HexagonII::ExtentBitsMask;
2480
2481  if (isSigned) // if value is signed
2482    return -1 << (bits - 1);
2483  else
2484    return 0;
2485}
2486
2487// Returns the max value that doesn't need to be extended.
2488int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
2489  const uint64_t F = MI->getDesc().TSFlags;
2490  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2491                    & HexagonII::ExtentSignedMask;
2492  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
2493                    & HexagonII::ExtentBitsMask;
2494
2495  if (isSigned) // if value is signed
2496    return ~(-1 << (bits - 1));
2497  else
2498    return ~(-1 << bits);
2499}
2500
2501// Returns true if an instruction can be converted into a non-extended
2502// equivalent instruction.
2503bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
2504
2505  short NonExtOpcode;
2506  // Check if the instruction has a register form that uses register in place
2507  // of the extended operand, if so return that as the non-extended form.
2508  if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2509    return true;
2510
2511  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2512    // Check addressing mode and retreive non-ext equivalent instruction.
2513
2514    switch (getAddrMode(MI)) {
2515    case HexagonII::Absolute :
2516      // Load/store with absolute addressing mode can be converted into
2517      // base+offset mode.
2518      NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
2519      break;
2520    case HexagonII::BaseImmOffset :
2521      // Load/store with base+offset addressing mode can be converted into
2522      // base+register offset addressing mode. However left shift operand should
2523      // be set to 0.
2524      NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2525      break;
2526    default:
2527      return false;
2528    }
2529    if (NonExtOpcode < 0)
2530      return false;
2531    return true;
2532  }
2533  return false;
2534}
2535
2536// Returns opcode of the non-extended equivalent instruction.
2537short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
2538
2539  // Check if the instruction has a register form that uses register in place
2540  // of the extended operand, if so return that as the non-extended form.
2541  short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2542    if (NonExtOpcode >= 0)
2543      return NonExtOpcode;
2544
2545  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2546    // Check addressing mode and retreive non-ext equivalent instruction.
2547    switch (getAddrMode(MI)) {
2548    case HexagonII::Absolute :
2549      return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2550    case HexagonII::BaseImmOffset :
2551      return Hexagon::getBaseWithRegOffset(MI->getOpcode());
2552    default:
2553      return -1;
2554    }
2555  }
2556  return -1;
2557}
2558