1//===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass expands a branch or jump instruction into a long branch if its
11// offset is too large to fit into its immediate field.
12//
13// FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
14//===----------------------------------------------------------------------===//
15
16#include "Mips.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MCTargetDesc/MipsMCNaCl.h"
19#include "MipsMachineFunction.h"
20#include "MipsTargetMachine.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/MathExtras.h"
27#include "llvm/Target/TargetInstrInfo.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetRegisterInfo.h"
30
31using namespace llvm;
32
33#define DEBUG_TYPE "mips-long-branch"
34
35STATISTIC(LongBranches, "Number of long branches.");
36
37static cl::opt<bool> SkipLongBranch(
38  "skip-mips-long-branch",
39  cl::init(false),
40  cl::desc("MIPS: Skip long branch pass."),
41  cl::Hidden);
42
43static cl::opt<bool> ForceLongBranch(
44  "force-mips-long-branch",
45  cl::init(false),
46  cl::desc("MIPS: Expand all branches to long format."),
47  cl::Hidden);
48
49namespace {
50  typedef MachineBasicBlock::iterator Iter;
51  typedef MachineBasicBlock::reverse_iterator ReverseIter;
52
53  struct MBBInfo {
54    uint64_t Size, Address;
55    bool HasLongBranch;
56    MachineInstr *Br;
57
58    MBBInfo() : Size(0), HasLongBranch(false), Br(nullptr) {}
59  };
60
61  class MipsLongBranch : public MachineFunctionPass {
62
63  public:
64    static char ID;
65    MipsLongBranch(TargetMachine &tm)
66        : MachineFunctionPass(ID), TM(tm),
67          IsPIC(TM.getRelocationModel() == Reloc::PIC_),
68          ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
69
70    const char *getPassName() const override {
71      return "Mips Long Branch";
72    }
73
74    bool runOnMachineFunction(MachineFunction &F) override;
75
76  private:
77    void splitMBB(MachineBasicBlock *MBB);
78    void initMBBInfo();
79    int64_t computeOffset(const MachineInstr *Br);
80    void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
81                       MachineBasicBlock *MBBOpnd);
82    void expandToLongBranch(MBBInfo &Info);
83
84    const TargetMachine &TM;
85    MachineFunction *MF;
86    SmallVector<MBBInfo, 16> MBBInfos;
87    bool IsPIC;
88    MipsABIInfo ABI;
89    unsigned LongBranchSeqSize;
90  };
91
92  char MipsLongBranch::ID = 0;
93} // end of anonymous namespace
94
95/// createMipsLongBranchPass - Returns a pass that converts branches to long
96/// branches.
97FunctionPass *llvm::createMipsLongBranchPass(MipsTargetMachine &tm) {
98  return new MipsLongBranch(tm);
99}
100
101/// Iterate over list of Br's operands and search for a MachineBasicBlock
102/// operand.
103static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
104  for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
105    const MachineOperand &MO = Br.getOperand(I);
106
107    if (MO.isMBB())
108      return MO.getMBB();
109  }
110
111  llvm_unreachable("This instruction does not have an MBB operand.");
112}
113
114// Traverse the list of instructions backwards until a non-debug instruction is
115// found or it reaches E.
116static ReverseIter getNonDebugInstr(ReverseIter B, ReverseIter E) {
117  for (; B != E; ++B)
118    if (!B->isDebugValue())
119      return B;
120
121  return E;
122}
123
124// Split MBB if it has two direct jumps/branches.
125void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
126  ReverseIter End = MBB->rend();
127  ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
128
129  // Return if MBB has no branch instructions.
130  if ((LastBr == End) ||
131      (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
132    return;
133
134  ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
135
136  // MBB has only one branch instruction if FirstBr is not a branch
137  // instruction.
138  if ((FirstBr == End) ||
139      (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
140    return;
141
142  assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
143
144  // Create a new MBB. Move instructions in MBB to the newly created MBB.
145  MachineBasicBlock *NewMBB =
146    MF->CreateMachineBasicBlock(MBB->getBasicBlock());
147
148  // Insert NewMBB and fix control flow.
149  MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
150  NewMBB->transferSuccessors(MBB);
151  NewMBB->removeSuccessor(Tgt, true);
152  MBB->addSuccessor(NewMBB);
153  MBB->addSuccessor(Tgt);
154  MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
155
156  NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end());
157}
158
159// Fill MBBInfos.
160void MipsLongBranch::initMBBInfo() {
161  // Split the MBBs if they have two branches. Each basic block should have at
162  // most one branch after this loop is executed.
163  for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E;)
164    splitMBB(&*I++);
165
166  MF->RenumberBlocks();
167  MBBInfos.clear();
168  MBBInfos.resize(MF->size());
169
170  const MipsInstrInfo *TII =
171      static_cast<const MipsInstrInfo *>(MF->getSubtarget().getInstrInfo());
172  for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
173    MachineBasicBlock *MBB = MF->getBlockNumbered(I);
174
175    // Compute size of MBB.
176    for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
177         MI != MBB->instr_end(); ++MI)
178      MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
179
180    // Search for MBB's branch instruction.
181    ReverseIter End = MBB->rend();
182    ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
183
184    if ((Br != End) && !Br->isIndirectBranch() &&
185        (Br->isConditionalBranch() ||
186         (Br->isUnconditionalBranch() &&
187          TM.getRelocationModel() == Reloc::PIC_)))
188      MBBInfos[I].Br = (++Br).base();
189  }
190}
191
192// Compute offset of branch in number of bytes.
193int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
194  int64_t Offset = 0;
195  int ThisMBB = Br->getParent()->getNumber();
196  int TargetMBB = getTargetMBB(*Br)->getNumber();
197
198  // Compute offset of a forward branch.
199  if (ThisMBB < TargetMBB) {
200    for (int N = ThisMBB + 1; N < TargetMBB; ++N)
201      Offset += MBBInfos[N].Size;
202
203    return Offset + 4;
204  }
205
206  // Compute offset of a backward branch.
207  for (int N = ThisMBB; N >= TargetMBB; --N)
208    Offset += MBBInfos[N].Size;
209
210  return -Offset + 4;
211}
212
213// Replace Br with a branch which has the opposite condition code and a
214// MachineBasicBlock operand MBBOpnd.
215void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
216                                   DebugLoc DL, MachineBasicBlock *MBBOpnd) {
217  const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
218      MBB.getParent()->getSubtarget().getInstrInfo());
219  unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
220  const MCInstrDesc &NewDesc = TII->get(NewOpc);
221
222  MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
223
224  for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
225    MachineOperand &MO = Br->getOperand(I);
226
227    if (!MO.isReg()) {
228      assert(MO.isMBB() && "MBB operand expected.");
229      break;
230    }
231
232    MIB.addReg(MO.getReg());
233  }
234
235  MIB.addMBB(MBBOpnd);
236
237  if (Br->hasDelaySlot()) {
238    // Bundle the instruction in the delay slot to the newly created branch
239    // and erase the original branch.
240    assert(Br->isBundledWithSucc());
241    MachineBasicBlock::instr_iterator II(Br);
242    MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
243  }
244  Br->eraseFromParent();
245}
246
247// Expand branch instructions to long branches.
248// TODO: This function has to be fixed for beqz16 and bnez16, because it
249// currently assumes that all branches have 16-bit offsets, and will produce
250// wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
251// are present.
252void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
253  MachineBasicBlock::iterator Pos;
254  MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
255  DebugLoc DL = I.Br->getDebugLoc();
256  const BasicBlock *BB = MBB->getBasicBlock();
257  MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
258  MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
259  const MipsSubtarget &Subtarget =
260      static_cast<const MipsSubtarget &>(MF->getSubtarget());
261  const MipsInstrInfo *TII =
262      static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo());
263
264  MF->insert(FallThroughMBB, LongBrMBB);
265  MBB->replaceSuccessor(TgtMBB, LongBrMBB);
266
267  if (IsPIC) {
268    MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
269    MF->insert(FallThroughMBB, BalTgtMBB);
270    LongBrMBB->addSuccessor(BalTgtMBB);
271    BalTgtMBB->addSuccessor(TgtMBB);
272
273    // We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
274    // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
275    // pseudo-instruction wrapping BGEZAL).
276    unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
277
278    if (!ABI.IsN64()) {
279      // $longbr:
280      //  addiu $sp, $sp, -8
281      //  sw $ra, 0($sp)
282      //  lui $at, %hi($tgt - $baltgt)
283      //  bal $baltgt
284      //  addiu $at, $at, %lo($tgt - $baltgt)
285      // $baltgt:
286      //  addu $at, $ra, $at
287      //  lw $ra, 0($sp)
288      //  jr $at
289      //  addiu $sp, $sp, 8
290      // $fallthrough:
291      //
292
293      Pos = LongBrMBB->begin();
294
295      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
296        .addReg(Mips::SP).addImm(-8);
297      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
298        .addReg(Mips::SP).addImm(0);
299
300      // LUi and ADDiu instructions create 32-bit offset of the target basic
301      // block from the target of BAL instruction.  We cannot use immediate
302      // value for this offset because it cannot be determined accurately when
303      // the program has inline assembly statements.  We therefore use the
304      // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
305      // are resolved during the fixup, so the values will always be correct.
306      //
307      // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
308      // expressions at this point (it is possible only at the MC layer),
309      // we replace LUi and ADDiu with pseudo instructions
310      // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
311      // blocks as operands to these instructions.  When lowering these pseudo
312      // instructions to LUi and ADDiu in the MC layer, we will create
313      // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
314      // operands to lowered instructions.
315
316      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
317        .addMBB(TgtMBB).addMBB(BalTgtMBB);
318      MIBundleBuilder(*LongBrMBB, Pos)
319          .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
320          .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
321                      .addReg(Mips::AT)
322                      .addMBB(TgtMBB)
323                      .addMBB(BalTgtMBB));
324
325      Pos = BalTgtMBB->begin();
326
327      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
328        .addReg(Mips::RA).addReg(Mips::AT);
329      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
330        .addReg(Mips::SP).addImm(0);
331
332      if (!Subtarget.isTargetNaCl()) {
333        MIBundleBuilder(*BalTgtMBB, Pos)
334          .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
335          .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
336                  .addReg(Mips::SP).addImm(8));
337      } else {
338        // In NaCl, modifying the sp is not allowed in branch delay slot.
339        BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
340          .addReg(Mips::SP).addImm(8);
341
342        MIBundleBuilder(*BalTgtMBB, Pos)
343          .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
344          .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
345
346        // Bundle-align the target of indirect branch JR.
347        TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
348      }
349    } else {
350      // $longbr:
351      //  daddiu $sp, $sp, -16
352      //  sd $ra, 0($sp)
353      //  daddiu $at, $zero, %hi($tgt - $baltgt)
354      //  dsll $at, $at, 16
355      //  bal $baltgt
356      //  daddiu $at, $at, %lo($tgt - $baltgt)
357      // $baltgt:
358      //  daddu $at, $ra, $at
359      //  ld $ra, 0($sp)
360      //  jr64 $at
361      //  daddiu $sp, $sp, 16
362      // $fallthrough:
363      //
364
365      // We assume the branch is within-function, and that offset is within
366      // +/- 2GB.  High 32 bits will therefore always be zero.
367
368      // Note that this will work even if the offset is negative, because
369      // of the +1 modification that's added in that case.  For example, if the
370      // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
371      //
372      // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
373      //
374      // and the bits [47:32] are zero.  For %highest
375      //
376      // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
377      //
378      // and the bits [63:48] are zero.
379
380      Pos = LongBrMBB->begin();
381
382      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
383        .addReg(Mips::SP_64).addImm(-16);
384      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
385        .addReg(Mips::SP_64).addImm(0);
386      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
387              Mips::AT_64).addReg(Mips::ZERO_64)
388                          .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
389      BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
390        .addReg(Mips::AT_64).addImm(16);
391
392      MIBundleBuilder(*LongBrMBB, Pos)
393          .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
394          .append(
395              BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
396                  .addReg(Mips::AT_64)
397                  .addMBB(TgtMBB, MipsII::MO_ABS_LO)
398                  .addMBB(BalTgtMBB));
399
400      Pos = BalTgtMBB->begin();
401
402      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
403        .addReg(Mips::RA_64).addReg(Mips::AT_64);
404      BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
405        .addReg(Mips::SP_64).addImm(0);
406
407      MIBundleBuilder(*BalTgtMBB, Pos)
408        .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
409        .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
410                .addReg(Mips::SP_64).addImm(16));
411    }
412
413    assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
414  } else {
415    // $longbr:
416    //  j $tgt
417    //  nop
418    // $fallthrough:
419    //
420    Pos = LongBrMBB->begin();
421    LongBrMBB->addSuccessor(TgtMBB);
422    MIBundleBuilder(*LongBrMBB, Pos)
423      .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
424      .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
425
426    assert(LongBrMBB->size() == LongBranchSeqSize);
427  }
428
429  if (I.Br->isUnconditionalBranch()) {
430    // Change branch destination.
431    assert(I.Br->getDesc().getNumOperands() == 1);
432    I.Br->RemoveOperand(0);
433    I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
434  } else
435    // Change branch destination and reverse condition.
436    replaceBranch(*MBB, I.Br, DL, &*FallThroughMBB);
437}
438
439static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
440  MachineBasicBlock &MBB = F.front();
441  MachineBasicBlock::iterator I = MBB.begin();
442  DebugLoc DL = MBB.findDebugLoc(MBB.begin());
443  BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
444    .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
445  BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
446    .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
447  MBB.removeLiveIn(Mips::V0);
448}
449
450bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
451  const MipsSubtarget &STI =
452      static_cast<const MipsSubtarget &>(F.getSubtarget());
453  const MipsInstrInfo *TII =
454      static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
455  LongBranchSeqSize =
456      !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
457
458  if (STI.inMips16Mode() || !STI.enableLongBranchPass())
459    return false;
460  if ((TM.getRelocationModel() == Reloc::PIC_) &&
461      static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
462      F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
463    emitGPDisp(F, TII);
464
465  if (SkipLongBranch)
466    return true;
467
468  MF = &F;
469  initMBBInfo();
470
471  SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
472  bool EverMadeChange = false, MadeChange = true;
473
474  while (MadeChange) {
475    MadeChange = false;
476
477    for (I = MBBInfos.begin(); I != E; ++I) {
478      // Skip if this MBB doesn't have a branch or the branch has already been
479      // converted to a long branch.
480      if (!I->Br || I->HasLongBranch)
481        continue;
482
483      int ShVal = STI.inMicroMipsMode() ? 2 : 4;
484      int64_t Offset = computeOffset(I->Br) / ShVal;
485
486      if (STI.isTargetNaCl()) {
487        // The offset calculation does not include sandboxing instructions
488        // that will be added later in the MC layer.  Since at this point we
489        // don't know the exact amount of code that "sandboxing" will add, we
490        // conservatively estimate that code will not grow more than 100%.
491        Offset *= 2;
492      }
493
494      // Check if offset fits into 16-bit immediate field of branches.
495      if (!ForceLongBranch && isInt<16>(Offset))
496        continue;
497
498      I->HasLongBranch = true;
499      I->Size += LongBranchSeqSize * 4;
500      ++LongBranches;
501      EverMadeChange = MadeChange = true;
502    }
503  }
504
505  if (!EverMadeChange)
506    return true;
507
508  // Compute basic block addresses.
509  if (TM.getRelocationModel() == Reloc::PIC_) {
510    uint64_t Address = 0;
511
512    for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)
513      I->Address = Address;
514  }
515
516  // Do the expansion.
517  for (I = MBBInfos.begin(); I != E; ++I)
518    if (I->HasLongBranch)
519      expandToLongBranch(*I);
520
521  MF->RenumberBlocks();
522
523  return true;
524}
525