PPCInstrInfo.cpp revision 770bcc7b15adbc978800db70dbb1c3c22913b52c 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
34                               unsigned& sourceReg,
35                               unsigned& destReg,
36                               unsigned& sourceSubIdx,
37                               unsigned& destSubIdx) const {
38  sourceSubIdx = destSubIdx = 0; // No sub-registers.
39
40  unsigned oc = MI.getOpcode();
41  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
43    assert(MI.getNumOperands() >= 3 &&
44           MI.getOperand(0).isReg() &&
45           MI.getOperand(1).isReg() &&
46           MI.getOperand(2).isReg() &&
47           "invalid PPC OR instruction!");
48    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49      sourceReg = MI.getOperand(1).getReg();
50      destReg = MI.getOperand(0).getReg();
51      return true;
52    }
53  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
54    assert(MI.getNumOperands() >= 3 &&
55           MI.getOperand(0).isReg() &&
56           MI.getOperand(2).isImm() &&
57           "invalid PPC ADDI instruction!");
58    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59      sourceReg = MI.getOperand(1).getReg();
60      destReg = MI.getOperand(0).getReg();
61      return true;
62    }
63  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
64    assert(MI.getNumOperands() >= 3 &&
65           MI.getOperand(0).isReg() &&
66           MI.getOperand(1).isReg() &&
67           MI.getOperand(2).isImm() &&
68           "invalid PPC ORI instruction!");
69    if (MI.getOperand(2).getImm() == 0) {
70      sourceReg = MI.getOperand(1).getReg();
71      destReg = MI.getOperand(0).getReg();
72      return true;
73    }
74  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75             oc == PPC::FMRSD) {      // fmr r1, r2
76    assert(MI.getNumOperands() >= 2 &&
77           MI.getOperand(0).isReg() &&
78           MI.getOperand(1).isReg() &&
79           "invalid PPC FMR instruction");
80    sourceReg = MI.getOperand(1).getReg();
81    destReg = MI.getOperand(0).getReg();
82    return true;
83  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC MCRF instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  }
92  return false;
93}
94
95unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                           int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::LD:
100  case PPC::LWZ:
101  case PPC::LFS:
102  case PPC::LFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                          int &FrameIndex) const {
115  switch (MI->getOpcode()) {
116  default: break;
117  case PPC::STD:
118  case PPC::STW:
119  case PPC::STFS:
120  case PPC::STFD:
121    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122        MI->getOperand(2).isFI()) {
123      FrameIndex = MI->getOperand(2).getIndex();
124      return MI->getOperand(0).getReg();
125    }
126    break;
127  }
128  return 0;
129}
130
131// commuteInstruction - We can commute rlwimi instructions, but only if the
132// rotate amt is zero.  We also have to munge the immediates a bit.
133MachineInstr *
134PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135  MachineFunction &MF = *MI->getParent()->getParent();
136
137  // Normal instructions can be commuted the obvious way.
138  if (MI->getOpcode() != PPC::RLWIMI)
139    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
140
141  // Cannot commute if it has a non-zero rotate count.
142  if (MI->getOperand(3).getImm() != 0)
143    return 0;
144
145  // If we have a zero rotate count, we have:
146  //   M = mask(MB,ME)
147  //   Op0 = (Op1 & ~M) | (Op2 & M)
148  // Change this to:
149  //   M = mask((ME+1)&31, (MB-1)&31)
150  //   Op0 = (Op2 & ~M) | (Op1 & M)
151
152  // Swap op1/op2
153  unsigned Reg0 = MI->getOperand(0).getReg();
154  unsigned Reg1 = MI->getOperand(1).getReg();
155  unsigned Reg2 = MI->getOperand(2).getReg();
156  bool Reg1IsKill = MI->getOperand(1).isKill();
157  bool Reg2IsKill = MI->getOperand(2).isKill();
158  bool ChangeReg0 = false;
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    Reg2IsKill = false;
166    ChangeReg0 = true;
167  }
168
169  // Masks.
170  unsigned MB = MI->getOperand(4).getImm();
171  unsigned ME = MI->getOperand(5).getImm();
172
173  if (NewMI) {
174    // Create a new instruction.
175    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176    bool Reg0IsDead = MI->getOperand(0).isDead();
177    return BuildMI(MF, MI->getDesc())
178      .addReg(Reg0, true, false, false, Reg0IsDead)
179      .addReg(Reg2, false, false, Reg2IsKill)
180      .addReg(Reg1, false, false, Reg1IsKill)
181      .addImm((ME+1) & 31)
182      .addImm((MB-1) & 31);
183  }
184
185  if (ChangeReg0)
186    MI->getOperand(0).setReg(Reg2);
187  MI->getOperand(2).setReg(Reg1);
188  MI->getOperand(1).setReg(Reg2);
189  MI->getOperand(2).setIsKill(Reg1IsKill);
190  MI->getOperand(1).setIsKill(Reg2IsKill);
191
192  // Swap the mask around.
193  MI->getOperand(4).setImm((ME+1) & 31);
194  MI->getOperand(5).setImm((MB-1) & 31);
195  return MI;
196}
197
198void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                              MachineBasicBlock::iterator MI) const {
200  BuildMI(MBB, MI, get(PPC::NOP));
201}
202
203
204// Branch analysis.
205bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
206                                 MachineBasicBlock *&FBB,
207                                 SmallVectorImpl<MachineOperand> &Cond) const {
208  // If the block has no terminators, it just falls into the block after it.
209  MachineBasicBlock::iterator I = MBB.end();
210  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
211    return false;
212
213  // Get the last instruction in the block.
214  MachineInstr *LastInst = I;
215
216  // If there is only one terminator instruction, process it.
217  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
218    if (LastInst->getOpcode() == PPC::B) {
219      TBB = LastInst->getOperand(0).getMBB();
220      return false;
221    } else if (LastInst->getOpcode() == PPC::BCC) {
222      // Block ends with fall-through condbranch.
223      TBB = LastInst->getOperand(2).getMBB();
224      Cond.push_back(LastInst->getOperand(0));
225      Cond.push_back(LastInst->getOperand(1));
226      return false;
227    }
228    // Otherwise, don't know what this is.
229    return true;
230  }
231
232  // Get the instruction before it if it's a terminator.
233  MachineInstr *SecondLastInst = I;
234
235  // If there are three terminators, we don't know what sort of block this is.
236  if (SecondLastInst && I != MBB.begin() &&
237      isUnpredicatedTerminator(--I))
238    return true;
239
240  // If the block ends with PPC::B and PPC:BCC, handle it.
241  if (SecondLastInst->getOpcode() == PPC::BCC &&
242      LastInst->getOpcode() == PPC::B) {
243    TBB =  SecondLastInst->getOperand(2).getMBB();
244    Cond.push_back(SecondLastInst->getOperand(0));
245    Cond.push_back(SecondLastInst->getOperand(1));
246    FBB = LastInst->getOperand(0).getMBB();
247    return false;
248  }
249
250  // If the block ends with two PPC:Bs, handle it.  The second one is not
251  // executed, so remove it.
252  if (SecondLastInst->getOpcode() == PPC::B &&
253      LastInst->getOpcode() == PPC::B) {
254    TBB = SecondLastInst->getOperand(0).getMBB();
255    I = LastInst;
256    I->eraseFromParent();
257    return false;
258  }
259
260  // Otherwise, can't handle this.
261  return true;
262}
263
264unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
265  MachineBasicBlock::iterator I = MBB.end();
266  if (I == MBB.begin()) return 0;
267  --I;
268  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
269    return 0;
270
271  // Remove the branch.
272  I->eraseFromParent();
273
274  I = MBB.end();
275
276  if (I == MBB.begin()) return 1;
277  --I;
278  if (I->getOpcode() != PPC::BCC)
279    return 1;
280
281  // Remove the branch.
282  I->eraseFromParent();
283  return 2;
284}
285
286unsigned
287PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
288                           MachineBasicBlock *FBB,
289                           const SmallVectorImpl<MachineOperand> &Cond) const {
290  // Shouldn't be a fall through.
291  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
292  assert((Cond.size() == 2 || Cond.size() == 0) &&
293         "PPC branch conditions have two components!");
294
295  // One-way branch.
296  if (FBB == 0) {
297    if (Cond.empty())   // Unconditional branch
298      BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
299    else                // Conditional branch
300      BuildMI(&MBB, get(PPC::BCC))
301        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
302    return 1;
303  }
304
305  // Two-way Conditional Branch.
306  BuildMI(&MBB, get(PPC::BCC))
307    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
308  BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
309  return 2;
310}
311
312bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
313                                   MachineBasicBlock::iterator MI,
314                                   unsigned DestReg, unsigned SrcReg,
315                                   const TargetRegisterClass *DestRC,
316                                   const TargetRegisterClass *SrcRC) const {
317  if (DestRC != SrcRC) {
318    // Not yet supported!
319    return false;
320  }
321
322  if (DestRC == PPC::GPRCRegisterClass) {
323    BuildMI(MBB, MI, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
324  } else if (DestRC == PPC::G8RCRegisterClass) {
325    BuildMI(MBB, MI, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
326  } else if (DestRC == PPC::F4RCRegisterClass) {
327    BuildMI(MBB, MI, get(PPC::FMRS), DestReg).addReg(SrcReg);
328  } else if (DestRC == PPC::F8RCRegisterClass) {
329    BuildMI(MBB, MI, get(PPC::FMRD), DestReg).addReg(SrcReg);
330  } else if (DestRC == PPC::CRRCRegisterClass) {
331    BuildMI(MBB, MI, get(PPC::MCRF), DestReg).addReg(SrcReg);
332  } else if (DestRC == PPC::VRRCRegisterClass) {
333    BuildMI(MBB, MI, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
334  } else if (DestRC == PPC::CRBITRCRegisterClass) {
335    BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
336  } else {
337    // Attempt to copy register that is not GPR or FPR
338    return false;
339  }
340
341  return true;
342}
343
344bool
345PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
346                                  unsigned SrcReg, bool isKill,
347                                  int FrameIdx,
348                                  const TargetRegisterClass *RC,
349                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
350  if (RC == PPC::GPRCRegisterClass) {
351    if (SrcReg != PPC::LR) {
352      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
353                                         .addReg(SrcReg, false, false, isKill),
354                                         FrameIdx));
355    } else {
356      // FIXME: this spills LR immediately to memory in one step.  To do this,
357      // we use R11, which we know cannot be used in the prolog/epilog.  This is
358      // a hack.
359      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
360      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
361                                         .addReg(PPC::R11, false, false, isKill),
362                                         FrameIdx));
363    }
364  } else if (RC == PPC::G8RCRegisterClass) {
365    if (SrcReg != PPC::LR8) {
366      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
367                              .addReg(SrcReg, false, false, isKill), FrameIdx));
368    } else {
369      // FIXME: this spills LR immediately to memory in one step.  To do this,
370      // we use R11, which we know cannot be used in the prolog/epilog.  This is
371      // a hack.
372      NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
373      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
374                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
375    }
376  } else if (RC == PPC::F8RCRegisterClass) {
377    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
378                              .addReg(SrcReg, false, false, isKill), FrameIdx));
379  } else if (RC == PPC::F4RCRegisterClass) {
380    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
381                              .addReg(SrcReg, false, false, isKill), FrameIdx));
382  } else if (RC == PPC::CRRCRegisterClass) {
383    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
384        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
385      // FIXME (64-bit): Enable
386      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
387                                         .addReg(SrcReg, false, false, isKill),
388                                         FrameIdx));
389      return true;
390    } else {
391      // FIXME: We use R0 here, because it isn't available for RA.  We need to
392      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
393      // to save all of the CRBits.
394      NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
395
396      // If the saved register wasn't CR0, shift the bits left so that they are
397      // in CR0's slot.
398      if (SrcReg != PPC::CR0) {
399        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
400        // rlwinm r0, r0, ShiftBits, 0, 31.
401        NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
402                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
403      }
404
405      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
406                                         .addReg(PPC::R0, false, false, isKill),
407                                         FrameIdx));
408    }
409  } else if (RC == PPC::CRBITRCRegisterClass) {
410    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
411    // backend currently only uses CR1EQ as an individual bit, this should
412    // not cause any bug. If we need other uses of CR bits, the following
413    // code may be invalid.
414    unsigned Reg = 0;
415    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
416      Reg = PPC::CR0;
417    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
418      Reg = PPC::CR1;
419    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
420      Reg = PPC::CR2;
421    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
422      Reg = PPC::CR3;
423    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
424      Reg = PPC::CR4;
425    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
426      Reg = PPC::CR5;
427    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
428      Reg = PPC::CR6;
429    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
430      Reg = PPC::CR7;
431
432    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
433                               PPC::CRRCRegisterClass, NewMIs);
434
435  } else if (RC == PPC::VRRCRegisterClass) {
436    // We don't have indexed addressing for vector loads.  Emit:
437    // R0 = ADDI FI#
438    // STVX VAL, 0, R0
439    //
440    // FIXME: We use R0 here, because it isn't available for RA.
441    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
442                                       FrameIdx, 0, 0));
443    NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
444         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
445  } else {
446    assert(0 && "Unknown regclass!");
447    abort();
448  }
449
450  return false;
451}
452
453void
454PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
455                                  MachineBasicBlock::iterator MI,
456                                  unsigned SrcReg, bool isKill, int FrameIdx,
457                                  const TargetRegisterClass *RC) const {
458  MachineFunction &MF = *MBB.getParent();
459  SmallVector<MachineInstr*, 4> NewMIs;
460
461  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
462    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
463    FuncInfo->setSpillsCR();
464  }
465
466  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
467    MBB.insert(MI, NewMIs[i]);
468}
469
470void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
471                                  bool isKill,
472                                  SmallVectorImpl<MachineOperand> &Addr,
473                                  const TargetRegisterClass *RC,
474                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
475  if (Addr[0].isFI()) {
476    if (StoreRegToStackSlot(MF, SrcReg, isKill,
477                            Addr[0].getIndex(), RC, NewMIs)) {
478      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
479      FuncInfo->setSpillsCR();
480    }
481
482    return;
483  }
484
485  unsigned Opc = 0;
486  if (RC == PPC::GPRCRegisterClass) {
487    Opc = PPC::STW;
488  } else if (RC == PPC::G8RCRegisterClass) {
489    Opc = PPC::STD;
490  } else if (RC == PPC::F8RCRegisterClass) {
491    Opc = PPC::STFD;
492  } else if (RC == PPC::F4RCRegisterClass) {
493    Opc = PPC::STFS;
494  } else if (RC == PPC::VRRCRegisterClass) {
495    Opc = PPC::STVX;
496  } else {
497    assert(0 && "Unknown regclass!");
498    abort();
499  }
500  MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
501    .addReg(SrcReg, false, false, isKill);
502  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
503    MachineOperand &MO = Addr[i];
504    if (MO.isReg())
505      MIB.addReg(MO.getReg());
506    else if (MO.isImm())
507      MIB.addImm(MO.getImm());
508    else
509      MIB.addFrameIndex(MO.getIndex());
510  }
511  NewMIs.push_back(MIB);
512  return;
513}
514
515void
516PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
517                                   unsigned DestReg, int FrameIdx,
518                                   const TargetRegisterClass *RC,
519                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
520  if (RC == PPC::GPRCRegisterClass) {
521    if (DestReg != PPC::LR) {
522      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
523                                         FrameIdx));
524    } else {
525      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
526                                         FrameIdx));
527      NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
528    }
529  } else if (RC == PPC::G8RCRegisterClass) {
530    if (DestReg != PPC::LR8) {
531      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
532                                         FrameIdx));
533    } else {
534      NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
535                                         FrameIdx));
536      NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
537    }
538  } else if (RC == PPC::F8RCRegisterClass) {
539    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
540                                       FrameIdx));
541  } else if (RC == PPC::F4RCRegisterClass) {
542    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
543                                       FrameIdx));
544  } else if (RC == PPC::CRRCRegisterClass) {
545    // FIXME: We use R0 here, because it isn't available for RA.
546    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
547                                       FrameIdx));
548
549    // If the reloaded register isn't CR0, shift the bits right so that they are
550    // in the right CR's slot.
551    if (DestReg != PPC::CR0) {
552      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
553      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
554      NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
555                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
556    }
557
558    NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
559  } else if (RC == PPC::CRBITRCRegisterClass) {
560
561    unsigned Reg = 0;
562    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
563      Reg = PPC::CR0;
564    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
565      Reg = PPC::CR1;
566    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
567      Reg = PPC::CR2;
568    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
569      Reg = PPC::CR3;
570    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
571      Reg = PPC::CR4;
572    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
573      Reg = PPC::CR5;
574    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
575      Reg = PPC::CR6;
576    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
577      Reg = PPC::CR7;
578
579    return LoadRegFromStackSlot(MF, Reg, FrameIdx,
580                                PPC::CRRCRegisterClass, NewMIs);
581
582  } else if (RC == PPC::VRRCRegisterClass) {
583    // We don't have indexed addressing for vector loads.  Emit:
584    // R0 = ADDI FI#
585    // Dest = LVX 0, R0
586    //
587    // FIXME: We use R0 here, because it isn't available for RA.
588    NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
589                                       FrameIdx, 0, 0));
590    NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
591                     .addReg(PPC::R0));
592  } else {
593    assert(0 && "Unknown regclass!");
594    abort();
595  }
596}
597
598void
599PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
600                                   MachineBasicBlock::iterator MI,
601                                   unsigned DestReg, int FrameIdx,
602                                   const TargetRegisterClass *RC) const {
603  MachineFunction &MF = *MBB.getParent();
604  SmallVector<MachineInstr*, 4> NewMIs;
605  LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
606  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
607    MBB.insert(MI, NewMIs[i]);
608}
609
610void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
611                                   SmallVectorImpl<MachineOperand> &Addr,
612                                   const TargetRegisterClass *RC,
613                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
614  if (Addr[0].isFI()) {
615    LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
616    return;
617  }
618
619  unsigned Opc = 0;
620  if (RC == PPC::GPRCRegisterClass) {
621    assert(DestReg != PPC::LR && "Can't handle this yet!");
622    Opc = PPC::LWZ;
623  } else if (RC == PPC::G8RCRegisterClass) {
624    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
625    Opc = PPC::LD;
626  } else if (RC == PPC::F8RCRegisterClass) {
627    Opc = PPC::LFD;
628  } else if (RC == PPC::F4RCRegisterClass) {
629    Opc = PPC::LFS;
630  } else if (RC == PPC::VRRCRegisterClass) {
631    Opc = PPC::LVX;
632  } else {
633    assert(0 && "Unknown regclass!");
634    abort();
635  }
636  MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
637  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
638    MachineOperand &MO = Addr[i];
639    if (MO.isReg())
640      MIB.addReg(MO.getReg());
641    else if (MO.isImm())
642      MIB.addImm(MO.getImm());
643    else
644      MIB.addFrameIndex(MO.getIndex());
645  }
646  NewMIs.push_back(MIB);
647  return;
648}
649
650/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
651/// copy instructions, turning them into load/store instructions.
652MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
653                                                  MachineInstr *MI,
654                                           const SmallVectorImpl<unsigned> &Ops,
655                                                  int FrameIndex) const {
656  if (Ops.size() != 1) return NULL;
657
658  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
659  // it takes more than one instruction to store it.
660  unsigned Opc = MI->getOpcode();
661  unsigned OpNum = Ops[0];
662
663  MachineInstr *NewMI = NULL;
664  if ((Opc == PPC::OR &&
665       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
666    if (OpNum == 0) {  // move -> store
667      unsigned InReg = MI->getOperand(1).getReg();
668      bool isKill = MI->getOperand(1).isKill();
669      NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
670                                .addReg(InReg, false, false, isKill),
671                                FrameIndex);
672    } else {           // move -> load
673      unsigned OutReg = MI->getOperand(0).getReg();
674      bool isDead = MI->getOperand(0).isDead();
675      NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
676                                .addReg(OutReg, true, false, false, isDead),
677                                FrameIndex);
678    }
679  } else if ((Opc == PPC::OR8 &&
680              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
681    if (OpNum == 0) {  // move -> store
682      unsigned InReg = MI->getOperand(1).getReg();
683      bool isKill = MI->getOperand(1).isKill();
684      NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
685                                .addReg(InReg, false, false, isKill),
686                                FrameIndex);
687    } else {           // move -> load
688      unsigned OutReg = MI->getOperand(0).getReg();
689      bool isDead = MI->getOperand(0).isDead();
690      NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
691                                .addReg(OutReg, true, false, false, isDead),
692                                FrameIndex);
693    }
694  } else if (Opc == PPC::FMRD) {
695    if (OpNum == 0) {  // move -> store
696      unsigned InReg = MI->getOperand(1).getReg();
697      bool isKill = MI->getOperand(1).isKill();
698      NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
699                                .addReg(InReg, false, false, isKill),
700                                FrameIndex);
701    } else {           // move -> load
702      unsigned OutReg = MI->getOperand(0).getReg();
703      bool isDead = MI->getOperand(0).isDead();
704      NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
705                                .addReg(OutReg, true, false, false, isDead),
706                                FrameIndex);
707    }
708  } else if (Opc == PPC::FMRS) {
709    if (OpNum == 0) {  // move -> store
710      unsigned InReg = MI->getOperand(1).getReg();
711      bool isKill = MI->getOperand(1).isKill();
712      NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
713                                .addReg(InReg, false, false, isKill),
714                                FrameIndex);
715    } else {           // move -> load
716      unsigned OutReg = MI->getOperand(0).getReg();
717      bool isDead = MI->getOperand(0).isDead();
718      NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
719                                .addReg(OutReg, true, false, false, isDead),
720                                FrameIndex);
721    }
722  }
723
724  return NewMI;
725}
726
727bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
728                                  const SmallVectorImpl<unsigned> &Ops) const {
729  if (Ops.size() != 1) return false;
730
731  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
732  // it takes more than one instruction to store it.
733  unsigned Opc = MI->getOpcode();
734
735  if ((Opc == PPC::OR &&
736       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
737    return true;
738  else if ((Opc == PPC::OR8 &&
739              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
740    return true;
741  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
742    return true;
743
744  return false;
745}
746
747
748bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
749  if (MBB.empty()) return false;
750
751  switch (MBB.back().getOpcode()) {
752  case PPC::BLR:   // Return.
753  case PPC::B:     // Uncond branch.
754  case PPC::BCTR:  // Indirect branch.
755    return true;
756  default: return false;
757  }
758}
759
760bool PPCInstrInfo::
761ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
762  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
763  // Leave the CR# the same, but invert the condition.
764  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
765  return false;
766}
767
768/// GetInstSize - Return the number of bytes of code the specified
769/// instruction may be.  This returns the maximum number of bytes.
770///
771unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
772  switch (MI->getOpcode()) {
773  case PPC::INLINEASM: {       // Inline Asm: Variable size.
774    const MachineFunction *MF = MI->getParent()->getParent();
775    const char *AsmStr = MI->getOperand(0).getSymbolName();
776    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
777  }
778  case PPC::DBG_LABEL:
779  case PPC::EH_LABEL:
780  case PPC::GC_LABEL:
781    return 0;
782  default:
783    return 4; // PowerPC instructions are all 4 bytes
784  }
785}
786