History log of /external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
cddc3e03e4ec99c0268c03a126195173e519ed58 04-Mar-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r256229

http://b/26987366

(cherry picked from commit f3ef5332fa3f4d5ec72c178a2b19dac363a19383)

Change-Id: Ic75dcb63191d65df1b69724576392c0aaeb47728
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
6948897e478cbd66626159776a8017b3c18579b9 01-Jul-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r239765

Bug: 20140355: This rebase pulls the upstream fix for the spurious
warnings mentioned in the bug.

Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b29de8ba0044548f0259b5eca180e07bdba992bc 12-Dec-2013 Bill Wendling <isanbard@gmail.com> Merging r197089:
------------------------------------------------------------------------
r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines

Fix the PPC subsumes-predicate check

For one predicate to subsume another, they must both check the same condition
register. Failure to check this prerequisite was causing miscompiles.

Fixes PR18003.
------------------------------------------------------------------------


git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
354362524a72b3fa43a6c09380b7ae3b2380cbba 19-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 18-Nov-2013 Alexey Samsonov <samsonov@google.com> Revert r194865 and r194874.

This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 15-Nov-2013 Juergen Ributzka <juergen@apple.com> [weak vtables] Remove a bunch of weak vtables

This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.

Differential Revision: http://llvm-reviews.chandlerc.com/D2068

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
ae4f3f6820c28a4ba4fab538f5ff4724cbe82d50 15-Jul-2013 Hal Finkel <hfinkel@anl.gov> Fix register subclass handling in PPCInstrInfo::insertSelect

PPCInstrInfo::insertSelect and PPCInstrInfo::canInsertSelect were computing the
common subclass of the true and false inputs, and then selecting either the
32-bit or the 64-bit isel variant based on the result of calling
PPC::GPRCRegClass.hasSubClassEq(RC) and PPC::G8RCRegClass.hasSubClassEq(RC)
(where RC is the common subclass). Unfortunately, this is not quite right: if
we have something like this:

%vreg8<def> = SELECT_CC_I8 %vreg4<kill>, %vreg7<kill>, %vreg6<kill>, 76;
G8RC_and_G8RC_NOX0:%vreg8 CRRC:%vreg4 G8RC_NOX0:%vreg7,%vreg6

then the common subclass of G8RC_and_G8RC_NOX0 and G8RC_NOX0 is G8RC_NOX0, and
G8RC_NOX0 is not a subclass of G8RC (because it also contains the ZERO8
pseudo-register). As a result, we also need to check the common subclass
against GPRC_NOR0 and G8RC_NOX0 explicitly.

This had not been a problem for clients of insertSelect that called
canInsertSelect first (because it had a compensating mistake), but insertSelect
is also used by the PPC pseudo-instruction expander, and this error was causing
a problem in that context.

This problem was found by csmith.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 16-Jun-2013 David Blaikie <dblaikie@gmail.com> DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs

Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
041399aad5a3d93c2dc9d2b70cb9b87d4a987ece 07-Jun-2013 Benjamin Kramer <benny.kra@googlemail.com> Fold variable that's only used in assert into the assert.

Avoids unused variable warnings in Release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
80ada583f3b40ffb201e54cd57c42f9518039c9e 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b45eb9fd275f857788cabb15ef8aabf0ff5907cc 08-May-2013 Hal Finkel <hfinkel@anl.gov> PPCInstrInfo::optimizeCompareInstr should not optimize FP compares

The floating-point record forms on PPC don't set the condition register bits
based on a comparison with zero (like the integer record forms do), but rather
based on the exception status bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
8a88cadaedcfa3bb020df1d100d67cecaf638f35 07-May-2013 Hal Finkel <hfinkel@anl.gov> Cleanup PPCInstrInfo::optimizeCompareInstr

Implement suggestions by Bill Schmidt in post-commit review. No functionality
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
abe64dc6f7363c7e6170568e382fb06d81d62f51 20-Apr-2013 Hal Finkel <hfinkel@anl.gov> Move PPC getSwappedPredicate for reuse

The getSwappedPredicate function can be used in other places (such as in
improvements to the PPCCTRLoops pass). Instead of trapping it as a static
function in PPCInstrInfo, move it into PPCPredicates with other
predicate-related things.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
87c1e42be7dadaea7c3e00fb7ccbd77633cea37f 20-Apr-2013 Hal Finkel <hfinkel@anl.gov> Fix PPC optimizeCompareInstr swapped-sub argument handling

When matching a compare with a subtract where the arguments of the compare are
swapped w.r.t. the arguments of the subtract, we need to negate the predicates
(or CR bit indices) of the users. This, however, is not the same as inverting
the predicate (negating LT -> GT, but inverting LT -> GE, for example). The ARM
backend seems to do this correctly, but when I adapted the code for the PPC
backend, I introduced an error in this logic.

Comparison optimization is now enabled again by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4029c3feed5c9a5b0793e3da140ecaabef19e3fe 19-Apr-2013 Hal Finkel <hfinkel@anl.gov> Disable PPC comparison optimization by default

This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do
I'm disabling this for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
860c08cad5b7c1359123bb2b0e74df4b6e48a15c 19-Apr-2013 Hal Finkel <hfinkel@anl.gov> Implement optimizeCompareInstr for PPC

Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.

This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
171a8adf3168aee2f739f91c1800e9025892c7b5 12-Apr-2013 Hal Finkel <hfinkel@anl.gov> Add PPC instruction record forms and associated query functions

This is prep. work for the implementation of optimizeCompare. Many PPC
instructions have 'record' forms (in almost all cases, this means that the RC
bit is set) that cause the result of the instruction to be compared with zero,
and the result of that comparison saved in a predefined condition register. In
order to add the record forms of the instructions without too much
copy-and-paste, the relevant functions have been refactored into multiclasses
which define both the record and normal forms.

Also, two TableGen-generated mapping functions have been added which allow
querying the instruction code for the record form given the normal form (and
vice versa).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4b040294816e49413c739825d801042bc76171a7 11-Apr-2013 Hal Finkel <hfinkel@anl.gov> Make PPCInstrInfo::isPredicated always return false

Because of how predication in implemented on PPC (only for branches), I think
that this is the right thing to do. No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179252 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
da47e17a6f58bb4dae22d3e79c69fcb1d254ba44 10-Apr-2013 Hal Finkel <hfinkel@anl.gov> PPC: Don't predicate a diamond with two counter decrements

I've not seen this happen in practice, and probably can't until we start
allowing decrement-counter-based conditional branches to be double predicated,
but just in case, don't allow predication of a diamond in which both sides have
ctr-defining branches. Even though the branching behavior of these can be
predicated, the counter-decrementing behavior cannot be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4e3172867d0c1acfda9d2cc88dfad23634e649eb 10-Apr-2013 Hal Finkel <hfinkel@anl.gov> Cleanup PPCInstrInfo::DefinesPredicate

Implement suggestions made by Bill Schmidt in post-commit review. Thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
90dd7fd167b6d09e4a7f37e35dcbfdc492546a79 10-Apr-2013 Hal Finkel <hfinkel@anl.gov> PPC: Prep for if conversion of bctr[l]

This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7eb0d8148e1210d9e31ab471477de47b53bab117 10-Apr-2013 Hal Finkel <hfinkel@anl.gov> Allow PPC B and BLR to be if-converted into some predicated forms

This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).

At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
13049aef8ad86795e94006dea0e097a8add85665 09-Apr-2013 Hal Finkel <hfinkel@anl.gov> Cleanup PPCEarlyReturn

Some general cleanup and only scan the end of a BB for branches (once we're
done with the terminators and debug values, then there should not be any other
branches). These address post-commit review suggestions by Bill Schmidt.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179112 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5ee67e8e76dfcaffa5e776ef3d5eeb80807a627b 08-Apr-2013 Hal Finkel <hfinkel@anl.gov> Generate PPC early conditional returns

PowerPC has a conditional branch to the link register (return) instruction: BCLR.
This should be used any time when we'd otherwise have a conditional branch to a
return. This adds a small pass, PPCEarlyReturn, which runs just prior to the
branch selection pass (and, importantly, after block placement) to generate
these conditional returns when possible. It will also eliminate unconditional
branches to returns (these happen rarely; most of the time these have already
been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice
optimization for small functions that do not maintain a stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
839b9096538f790a2bb060547df24703807cb83b 06-Apr-2013 Hal Finkel <hfinkel@anl.gov> Implement PPCInstrInfo::FoldImmediate

There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
ff56d1a2011f239e114267c13302ea26db4f8046 06-Apr-2013 Hal Finkel <hfinkel@anl.gov> Enable early if conversion on PPC

On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.

Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
f25f93b685a6cb91d8370ae5dc1436a863a670d2 27-Mar-2013 Hal Finkel <hfinkel@anl.gov> Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in PPCInstrInfo

These functions should have the same list of load/store instructions. Now that
all load/store forms have been normalized (to single instructions or pseudos)
they can be resynchronized.

Found by inspection, although hopefully this will improve optimization. I've
also added some comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
fc8058696820332cfd3d382f6534edc96420a0b1 27-Mar-2013 Hal Finkel <hfinkel@anl.gov> Remove more dead LR-as-GPR PPC code

I had removed similar code a few days ago, but somehow missed this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b7e11e400dabced046e7ec53a66926716563bb36 27-Mar-2013 Hal Finkel <hfinkel@anl.gov> Don't spill PPC VRSAVE on non-Darwin (even in SjLj)

As Bill Schmidt pointed out to me, only on Darwin do we need to spill/restore
VRSAVE in the SjLj code. For non-Darwin, don't spill/restore VRSAVE (and I've
added some asserts to make sure that we're not).

As it turns out, we're not currently handling the Darwin case correctly (I've
added a FIXME in the test case). I've tried adding various implied register
definitions/uses to force the spill without success, so I'll need to address
this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3f2c047f32c9b488d9c49bb2dc87b979530dab3f 23-Mar-2013 Hal Finkel <hfinkel@anl.gov> Note in PPCFunctionInfo VRSAVE spills

In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7257fda1b3b047f6fd46df8a9999580fcfafbfae 23-Mar-2013 Hal Finkel <hfinkel@anl.gov> Remove dead PPC LR spilling code

The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
86765fbe170198e7bb40fd8499d1354f4c786f60 22-Mar-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> Remove ABI-duplicated call instruction patterns.

We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.

No change in generated code expected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3ea1b064a0b9c3d161b0f77a9e957970f98907ab 22-Mar-2013 Hal Finkel <hfinkel@anl.gov> Fix a register-class comparison bug in PPCCTRLoops

Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
10f7f2a222d0e83dc0c33ad506a7686190c2f7a2 21-Mar-2013 Hal Finkel <hfinkel@anl.gov> Add support for spilling VRSAVE on PPC

Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
a548afc98fd4c61a8dfdd550ba57c37f2cfe3ed9 19-Mar-2013 Hal Finkel <hfinkel@anl.gov> Prepare to make r0 an allocatable register on PPC

Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:

1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.

2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).

This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.

Once the CR spilling code is improved, we'll be able to allocate r0.

Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.

As r0 is still reserved, no functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
324972904353594ad4a0cdfc79370f85e9fb9c8f 17-Mar-2013 Hal Finkel <hfinkel@anl.gov> Improve PPC VR (Altivec) register spilling

This change cleans up two issues with Altivec register spilling:

1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)

2. The code assumed that r0 would always be available (true for now, but this
will change)

The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
0cfb42adb5072fb19a01dba3ea58a33fd5927947 15-Mar-2013 Hal Finkel <hfinkel@anl.gov> Allocate the RS spill slot for any PPC function with spills and a large stack frame

For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.

I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7285e8d98c9a44b7efe792462188cfe713dd9641 12-Mar-2013 Hal Finkel <hfinkel@anl.gov> PPC should always use the register scavenger for CR spilling

This removes the -disable-ppc[32|64]-regscavenger options; the code
that uses the register scavenger has been working well (and has been the default)
for some time, and we don't need options to enable the old (broken) CR spilling code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
a9fa4fd9736f7d1066223f32fa54efbe86c0fceb 28-Nov-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove all references to TargetInstrInfoImpl.

This class has been merged into its super-class TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
26160f4e6403f3ddd7c4599422578cb46777103d 10-Oct-2012 Bill Schmidt <wschmidt@linux.vnet.ibm.com> When generating spill and reload code for vector registers on PowerPC,
the compiler makes use of GPR0. However, there are two flavors of
GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0
(X0). The spill/reload code makes use of R0 regardless of whether we
are generating 32- or 64-bit code.

This patch corrects the problem in the obvious manner, using X0 and
ADDI8 for 64-bit and R0 and ADDI for 32-bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
621b77ade2ff46d1d8594bddee6931b2f4a14706 28-Aug-2012 Hal Finkel <hfinkel@anl.gov> Add PPC Freescale e500mc and e5500 subtargets.

Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7164288c3eb52e20454fc757440f867f04eb13a4 19-Jun-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Implement PPCInstrInfo::isCoalescableExtInstr().

The PPC::EXTSW instruction preserves the low 32 bits of its input, just
like some of the x86 instructions. Use it to reduce register pressure
when the low 32 bits have multiple uses.

This requires a small change to PeepholeOptimizer since EXTSW takes a
64-bit input register.

This is related to PR5997.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7255d2a8084cb6aa96ea0e5f30acfff76df04ee8 08-Jun-2012 Hal Finkel <hfinkel@anl.gov> Enable PPC CTR loop formation by default.

Thanks to Jakob's help, this now causes no new test suite failures!

Over the entire test suite, this gives an average 1% speedup. The largest speedups are:
SingleSource/Benchmarks/Misc/pi - 108%
SingleSource/Benchmarks/CoyoteBench/lpbench - 54%
MultiSource/Benchmarks/Prolangs-C/unix-smail/unix-smail - 50%
SingleSource/Benchmarks/Shootout/ary3 - 32%
SingleSource/Benchmarks/Shootout-C++/matrix - 30%

The largest slowdowns are:
MultiSource/Benchmarks/mediabench/gsm/toast/toast - -30%
MultiSource/Benchmarks/Prolangs-C/bison/mybison - -25%
MultiSource/Benchmarks/BitBench/uuencode/uuencode - -22%
MultiSource/Applications/d/make_dparser - -14%
SingleSource/Benchmarks/Shootout-C++/ary - -13%

In light of these slowdowns, additional profiling work is obviously needed!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
09fdc7baae1b6905fe18df48e2278e74d4e39ccd 08-Jun-2012 Hal Finkel <hfinkel@anl.gov> Disable the PPC CTR-Loops pass by default.

The pass itself works well, but the something in the Machine* infrastructure
does not understand terminators which define registers. Without the ability
to use the block-placement pass, etc. this causes performance regressions (and
so is turned off by default). Turning off the analysis turns off the problems
with the Machine* infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
99f823f94374917174f96a7689955b8463db6816 08-Jun-2012 Hal Finkel <hfinkel@anl.gov> Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.

This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c909950c384e8234a7b3c5a76b7f79e3f7012ceb 20-Apr-2012 Craig Topper <craig.topper@gmail.com> Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4d989ac93ce608057fb6b13a4068264ab037ecd5 01-Apr-2012 Hal Finkel <hfinkel@anl.gov> Add instruction itinerary for the PPC64 A2 core.

This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5b00ceaeeabff8c25abb09926343c3fcb06053d8 31-Mar-2012 Hal Finkel <hfinkel@anl.gov> Fix dynamic linking on PPC64.

Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.

This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.

The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
234bb38d6c421ea22229087a9835afe99e531276 07-Dec-2011 Hal Finkel <hfinkel@anl.gov> make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7ad6b7d35978e1bb89de90aa732cf2f57377d69d 07-Dec-2011 Hal Finkel <hfinkel@anl.gov> 64-bit LR8 load should use X11 not R11

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d21e930eac3d99dd77ee33ea5826700b4bc97ae8 06-Dec-2011 Hal Finkel <hfinkel@anl.gov> add RESTORE_CR and support CR unspills

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3fd0018af1b692cabfa5a002bf41f1e756aa9dde 05-Dec-2011 Hal Finkel <hfinkel@anl.gov> enable PPC register scavenging by default (update tests and remove some FIXMEs)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
64c34e253563a8ba6b41fbce2bb020632cf65961 02-Dec-2011 Hal Finkel <hfinkel@anl.gov> update PPC 940 hazard rec. to function in postRA mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
768c65f677af3f05c2e94982043f90a1bfaceda5 22-Nov-2011 Hal Finkel <hfinkel@anl.gov> add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
978e0dfe46e481bfb1281e683aa308329e879e95 15-Nov-2011 Jay Foad <jay.foad@gmail.com> Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
0839033cbca20a1d1348bdf1c9f63fb263b248a6 08-Nov-2011 NAKAMURA Takumi <geek4civic@gmail.com> PPCInstrInfo.cpp: Fix one "unused" warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
ed8db320af68556de5fcfe2cbec688003acc33f5 21-Oct-2011 Richard Smith <richard-llvm@metafoo.co.uk> Fix unused variable warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5bdab4a63cab2ed2f96a3490fa2349550da7c7f9 20-Oct-2011 Dan Gohman <gohman@apple.com> Disable the PPC hazard recognizer. It currently only supports
top-down scheduling and top-down scheduling is going away.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 17-Oct-2011 Hal Finkel <hfinkel@anl.gov> Add PPC 440 scheduler and some associated tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
01faf432d9d81212b492f326594d43a951fe64f0 04-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Teach PPCInstrInfo to handle sub-classes.

This has already been done for most other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 24-Aug-2011 Evan Cheng <evan.cheng@apple.com> Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
94b9550a32d189704a8eae55505edf62662c0534 26-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
966aeb5788c242cfaca35c56c0ddc0ff778d4376 25-Jul-2011 Evan Cheng <evan.cheng@apple.com> Refactor PPC target to separate MC routines from Target routines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
59ee62d2418df8db499eca1ae17f5900dc2dcbba 11-Jul-2011 Evan Cheng <evan.cheng@apple.com> - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4db3cffe94a5285239cc0056f939c6b74a5ca0b6 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> Hide the call to InitMCInstrInfo into tblgen generated ctor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d5b03f252c0db6b49a242abab63d7c5a260fceae 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
22fee2dff4c43b551aefa44a96ca74fcade6bfac 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
2da8bc8a5f7705ac131184cd247f48500da0d74e 24-Dec-2010 Andrew Trick <atrick@apple.com> Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
6e8f4c404825b79f9b9176483653f1aa927dfbde 24-Dec-2010 Andrew Trick <atrick@apple.com> whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
59db5496f4fc2ef6111569e542f8b65480ef14c1 21-Sep-2010 Chris Lattner <sabre@nondot.org> convert targets to the new MF.getMachineMemOperand interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
78e6e009223a38739797629ca2d217acf86dda93 17-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Remove the isMoveInstr() hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7431beaba2a01c3fe299c861b2ec85cbf1dc81c4 17-Jul-2010 Bill Wendling <isanbard@gmail.com> Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission and
thus is a much more meaningful name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
a90c3f600d5bea9e01722d7df5752f9adfcf4635 16-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit COPY instead of FMR/FMSD instructions for floating point conversion on
PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7a79fcb55b83b8b98b9853c390cc5bf8ce382dd3 16-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memory
operands.

Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't
since missing memoperands should not affect correctness.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108540 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
600f171486708734e2b9c9c617528cfc51c16850 11-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> RISC architectures get their memory operand folding for free.

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
27689b0affee8fb1bfbef11dcc84287b7757cfe8 11-Jul-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Replace copyRegToReg with copyPhysReg for PowerPC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3bf912593301152b65accb9d9c37a95172f1df5a 18-Jun-2010 Stuart Hastings <stuart@apple.com> Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5f07d5224ddc32f405d7e19de8e58e91ab2816bc 20-May-2010 Dale Johannesen <dalej@apple.com> The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 06-May-2010 Dan Gohman <gohman@apple.com> Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
746ad69e088176819981b4b2c5ac8dcd49f5e60e 06-May-2010 Evan Cheng <evan.cheng@apple.com> Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
9f2cda73e470673ab63509adc9d096b0a1d13c54 05-May-2010 Dan Gohman <gohman@apple.com> No-ops emitted for scheduling don't correspond with anything in the
user's source, so don't arbitrarily assign them a debug location.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
8601a3d4decff0a380e059b037dabf71075497d3 29-Apr-2010 Evan Cheng <evan.cheng@apple.com> Frame index can be negative.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
0965217e74fe07f1451350a80114ab566ced5de0 26-Apr-2010 Evan Cheng <evan.cheng@apple.com> Add PPC specific emitFrameIndexDebugValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
82bcd236937b378e56e46bdde9c17a3ea3377068 15-Apr-2010 Dan Gohman <gohman@apple.com> EnablePPC64RS and EnablePPC32RS are used in multiple files, so they
can't be static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101377 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
375be7730a6f3dee7a6dc319ee6c355a11ac99ad 07-Apr-2010 Dale Johannesen <dalej@apple.com> Educate GetInstrSizeInBytes implementations that
DBG_VALUE does not generate code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c7f3ace20c325521c68335a1689645b43b06ddf0 02-Apr-2010 Chris Lattner <sabre@nondot.org> use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
93d6a7e9c21204c52d6efec6c672163e7de79660 02-Apr-2010 Dale Johannesen <dalej@apple.com> Teach AnalyzeBranch, RemoveBranch and the branch
folder to be tolerant of debug info following the
branch(es) at the end of a block.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
baafcbb4dbbda50d5b811b6888c77fd64d073865 26-Feb-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Merge PPC instructions FMRS and FMRD into a single FMR instruction.

This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.

Also allow folding of memory operands on FMRSD.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
243296690ec78fc918762bd73896b09e26537f47 26-Feb-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().

The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c12da8d30a1394847ee4608fcd54daa24b889b37 12-Feb-2010 Dale Johannesen <dalej@apple.com> When save/restoring CR at prolog/epilog, in a large
stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
864e2efce2cb5d02e376933933d96074723fe77c 05-Dec-2009 Dan Gohman <gohman@apple.com> Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
af76e592c7f9deff0e55c13dbb4a34f07f1c7f64 22-Aug-2009 Chris Lattner <sabre@nondot.org> Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d90183d25dcbc0eabde56319fed4e8d6ace2e6eb 02-Aug-2009 Chris Lattner <sabre@nondot.org> Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.

The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
23ed52752bb40a9085c9d36bbc6603972c3e0080 24-Jul-2009 Eli Friedman <eli.friedman@gmail.com> Remove unused member functions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
dac237e18209b697a8ba122d0ddd9cad4dfba1f8 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
6a3a1ba97e996bfdc061f9a51bd4cf4915962913 03-Jul-2009 Tilmann Scheller <tilmann.scheller@googlemail.com> Various small changes related to the Condition Register on PowerPC.

Don't spill to the CR save area when using the SVR4 ABI for now.
Don't rely on constants assigned for registers to be in order (they aren't assigned in order).
Make sure CR bits are mapped to the corresponding CR field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
2578ba26e72e36dde64be0f52a2788480aad3378 01-Jul-2009 Evan Cheng <evan.cheng@apple.com> Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 13-May-2009 Bill Wendling <isanbard@gmail.com> Change MachineInstrBuilder::addReg() to take a flag instead of a list of
booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
82ae933e55839713ea039e7c6353483b14dc5724 09-May-2009 Evan Cheng <evan.cheng@apple.com> PPC::B and PPC::BCC's target operand may be an immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
97357614b5957cc167c261d3be54713802715d9a 18-Feb-2009 Dan Gohman <gohman@apple.com> Factor out the code to add a MachineOperand to a MachineInstrBuilder.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
536a2f1f8467a17f6d145bd83f25faae1f689839 13-Feb-2009 Dale Johannesen <dalej@apple.com> Remove refs to non-DebugLoc version of BuildMI from PowerPC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
21b5541814d57d0a31f353948e4e933dbb1af6a4 13-Feb-2009 Dale Johannesen <dalej@apple.com> Eliminate a couple of non-DebugLoc BuildMI variants.
Modify callers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d1c321a89ab999b9bb602b0f398ecd4c2022262c 12-Feb-2009 Bill Wendling <isanbard@gmail.com> Move debug loc info along when the spiller creates new instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
dc54d317e7a381ef8e4aca80d54ad1466bb85dda 09-Feb-2009 Evan Cheng <evan.cheng@apple.com> Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
770bcc7b15adbc978800db70dbb1c3c22913b52c 06-Feb-2009 Evan Cheng <evan.cheng@apple.com> Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 20-Jan-2009 Evan Cheng <evan.cheng@apple.com> Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c54baa2d43730f1804acfb4f4e738fba72f966bd 03-Dec-2008 Dan Gohman <gohman@apple.com> Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 18-Nov-2008 Dan Gohman <gohman@apple.com> Add more const qualifiers. This fixes build breakage from r59540.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
8e8b8a223c2b0e69f44c0639f846260c8011668f 16-Oct-2008 Dan Gohman <gohman@apple.com> Const-ify several TargetInstrInfo methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d735b8019b0f297d7c14b55adcd887af24d8e602 03-Oct-2008 Dan Gohman <gohman@apple.com> Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
014278e6a11fa0767853b831e5bf51b95bf541c5 13-Sep-2008 Dan Gohman <gohman@apple.com> Remove isImm(), isReg(), and friends, in favor of
isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
940f83e772ca2007d62faffc83094bd7e8da6401 26-Aug-2008 Owen Anderson <resistor@mac.com> Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
44eb65cf58e3ab9b5621ce72256d1621a18aeed7 15-Aug-2008 Owen Anderson <resistor@mac.com> Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
8e5f2c6f65841542e2a7092553fe42a00048e4c7 08-Jul-2008 Dan Gohman <gohman@apple.com> Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
9f1c8317a4676945b4961ddb9827ef2412551620 03-Jul-2008 Evan Cheng <evan.cheng@apple.com> - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4406604047423576e36657c7ede266ca42e79642 01-Jul-2008 Dan Gohman <gohman@apple.com> Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 16-Jun-2008 Evan Cheng <evan.cheng@apple.com> Add option to commuteInstruction() which forces it to create a new (commuted) instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
52e724ad7e679ee590f4bd763d55280586a8f1bc 16-Apr-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
71a2cb25ebc818383dd0f80475bc166f834e8d99 20-Mar-2008 Chris Lattner <sabre@nondot.org> detabify llvm, patch by Mike Stump!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4a66e9a57e679b4f3243bf2061daf53c70102030 10-Mar-2008 Bill Wendling <isanbard@gmail.com> Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
cb341de0e238f80dabf3da7b4f2aad58de6914bd 10-Mar-2008 Chris Lattner <sabre@nondot.org> fix 80 col violations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
9348c69dcfe1aa1e7f92752a18222dcfbcd96214 10-Mar-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Stylistic modifications. No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
0404cd97e4f6ebfe4f8057d4e21119d77654dff2 10-Mar-2008 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Add description of individual bits in CR. This fix PR1765.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
880d0f6018b6928bdcad291be60c801238619955 05-Mar-2008 Bill Wendling <isanbard@gmail.com> Use a command-line option to turn register scavenging on/off for PPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7194aaf738a1b89441635340403f1c5b06ae18ef 03-Mar-2008 Bill Wendling <isanbard@gmail.com> This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
a4d16a1f0dcdd1ab2862737105f900e2c577532d 13-Feb-2008 Evan Cheng <evan.cheng@apple.com> commuteInstr() can now commute non-ssa machine instrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
5fd79d0560570fed977788a86fa038b898564dfa 08-Feb-2008 Evan Cheng <evan.cheng@apple.com> It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
cc8cd0cbf12c12916d4b38ef0de5be5501c8270e 07-Jan-2008 Chris Lattner <sabre@nondot.org> remove MachineOpCode typedef.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
43dbe05279b753aabda571d9c83eaeb36987001a 07-Jan-2008 Owen Anderson <resistor@mac.com> Move even more functionality from MRegisterInfo into TargetInstrInfo.

Some day I'll get it all moved over...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
f6372aa1cc568df19da7c5023e83c75aa9404a07 01-Jan-2008 Owen Anderson <resistor@mac.com> Move some more instruction creation methods from RegisterInfo into InstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
264e6fec9f3962cb269031d6d84cee9f896e0286 01-Jan-2008 Chris Lattner <sabre@nondot.org> Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
641055225092833197efe8e5bce01d50bcf1daae 01-Jan-2008 Chris Lattner <sabre@nondot.org> Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 31-Dec-2007 Owen Anderson <resistor@mac.com> Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 31-Dec-2007 Chris Lattner <sabre@nondot.org> Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on
switching everything over, so new clients should just start using the
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(),
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
f73823000e2d5d6e1cf65bdf5a107297e18d35fb 30-Dec-2007 Chris Lattner <sabre@nondot.org> More cleanups for MachineOperand:
- Eliminate the static "print" method for operands, moving it
into MachineOperand::print.
- Change various set* methods for register flags to take a bool
for the value to set it to. Remove unset* methods.
- Group methods more logically by operand flavor in MachineOperand.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 30-Dec-2007 Chris Lattner <sabre@nondot.org> Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
718cb665ca6ce2bc4d8e8479f46a45db91b49f86 07-Sep-2007 Owen Anderson <resistor@mac.com> Add lengthof and endof templates that hide a lot of sizeof computations.
Patch by Sterling Stein!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
13e8b51e3ec014c5d7ae83afdf3b8fd29c3a461d 13-Jun-2007 Dale Johannesen <dalej@apple.com> Handle blocks with 2 unconditional branches in AnalyzeBranch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8 08-Jun-2007 Evan Cheng <evan.cheng@apple.com> Add a utility routine to check for unpredicated terminator instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
126f17a17625876adb63f06d043fc1b1e4f0361c 21-May-2007 Evan Cheng <evan.cheng@apple.com> BlockHasNoFallThrough() now returns true if block ends with a return instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b5cdaa257e167a08a8a54ea9249d847ccc415ce0 18-May-2007 Evan Cheng <evan.cheng@apple.com> RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
1e341729dd003ca33ecea4abf13134f20062c5f8 25-Apr-2007 Evan Cheng <evan.cheng@apple.com> Relex assertions to account for additional implicit def / use operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 07-Dec-2006 Bill Wendling <isanbard@gmail.com> What should be the last unnecessary <iostream>s in the library.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c0f64ffab93d11fb27a3b8a0707b77400918a20e 28-Nov-2006 Evan Cheng <evan.cheng@apple.com> Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
18258c640466274c26e89016e361ec411ff78520 17-Nov-2006 Chris Lattner <sabre@nondot.org> convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
289c2d5f4566d8d7722e3934f4763d3df92886f3 17-Nov-2006 Chris Lattner <sabre@nondot.org> rename PPC::COND_BRANCH to PPC::BCC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
df4ed6350b2a51f71c0980e86c9078f4046ea706 17-Nov-2006 Chris Lattner <sabre@nondot.org> start using PPC predicates more consistently.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
6ce7dc2a97260eea5fba414332796464912b9359 15-Nov-2006 Evan Cheng <evan.cheng@apple.com> Properly transfer kill / dead info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7ce45783531cfa81bfd7be561ea7e4738e8c6ca8 14-Nov-2006 Evan Cheng <evan.cheng@apple.com> Matches MachineInstr changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
ef13982aa7f3e57e82cd48370e79033dff0da295 28-Oct-2006 Chris Lattner <sabre@nondot.org> implement the BlockHasNoFallThrough hook


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7c4fe259f8bfeae542cfef25c1f1e9b1ff25a39b 21-Oct-2006 Chris Lattner <sabre@nondot.org> Implement support for branch reversal, fix a bug in branch analysis.
This provides stuff like:

cmpw cr0, r15, r29
mr r14, r15
- bge cr0, LBB3_111 ;bb656
- b LBB3_90 ;bb501
+ blt cr0, LBB3_90 ;bb501
LBB3_111: ;bb656
lwz r18, 68(r1)

which is particularly good for dispatch group formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
879d09cf130f3760a08865913c04d9ff328fad5f 21-Oct-2006 Chris Lattner <sabre@nondot.org> Simplify code, no functionality change


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
54108068b71a7dbc48f4ebf1b2d7d87ca541070a 21-Oct-2006 Chris Lattner <sabre@nondot.org> implement support for inserting a cond branch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
2dc7723474c54efcbcac6265dad0a7271902f1a5 17-Oct-2006 Chris Lattner <sabre@nondot.org> add support for inserting an uncond branch


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
c50e2bcdf7bff1f9681ab80e52691f274950fab5 13-Oct-2006 Chris Lattner <sabre@nondot.org> implement branch inspection/modification methods.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
804e06704261f233111913a047ef7f7dec1b8725 11-Jul-2006 Chris Lattner <sabre@nondot.org> In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b410dc99774d52b4491750dab10b91cca1d661d8 21-Jun-2006 Chris Lattner <sabre@nondot.org> Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b1d26f66658cff3ceb7d44a72fbc8c8e975532f9 17-Jun-2006 Chris Lattner <sabre@nondot.org> Implement the getPointerRegClass method, which is required for the ptr_rc
magic to work.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
e53f4a055f74bded20d6129b4724ddd17fd199f6 04-May-2006 Chris Lattner <sabre@nondot.org> Move some methods out of MachineInstr into MachineOperand


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
9c09c9ec9dab61450800b42cbf746164aa076b88 16-Mar-2006 Chris Lattner <sabre@nondot.org> teach the ppc backend how to spill/reload vector regs


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
335fd3c7c2057b4e5fedb3161df44d7bc1759791 16-Mar-2006 Chris Lattner <sabre@nondot.org> Add support for copying registers. still needed: spilling and reloading them


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
bbf1c72d51a77bf54c9c684b90a78e59f0b70b2f 06-Mar-2006 Chris Lattner <sabre@nondot.org> implement TII::insertNoop


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
3b478b31e297208ef2c9f74750a8a603eb3726fb 02-Feb-2006 Nate Begeman <natebegeman@mac.com> add 64b gpr store to the possible list of isStoreToStackSlot opcodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
6524287c53cf727a8ef33517403fcb1bbd7adff9 02-Feb-2006 Chris Lattner <sabre@nondot.org> implement isStoreToStackSlot for PPC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
408396014742a05cad1c91949d2226169e3f9d80 02-Feb-2006 Chris Lattner <sabre@nondot.org> Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
14c09b81ead8fe8b754fca2d0a8237cb810b37d6 19-Oct-2005 Chris Lattner <sabre@nondot.org> teach ppc backend these are copies


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 18-Oct-2005 Nate Begeman <natebegeman@mac.com> First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
21e463b2bf864671a87ebe386cb100ef9349a540 16-Oct-2005 Nate Begeman <natebegeman@mac.com> More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
16e71f2f70811c69c56052dd146324fe20e31db5 15-Oct-2005 Chris Lattner <sabre@nondot.org> Rename PPC32*.h to PPC*.h

This completes the grand PPC file renaming


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
2668959b8879097db368aec7d76c455260abc75b 15-Oct-2005 Chris Lattner <sabre@nondot.org> Rename PowerPC*.h to PPC*.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
4c7b43b43fdf943c7298718e15ab5d6dfe345be7 15-Oct-2005 Chris Lattner <sabre@nondot.org> Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
eb5d47d99db0d9e4fc11f136fbacbd507c71a4c2 07-Oct-2005 Chris Lattner <sabre@nondot.org> Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC. We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
919c032fa4511468aadc6f50d6ed9c50890710b3 01-Oct-2005 Chris Lattner <sabre@nondot.org> Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
043870dd85ea41e8972c304b122070a417c8a4bc 09-Sep-2005 Chris Lattner <sabre@nondot.org> Teach the code generator that rlwimi is commutable if the rotate amount
is zero. This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 22-Apr-2005 Misha Brukman <brukman+llvm@gmail.com> Remove trailing whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
7af0248af47fbd86ec65d308adda22ec367accc4 12-Apr-2005 Nate Begeman <natebegeman@mac.com> Initial support for allocation condition registers


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
cb90de37a720b0b00d6303b49b8df6d5ac5f34f9 08-Oct-2004 Nate Begeman <natebegeman@mac.com> Add ori reg, reg, 0 as a move instruction. This can be generated from
loading a 32bit constant into a register whose low halfword is all zeroes.

We now omit the ori after the lis for the following C code:

int bar(int y) { return y * 0x00F0000; }

_bar:
.LBB_bar_0: ; entry
; IMPLICIT_DEF
lis r2, 15
mullw r3, r3, r2
blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
f2ccb77ee9d8ab35866dae111fa36929689c7511 17-Aug-2004 Misha Brukman <brukman+llvm@gmail.com> PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp