PPCInstrInfo.cpp revision 97357614b5957cc167c261d3be54713802715d9a 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
34                               unsigned& sourceReg,
35                               unsigned& destReg,
36                               unsigned& sourceSubIdx,
37                               unsigned& destSubIdx) const {
38  sourceSubIdx = destSubIdx = 0; // No sub-registers.
39
40  unsigned oc = MI.getOpcode();
41  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
43    assert(MI.getNumOperands() >= 3 &&
44           MI.getOperand(0).isReg() &&
45           MI.getOperand(1).isReg() &&
46           MI.getOperand(2).isReg() &&
47           "invalid PPC OR instruction!");
48    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49      sourceReg = MI.getOperand(1).getReg();
50      destReg = MI.getOperand(0).getReg();
51      return true;
52    }
53  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
54    assert(MI.getNumOperands() >= 3 &&
55           MI.getOperand(0).isReg() &&
56           MI.getOperand(2).isImm() &&
57           "invalid PPC ADDI instruction!");
58    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59      sourceReg = MI.getOperand(1).getReg();
60      destReg = MI.getOperand(0).getReg();
61      return true;
62    }
63  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
64    assert(MI.getNumOperands() >= 3 &&
65           MI.getOperand(0).isReg() &&
66           MI.getOperand(1).isReg() &&
67           MI.getOperand(2).isImm() &&
68           "invalid PPC ORI instruction!");
69    if (MI.getOperand(2).getImm() == 0) {
70      sourceReg = MI.getOperand(1).getReg();
71      destReg = MI.getOperand(0).getReg();
72      return true;
73    }
74  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75             oc == PPC::FMRSD) {      // fmr r1, r2
76    assert(MI.getNumOperands() >= 2 &&
77           MI.getOperand(0).isReg() &&
78           MI.getOperand(1).isReg() &&
79           "invalid PPC FMR instruction");
80    sourceReg = MI.getOperand(1).getReg();
81    destReg = MI.getOperand(0).getReg();
82    return true;
83  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC MCRF instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  }
92  return false;
93}
94
95unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                           int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::LD:
100  case PPC::LWZ:
101  case PPC::LFS:
102  case PPC::LFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                          int &FrameIndex) const {
115  switch (MI->getOpcode()) {
116  default: break;
117  case PPC::STD:
118  case PPC::STW:
119  case PPC::STFS:
120  case PPC::STFD:
121    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122        MI->getOperand(2).isFI()) {
123      FrameIndex = MI->getOperand(2).getIndex();
124      return MI->getOperand(0).getReg();
125    }
126    break;
127  }
128  return 0;
129}
130
131// commuteInstruction - We can commute rlwimi instructions, but only if the
132// rotate amt is zero.  We also have to munge the immediates a bit.
133MachineInstr *
134PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135  MachineFunction &MF = *MI->getParent()->getParent();
136
137  // Normal instructions can be commuted the obvious way.
138  if (MI->getOpcode() != PPC::RLWIMI)
139    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
140
141  // Cannot commute if it has a non-zero rotate count.
142  if (MI->getOperand(3).getImm() != 0)
143    return 0;
144
145  // If we have a zero rotate count, we have:
146  //   M = mask(MB,ME)
147  //   Op0 = (Op1 & ~M) | (Op2 & M)
148  // Change this to:
149  //   M = mask((ME+1)&31, (MB-1)&31)
150  //   Op0 = (Op2 & ~M) | (Op1 & M)
151
152  // Swap op1/op2
153  unsigned Reg0 = MI->getOperand(0).getReg();
154  unsigned Reg1 = MI->getOperand(1).getReg();
155  unsigned Reg2 = MI->getOperand(2).getReg();
156  bool Reg1IsKill = MI->getOperand(1).isKill();
157  bool Reg2IsKill = MI->getOperand(2).isKill();
158  bool ChangeReg0 = false;
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    Reg2IsKill = false;
166    ChangeReg0 = true;
167  }
168
169  // Masks.
170  unsigned MB = MI->getOperand(4).getImm();
171  unsigned ME = MI->getOperand(5).getImm();
172
173  if (NewMI) {
174    // Create a new instruction.
175    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176    bool Reg0IsDead = MI->getOperand(0).isDead();
177    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178      .addReg(Reg0, true, false, false, Reg0IsDead)
179      .addReg(Reg2, false, false, Reg2IsKill)
180      .addReg(Reg1, false, false, Reg1IsKill)
181      .addImm((ME+1) & 31)
182      .addImm((MB-1) & 31);
183  }
184
185  if (ChangeReg0)
186    MI->getOperand(0).setReg(Reg2);
187  MI->getOperand(2).setReg(Reg1);
188  MI->getOperand(1).setReg(Reg2);
189  MI->getOperand(2).setIsKill(Reg1IsKill);
190  MI->getOperand(1).setIsKill(Reg2IsKill);
191
192  // Swap the mask around.
193  MI->getOperand(4).setImm((ME+1) & 31);
194  MI->getOperand(5).setImm((MB-1) & 31);
195  return MI;
196}
197
198void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                              MachineBasicBlock::iterator MI) const {
200  DebugLoc DL = DebugLoc::getUnknownLoc();
201  if (MI != MBB.end()) DL = MI->getDebugLoc();
202
203  BuildMI(MBB, MI, DL, get(PPC::NOP));
204}
205
206
207// Branch analysis.
208bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                 MachineBasicBlock *&FBB,
210                                 SmallVectorImpl<MachineOperand> &Cond,
211                                 bool AllowModify) const {
212  // If the block has no terminators, it just falls into the block after it.
213  MachineBasicBlock::iterator I = MBB.end();
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
215    return false;
216
217  // Get the last instruction in the block.
218  MachineInstr *LastInst = I;
219
220  // If there is only one terminator instruction, process it.
221  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
222    if (LastInst->getOpcode() == PPC::B) {
223      TBB = LastInst->getOperand(0).getMBB();
224      return false;
225    } else if (LastInst->getOpcode() == PPC::BCC) {
226      // Block ends with fall-through condbranch.
227      TBB = LastInst->getOperand(2).getMBB();
228      Cond.push_back(LastInst->getOperand(0));
229      Cond.push_back(LastInst->getOperand(1));
230      return false;
231    }
232    // Otherwise, don't know what this is.
233    return true;
234  }
235
236  // Get the instruction before it if it's a terminator.
237  MachineInstr *SecondLastInst = I;
238
239  // If there are three terminators, we don't know what sort of block this is.
240  if (SecondLastInst && I != MBB.begin() &&
241      isUnpredicatedTerminator(--I))
242    return true;
243
244  // If the block ends with PPC::B and PPC:BCC, handle it.
245  if (SecondLastInst->getOpcode() == PPC::BCC &&
246      LastInst->getOpcode() == PPC::B) {
247    TBB =  SecondLastInst->getOperand(2).getMBB();
248    Cond.push_back(SecondLastInst->getOperand(0));
249    Cond.push_back(SecondLastInst->getOperand(1));
250    FBB = LastInst->getOperand(0).getMBB();
251    return false;
252  }
253
254  // If the block ends with two PPC:Bs, handle it.  The second one is not
255  // executed, so remove it.
256  if (SecondLastInst->getOpcode() == PPC::B &&
257      LastInst->getOpcode() == PPC::B) {
258    TBB = SecondLastInst->getOperand(0).getMBB();
259    I = LastInst;
260    if (AllowModify)
261      I->eraseFromParent();
262    return false;
263  }
264
265  // Otherwise, can't handle this.
266  return true;
267}
268
269unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
270  MachineBasicBlock::iterator I = MBB.end();
271  if (I == MBB.begin()) return 0;
272  --I;
273  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
274    return 0;
275
276  // Remove the branch.
277  I->eraseFromParent();
278
279  I = MBB.end();
280
281  if (I == MBB.begin()) return 1;
282  --I;
283  if (I->getOpcode() != PPC::BCC)
284    return 1;
285
286  // Remove the branch.
287  I->eraseFromParent();
288  return 2;
289}
290
291unsigned
292PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
293                           MachineBasicBlock *FBB,
294                           const SmallVectorImpl<MachineOperand> &Cond) const {
295  // FIXME this should probably have a DebugLoc argument
296  DebugLoc dl = DebugLoc::getUnknownLoc();
297  // Shouldn't be a fall through.
298  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
299  assert((Cond.size() == 2 || Cond.size() == 0) &&
300         "PPC branch conditions have two components!");
301
302  // One-way branch.
303  if (FBB == 0) {
304    if (Cond.empty())   // Unconditional branch
305      BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
306    else                // Conditional branch
307      BuildMI(&MBB, dl, get(PPC::BCC))
308        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
309    return 1;
310  }
311
312  // Two-way Conditional Branch.
313  BuildMI(&MBB, dl, get(PPC::BCC))
314    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
315  BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
316  return 2;
317}
318
319bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
320                                   MachineBasicBlock::iterator MI,
321                                   unsigned DestReg, unsigned SrcReg,
322                                   const TargetRegisterClass *DestRC,
323                                   const TargetRegisterClass *SrcRC) const {
324  if (DestRC != SrcRC) {
325    // Not yet supported!
326    return false;
327  }
328
329  DebugLoc DL = DebugLoc::getUnknownLoc();
330  if (MI != MBB.end()) DL = MI->getDebugLoc();
331
332  if (DestRC == PPC::GPRCRegisterClass) {
333    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
334  } else if (DestRC == PPC::G8RCRegisterClass) {
335    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
336  } else if (DestRC == PPC::F4RCRegisterClass) {
337    BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
338  } else if (DestRC == PPC::F8RCRegisterClass) {
339    BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
340  } else if (DestRC == PPC::CRRCRegisterClass) {
341    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
342  } else if (DestRC == PPC::VRRCRegisterClass) {
343    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
344  } else if (DestRC == PPC::CRBITRCRegisterClass) {
345    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
346  } else {
347    // Attempt to copy register that is not GPR or FPR
348    return false;
349  }
350
351  return true;
352}
353
354bool
355PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
356                                  unsigned SrcReg, bool isKill,
357                                  int FrameIdx,
358                                  const TargetRegisterClass *RC,
359                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
360  DebugLoc DL = DebugLoc::getUnknownLoc();
361  if (RC == PPC::GPRCRegisterClass) {
362    if (SrcReg != PPC::LR) {
363      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
364                                         .addReg(SrcReg, false, false, isKill),
365                                         FrameIdx));
366    } else {
367      // FIXME: this spills LR immediately to memory in one step.  To do this,
368      // we use R11, which we know cannot be used in the prolog/epilog.  This is
369      // a hack.
370      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
371      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
372                                         .addReg(PPC::R11, false, false, isKill),
373                                         FrameIdx));
374    }
375  } else if (RC == PPC::G8RCRegisterClass) {
376    if (SrcReg != PPC::LR8) {
377      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
378                              .addReg(SrcReg, false, false, isKill), FrameIdx));
379    } else {
380      // FIXME: this spills LR immediately to memory in one step.  To do this,
381      // we use R11, which we know cannot be used in the prolog/epilog.  This is
382      // a hack.
383      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
384      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
385                            .addReg(PPC::X11, false, false, isKill), FrameIdx));
386    }
387  } else if (RC == PPC::F8RCRegisterClass) {
388    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
389                              .addReg(SrcReg, false, false, isKill), FrameIdx));
390  } else if (RC == PPC::F4RCRegisterClass) {
391    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
392                              .addReg(SrcReg, false, false, isKill), FrameIdx));
393  } else if (RC == PPC::CRRCRegisterClass) {
394    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
395        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
396      // FIXME (64-bit): Enable
397      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
398                                         .addReg(SrcReg, false, false, isKill),
399                                         FrameIdx));
400      return true;
401    } else {
402      // FIXME: We use R0 here, because it isn't available for RA.  We need to
403      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
404      // to save all of the CRBits.
405      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
406
407      // If the saved register wasn't CR0, shift the bits left so that they are
408      // in CR0's slot.
409      if (SrcReg != PPC::CR0) {
410        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
411        // rlwinm r0, r0, ShiftBits, 0, 31.
412        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
413                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
414      }
415
416      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
417                                         .addReg(PPC::R0, false, false, isKill),
418                                         FrameIdx));
419    }
420  } else if (RC == PPC::CRBITRCRegisterClass) {
421    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
422    // backend currently only uses CR1EQ as an individual bit, this should
423    // not cause any bug. If we need other uses of CR bits, the following
424    // code may be invalid.
425    unsigned Reg = 0;
426    if (SrcReg >= PPC::CR0LT || SrcReg <= PPC::CR0UN)
427      Reg = PPC::CR0;
428    else if (SrcReg >= PPC::CR1LT || SrcReg <= PPC::CR1UN)
429      Reg = PPC::CR1;
430    else if (SrcReg >= PPC::CR2LT || SrcReg <= PPC::CR2UN)
431      Reg = PPC::CR2;
432    else if (SrcReg >= PPC::CR3LT || SrcReg <= PPC::CR3UN)
433      Reg = PPC::CR3;
434    else if (SrcReg >= PPC::CR4LT || SrcReg <= PPC::CR4UN)
435      Reg = PPC::CR4;
436    else if (SrcReg >= PPC::CR5LT || SrcReg <= PPC::CR5UN)
437      Reg = PPC::CR5;
438    else if (SrcReg >= PPC::CR6LT || SrcReg <= PPC::CR6UN)
439      Reg = PPC::CR6;
440    else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
441      Reg = PPC::CR7;
442
443    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
444                               PPC::CRRCRegisterClass, NewMIs);
445
446  } else if (RC == PPC::VRRCRegisterClass) {
447    // We don't have indexed addressing for vector loads.  Emit:
448    // R0 = ADDI FI#
449    // STVX VAL, 0, R0
450    //
451    // FIXME: We use R0 here, because it isn't available for RA.
452    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
453                                       FrameIdx, 0, 0));
454    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
455         .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
456  } else {
457    assert(0 && "Unknown regclass!");
458    abort();
459  }
460
461  return false;
462}
463
464void
465PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
466                                  MachineBasicBlock::iterator MI,
467                                  unsigned SrcReg, bool isKill, int FrameIdx,
468                                  const TargetRegisterClass *RC) const {
469  MachineFunction &MF = *MBB.getParent();
470  SmallVector<MachineInstr*, 4> NewMIs;
471
472  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
473    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
474    FuncInfo->setSpillsCR();
475  }
476
477  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
478    MBB.insert(MI, NewMIs[i]);
479}
480
481void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
482                                  bool isKill,
483                                  SmallVectorImpl<MachineOperand> &Addr,
484                                  const TargetRegisterClass *RC,
485                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
486  if (Addr[0].isFI()) {
487    if (StoreRegToStackSlot(MF, SrcReg, isKill,
488                            Addr[0].getIndex(), RC, NewMIs)) {
489      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
490      FuncInfo->setSpillsCR();
491    }
492
493    return;
494  }
495
496  DebugLoc DL = DebugLoc::getUnknownLoc();
497  unsigned Opc = 0;
498  if (RC == PPC::GPRCRegisterClass) {
499    Opc = PPC::STW;
500  } else if (RC == PPC::G8RCRegisterClass) {
501    Opc = PPC::STD;
502  } else if (RC == PPC::F8RCRegisterClass) {
503    Opc = PPC::STFD;
504  } else if (RC == PPC::F4RCRegisterClass) {
505    Opc = PPC::STFS;
506  } else if (RC == PPC::VRRCRegisterClass) {
507    Opc = PPC::STVX;
508  } else {
509    assert(0 && "Unknown regclass!");
510    abort();
511  }
512  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
513    .addReg(SrcReg, false, false, isKill);
514  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
515    MIB.addOperand(Addr[i]);
516  NewMIs.push_back(MIB);
517  return;
518}
519
520void
521PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
522                                   unsigned DestReg, int FrameIdx,
523                                   const TargetRegisterClass *RC,
524                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
525  if (RC == PPC::GPRCRegisterClass) {
526    if (DestReg != PPC::LR) {
527      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
528                                                 DestReg), FrameIdx));
529    } else {
530      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
531                                                 PPC::R11), FrameIdx));
532      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
533    }
534  } else if (RC == PPC::G8RCRegisterClass) {
535    if (DestReg != PPC::LR8) {
536      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
537                                         FrameIdx));
538    } else {
539      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
540                                                 PPC::R11), FrameIdx));
541      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
542    }
543  } else if (RC == PPC::F8RCRegisterClass) {
544    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
545                                       FrameIdx));
546  } else if (RC == PPC::F4RCRegisterClass) {
547    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
548                                       FrameIdx));
549  } else if (RC == PPC::CRRCRegisterClass) {
550    // FIXME: We use R0 here, because it isn't available for RA.
551    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
552                                       FrameIdx));
553
554    // If the reloaded register isn't CR0, shift the bits right so that they are
555    // in the right CR's slot.
556    if (DestReg != PPC::CR0) {
557      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
558      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
559      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
560                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
561    }
562
563    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
564  } else if (RC == PPC::CRBITRCRegisterClass) {
565
566    unsigned Reg = 0;
567    if (DestReg >= PPC::CR0LT || DestReg <= PPC::CR0UN)
568      Reg = PPC::CR0;
569    else if (DestReg >= PPC::CR1LT || DestReg <= PPC::CR1UN)
570      Reg = PPC::CR1;
571    else if (DestReg >= PPC::CR2LT || DestReg <= PPC::CR2UN)
572      Reg = PPC::CR2;
573    else if (DestReg >= PPC::CR3LT || DestReg <= PPC::CR3UN)
574      Reg = PPC::CR3;
575    else if (DestReg >= PPC::CR4LT || DestReg <= PPC::CR4UN)
576      Reg = PPC::CR4;
577    else if (DestReg >= PPC::CR5LT || DestReg <= PPC::CR5UN)
578      Reg = PPC::CR5;
579    else if (DestReg >= PPC::CR6LT || DestReg <= PPC::CR6UN)
580      Reg = PPC::CR6;
581    else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
582      Reg = PPC::CR7;
583
584    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
585                                PPC::CRRCRegisterClass, NewMIs);
586
587  } else if (RC == PPC::VRRCRegisterClass) {
588    // We don't have indexed addressing for vector loads.  Emit:
589    // R0 = ADDI FI#
590    // Dest = LVX 0, R0
591    //
592    // FIXME: We use R0 here, because it isn't available for RA.
593    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
594                                       FrameIdx, 0, 0));
595    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
596                     .addReg(PPC::R0));
597  } else {
598    assert(0 && "Unknown regclass!");
599    abort();
600  }
601}
602
603void
604PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
605                                   MachineBasicBlock::iterator MI,
606                                   unsigned DestReg, int FrameIdx,
607                                   const TargetRegisterClass *RC) const {
608  MachineFunction &MF = *MBB.getParent();
609  SmallVector<MachineInstr*, 4> NewMIs;
610  DebugLoc DL = DebugLoc::getUnknownLoc();
611  if (MI != MBB.end()) DL = MI->getDebugLoc();
612  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
613  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
614    MBB.insert(MI, NewMIs[i]);
615}
616
617void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
618                                   SmallVectorImpl<MachineOperand> &Addr,
619                                   const TargetRegisterClass *RC,
620                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
621  if (Addr[0].isFI()) {
622    LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
623                         DestReg, Addr[0].getIndex(), RC, NewMIs);
624    return;
625  }
626
627  unsigned Opc = 0;
628  if (RC == PPC::GPRCRegisterClass) {
629    assert(DestReg != PPC::LR && "Can't handle this yet!");
630    Opc = PPC::LWZ;
631  } else if (RC == PPC::G8RCRegisterClass) {
632    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
633    Opc = PPC::LD;
634  } else if (RC == PPC::F8RCRegisterClass) {
635    Opc = PPC::LFD;
636  } else if (RC == PPC::F4RCRegisterClass) {
637    Opc = PPC::LFS;
638  } else if (RC == PPC::VRRCRegisterClass) {
639    Opc = PPC::LVX;
640  } else {
641    assert(0 && "Unknown regclass!");
642    abort();
643  }
644  DebugLoc DL = DebugLoc::getUnknownLoc();
645  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
646  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
647    MIB.addOperand(Addr[i]);
648  NewMIs.push_back(MIB);
649  return;
650}
651
652/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
653/// copy instructions, turning them into load/store instructions.
654MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
655                                                  MachineInstr *MI,
656                                           const SmallVectorImpl<unsigned> &Ops,
657                                                  int FrameIndex) const {
658  if (Ops.size() != 1) return NULL;
659
660  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
661  // it takes more than one instruction to store it.
662  unsigned Opc = MI->getOpcode();
663  unsigned OpNum = Ops[0];
664
665  MachineInstr *NewMI = NULL;
666  if ((Opc == PPC::OR &&
667       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
668    if (OpNum == 0) {  // move -> store
669      unsigned InReg = MI->getOperand(1).getReg();
670      bool isKill = MI->getOperand(1).isKill();
671      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
672                                .addReg(InReg, false, false, isKill),
673                                FrameIndex);
674    } else {           // move -> load
675      unsigned OutReg = MI->getOperand(0).getReg();
676      bool isDead = MI->getOperand(0).isDead();
677      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
678                                .addReg(OutReg, true, false, false, isDead),
679                                FrameIndex);
680    }
681  } else if ((Opc == PPC::OR8 &&
682              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
683    if (OpNum == 0) {  // move -> store
684      unsigned InReg = MI->getOperand(1).getReg();
685      bool isKill = MI->getOperand(1).isKill();
686      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
687                                .addReg(InReg, false, false, isKill),
688                                FrameIndex);
689    } else {           // move -> load
690      unsigned OutReg = MI->getOperand(0).getReg();
691      bool isDead = MI->getOperand(0).isDead();
692      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
693                                .addReg(OutReg, true, false, false, isDead),
694                                FrameIndex);
695    }
696  } else if (Opc == PPC::FMRD) {
697    if (OpNum == 0) {  // move -> store
698      unsigned InReg = MI->getOperand(1).getReg();
699      bool isKill = MI->getOperand(1).isKill();
700      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
701                                .addReg(InReg, false, false, isKill),
702                                FrameIndex);
703    } else {           // move -> load
704      unsigned OutReg = MI->getOperand(0).getReg();
705      bool isDead = MI->getOperand(0).isDead();
706      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
707                                .addReg(OutReg, true, false, false, isDead),
708                                FrameIndex);
709    }
710  } else if (Opc == PPC::FMRS) {
711    if (OpNum == 0) {  // move -> store
712      unsigned InReg = MI->getOperand(1).getReg();
713      bool isKill = MI->getOperand(1).isKill();
714      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
715                                .addReg(InReg, false, false, isKill),
716                                FrameIndex);
717    } else {           // move -> load
718      unsigned OutReg = MI->getOperand(0).getReg();
719      bool isDead = MI->getOperand(0).isDead();
720      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
721                                .addReg(OutReg, true, false, false, isDead),
722                                FrameIndex);
723    }
724  }
725
726  return NewMI;
727}
728
729bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
730                                  const SmallVectorImpl<unsigned> &Ops) const {
731  if (Ops.size() != 1) return false;
732
733  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
734  // it takes more than one instruction to store it.
735  unsigned Opc = MI->getOpcode();
736
737  if ((Opc == PPC::OR &&
738       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
739    return true;
740  else if ((Opc == PPC::OR8 &&
741              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
742    return true;
743  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
744    return true;
745
746  return false;
747}
748
749
750bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
751  if (MBB.empty()) return false;
752
753  switch (MBB.back().getOpcode()) {
754  case PPC::BLR:   // Return.
755  case PPC::B:     // Uncond branch.
756  case PPC::BCTR:  // Indirect branch.
757    return true;
758  default: return false;
759  }
760}
761
762bool PPCInstrInfo::
763ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
764  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
765  // Leave the CR# the same, but invert the condition.
766  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
767  return false;
768}
769
770/// GetInstSize - Return the number of bytes of code the specified
771/// instruction may be.  This returns the maximum number of bytes.
772///
773unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
774  switch (MI->getOpcode()) {
775  case PPC::INLINEASM: {       // Inline Asm: Variable size.
776    const MachineFunction *MF = MI->getParent()->getParent();
777    const char *AsmStr = MI->getOperand(0).getSymbolName();
778    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
779  }
780  case PPC::DBG_LABEL:
781  case PPC::EH_LABEL:
782  case PPC::GC_LABEL:
783    return 0;
784  default:
785    return 4; // PowerPC instructions are all 4 bytes
786  }
787}
788