PPCInstrInfo.cpp revision 919c032fa4511468aadc6f50d6ed9c50890710b3 
1//===- PPC32InstrInfo.cpp - PowerPC32 Instruction Information ---*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPC32InstrInfo.h"
15#include "PPC32GenInstrInfo.inc"
16#include "PowerPC.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include <iostream>
19using namespace llvm;
20
21PPC32InstrInfo::PPC32InstrInfo()
22  : TargetInstrInfo(PPC32Insts, sizeof(PPC32Insts)/sizeof(PPC32Insts[0])) {}
23
24bool PPC32InstrInfo::isMoveInstr(const MachineInstr& MI,
25                                 unsigned& sourceReg,
26                                 unsigned& destReg) const {
27  MachineOpCode oc = MI.getOpcode();
28  if (oc == PPC::OR) {                      // or r1, r2, r2
29    assert(MI.getNumOperands() == 3 &&
30           MI.getOperand(0).isRegister() &&
31           MI.getOperand(1).isRegister() &&
32           MI.getOperand(2).isRegister() &&
33           "invalid PPC OR instruction!");
34    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
35      sourceReg = MI.getOperand(1).getReg();
36      destReg = MI.getOperand(0).getReg();
37      return true;
38    }
39  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
40    assert(MI.getNumOperands() == 3 &&
41           MI.getOperand(0).isRegister() &&
42           MI.getOperand(2).isImmediate() &&
43           "invalid PPC ADDI instruction!");
44    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
45      sourceReg = MI.getOperand(1).getReg();
46      destReg = MI.getOperand(0).getReg();
47      return true;
48    }
49  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
50    assert(MI.getNumOperands() == 3 &&
51           MI.getOperand(0).isRegister() &&
52           MI.getOperand(1).isRegister() &&
53           MI.getOperand(2).isImmediate() &&
54           "invalid PPC ORI instruction!");
55    if (MI.getOperand(2).getImmedValue()==0) {
56      sourceReg = MI.getOperand(1).getReg();
57      destReg = MI.getOperand(0).getReg();
58      return true;
59    }
60  } else if (oc == PPC::FMRS || oc == PPC::FMRD) {      // fmr r1, r2
61    assert(MI.getNumOperands() == 2 &&
62           MI.getOperand(0).isRegister() &&
63           MI.getOperand(1).isRegister() &&
64           "invalid PPC FMR instruction");
65    sourceReg = MI.getOperand(1).getReg();
66    destReg = MI.getOperand(0).getReg();
67    return true;
68  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
69    assert(MI.getNumOperands() == 2 &&
70           MI.getOperand(0).isRegister() &&
71           MI.getOperand(1).isRegister() &&
72           "invalid PPC MCRF instruction");
73    sourceReg = MI.getOperand(1).getReg();
74    destReg = MI.getOperand(0).getReg();
75    return true;
76  }
77  return false;
78}
79
80// commuteInstruction - We can commute rlwimi instructions, but only if the
81// rotate amt is zero.  We also have to munge the immediates a bit.
82MachineInstr *PPC32InstrInfo::commuteInstruction(MachineInstr *MI) const {
83  // Normal instructions can be commuted the obvious way.
84  if (MI->getOpcode() != PPC::RLWIMI)
85    return TargetInstrInfo::commuteInstruction(MI);
86
87  // Cannot commute if it has a non-zero rotate count.
88  if (MI->getOperand(3).getImmedValue() != 0)
89    return 0;
90
91  // If we have a zero rotate count, we have:
92  //   M = mask(MB,ME)
93  //   Op0 = (Op1 & ~M) | (Op2 & M)
94  // Change this to:
95  //   M = mask((ME+1)&31, (MB-1)&31)
96  //   Op0 = (Op2 & ~M) | (Op1 & M)
97
98  // Swap op1/op2
99  unsigned Reg1 = MI->getOperand(1).getReg();
100  unsigned Reg2 = MI->getOperand(2).getReg();
101  MI->SetMachineOperandReg(2, Reg1);
102  MI->SetMachineOperandReg(1, Reg2);
103
104  // Swap the mask around.
105  unsigned MB = MI->getOperand(4).getImmedValue();
106  unsigned ME = MI->getOperand(5).getImmedValue();
107  MI->getOperand(4).setImmedValue((ME+1) & 31);
108  MI->getOperand(5).setImmedValue((MB-1) & 31);
109  return MI;
110}
111