1/* ------------------------------------------------------------------ 2 * Copyright (C) 1998-2009 PacketVideo 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either 13 * express or implied. 14 * See the License for the specific language governing permissions 15 * and limitations under the License. 16 * ------------------------------------------------------------------- 17 */ 18 19#ifndef _SAD_HALFPEL_INLINE_H_ 20#define _SAD_HALFPEL_INLINE_H_ 21 22#ifdef __cplusplus 23extern "C" 24{ 25#endif 26 27/* Intentionally not using the gcc asm version, since it is 28 * slightly slower than the plain C version on modern GCC versions. */ 29#if !defined(__CC_ARM) /* Generic C version */ 30 31 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 32 { 33 tmp = (tmp2 >> 1) - tmp; 34 if (tmp > 0) sad += tmp; 35 else sad -= tmp; 36 37 return sad; 38 } 39 40 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 41 { 42 tmp = (tmp >> 2) - tmp2; 43 if (tmp > 0) sad += tmp; 44 else sad -= tmp; 45 46 return sad; 47 } 48 49#elif defined(__CC_ARM) /* only work with arm v5 */ 50 51 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 52 { 53 __asm 54 { 55 rsbs tmp, tmp, tmp2, asr #1 ; 56 rsbmi tmp, tmp, #0 ; 57 add sad, sad, tmp ; 58 } 59 60 return sad; 61 } 62 63 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 64 { 65 __asm 66 { 67 rsbs tmp, tmp2, tmp, asr #2 ; 68 rsbmi tmp, tmp, #0 ; 69 add sad, sad, tmp ; 70 } 71 72 return sad; 73 } 74 75#elif defined(__GNUC__) && defined(__arm__) /* ARM GNU COMPILER */ 76 77 __inline int32 INTERP1_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 78 { 79 __asm__ volatile( 80 "rsbs %1, %1, %2, asr #1\n\t" 81 "rsbmi %1, %1, #0\n\t" 82 "add %0, %0, %1" 83 : "+r"(sad), "+r"(tmp) 84 : "r"(tmp2) 85 ); 86 87 return sad; 88 } 89 90 __inline int32 INTERP2_SUB_SAD(int32 sad, int32 tmp, int32 tmp2) 91 { 92 __asm__ volatile( 93 "rsbs %1, %2, %1, asr #2\n\t" 94 "rsbmi %1, %1, #0\n\t" 95 "add %0, %0, %1" 96 : "+r"(sad), "+r"(tmp) 97 : "r"(tmp2) 98 ); 99 100 return sad; 101 } 102 103#endif 104 105#ifdef __cplusplus 106} 107#endif 108 109#endif //_SAD_HALFPEL_INLINE_H_ 110 111